Packaging substrate and manufacturing method of packaging substrate

Abstract

A method for manufacturing a packaging substrate and a packaging substrate using the same are disclosed. The packaging substrate includes a core layer, the core layer including a glass substrate and a cavity portion. The glass substrate has a first surface and a second surface facing each other. The cavity portion extends through the glass substrate. A cavity module is disposed in the cavity portion. The cavity module includes a plurality of arranged electronic devices, a first insulating layer, and a third insulating layer. The first insulating layer surrounds each of the electronic devices. The third insulating layer contains a molding material and is arranged such that the molding material surrounds the electronic devices. The first insulating layer is disposed on the entire surface of each electronic device except for one surface, or on the entire surface of each electronic device. The core layer includes a second insulating layer embedded in the portion of the cavity portion excluding the cavity module.

Description

Technical Field

[0001] This embodiment relates to a packaging substrate, a semiconductor package, a method for manufacturing the packaging substrate, and a method for manufacturing the semiconductor package. Prior Technology

[0002] In the manufacture of electronic components, the process of implementing circuits on semiconductor wafers is called the front-end (FE) process, and the process of assembling wafers in a state that can be used in actual products is called the back-end (BE) process, which includes the packaging process.

[0003] The four core technologies driving the rapid development of electronic products recently are semiconductor technology, semiconductor packaging technology, manufacturing process technology, and software technology. Semiconductor technology is evolving in various forms, such as linewidths below the micrometer level (nanometer units), more than ten million cells, high-speed operation, and the generation of large amounts of heat. However, it still lacks the technological support for relatively complete packaging of these semiconductors. Therefore, the electrical performance of semiconductors sometimes depends on packaging technology and corresponding electrical connections, rather than the performance of the semiconductor technology itself.

[0004] Ceramic or resin materials are suitable for use as packaging substrates. However, in the case of ceramic substrates such as silicon substrates, the high resistance or high dielectric constant makes it difficult to mount high-performance, high-frequency semiconductor devices. While resin substrates can mount relatively high-performance, high-frequency semiconductor devices, there are limitations in reducing the spacing between wiring traces.

[0005] Recently, silicon or glass has been found to be suitable for high-end packaging substrates. By forming vias on the silicon or glass substrate and applying conductive material to these vias, the wiring length between the device and the motherboard can be shortened, and excellent electrical characteristics can be obtained.

[0006] Furthermore, semiconductor packages generate heat during operation, and sometimes additional heat dissipation devices are included to dissipate this heat.

[0007] As relevant prior art, there are Korean Patent No. 10-2543188 and US Patent No. 11676942 B2, etc. Summary of the Invention

[0008] [Technical Issues] [ ]

[0009] The purpose of this embodiment is to provide a method for manufacturing a packaging substrate that can prevent undulation phenomena that may occur due to gaps between electronic devices and / or gaps between cavities and electronic devices in a packaging substrate using a glass substrate, and a packaging substrate using the same.

[0010] [Solution to the problem] [ ]

[0011] To achieve the above objectives, a packaging substrate according to one or more embodiments includes a core layer, the core layer including a glass core and a cavity portion, the glass core having a first surface and a second surface facing each other, and the cavity portion penetrating the glass core.

[0012] A cavity module and a second insulating layer are arranged in the aforementioned cavity.

[0013] The aforementioned cavity module includes multiple electronic components, a first insulating layer, and a third insulating layer.

[0014] The first insulating layer is a layer in which each of the aforementioned electronic devices is surrounded by a coating material.

[0015] The aforementioned third insulating layer is a layer of multiple aforementioned electronic devices arranged and surrounded by molding material.

[0016] The first insulating layer may be disposed on the entire surface of each of the aforementioned electronic devices except for one surface, or disposed on the entire surface of each of the aforementioned electronic devices.

[0017] The second insulating layer can be embedded in the internal space of the cavity portion, excluding the cavity module.

[0018] The first insulating layer and the third insulating layer may have different dielectric constants.

[0019] The dielectric constant of the coating material can be lower than that of the molding material of the third insulating layer.

[0020] The high-frequency relative permittivity Dk is the relative permittivity at a high frequency of 5.8 GHz.

[0021] Dk1 is the high-frequency relative permittivity of the first insulating layer, and Dk3 is the high-frequency relative permittivity of the third insulating layer.

[0022] The difference between Dk1 and Dk3 can be greater than 0.1.

[0023] Df1 is the dielectric loss factor of the first insulating layer, and Df3 is the dielectric loss factor of the third insulating layer.

[0024] The difference between Df1 and Df3 can be greater than 0.0001.

[0025] The dielectric constant of the first insulating layer can be lower than that of the second insulating layer.

[0026] Df1 is the dielectric loss factor of the first insulating layer, and Df2 is the dielectric loss factor of the second insulating layer.

[0027] The difference between Df1 and Df2 can be greater than 0.1.

[0028] The aforementioned first insulating layer may include an inorganic deposition layer, a liquid crystal polymer (LCP), an epoxy molding compound (EMC), an Ajinomoto build-up film (ABF), or a modified polyimide (MPI).

[0029] Electronic device connection electrodes can be arranged on the aforementioned electronic device.

[0030] The cavity module described above may include cavity connection electrodes.

[0031] The cavity connection electrode is a connection electrode that is electrically connected to the electronic device connection electrode and exposed on the surface of the cavity module.

[0032] The aforementioned electronic devices may include passive devices, active devices, or both.

[0033] The first insulating layer may also be provided with a through hole that penetrates the first insulating layer.

[0034] The third insulating layer may also be provided with a through hole that penetrates at least a portion of the third insulating layer.

[0035] The interior of the aforementioned first insulating layer through-hole and the aforementioned third insulating layer through-hole may be partially or entirely filled with electrode material.

[0036] To achieve the above objectives, a method for manufacturing a packaging substrate according to one or more embodiments includes: a preparation step of preparing a glass substrate and a cavity module having a cavity portion disposed thereon; and a stacking step of arranging the cavity module in the cavity portion and providing a second insulating layer on the glass substrate.

[0037] The aforementioned cavity module includes multiple electronic components, a first insulating layer, and a third insulating layer.

[0038] The first insulating layer is a layer in which each of the aforementioned electronic devices is surrounded by a coating material.

[0039] The first insulating layer may be disposed on the entire surface of each of the aforementioned electronic devices except for one surface, or disposed on the entire surface of each of the aforementioned electronic devices.

[0040] The aforementioned third insulating layer is a layer of multiple aforementioned electronic devices arranged and surrounded by molding material.

[0041] The second insulating layer can be embedded in the internal space of the cavity portion, excluding the cavity module.

[0042] The first insulating layer and the third insulating layer may have different dielectric constants.

[0043] The aforementioned cavity module can be manufactured using cavity module manufacturing steps.

[0044] The above-mentioned cavity module manufacturing steps include: an arrangement process, arranging adjacent electronic devices; a first insulation process, setting a first insulating layer on the surface of the arranged electronic devices; and a molding process, molding the electronic devices with the first insulating layer using a molding material to manufacture a cavity module containing a third insulating layer.

[0045] The aforementioned molding materials may include epoxy molding compound (EMC), Ajinomoto build-up film (ABF), or modified polyimide (MPI).

[0046] The cavity module manufacturing steps may also include a cavity electrode formation process after the molding process.

[0047] The cavity electrode forming process described above involves removing a portion of the molding material, forming an electrode that connects to the electronic device, and arranging the cavity module connection electrode that connects to the electrode.

[0048] [The effects of the invention] [ ]

[0049] The packaging substrate and its manufacturing method according to this embodiment can improve the quality of the packaging substrate by preventing undulations in the cavity of the embedded electronic device.

[0050] This embodiment can improve the undulation phenomenon of the cavity and prevent leakage current in electronic devices including passive and / or active components.

[0051] This embodiment can prevent short circuits caused by contact between adjacent electronic devices. For example, this embodiment can prevent unintentional short circuits that may occur during the manufacturing process of forming a conductive layer on the side of the cavity.

[0052] This embodiment can prevent the electronic devices from changing position by forming a third insulating layer, thereby preventing contact between electronic devices and preventing unintentional short circuits between electronic devices. Simple Explanation of the Diagram

[0053] Figure 1 is a conceptual diagram illustrating the cross-sectional structure of the packaging substrate according to this embodiment. Figures 2A and 2B are conceptual diagrams illustrating the cross-sectional structure of the packaging substrate according to different embodiments. Figure 3A is a conceptual diagram illustrating the process of generating the cross-sectional structure of the packaging substrate in Figure 2A. Figure 3B is a conceptual diagram illustrating the process of generating the cross-sectional structure of the packaging substrate in Figure 2B. Figure 4 is a cross-sectional flowchart illustrating the process of generating the core distribution layer during the manufacturing process of the packaging substrate according to this embodiment. Figure 5 is a cross-sectional flowchart illustrating the process of generating an insulating layer during the manufacturing of the packaging substrate according to this embodiment. Figure 6 shows an example of the cross-sectional structure of the core layer of the packaging substrate according to this embodiment. Figure 7 shows an example of the cross-sectional structure of the core layer of the packaging substrate produced according to this embodiment. Figure 8 is a cross-sectional flowchart illustrating the manufacturing method of the packaging substrate according to this embodiment. Figure 9 is a flowchart illustrating a method for manufacturing a packaging substrate according to another embodiment, with cross-section shown. Implementation

[0054] The following detailed description is provided to aid the reader in fully understanding the methods, apparatus, and / or systems described herein. However, various changes, modifications, and equivalents of the methods, apparatus, and / or systems described herein will become apparent after understanding the disclosure of this application. For example, the order of operations described herein is merely illustrative and is not limited to those set forth herein. The order of operations may be changed, as will become apparent after understanding the disclosure of this application, except for operations that must occur in a specific order. Furthermore, after understanding the disclosure of this application, descriptions of known features may be omitted to increase clarity and conciseness. However, the omission of features and their descriptions is not intended to acknowledge their common sense.

[0055] The features described herein may be embodied in different forms and should not be construed as limited to the examples described herein. Rather, the examples described herein are provided merely to illustrate some of the many possible ways in which the methods, apparatus, and / or systems described herein will become apparent upon understanding the disclosure of this application.

[0056] Although terms such as “first,” “second,” and “third” may be used herein to describe various components, parts, regions, layers, or sections, these components, parts, regions, layers, or sections should not be limited by these terms. Rather, these terms are used only to distinguish one component, part, region, layer, or section from another. Therefore, without departing from the teachings of the examples described herein, the first component, part, region, layer, or section mentioned in the examples may also be referred to as the second component, part, region, layer, or section.

[0057] Throughout the specification, when a device such as a layer, region, or substrate is described as "on another device," "connected to another device," or "coupled to another device," it can be directly "on another device," "connected to another device," or "coupled to another device," or there may be one or more other devices between them. Conversely, when a device is described as "directly on another device," "directly connected to another device," or "directly coupled to another device," there cannot be other devices inserted between them. Similarly, expressions such as "between," "immediately between," "adjacent to," and "closely adjacent" can also be interpreted as described above.

[0058] The terminology used herein is for the purpose of describing particular examples only and is not intended to limit this disclosure. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. As used herein, the term “and / or” includes any one of the associated listed items and any combination of any two or more items. As used herein, the terms “comprising,” “including,” and “having” specify the presence of the stated features, digits, operations, devices, components, and / or combinations thereof, but do not exclude the presence or addition of one or more other features, digits, operations, devices, components, and / or combinations thereof. The use of the term “may” in relation to examples or embodiments (e.g., regarding what an example or embodiment may include or implement) means that there exists at least one example or embodiment that includes or implements such a feature, and that all examples are not limited thereto.

[0059] In this application, "B is placed on A" means that B is placed in direct contact with A or is placed on top of A with another layer or structure inserted therebetween, and therefore should not be construed as limited to B being placed in direct contact with A.

[0060] Unless otherwise defined, all terms used herein, including technical and scientific terms, shall have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains, upon understanding this disclosure and after understanding this disclosure. Terms such as those defined in common dictionaries shall be interpreted as having the same meaning as they have in the context of the relevant art and this disclosure, and shall not be interpreted in an idealized or overly formal manner unless expressly defined herein.

[0061] In one or more examples, the description of “A and / or B” means “A, B, or A and B”.

[0062] In one or more examples, terms such as “first,” “second,” “A,” or “B” are used to distinguish the same terms.

[0063] In one or more examples, unless otherwise stated, the expression singular is interpreted as including the meaning of singular or plural as interpreted in the context.

[0064] In one or more of the examples above, the coefficient of thermal expansion recorded without a specific temperature refers to the coefficient of thermal expansion at room temperature or ambient temperature.

[0065] Figure 1 is a conceptual diagram illustrating the cross-sectional structure of the packaging substrate according to this embodiment. Figures 2A and 2B are conceptual diagrams illustrating the cross-sectional structures of the packaging substrate according to different embodiments, respectively. Figure 3A is a conceptual diagram illustrating the process of generating the cross-sectional structure of the packaging substrate of Figure 2A. Figure 3B is a conceptual diagram illustrating the process of generating the cross-sectional structure of Figure 2B.

[0066] To achieve the above objectives, the semiconductor device 100 according to this embodiment includes: a semiconductor device section 30, wherein one or more semiconductor devices (first semiconductor device 32, second semiconductor device 34, and third semiconductor device 36) are located in the semiconductor device section; a packaging substrate 20 electrically connected to the semiconductor devices; and a main board 10 electrically connected to the packaging substrate 20, which transmits external electrical signals to the semiconductor devices (first semiconductor device 32, second semiconductor device 34, and third semiconductor device 36) and connects the semiconductor devices to the external electrical signals.

[0067] According to one embodiment, the packaging substrate 20 includes: a core layer 22; an upper layer 26 located on one side of the core layer 22; and a cavity portion 28, wherein a cavity device 40 may be located in the cavity portion 28. In FIG1, the cavity device 40 is exemplified as being arranged at the lower end of the packaging substrate 20, but is not limited to being arranged at the lower end.

[0068] The aforementioned semiconductor device section 30 refers to a device mounted on a semiconductor device and attached to the aforementioned packaging substrate 20 via connecting electrodes or the like. Specifically, as the aforementioned semiconductor device section 30, for example, computing devices such as CPUs and GPUs (first semiconductor device: 32, second semiconductor device: 34), memory devices such as memory chips (third semiconductor device: 36), etc., can be used without limitation.

[0069] The aforementioned motherboard 10 can be a motherboard for printed circuit boards, printed wiring boards, etc.

[0070] The aforementioned packaging substrate 20 may optionally further include a lower layer 29 located below the core layer.

[0071] The core layer 22 may include: a glass substrate 21, including a first region 221 and a second region 222, wherein the first region 221 has a first thickness 211, the second region 222 is adjacent to the first region 221 and has a second thickness 212, wherein the second thickness 212 is thinner than the first thickness or is 0; a plurality of core vias 23, which penetrate the glass substrate 21 in the thickness direction; and a core distribution layer 24, which is located on the surface of the glass substrate 21 or the core vias 23, and electrically connects the first surface 213 of the glass substrate 21 and the second surface 214 facing the first surface through the core vias 23.

[0072] The second region 222 of the core layer 22 can function as a cavity structure.

[0073] In the same region, the glass substrate 21 has a first surface 213 and a second surface 214 facing each other. The two surfaces are generally parallel to each other, so that the glass substrate 21 has a certain thickness as a whole.

[0074] The internal space 281 formed by the thickness difference between the first region 221 and the second region 222 serves to accommodate part or all of the cavity device 40. Figures 2B and 3B illustrate a full cavity where the glass substrate in the second region has been removed. However, this embodiment is not limited to this; a semi-cavity is also applicable. Examples of semi-cavities are shown in Figures 2A and 3A.

[0075] The glass substrate 21 may include through-holes 23 penetrating the first surface 213 and the second surface 214. When the second thickness is not zero, the through-holes 23 may be formed in both the first region 221 and the second region 222, and may be formed with the desired spacing and pattern. Alternatively, when the second thickness is zero, the through-holes 23 may be formed in the first region 221, and may be formed with the desired spacing and pattern.

[0076] Traditionally, silicon substrates and organic substrates have been used as packaging substrates for semiconductor devices. However, with silicon substrates, parasitic devices can arise when used in high-speed circuits due to the characteristics of semiconductors, resulting in relatively high power losses. Furthermore, organic substrates require large areas to form more complex patterns, which is not in line with the trend towards manufacturing ultra-miniaturized electronic devices. To form complex patterns within a predetermined size, pattern miniaturization is practically necessary, but this is limited by the properties of materials such as polymers used in organic substrates.

[0077] In this embodiment, as a method to solve these problems, a glass substrate 21 is used as a support for the core layer 22. In addition, along with the glass substrate 21, a through-hole 23 formed through the glass substrate 21 is also used, thereby providing a packaging substrate 20 with shorter current length, smaller size, faster response and less loss characteristics.

[0078] The glass substrate 21 described above is preferably a glass substrate suitable for semiconductors, such as a borosilicate glass substrate, an alkali-free glass substrate, etc., but the present invention is not limited thereto.

[0079] The via 23 penetrates the glass substrate 21. The via 23 can be formed by removing a predetermined area of ​​the glass substrate 21, specifically by etching the plate-shaped glass using physical and / or chemical methods.

[0080] Specifically, when forming the aforementioned through-hole 23, methods such as chemical etching or laser etching can be used after forming defects (flaws) on the surface of the glass substrate by means of laser or other methods, but the present invention is not limited thereto.

[0081] Based on the unit area (1cm × 1cm) of the glass substrate 21, the number of through-holes 23 can be 100 to 3,000, 100 to 2,500, or 225 to 1,024. When the above spacing conditions are met, it is more conducive to the formation of conductive layers, etc., and the performance of the packaging substrate can be improved.

[0082] The aforementioned core distribution layer 24 includes a core distribution pattern 241 and a core insulating layer 223. The core distribution pattern 241 is a conductive layer that electrically connects the first and second surfaces of the glass substrate through core vias. The core insulating layer 223 surrounds the core distribution pattern. A conductive layer is formed inside the core layer 22 through core vias to serve as an electrical path across the glass substrate 21, thereby connecting the upper and lower parts of the glass substrate over a relatively short distance, resulting in faster electrical signal transmission and lower loss characteristics. For example, the conductive layer can be a copper plating layer, but the invention is not limited thereto.

[0083] The aforementioned cavity 28 is generally circular, triangular, quadrilateral, hexagonal, octagonal, or cross-shaped, and its shape is not limited.

[0084] The cavity device 40 can be cylindrical, cuboid, or polygonal in shape.

[0085] The cavity portion 28 may include a cavity distribution pattern, which serves as a conductive layer connecting the cavity device 40 and the core distribution layer 24, and an insulating layer surrounding the cavity distribution pattern.

[0086] On the other hand, according to another embodiment, the cavity portion can be implemented in the form of penetrating the first surface 213 and the second surface 214 of the glass substrate 21. In this case, the cavity portion can be formed according to a process similar to the formation process of the through-hole 23, and the area and shape penetrating the glass substrate 21 can be different from the area and shape of the through-hole 23.

[0087] In this embodiment, after arranging the cavity devices 40 in the cavity portion, an insulating layer can be generated. That is, an insulating layer can also be generated in the cavity portion through the process of generating the core insulating layer 223 described above.

[0088] The core distribution pattern 241 can be formed into a pattern that can be electrically connected to the cavity device 40.

[0089] The cavity device 40 mentioned above may include active devices such as transistors or power transmission devices such as multilayer ceramic capacitors (MLCCs), i.e., passive devices.

[0090] When the cavity device 40 described above is adapted to convert the electrical signal between the motherboard and the semiconductor device into an appropriate level, such as a transistor, the transistor is adapted to the path of the package substrate 20. Therefore, a semiconductor device 100 with higher efficiency and higher speed can be provided.

[0091] Furthermore, power transmission devices such as multilayer ceramic capacitors (MLCCs) play a crucial role in the performance of semiconductor devices. Typically, over 200 types of passive power transmission devices are used in semiconductor devices, and their performance during power transmission is also affected by the characteristics of the conductive layer surrounding the device. In one embodiment, non-circular vias can be used where a low-resistance conductive layer is required, such as in the aforementioned power transmission devices, instead of circular vias.

[0092] On the other hand, the aforementioned cavity device 40 can be in the form of a single passive device such as a capacitor being inserted, or it can be formed in the form of being embedded between insulating layers (cavity device insulating layers) such that a device group including multiple passive devices is exposed to electrodes and then inserted into the cavity device. In the latter case, the workability of manufacturing the packaging substrate can be improved more smoothly, and the insulating layer can be more advantageously and reliably disposed in the space between complex devices.

[0093] The glass substrate 21 serves as an intermediary, connecting the semiconductor device section 30 and the main board 10 to the upper and lower parts respectively. The vias 23 serve as paths for transmitting their electrical signals, thus achieving smooth signal transmission. To distinguish them from the vias in the second region 222 described below, the vias arranged in the first region 221 are referred to as first region vias.

[0094] The upper layer 26 is located on the first surface 213.

[0095] The upper layer 26 may include an upper partition layer 25 and an upper connection layer 27 located on the upper partition layer 25. The topmost part of the upper layer 26 may be protected by a cover layer 60 with an opening that allows the connection electrodes of the semiconductor device to directly contact each other.

[0096] The aforementioned upper distribution layer 25 may include: an upper insulating layer 253 located on the aforementioned first surface; and an upper distribution pattern 251, which is a conductive layer having a predetermined pattern and at least a portion thereof electrically connected to the aforementioned core distribution layer 24, the upper distribution pattern 251 being embedded in the aforementioned upper insulating layer 253. The upper distribution layers 25 arranged above and below each other can be connected to each other through blind vias 252.

[0097] As the aforementioned upper insulating layer 253, it can be used as an insulating layer suitable for semiconductor devices or packaging substrates. For example, epoxy resin including fillers can be used, but the present invention is not limited thereto.

[0098] The aforementioned insulating layer can be formed by forming an insulating coating and then curing it. Alternatively, the insulating layer can be formed by laminating an insulating film, which is in an uncured or semi-cured state, onto the core layer 22 and then curing it. In this case, if a depressurized lamination method is used, the insulating material is embedded in the space inside the core through-hole 23, thereby enabling efficient processing.

[0099] According to one embodiment, even when multiple insulating layers are stacked, it may be substantially difficult to distinguish between the insulating layers, which are collectively referred to as the upper insulating layer. Furthermore, the core insulating layer 223 and the upper insulating layer 253 may be made of the same insulating material, in which case their boundaries may be substantially indistinguishable. Alternatively, according to another embodiment, the boundaries of the insulating layers can be formed by setting different pressures and temperatures for curing the multiple insulating layers.

[0100] The aforementioned upper distribution pattern 251 refers to a conductive layer located within the upper insulating layer 253 in a predetermined shape, which can be formed, for example, by a build-up layer method. Specifically, after forming the insulating layer, unnecessary portions of the insulating layer are removed, and then a conductive layer is formed by a method such as copper plating. Unnecessary portions of the conductive layer are selectively removed, and then an insulating layer is formed again on the conductive layer. Unnecessary portions are removed again, and then a conductive layer is formed by a method such as plating. By repeating the above process, an upper distribution pattern 251 with a conductive layer formed in the vertical or horizontal direction in the desired pattern can be formed.

[0101] The aforementioned upper parting pattern 251 is located between the core layer 22 and the semiconductor device section 30, and is therefore formed to include fine patterns in at least a portion thereof, so as to facilitate the smooth transmission of electrical signals between the core layer 22 and the semiconductor device section 30 and to adequately accommodate the required complex patterns. Here, a fine pattern refers to a pattern with a width and spacing of less than 4 μm, or a pattern with a width and spacing of less than 3.5 μm, or a pattern with a width and spacing of less than 3 μm, or a pattern with a width and spacing of less than 2.5 μm, or a pattern with a width and spacing of 2.3 μm or less. The aforementioned width and spacing can be 1 μm or more (the description of fine patterns is the same below).

[0102] The aforementioned upper connection layer 27 includes: an upper connection pattern 272, at least a portion of which is electrically connected to the aforementioned upper distribution pattern 251 and located in the aforementioned upper insulating layer 253; and an upper connection electrode 271, which electrically connects the aforementioned semiconductor device portion 30 and the aforementioned upper connection pattern 272.

[0103] The aforementioned upper connection pattern 272 may be located on one side of the upper insulating layer 253, or it may be embedded in such a way that at least a portion of it is exposed on the upper insulating layer. For example, when the upper connection pattern is located on one side of the upper insulating layer, the upper insulating layer can be formed by methods such as plating. When the upper connection pattern is embedded in such a way that a portion of it is exposed on the upper insulating layer, after forming a copper plating layer, a portion of the insulating layer or conductive layer can be removed by methods such as surface polishing or surface etching.

[0104] Similar to the upper distribution pattern 251 described above, at least a portion of the upper connection pattern 272 may include fine patterns. The upper connection pattern 272, including fine patterns, allows for greater electrical connection of devices even in a narrow area, thereby facilitating smoother electrical signal connections between devices or with the outside, and enabling more integrated packaging.

[0105] The aforementioned upper connecting electrode 271 can be directly connected to the aforementioned semiconductor device section 30 via terminals or the like, or can be connected via a device connecting section 51 such as a solder ball.

[0106] In the case of a semi-cavity substrate, the cavity portion 28 may include a cavity distribution layer 282 and an internal space 281. The cavity distribution layer 282 is located above and / or below the second region 222 and is electrically connected to the core distribution pattern 241. The cavity device 40 is located in the internal space 281. The cavity distribution layer 282 may be formed through a core through-hole 23 in the second region 222 (see Figure 3A).

[0107] Specifically, compared to the first region 221, the glass substrate 21 of the second region 222 is thinner, and the cavity device 40 can be located in the internal space 281 formed by the thickness difference. In addition, the core via 23 and core distribution layer 24 formed on the glass substrate 21 serve as electrical connection structures connecting the cavity device 40 and external devices.

[0108] Alternatively, a cavity portion can be formed that penetrates the first region 221 instead of the second region 222, that is, it penetrates the first surface 213 and the second surface 214 of the glass substrate 21, and the cavity device 40 can be arranged in the cavity portion.

[0109] The aforementioned packaging substrate 20 is also connected to the motherboard 10. The terminals of the motherboard 10 can be directly connected to the core distribution pattern 241 located on at least a portion of the second surface 214 of the core layer 22, and the motherboard 10 can be electrically connected via a board connection portion 52, such as solder balls. Furthermore, the core distribution pattern 241 connected to the motherboard 10 can be connected to the motherboard 10 via a lower layer (not shown) located at the bottom of the core layer 22. The device connection portion 51 and the board connection portion 52 are collectively referred to as connection portion 50.

[0110] According to one example, apart from the glass substrate 21 described above, the packaging substrate 20 located between the semiconductor device section 30 and the mainboard 10 may not actually require an additional substrate.

[0111] Conventionally, interpolators and organic substrates are stacked together and used for the connection between the device and the motherboard. This multi-level structure is understood to be adopted for at least two reasons: firstly, directly attaching the device's fine patterns to the motherboard presents dimensional problems; and secondly, differences in thermal expansion coefficients can lead to wiring damage during bonding or during the operation of the semiconductor device. In this embodiment, the aforementioned problems are solved by using a glass substrate with a thermal expansion coefficient similar to that of the semiconductor device, and forming fine patterns of sufficient scale for device mounting on the first surface and upper layer of the glass substrate.

[0112] The following describes a method for manufacturing a packaging substrate according to an embodiment of the present invention.

[0113] Figures 4 and 5 are cross-sectional flowcharts illustrating the manufacturing process of the packaging substrate according to this embodiment.

[0114] First, as shown in part (a) of FIG4, a glass substrate 21a having a flat first surface and a second surface is prepared, and a defect 21b (groove) is formed at a predetermined position on the glass surface to form a through-hole. The glass substrate described above can be a glass substrate suitable for electronic devices, for example, an alkali-free glass core, but the present invention is not limited thereto. As a commercially available product, products manufactured by companies such as Corning Incorporated, Schott AG, and AGC can be used. The defect (groove) can be formed by methods such as mechanical etching or laser irradiation.

[0115] As shown in part (b) of Figure 4, an etching step is performed to form a through-hole 23 in a glass substrate 21a with a defect 21b (groove) by means of a physical or chemical etching process. During the etching process, the surface of the glass substrate 21a can be etched simultaneously with the formation of the through-hole in the defective portion of the glass substrate. In order to prevent etching of the glass surface, a masking film or the like can be applied. However, considering the trouble of applying and removing the masking film, the defective glass substrate itself can be etched. In this case, the thickness of the glass substrate with the through-hole can be slightly thinner than the original thickness of the glass substrate.

[0116] Then, as shown in portions (c) and (d) of FIG4, the core layer fabrication step can be performed by forming a conductive layer 21d on the glass substrate. Typically, the conductive layer can be a metal layer including copper, but the present invention is not limited thereto.

[0117] The surfaces of glass (including the surface of the glass substrate and the surface of the through-hole) and copper metal have different properties, resulting in poor adhesion. In this embodiment, both dry and wet methods are used to improve the adhesion between the glass surface and the metal.

[0118] The dry method is a sputtering method, which involves forming a seed layer 21c on the glass surface and the inner diameter of the core via by sputtering metal. When forming the seed layer, dissimilar metals such as titanium, chromium, and nickel can be sputtered together with copper. In this case, it is believed that the adhesion between the glass and the metal is improved through the anchoring effect of the interaction between the glass surface morphology and the metal particles.

[0119] The wet method is a method for primer treatment, which forms the primer layer 21c by pretreatment with a compound having functional groups such as amines. Depending on the desired level of adhesion, after pretreatment with a silane coupling agent, primer treatment can be performed using a compound or particles having amine functional groups. As mentioned above, the support substrate of this embodiment needs to have high performance sufficient to form fine patterns, and this state needs to be maintained even after primer treatment. Therefore, when such primer contains nanoparticles, nanoparticles with an average diameter of 150 nm or less are preferably used; for example, particles with amine groups are preferably used as nanoparticles. For example, the above-mentioned primer layer can be formed by applying an adhesion improver manufactured by MEC's ​​CZ series, etc.

[0120] In the aforementioned seed layer / primer layer 21c, the conductive layer can be selectively formed into a metal layer with or without removing portions where a conductive layer is not required. Furthermore, the seed layer / primer layer 21c selectively processes portions where a conductive layer needs to be formed or portions where a conductive layer does not need to be formed into either an activated or deactivated state for subsequent processes. For example, the activation or deactivation process can utilize light irradiation treatment such as laser treatment with a predetermined wavelength or chemical treatment. While copper plating methods suitable for manufacturing semiconductor devices can be used when forming the metal layer, the present invention is not limited to these methods.

[0121] As shown in part (e) of Figure 4, when a portion of the core distribution layer is not required, it can be removed, or after partial removal or non-activation treatment of the seed layer, metal plating can be performed to form a conductive layer in a predetermined pattern, thereby forming the etched layer 21e of the core distribution layer.

[0122] Figure 5 illustrates the preparation steps for forming an insulating layer and an upper distribution pattern according to one embodiment.

[0123] As shown in part (a) of Figure 5, after forming the core distribution layer as the conductive layer described above, the core via can undergo an insulating layer formation step of filling the empty spaces with an insulating layer. At this time, the applicable insulating layer can be an insulating layer prepared in the form of a thin film, for example, it can be applied by a method such as depressurized lamination of a thin film insulating layer. When depressurized lamination is performed in this manner, the insulating layer is fully embedded in the empty spaces inside the core via, thereby forming a core insulating layer without gaps.

[0124] Figure 5, from (b) to (e), illustrates the steps involved in preparing the upper layer.

[0125] This step involves forming an upper insulating layer and an upper distribution pattern on the core layer. The upper insulating layer can be formed by coating a resin composition for forming insulating layer 23a or by stacking insulating films; stacking insulating films is preferred. The insulating films can be stacked by laminating and curing them. In this case, if a depressurized lamination method is used, the insulating resin can be sufficiently embedded in layers, such as those without conductive layers, inside the core through-holes. At least a portion of the upper insulating layer is also in direct contact with the glass substrate, thus a layer with sufficient adhesion is suitable. Specifically, the glass substrate and the upper insulating layer preferably have an adhesion test value of 4B or higher according to ASTM D3359.

[0126] The upper parting pattern can be formed by repeatedly forming the above-mentioned insulating layer 23a, forming the conductive layer 23c with a predetermined pattern and etching unnecessary parts to form the etched layer 23d of the conductive layer. In the case of conductive layers formed adjacent to the insulating layer, the blind holes 23b are formed by performing a plating process after forming the insulating layer. Blind holes can be formed by dry etching methods such as laser etching and plasma etching, or by wet etching methods using a mask layer and an etching solution.

[0127] Afterwards, although not shown in the figure, an upper connecting layer and a covering layer can be formed.

[0128] The upper connection pattern and upper connection electrode can also be formed through a process similar to that used to form the upper partial coupling layer. Specifically, it can be formed by an etched layer forming an insulating layer on the insulating layer 23e, followed by a conductive layer, and then another etched layer forming a conductive layer. However, it can also be formed by selectively forming the conductive layer without etching. An opening (not shown in the figure) is formed in the cover layer at a position corresponding to the upper connection electrode, and it can be configured to expose the upper connection electrode and allow it to be directly connected to a device connection portion or a device terminal.

[0129] Once the upper layer is formed, the lower layer can be fabricated by forming the lower connecting layer and the capping layer. The lower subdivision layer and / or the lower connecting layer can be formed in a manner similar to the upper connecting layer and capping layer formation steps described above. Optionally, the capping layer can also be formed.

[0130] Electronic devices primarily utilize methods that form insulating layers by laminating insulating films (e.g., Ajinomoto composite film (ABF)). In this process, undulation may occur. In particular, cavities where embedded devices are arranged may experience severe undulation due to gaps between devices and / or gaps between the cavity sides and the devices. Due to severe undulation, leakage current may be generated within the cavity. This leakage current can be fatal to active devices.

[0131] When electronic devices are placed in cavities, especially when multiple electronic devices are placed in cavities, phenomena such as unintentional reduction in the accuracy of the electronic device placement or unintentional bending of the glass core during manufacturing may occur, which may lead to defects in the packaging substrate. For example, when devices are arranged adjacent to each other and / or devices to electrodes, short circuits may occur due to the characteristics of devices with exposed electrodes coming into contact with each other, resulting in defects in the packaging substrate.

[0132] Therefore, this embodiment proposes an invention that can substantially prevent fluctuations in the cavity of embedded electronic devices. This achieves the goals of preventing leakage current in the packaging substrate and reducing defects in the packaging substrate. This embodiment proposes performing the process of forming the insulating layer not just once, but multiple times, or utilizing a cavity module that modularizes two or more electronic devices.

[0133] Figure 6 shows an example of the cross-sectional structure of the core layer of the packaging substrate produced according to this embodiment. Figure 6 is a diagram showing a conceptually simplified packaging substrate for explaining the core layer produced according to this embodiment, and the description can be applied with reference to Figures 1 to 3.

[0134] The packaging substrate may have a core layer 22 comprising a glass core 21 having a first surface and a second surface facing each other, and a core through-hole penetrating the glass core 21. Electrodes 63 may be formed on the surface of the glass core 21. Alternatively, for example, as shown in FIG6, the cavity portion is formed to penetrate both the first surface and the second surface of the glass core 21, and electronic devices 40 are arranged inside the cavity portion.

[0135] As described above, the electronic device 40 may include both passive and active devices. The cavity portion can be formed together with the aforementioned through-hole by etching or the like. Alternatively, the cavity portion can be formed independently after the formation of the through-hole or before the formation of the through-hole.

[0136] The entire surface of an electronic device 40 disposed inside a cavity, except for one surface, can be surrounded by a first insulating layer 61. For example, an electronic device 40 is disposed in a cavity, and is arranged such that i) the entire surface of the electronic device 40 except for one surface, or ii) the entire surface of the electronic device 40 is covered with a coating material to form a first insulating layer. A module containing electronic devices and a first insulating layer can be referred to as a cavity module. That is, a cavity module can include i) a plurality of electronic devices arranged in a row and ii) a first insulating layer surrounding each of the aforementioned electronic devices.

[0137] For example, when the electronic device 40 has a hexahedral shape, the five surfaces of the electronic device 40, excluding one surface (e.g., the bottom surface), can be surrounded by the first insulating layer 61. Alternatively, the edge of the upper surface of the electronic device 40 can be surrounded by the first insulating layer 61. That is, the first insulating layer 61 can be formed at the edge of the upper surface of the electronic device 40.

[0138] For example, when the electronic device 40 has a cylindrical shape, the sides and / or top of the electronic device 40, excluding the bottom surface, can be surrounded by the first insulating layer 61. Alternatively, the edge of the upper surface of the electronic device 40 can be surrounded by the first insulating layer 61. That is, the first insulating layer 61 can be formed at the edge of the upper surface of the electronic device 40.

[0139] For example, one or more connection electrodes can be formed in the bottom direction of the electronic device 40. Alternatively, for example, the five surfaces of the electronic device 40 other than the top surface can be surrounded by the first insulating layer 61. Alternatively, for example, the edge of the bottom surface of the electronic device 40 can be surrounded by the first insulating layer 61. That is, the first insulating layer 61 can be formed at the edge of the bottom surface of the electronic device 40. In this case, for example, one or more connection electrodes can be formed in the top direction of the electronic device 40.

[0140] The first insulating layer 61 is formed on the entire surface of the electronic device 40 except for one surface, thereby preventing short circuits caused by contact between side-by-side electronic devices. In addition, the first insulating layer 61 formed on the entire surface of the electronic device 40 except for one surface or on the entire surface of the electronic device 40 can prevent unintentional short circuits that may occur during the manufacturing process of forming a conductive layer on the side of the cavity portion 28.

[0141] Additionally, as shown in FIG. 6, the core layer 22 may include a second insulating layer 62 stacked on the first surface and the second surface. The portion of the cavity 28 shown in FIG. 6, excluding the electronic device 40 and the first insulating layer 61, may be filled with the second insulating layer 62. That is, after the cavity module is arranged in the cavity 28, there may be remaining space inside the cavity, where the second insulating layer 62 can be formed. For example, as shown in FIG. 6, the core layer 22 may include a second insulating layer 62 embedded in the remaining portion of the cavity 28 excluding the cavity module. For example, the second insulating layer 62 may be stacked and solidified on the upper part (e.g., the first surface) and the lower part (e.g., the second surface) of the glass core 21, thereby creating the second insulating layer.

[0142] The aforementioned electronic device 40 can be connected to the connecting electrode.

[0143] The connecting electrodes can be arranged on the exposed surface of the electronic device 40 where the first insulating layer 61 is not arranged.

[0144] The connecting electrode can be arranged to penetrate the first insulating layer 61 of the aforementioned electronic device 40. The connecting electrode can be in the form of a blind hole.

[0145] The first insulating layer may also have a through-hole (not shown in the figure) extending through it. Part or all of the through-hole may be filled with electrode material.

[0146] One end of the aforementioned through-hole in the first insulating layer can contact the aforementioned electronic device 40, and the other end of the aforementioned through-hole in the first insulating layer can be exposed to the outside of the cavity portion 28.

[0147] The aforementioned first insulating layer through-hole can be arranged to penetrate the aforementioned cavity portion 28 vertically without directly contacting the aforementioned electronic device 40.

[0148] The electrode material described above can be a conductive material, such as a conductive metal. For example, copper, copper alloys, silver, etc., can be used, but the present invention is not limited thereto.

[0149] The material (coating material) of the first insulating layer 61 can be the same as the material of the second insulating layer 62, or a different material can be used. In the latter case, materials with different dielectric constants can be used.

[0150] For example, the first insulating layer 61 and the second insulating layer 62 may have different dielectric constants. For example, the dielectric constant of the first insulating layer 61 may be equal to or lower than the dielectric constant of the second insulating layer 62. In this case, it has the advantage that sufficient insulation effect can be expected for each electronic device while substantially suppressing fluctuations in the cavity.

[0151] The first insulating layer 61 and the second insulating layer 62 may each include insulating materials.

[0152] For example, the above-mentioned insulating material may be a polymer resin, a mixture of polymer resin and filler (inorganic particles, organic particles, organic-inorganic composite particles, etc.), an inorganic deposition layer, etc.

[0153] For example, the polymer resin described above can be acrylic resin, epoxy resin, or a modified resin thereof, and can be a material suitable for use in electronic devices for purposes such as molding. For example, liquid crystal polymer (LCP) can be used.

[0154] For example, the above-mentioned mixed material can be a mixture of acrylic resin and filler, a mixture of acrylic resin and epoxy resin and filler, or a mixture of epoxy resin and filler, etc. The filler can be inorganic particles, for example, silicon dioxide particles. As a commercial product, it can be applied to Ajinomoto composite film (ABF), epoxy molding compound (EMC), and modified polyimide (MPI), etc., but the present invention is not limited thereto.

[0155] For example, the inorganic deposition layer described above may be a silicon oxide deposition layer or a silicon nitride deposition layer, etc., but the present invention is not limited thereto.

[0156] The first insulating layer 61 and the second insulating layer 62 can be made of materials with the same or different coefficients of thermal expansion (CTE). Preferably, materials with a small difference between the CTE of the first insulating layer 61 and the CTE of the second insulating layer 62 can be used.

[0157] The difference in the coefficients of thermal expansion between the materials of the first insulating layer and the second insulating layer can be less than 2 ppm / ℃, less than 1.5 ppm / ℃, less than 1 ppm / ℃, or less than 0.5 ppm / ℃. The difference in the coefficients of thermal expansion can be greater than 0 ppm / ℃, greater than 0.1 ppm / ℃, or greater than 0.2 ppm / ℃.

[0158] The coefficient of thermal expansion of the first insulating layer 61 can be 8 ppm / ℃ or higher, 10 ppm / ℃ or higher, 12 ppm / ℃ or higher, or 14 ppm / ℃ or higher. The coefficient of thermal expansion can be 20 ppm / ℃ or lower, 18 ppm / ℃ or lower, or 17 ppm / ℃ or lower.

[0159] The coefficient of thermal expansion of the second insulating layer 62 can be 8 ppm / ℃ or higher, 10 ppm / ℃ or higher, or 12 ppm / ℃ or higher. The coefficient of thermal expansion can be 20 ppm / ℃ or lower, 18 ppm / ℃ or lower, 16 ppm / ℃ or lower, or 14 ppm / ℃ or lower.

[0160] The first insulating layer 61 and the second insulating layer 62 described above can be made of materials with different dielectric constants. Preferably, the materials of the insulating layers can be selected such that the dielectric constant of the first insulating layer 61 is lower than that of the second insulating layer 62.

[0161] The first insulating layer 61 and the second insulating layer 62 are preferably made of materials with different relative permittivity Dk at a high frequency of 5.8 GHz. For example, the difference between Dk of the first insulating layer 61 and Dk of the second insulating layer 62 can be 0.1 or more. The difference in Dk can be 0.1 or more, 0.13 or more, 0.16 or more, or 0.2 or more. The difference in Dk can be less than 1, less than 0.8, less than 0.6, less than 0.5, less than 0.4, less than 0.3, or less than 0.25.

[0162] The Dk of the first insulating layer 61 can be 2.3 or higher, 2.5 or higher, 2.7 or higher, or 2.9 or higher. The Dk can be 3.4 or lower, 3.2 or lower, or 3.1 or lower.

[0163] The Dk of the second insulating layer 62 can be 3.0 or higher, 3.1 or higher, or 3.2 or higher. The Dk can be 3.6 or lower, 3.5 or lower, or 3.4 or lower.

[0164] The Dk of the first insulating layer 61 can be smaller than the Dk of the second insulating layer 62.

[0165] The first insulating layer 61 and the second insulating layer 62 can be made of materials with the same or different dielectric loss factors Df. For example, materials where the difference between the Df of the first insulating layer 61 and the Df of the second insulating layer 62 is 0.0001 or more can be used. The difference in Df can be 0.0001 or more, 0.0005 or more, or 0.001 or more. The difference in Df can be less than 0.02.

[0166] The Df of the first insulating layer 61 can be less than 0.004, less than 0.0038, or less than 0.0036. The Df can be greater than 0.001, greater than 0.0015, greater than 0.0018, or greater than 0.002.

[0167] The Df of the second insulating layer 62 can be less than 0.005, less than 0.0048, or less than 0.0046. The Df can be greater than 0.003, greater than 0.0032, or greater than 0.0034.

[0168] The Df of the first insulating layer 61 can be smaller than the Df of the second insulating layer 62.

[0169] For example, the second insulating layer 62 can be made of ABF, and the first insulating layer 61 can be made of LCP. For example, the second insulating layer 62 can be made of EMC, and the first insulating layer 61 can be made of LCP. For example, ABP with different dielectric constants can be applied to the second insulating layer 62 and the first insulating layer 61.

[0170] For example, regarding the formation of the first insulating layer 61, as an example, the insulating layer can be formed on the surface of the electronic device 40 by using a varnish-type method, a selective lamination method, a deposition method, or the like.

[0171] For the second insulating layer 62, the commonly used method for forming an insulating layer in the cavity of the packaging substrate can be applied, or the method used for forming the first insulating layer 61 can be applied.

[0172] Figure 7 shows an example of the cross-sectional structure of the core layer of the packaging substrate produced according to this embodiment. Figure 7 is a diagram showing a conceptually simplified packaging substrate for explaining the core layer produced according to this embodiment, and the description can be applied with reference to Figures 1 to 3.

[0173] The packaging substrate may include a core layer 22, which includes a glass core 21 having a first surface and a second surface facing each other, and a through-hole penetrating the glass core 21. Electrodes 63 may be formed on the surface of the glass core 21. Cavities are formed such that they all penetrate the first surface and the second surface of the glass core 21, and cavity modules are disposed inside the cavity portions. That is, cavity modules may be disposed in the cavity portions.

[0174] As described above, the electronic device 40 may include a passive device, an active device, or both. The cavity portion may be formed simultaneously with the aforementioned through-hole by etching or the like, or it may be formed independently after or before the formation of the through-hole.

[0175] Furthermore, the cavity module arranged inside the cavity portion 28 according to FIG. 7 may include: i) a plurality of electronic devices arranged in a row; ii) a first insulating layer 61 surrounding each of the aforementioned electronic devices 40; and iii) a third insulating layer 71 containing molding material and arranged such that the molding material surrounds the aforementioned electronic devices. The entire surface of the electronic device 40, except for one surface, or the entire surface of the electronic device 40, may be surrounded by the first insulating layer 61. That is, for example, electronic devices 40 may be arranged in the cavity portion according to FIG. 7, and the first insulating layer may be formed on the entire surface of the electronic device 40, except for one surface, or the entire surface of the electronic device 40, and a third insulating layer 71 comprising molding material and surrounding the electronic device on which the first insulating layer is formed may be formed.

[0176] The electronic device, the first insulating layer surrounding the electronic device, and the third insulating layer surrounding the electronic device on which the first insulating layer is formed are collectively referred to as a cavity module. That is, the cavity module may include: i) a plurality of electronic devices arranged in a row; ii) a first insulating layer surrounding each of the electronic devices; and iii) a third insulating layer 71 comprising a molding material and arranged such that the molding material surrounds the electronic device.

[0177] The aforementioned third insulating layer fixes the relative positions of the electronic devices surrounded by the aforementioned first insulating layer in an arranged state, and modularizes them to form a cavity module.

[0178] Since the descriptions of electronic components 40, the first insulating layer 61, the second insulating layer 62, etc., are repeated above, detailed descriptions are omitted. The molding material of the third insulating layer 71 will be described later.

[0179] As shown in Figure 7, the remaining portion of the cavity 28, excluding the aforementioned electronic device 40, the first insulating layer 61, and the third insulating layer 71, can be filled with the second insulating layer 62. That is, after the cavity module is arranged in the cavity 28, there can be remaining space inside the cavity, where the second insulating layer 62 can be formed as an insulating material. For example, as shown in Figure 7, the core layer 22 can form the second insulating layer 62 by embedding insulating material in the remaining portion of the cavity 28 excluding the aforementioned cavity module. For example, the second insulating layer 62 can be stacked and cured on the upper part (e.g., the first surface) and the lower part (e.g., the second surface) of the glass core 21, thereby creating the second insulating layer.

[0180] When the cavity module includes two or more electronic devices, the spacing between adjacent electronic devices 40 can be 30 μm or more, 50 μm or more, or 80 μm or more. Furthermore, the spacing can be less than 300 μm, less than 250 μm, or less than 200 μm. By maintaining this spacing, interference between electronic devices within the cavity can be minimized, and space utilization can be improved.

[0181] The thickness of the aforementioned cavity module can be 335 μm or more, 370 μm or more, or 400 μm or more. Furthermore, the aforementioned thickness can be 1,000 μm or less, 900 μm or less, 800 μm or less, 700 μm or less, 665 μm or less, 620 μm or less, or 600 μm or less. The aforementioned thickness can be substantially the same as the thickness of the aforementioned glass substrate 21, or the thickness difference can be 1 μm or more and 30 μm or less.

[0182] The molding material of the third insulating layer 71 may include a material capable of properly securing the device and preventing electrical short circuits. Exemplarily, it may include at least one selected from the group consisting of epoxy resins, polyimide resins, polyurethane resins, polyester resins, acrylate resins, and polyimide resins. Exemplarily, the molding material may include epoxy molding compound (EMC), glass fiber reinforced epoxy resin (FR-4), etc. The molding material may contain other additives, phenolic resins, carbon black, flame retardants, fillers, etc. The fillers that may be included in the molding material may be particulate fillers, and the particle size of the fillers may be from 1 μm to 20 μm or from 2 μm to 15 μm.

[0183] The aforementioned electronic device 40 can be connected to the connecting electrode.

[0184] The connecting electrodes can be arranged on the exposed surface of the electronic device 40 where the first insulating layer 61 is not disposed. The connecting electrodes can also be arranged on the exposed surface of the electronic device 40 where neither the first insulating layer 61 nor the third insulating layer 71 is disposed.

[0185] The connecting electrode can be arranged to penetrate the first insulating layer 61 of the electronic device 40. The connecting electrode can also be arranged to penetrate both the first insulating layer 61 and the third insulating layer 71 of the electronic device 40. The connecting electrode can be in the form of a blind via. Specifically, in the electronic device 40, a portion of each of the first insulating layer 61 and the third insulating layer 71 can be removed in the form of a through-hole or the like, and conductive material can be embedded therein to form a connecting electrode.

[0186] The first insulating layer may also have a through-hole (not shown in the figure) extending through it. Part or all of the through-hole may be filled with electrode material.

[0187] The aforementioned third insulating layer may also have through-holes (not shown in the figure) extending through it. Part or all of the through-holes may be filled with electrode material.

[0188] One end of the aforementioned through-hole in the first insulating layer can contact the aforementioned electronic device 40, and the other end of the aforementioned through-hole in the first insulating layer can be exposed to the outside of the first insulating layer.

[0189] One end of the first insulating layer through hole is in contact with the electronic device 40, and the other end of the first insulating layer through hole is in contact with one end of the third insulating layer through hole. The other end of the third insulating layer through hole can be exposed to the outside of the cavity portion 28.

[0190] The aforementioned third insulating layer through-hole can be arranged to penetrate the aforementioned cavity 28 vertically without directly contacting the aforementioned electronic device 40.

[0191] As the electrode material described above, conductive materials can be used, such as conductive metals. For example, copper, copper alloys, silver, etc., can be used, but the present invention is not limited thereto.

[0192] The materials of the first insulating layer 61, the second insulating layer 62, and the third insulating layer 71 can be the same. Alternatively, different materials can be used, which is more preferable. In the latter case, materials with different dielectric constants can be used.

[0193] The dielectric constants of the first insulating layer 61, the second insulating layer 62, and the third insulating layer 71 may be different. For example, the dielectric constant of the first insulating layer 61 may be equal to or lower than the dielectric constants of the second insulating layer 62 and the third insulating layer 71. In this case, it has the advantage that sufficient insulation effect can be expected for each electronic device while substantially suppressing fluctuations in the cavity.

[0194] The first insulating layer 61 and the second insulating layer 62 may each include insulating material, and the third insulating layer 71 may include molding material.

[0195] As the aforementioned insulating material and molding material, polymer resins, polymer resin and filler (inorganic particles, organic particles, organic-inorganic composite particles, etc.) mixed materials, inorganic deposited layers, etc., can be used.

[0196] The aforementioned polymer resin can be acrylic resin, epoxy resin, or a modified resin thereof, and can be a material suitable for electronic devices for molding or other purposes. For example, liquid crystal polymers (LCPs) can be used.

[0197] The aforementioned mixed materials can be mixtures of acrylic resin and fillers, mixtures of acrylic resin and epoxy resin and fillers, or mixtures of epoxy resin and fillers, etc. The fillers can be inorganic particles, for example, silicon dioxide particles. As commercial products, they can be applied to Ajinomoto composite films (ABF), epoxy molding compounds (EMC), and modified polyimide (MPI), etc., but the present invention is not limited thereto.

[0198] For example, the inorganic deposition layer described above may be a silicon oxide deposition layer or a silicon nitride deposition layer, etc., but the present invention is not limited thereto.

[0199] For example, the first insulating layer 61 may include an inorganic deposition layer, liquid crystal polymer (LCP), epoxy molding compound (EMC), Ajinomoto composite film (ABF), or modified polyimide (MPI).

[0200] For example, the second insulating layer 62 may include an organic-inorganic composite material, specifically, it may include an Ajinomoto-based membrane (ABF), but is not limited thereto.

[0201] For example, the third insulating layer 71 may include molding materials such as epoxy molding compound (EMC), Ajinomoto composite film (ABF), or modified polyimide (MPI).

[0202] The ABF of the second insulating layer and the ABF of the third insulating layer can have different properties. Specifically, even materials that are both called ABF may have different physical properties such as coefficient of thermal expansion and dielectric constant, depending on the specific type of resin used and the content of inorganic particles used.

[0203] The first insulating layer 61, the second insulating layer 62, and the third insulating layer 71 can be made of materials having the same or different coefficients of thermal expansion (CTE). Preferably, materials with small differences in the CTE of the first insulating layer 61, the second insulating layer 62, and the third insulating layer 71 can be used.

[0204] The difference in the coefficients of thermal expansion between the materials of the first insulating layer and the third insulating layer can be less than 2 ppm / ℃, less than 1.5 ppm / ℃, less than 1 ppm / ℃, or less than 0.5 ppm / ℃. The difference in the coefficients of thermal expansion can be greater than 0 ppm / ℃, greater than 0.1 ppm / ℃, or greater than 0.2 ppm / ℃.

[0205] The coefficient of thermal expansion of the first insulating layer 61 can be 8 ppm / ℃ or higher, 10 ppm / ℃ or higher, 12 ppm / ℃ or higher, or 14 ppm / ℃ or higher. The coefficient of thermal expansion can be 20 ppm / ℃ or lower, 18 ppm / ℃ or lower, or 17 ppm / ℃ or lower.

[0206] The coefficient of thermal expansion of the second insulating layer 62 can be 8 ppm / ℃ or higher, 10 ppm / ℃ or higher, or 12 ppm / ℃ or higher. The coefficient of thermal expansion can be 20 ppm / ℃ or lower, 18 ppm / ℃ or lower, 16 ppm / ℃ or lower, or 14 ppm / ℃ or lower.

[0207] The coefficient of thermal expansion of the third insulating layer 71 can be 8 ppm / ℃ or higher, 10 ppm / ℃ or higher, or 12 ppm / ℃ or higher. The coefficient of thermal expansion can be 20 ppm / ℃ or lower, 18 ppm / ℃ or lower, 16 ppm / ℃ or lower, or 14 ppm / ℃ or lower.

[0208] The materials of the first insulating layer 61, the second insulating layer 62, and the third insulating layer 71 can have different dielectric constants. Preferably, the materials of the insulating layers can be selected such that the dielectric constant of the first insulating layer 61 is lower than the dielectric constant of the second insulating layer 62 and the third insulating layer 71. Preferably, the materials of the insulating layers can be selected such that the dielectric constant of the second insulating layer 62 is lower than the dielectric constant of the third insulating layer 71.

[0209] Preferably, the first insulating layer 61, the second insulating layer 62, and the third insulating layer 71 are made of materials with different relative permittivity Dk at a high frequency of 5.8 GHz. For example, the difference between Dk of the first insulating layer 61 and Dk of the third insulating layer 71 can be 0.1 or more. The difference in Dk can be 0.1 or more, 0.13 or more, 0.16 or more, or 0.2 or more. The difference in Dk can be less than 1, less than 0.8, less than 0.6, less than 0.5, less than 0.4, less than 0.3, or less than 0.25.

[0210] The Dk of the first insulating layer 61 can be 2.3 or higher, 2.5 or higher, 2.7 or higher, or 2.9 or higher. The Dk can be 3.4 or lower, 3.2 or lower, or 3.1 or lower.

[0211] The Dk of the second insulating layer 62 can be 3.0 or higher, 3.1 or higher, or 3.2 or higher. The Dk can be 3.6 or lower, 3.5 or lower, or 3.4 or lower.

[0212] The Dk of the third insulating layer 71 can be 3.0 or higher, 3.1 or higher, or 3.2 or higher. The aforementioned Dk can be 3.6 or lower, 3.5 or lower, or 3.4 or lower.

[0213] The Dk of the first insulating layer 61 can be smaller than the Dk of the third insulating layer 71.

[0214] The materials of the first insulating layer 61, the second insulating layer 62, and the third insulating layer 71 can have different or different dielectric loss factors Df. For example, a material where the difference between the Df of the first insulating layer 61 and the Df of the third insulating layer 71 is 0.0001 or more can be used. The difference in Df can be 0.0001 or more, 0.0005 or more, or 0.001 or more. The difference in Df can be less than 0.02.

[0215] The Df of the first insulating layer 61 can be less than 0.004, less than 0.0038, or less than 0.0036. The Df can be greater than 0.001, greater than 0.0015, greater than 0.0018, or greater than 0.002.

[0216] The Df of the second insulating layer 62 can be less than 0.005, less than 0.0048, or less than 0.0046. The Df can be greater than 0.003, greater than 0.0032, or greater than 0.0034.

[0217] The Df of the third insulating layer 71 can be less than 0.005, less than 0.0048, or less than 0.0046. The Df can be greater than 0.003, greater than 0.0032, or greater than 0.0034.

[0218] The Df of the first insulating layer 61 can be smaller than the Df of the third insulating layer 71.

[0219] The Df of the first insulating layer 61 can be smaller than the Df of the second insulating layer 62 and the Df of the third insulating layer 71.

[0220] The bending strength of the third insulating layer 71 at 25°C can be 5 kg / mm² or more, 7 kg / mm² or more, or 10 kg / mm² or more. Alternatively, the bending strength can be 25 kg / mm² or less, 20 kg / mm² or less, or 18 kg / mm² or less.

[0221] The flexural modulus of the third insulating layer 71 at 25°C can be 1,200 kg / mm² or more, 1,300 kg / mm² or more, or 1,400 kg / mm² or more. Alternatively, the flexural modulus can be 2,500 kg / mm² or less, 2,300 kg / mm² or less, or 2,100 kg / mm² or less.

[0222] The aforementioned third insulating layer 71 can have an elongation of 0.3% to 7% at 23°C.

[0223] The thermal conductivity of the third insulating layer 71 can be 0.3 W / m·K or higher, 0.5 W / m·K or higher, or 0.7 W / m·K or higher. Alternatively, the thermal conductivity can be 2.3 W / m·K or lower, 2.0 W / m·K or lower, or 1.8 W / m·K or lower.

[0224] Because the third insulating layer 71 has these physical properties, electronic devices can be stably fixed and insulated.

[0225] For example, the third insulating layer 71 can be made of EMC, the second insulating layer 62 can be made of ABF, and the first insulating layer 61 can be made of LCP. The EMC of the third insulating layer and the EMC of the second insulating layer can have different dielectric constants. For example, the third insulating layer 71 can be made of ABF, the second insulating layer 62 can be made of ABF, and the first insulating layer 61 can be made of LCP. The ABF of the third insulating layer and the ABF of the second insulating layer can have different dielectric constants. For example, the third insulating layer 71, the second insulating layer 62, and the first insulating layer 61 can be made of EMP with different dielectric constants. For example, the third insulating layer 71, the second insulating layer 62, and the first insulating layer 61 can be made of ABP with different dielectric constants.

[0226] For example, in terms of controlling the dielectric constant, preferably, the third insulating layer 71 is made of EMC, the second insulating layer 62 is made of ABF, and the first insulating layer 61 is made of LCP.

[0227] For example, regarding the formation of the first insulating layer 61, as an example, the first insulating layer 61 can be formed on the surface of the electronic device 40 by applying a varnish-type method, a selective lamination method, or a deposition method.

[0228] For the second insulating layer 62, the commonly used method for forming an insulating layer in the cavity of the packaging substrate can be applied, or the method used for forming the first insulating layer 61 can be applied.

[0229] For the third insulating layer 71, a method for forming a molding portion can be used. For example, a method can be used to arrange a mold on an electronic device on which the first insulating layer is formed, inject molding material into the mold, and then cure the molding material.

[0230] Figures 6 and 7 illustrate a method for manufacturing a packaging substrate according to the disclosed embodiment.

[0231] The packaging substrate according to FIG6 can be manufactured by forming a glass core 21 with a cavity and an electronic device 40 with a first insulating layer 61, arranging the electronic device 40 in the cavity, and stacking a second insulating layer 62 on the glass substrate.

[0232] As shown in FIG7, the encapsulation substrate can be manufactured by forming a glass core 21 with cavity portions and cavity modules, the cavity portions being arranged with the cavity modules, and a second insulating layer 62 being stacked on the glass substrate.

[0233] Specifically, this specification presents embodiments for producing a packaging substrate according to the following implementation methods.

[0234] In one embodiment, electronic components are selected and arranged in a mold; then, a first insulating layer can be coated (or sputtered) onto each of the aforementioned electronic components. Subsequently, if desired, electrodes or the like can be formed after removing at least a portion of the first insulating layer coated on a specific surface (e.g., top or bottom) of the aforementioned electronic components. Subsequently, if desired, a cavity module can be formed by arranging molding material in the mold on which the aforementioned electronic components are arranged and allowing it to cure. Optionally, cavity electrodes can be formed by removing a portion of the molding material.

[0235] A cavity module can be arranged on a glass substrate with cavities, and a second insulating layer can be formed on it. The second insulating layer can be formed by a process of forming a redistribution layer (RDL).

[0236] Figure 8 is a cross-sectional flowchart of the manufacturing method of the packaging substrate according to this embodiment.

[0237] The steps for forming the first insulating layer and the second insulating layer on the packaging substrate will be explained in more detail below with reference to Figure 8.

[0238] For example, as shown in part (a) of Figure 8, electronic devices 40 can be attached to an adhesive film 33 (support) such as PI tape (polyimide tape).

[0239] Subsequently, as shown in part (b) of FIG8, exemplarily, a first insulating layer 61 may be formed on some surfaces of the electronic device 40 disposed in the cavity portion 28, other than the top or bottom surface. For example, the first insulating layer 61 may be formed on some surfaces of the electronic device 40 other than the top or bottom surface by performing a sputtering, coating, or molding process on the electronic device 40 in the cavity portion 28. For example, one or more connecting electrodes may be formed in the bottom direction of the electronic device 40. For example, one or more connecting electrodes may be formed in the top direction or the downward direction of the electronic device 40. Here, a glass core 21 may be disposed such that the electronic device is disposed within the cavity portion. At this time, electrodes 63, such as a core distribution layer, may be disposed on the glass core 21.

[0240] Secondly, as shown in part (c) of FIG8, a process of lamination on top of the second insulating layer 62 can be performed. The second insulating layer 62 can be laminated over the entire first surface of the glass core 21, and during curing (pre-curing), as shown in part (d) of FIG8, the second insulating layer 62 can be embedded in the internal space of the cavity. For example, the second insulating layer 62 may include an insulating mixture, which may include inorganic particles and polymer resin. For example, the second insulating layer 62 may include the Ajinomoto composite film (ABF) described above.

[0241] The adhesive film can be removed in subsequent processes as needed. For example, the adhesive film may be one whose adhesive strength can be reduced by ultraviolet irradiation, etc. By reducing the adhesive strength of the adhesive film by directly or through ultraviolet irradiation of the glass core, the adhesive film can be easily removed from the glass core. Furthermore, the position of the electronic device can be fixed by curing a pre-cured second insulating layer. If the degree of bending is controlled below a certain level, it can be used in subsequent processes without fixing the adhesive film.

[0242] Next, as shown in part (e) of FIG8, a process of lamination on bottom of the second insulating layer 62 can be performed. The second insulating layer 62 can be laminated over the entire second surface of the glass core 21, and when curing (pre-curing) is performed, as shown in part (f) of FIG8, the second insulating layer 62 can be embedded in the internal space of the cavity portion 28.

[0243] Therefore, according to FIG8, in one embodiment, a through-hole is formed in the glass core 21, which includes a first surface and a second surface facing each other, and a cavity portion penetrating the first surface and the second surface of the glass core 21 can be formed. Alternatively, a method for manufacturing a packaging substrate can be provided, wherein a glass core 21 having undergone the above-described process is prepared; electronic devices 40 are arranged in the cavity portion 28, and a first insulating layer 61 is formed on a portion of the surfaces of the arranged electronic devices 40, excluding the bottom surface; and a second insulating layer 62 is stacked on the first surface and the second surface.

[0244] A method for manufacturing a packaging substrate according to another embodiment includes: a preparation step of preparing a glass substrate and a cavity module having a cavity portion arranged therein; and a stacking step of arranging the cavity module in the cavity portion and providing a second insulating layer on the glass substrate.

[0245] Since the descriptions of glass substrates, cavity modules, etc., are redundant with the above descriptions, they will be omitted.

[0246] The aforementioned cavity module can be manufactured using cavity module manufacturing steps.

[0247] The manufacturing steps of the cavity module include: an arrangement process, arranging adjacent electronic devices; a first insulation process, setting a first insulating layer on the surface of the arranged electronic devices; and a molding process, molding the electronic devices with the first insulating layer using a molding material to form a cavity module containing a third insulating layer.

[0248] The cavity module manufacturing steps may also include a cavity electrode formation process after the molding process.

[0249] The cavity electrode forming process described above may be a process of removing a portion of the molding material, forming an electrode that is connected to the connecting electrode of the electronic device, and arranging the cavity module connecting electrode connected to the electrode.

[0250] Figure 9 is a cross-sectional flowchart illustrating a method for manufacturing a packaging substrate according to another embodiment. The description will be more detailed with reference to Figure 9.

[0251] Figure 9, in parts (a), (b), and (c), illustrates the manufacturing steps of the cavity module.

[0252] For example, as shown in part (a) of FIG9, the electronic device 40 is arranged on a support (e.g., an adhesive film such as PI tape (polyimide tape)) that can fix the position of the electronic device.

[0253] Subsequently, as shown in part (b) of FIG9, a first insulating layer 61 may be formed on some surfaces of the arranged electronic devices 40, other than the top or bottom surface. For example, the first insulating layer 61 may be formed on the electronic devices 40 by means of sputtering or coating. For example, one or more connection electrodes may be formed in the bottom direction of the electronic devices 40. For example, one or more connection electrodes may be formed in the top direction of the electronic devices 40.

[0254] Secondly, as shown in part (c) of FIG9, a third insulating layer 71 comprising molding material and arranged such that the molding material surrounds the electronic device 40 having the first insulating layer formed thereon can be formed. For example, by injecting molding material into a molding structure including sidewalls, the molding material surrounds the electronic device 40 having the first insulating layer formed thereon, and the third insulating layer 71 is formed by curing the molding material.

[0255] Alternatively, the cavity module manufactured in this manner may also include cavity connection electrodes.

[0256] Figure 9, in sections (d), (e), and (f), illustrates the manufacturing steps of the packaging substrate.

[0257] As shown in part (d) of Figure 9, a cavity module is arranged in the cavity portion 28 of the glass substrate 21, which allows for the lamination of the second insulating layer 62 onto the first surface. The second insulating layer 62 can be laminated over the entire first surface of the glass core 21, and during curing (pre-curing), the second insulating layer 62 can be embedded in the internal space of the cavity portion 28.

[0258] If necessary, the process described in Figure 9(d) can be performed with the adhesive film placed at the lower end of the glass substrate. When the glass substrate has a full cavity, the adhesive film can indicate the position of the cavity module.

[0259] The aforementioned adhesive film can be removed in a subsequent process. For example, the adhesive film may be one whose adhesive strength can be reduced by ultraviolet irradiation or the like. By reducing the adhesive strength of the adhesive film by directly or through ultraviolet irradiation of the glass core, the adhesive film can be easily removed from the glass core. Furthermore, the electronic device can be fixed in place by means of a second insulating layer that has undergone pre-curing treatment.

[0260] Next, as shown in part (e) of FIG9, a process of lamination on bottom of the second insulating layer 62 can be performed. The second insulating layer 62 can be laminated over the entire second surface of the glass core 21, and during curing (pre-curing), as shown in part (f) of FIG9, the second insulating layer 62 can be embedded in the internal space of the cavity portion 28. A boundary between the second insulating layer 62 and the third insulating layer can be observed on the second insulating layer 62. In cross-section, a boundary line with a color difference can be observed as the boundary. In cross-section, a color-changing band with a relatively constant thickness (e.g., a gradient color change) can be observed as the boundary. Exemplarily, the constant interval can be 2 μm to 30 μm, or 3 μm to 10 μm.

[0261] The method for manufacturing the packaging substrate according to the above embodiments and the packaging substrate using the same can prevent fluctuations caused by gaps between devices and / or gaps between the cavity and the device, and can prevent leakage current in the cavity.

[0262] Furthermore, by forming a second insulating layer arranged to surround electronic devices on which the first insulating layer is formed, and a third insulating layer having a different dielectric constant, short circuits caused by contact between side-by-side electronic devices can be prevented, and the positions of the electronic devices can be prevented from changing. This avoids contact between electronic devices and prevents accidental short circuits that may occur during the manufacturing process of forming the conductive layer.

[0263] The above description refers to the embodiments illustrated in the accompanying drawings, but these are merely examples. Those skilled in the art will understand that various modifications and equivalent embodiments can be derived from this description. In other words, the scope of this specification is not limited to the above-described embodiments, but rather includes various modifications or variations made by those skilled in the art using the basic concepts of the embodiments defined in the claims. Therefore, the true scope of protection of this specification should be determined based on the technical concept of the claims.

[0264] 10: Motherboard 20: Packaging substrate 21: Glass substrate / glass core 21a: Glass substrate 21b: Defect 21c: Seed layer / primer layer 21d: Conductive layer 22: Core layer 23: Core through hole 23a: Insulation layer 23b: Blind hole 23c: Conductive layer 23d: Etched layer 23e: Insulation layer 24: Core Distribution Layer 25: Upper part layer 26: Upper layer 27: Upper connecting layer 28: Cavity 29: Lower layer 30: Semiconductor Devices Division 32: First semiconductor device 33: Support 34: Second semiconductor device 36: Third semiconductor device 40: Electronic Components / Cavity Components 50: Connecting part 51: Device connection section 52: Plate connection part 60: Covering layer 61: First insulating layer 62: Second insulating layer 63: Electrode 71: Third Insulation Layer 100: Semiconductor devices 211: First thickness 212: Second thickness 213: First Surface 214: Second Surface 221: Area 1 222: Second Zone 223: Core insulation layer 241: Core Distribution Pattern 251: Upper part pattern 252: Blind Hole 253: Upper insulation layer 271: Upper connecting electrode 272: Upper connecting pattern 281: Interior Space 282: Cavity Distribution Layer

Claims

1. A packaging substrate comprising a core layer, the core layer including a glass core and a cavity portion, the glass core having a first surface and a second surface facing each other, the cavity portion penetrating the glass core, a cavity module and a second insulating layer disposed in the cavity portion, the cavity module including a plurality of electronic devices, a first insulating layer and a third insulating layer, the first insulating layer being a layer of coating material surrounding each of the electronic devices, the third insulating layer being a layer of molding material surrounding the plurality of electronic devices, the second insulating layer being embedded in the internal space of the cavity portion excluding the cavity module, and a third insulating layer through-hole penetrating at least a portion of the third insulating layer being disposed in the third insulating layer, a portion or all of the interior of the third insulating layer through-hole being filled with electrode material, wherein... The first insulating layer is further provided with a first insulating layer through hole that penetrates the first insulating layer, and part or all of the interior of the first insulating layer through hole is filled with electrode material.

2. The packaging substrate as claimed in claim 1, wherein the dielectric constant of the coating material is lower than the dielectric constant of the molding material.

3. A packaging substrate comprising a core layer, the core layer comprising a glass core and a cavity portion, the glass core having a first surface and a second surface facing each other, the cavity portion penetrating the glass core, a cavity module and a second insulating layer disposed in the cavity portion, the cavity module comprising a plurality of electronic devices, a first insulating layer and a third insulating layer, the first insulating layer being a layer of coating material surrounding each of the electronic devices, the third insulating layer being a layer of molding material surrounding the plurality of electronic devices, the second insulating layer being embedded in the internal space of the cavity portion excluding the cavity module, and a third insulating layer via penetrating at least a portion of the third insulating layer being disposed in the third insulating layer, a portion or all of the interior of the third insulating layer via being filled with an electrode material, wherein the high-frequency relative permittivity Dk is the relative permittivity at a high frequency of 5.8 GHz, Dk1 is the high-frequency relative permittivity of the first insulating layer, Dk3 is the high-frequency relative permittivity of the third insulating layer, and the difference between Dk1 and Dk3 is 0.1 or more.

4. A packaging substrate comprising a core layer, the core layer comprising a glass core and a cavity portion, the glass core having a first surface and a second surface facing each other, the cavity portion penetrating the glass core, a cavity module and a second insulating layer disposed in the cavity portion, the cavity module comprising a plurality of electronic devices, a first insulating layer and a third insulating layer, the first insulating layer being a layer of coating material surrounding each of the electronic devices, the third insulating layer being a layer of molding material surrounding the plurality of electronic devices, the second insulating layer being embedded in the internal space of the cavity portion excluding the cavity module, and a third insulating layer through-hole penetrating at least a portion of the third insulating layer being disposed in the third insulating layer, a portion or all of the interior of the third insulating layer through-hole being filled with electrode material, wherein the dielectric constant of the first insulating layer is lower than the dielectric constant of the second insulating layer, Df1 is the dielectric loss factor of the first insulating layer, Df2 is the dielectric loss factor of the second insulating layer, and the difference between Df1 and Df2 is 0.1 or more.

5. The packaging substrate as described in claim 4, wherein, Electronic device connection electrodes are arranged on the aforementioned electronic device, and the aforementioned cavity module includes cavity connection electrodes, which are electrically connected to the aforementioned electronic device connection electrodes and exposed on the surface of the aforementioned cavity module.

6. The packaging substrate as claimed in claim 4, wherein the electronic device has an exposed surface, the first insulating layer is not disposed on the exposed surface, and wherein the electronic device connection electrode is disposed on the exposed surface.

7. A packaging substrate comprising a core layer, the core layer comprising a glass core and a cavity portion, the glass core having a first surface and a second surface facing each other, the cavity portion penetrating the glass core, a cavity module and a second insulating layer disposed in the cavity portion, the cavity module comprising a plurality of electronic devices, a first insulating layer and a third insulating layer, the first insulating layer being a layer of coating material surrounding each of the electronic devices, the third insulating layer being a layer of molding material surrounding the plurality of electronic devices, the second insulating layer being embedded in the internal space of the cavity portion excluding the cavity module, and a third insulating layer through-hole penetrating at least a portion of the third insulating layer being disposed in the third insulating layer, a portion or all of the interior of the third insulating layer through-hole being filled with electrode material, wherein the third insulating layer is configured to penetrate the cavity portion in a vertical direction and not directly contact the electronic devices.

8. A method for manufacturing a packaging substrate, comprising: The preparation step involves preparing a glass substrate with a cavity portion and a cavity module; and the stacking step involves arranging the cavity module in the cavity portion and setting a second insulating layer on the glass substrate. The cavity module includes multiple electronic devices, a first insulating layer, and a third insulating layer. The first insulating layer is a layer that surrounds each of the electronic devices with a coating material. The third insulating layer is a layer that surrounds the multiple electronic devices with a molding material. The second insulating layer is embedded in the internal space of the cavity portion, excluding the cavity module. The third insulating layer further includes a third insulating layer through-hole penetrating at least a portion of the third insulating layer. The interior of the third insulating layer through-hole is partially or entirely filled with electrode material. The first insulating layer further includes a first insulating layer through-hole penetrating the first insulating layer, and the interior of the first insulating layer through-hole is partially or entirely filled with electrode material.

9. The method of claim 8, wherein the cavity module is manufactured through a cavity module manufacturing step, wherein the cavity module manufacturing step includes: The arrangement process involves arranging adjacent electronic devices; the first insulation process involves depositing the first insulating layer on the surface of the arranged electronic devices. The molding process involves molding the electronic device with the first insulating layer using the molding material to manufacture the cavity module containing the third insulating layer.

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