A semiconductor device bonding alignment apparatus and method

TWI939355BActive Publication Date: 2026-09-11CELLO TECH
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Patent Information

Application Number
TW115119311
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2026-05-18
Publication Date
2026-09-11
Estimated Expiration
2046-05-17

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Abstract

A semiconductor device bonding alignment apparatus includes a gripping unit, a carrier unit, a resistance measurement unit, a laser ranging unit, and a photosensitive measurement unit. The gripping unit picks up a first component to be bonded, and the carrier unit places a second component to be bonded. The first and second components to be bonded are defined with a parallelism. The resistance measurement unit performs a first measurement and adjusts the parallelism to be within a first measurement range. The laser ranging unit performs a second measurement and adjusts the parallelism to be within a second measurement range. The photosensitive measurement unit performs a third measurement and adjusts the parallelism to be within a third measurement range.
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Claims

1. A semiconductor device bonding and alignment apparatus, comprising: A gripping unit includes a vacuum chuck and a first adjustment unit for adjusting the vacuum chuck, the vacuum chuck being configured to grip a first component to be bonded; a carrier unit is disposed below the gripping unit and includes a carrier disk and a second adjustment unit for adjusting the carrier disk, the carrier disk being configured to place a second component to be bonded, wherein a first surface of the first component to be bonded and a second surface of the second component to be bonded extend along a planar direction and face each other, the first surface and the second surface substantially overlap in a vertical direction to define a parallelism; a resistance measurement unit is configured to perform a first measurement on the vacuum chuck, the first adjustment unit and the second adjustment unit adjusting according to the result of the first measurement to ensure that the parallelism is within a first measurement range; A laser ranging unit is configured to perform a second measurement on the carrier disk, and the first adjustment unit and the second adjustment unit adjust according to the result of the second measurement so that the parallelism is within a second measurement range with a measurement scale smaller than the first measurement range; and a photosensitive measurement unit is configured to perform a third measurement on the first element to be bonded and the second element to be bonded, and the first adjustment unit and the second adjustment unit adjust according to the result of the third measurement so that the parallelism is within a third measurement range with a measurement scale smaller than the second measurement range; wherein the first measurement range is configured to be determined according to an electrical signal parameter output by the resistance measurement unit, the second measurement range is configured to be determined according to an optical signal parameter output by the laser ranging unit, and the third measurement range is configured to be determined according to a moiré pattern output by the photosensitive measurement unit.

2. The semiconductor element bonding and alignment apparatus as described in claim 1, wherein, The electrical signal parameters include a voltage signal, a resistance signal, or a combination thereof.

3. The semiconductor element bonding and alignment apparatus as described in claim 1, wherein, The optical signal parameters include a time of flight, a beam splitting interferometer, or a combination thereof.

4. The semiconductor element bonding and alignment apparatus as described in claim 1, wherein, The moiré pattern includes the number of moiré patterns, the density of moiré patterns, the degree of overlap of moiré patterns, or a combination thereof.

5. The semiconductor element bonding and alignment apparatus as described in claim 1, wherein, The parallelism includes an angle difference, a height difference, or a combination thereof between the first element to be bonded and the second element to be bonded.

6. The semiconductor element bonding and alignment apparatus as claimed in claim 1, wherein, The first measurement range is when the angle difference of the parallelism is between 0.01° and 1°, or when the height difference of the parallelism is between 1 micrometer and 100 micrometers.

7. The semiconductor element bonding and alignment apparatus as described in claim 1, wherein, The second measurement range is a parallelism angle difference between 0.001° and 0.01°, or a parallelism height difference between 0.1 micrometers and 1 micrometer.

8. The semiconductor element bonding and alignment apparatus as claimed in claim 1, wherein, The third measurement range is when the angle difference of the parallelism is less than 0.001°, or the height difference of the parallelism is less than 0.1 micrometers.

9. A method for bonding and aligning semiconductor devices, comprising: A first component to be bonded and a second component to be bonded are provided. A first surface of the first component to be bonded and a second surface of the second component to be bonded extend along a planar direction and are disposed facing each other. The first surface and the second surface substantially overlap in a vertical direction to define a parallelism. A first measurement is performed on a vacuum chuck that picks up the first component to be bonded by a resistance measurement unit. Based on the result of the first measurement, the first component to be bonded and the second component to be bonded are adjusted so that the parallelism is within a first measurement range. A second measurement is performed on a carrier disk that carries the second component to be bonded by a laser ranging unit. Based on the result of the second measurement, the first component to be bonded and the second component to be bonded are adjusted so that the parallelism is within a second measurement range. A third measurement is performed on the first component to be bonded and the second component to be bonded by a photosensitive measurement unit. And adjust the first element to be bonded and the second element to be bonded according to the result of the third measurement so that the parallelism is within a third measurement range; wherein the measurement scale of the first measurement range is larger than the second measurement range, and the measurement scale of the second measurement range is larger than the third measurement range; and wherein the first measurement range is configured to be determined according to an electrical signal parameter output by the resistance measurement unit, the second measurement range is configured to be determined according to an optical signal parameter output by the laser ranging unit, and the third measurement range is configured to be determined according to a moiré pattern output by the photosensitive measurement unit.

10. The semiconductor element bonding alignment method as described in claim 9, wherein, The moiré pattern includes the number of moiré patterns, the density of moiré patterns, the degree of overlap of moiré patterns, or a combination thereof.

Citation Information

Patent Citations

  • System and apparatus for pick-and-place assembly

    TW202327440A

  • Semiconductor structure and method of overlay measurement of semiconductor structure

    TW202443309A