Interconnection structure of integrated circuit and method for forming the same

TWI939356BActive Publication Date: 2026-09-11UNITED MICROELECTRONICS CORP
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Patent Information

Application Number
TW115121568
Authority / Receiving Office
TW · TW
Patent Type
Patents
Current Assignee / Owner
Filing Date
2026-06-02
Publication Date
2026-09-11
Estimated Expiration
2046-06-01

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    Figure TWG2TB001911014_003
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Abstract

An interconnect structure includes a dielectric layer, a trench defined in the dielectric layer, a barrier layer disposed along the sidewalls and bottom surface of the trench, an adhesion layer disposed on the barrier layer, a filler metal disposed within the trench, and a first alloy layer disposed at the interface between the filler metal and the adhesion layer. The first alloy layer is an alloy of the metal material of the adhesion layer and the metal-doped filler metal.
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Claims

1. An interconnect structure, comprising: A dielectric layer including a trench; a barrier layer disposed along the sidewalls and bottom surface of the trench; an adhesion layer disposed on the barrier layer, the adhesion layer including a first metal material; a filler metal disposed within the trench, the filler metal including a second metal material and a metal dopant; and a first alloy layer disposed at the interface between the filler metal and the adhesion layer, the first alloy layer including the first metal material and the metal dopant.

2. The interconnect structure as described in claim 1, wherein the barrier layer comprises tantalum nitride (TaN).

3. The interconnect structure as described in claim 1, wherein the first metallic material includes cobalt (Co).

4. The interconnect structure as described in claim 1, wherein the second metallic material includes copper (Cu).

5. The interconnect structure as described in claim 1, wherein the metal doping includes titanium (Ti).

6. The interconnect structure as described in claim 1, wherein the first alloy layer comprises a cobalt-titanium alloy (CoTi).

7. The interconnect structure as described in claim 1 further includes a cover layer disposed on a top surface of the filler metal, wherein the cover layer includes the first metal material.

8. The interconnect structure as described in claim 7 further includes a second alloy layer disposed between the filler metal and the capping layer, wherein the second alloy layer includes the first metal material and the metal dopant.

9. The interconnect structure as described in claim 8, wherein the second alloy layer and the first alloy layer continuously surround the filler metal.

10. The internal interconnect structure as described in claim 7, wherein the cover layer is further disposed on a top surface of the attachment layer and a top surface of the barrier layer.

11. A method for manufacturing an interconnect structure, comprising: A trench is formed in a dielectric layer; a barrier layer is formed along the sidewalls and bottom of the trench; An adhesion layer is formed on the barrier layer, the adhesion layer comprising a first metal material; a filler metal is formed to fill the trench, the filler metal comprising a second metal material and a metal dopant; and a first alloy layer is formed at the interface between the filler metal and the adhesion layer, the first alloy layer comprising the first metal material and the metal dopant.

12. The method for manufacturing the interconnect structure as described in claim 11, wherein the step of forming the first alloy layer includes: A heat treatment is performed to drive the metal dopant in the filler metal to migrate to the interface between the filler metal and the attached layer.

13. The method of manufacturing the interconnect structure as described in claim 12, wherein the temperature of the heat treatment is between 300 and 350 degrees Celsius, and the time of the heat treatment is between 20 and 60 seconds.

14. The method for manufacturing the interconnect structure as described in claim 11 further includes: A cleaning step is performed on the top surface of the filler metal; A capping layer is formed over the top surface of the filler metal, wherein the capping layer includes the first metal material; and a second alloy layer is formed between the filler metal and the top surface of the capping layer, wherein the second alloy layer includes the first metal material and the metal dopant.

15. The method for manufacturing the interconnect structure as described in claim 14, wherein the step of forming the second alloy layer includes: A heat treatment is performed to drive the metal dopant in the filler metal to migrate to the top surface of the filler metal.

16. A method for manufacturing an interconnect structure as described in claim 11, wherein the barrier layer comprises tantalum nitride (TaN).

17. A method for manufacturing an interconnect structure as described in claim 11, wherein the first metallic material comprises cobalt (Co).

18. A method for manufacturing an interconnect structure as described in claim 11, wherein the second metallic material comprises copper (Cu).

19. A method for manufacturing an interconnect structure as described in claim 11, wherein the metal doping includes titanium (Ti).

20. A method for manufacturing an interconnect structure as described in claim 11, wherein the first alloy layer comprises a cobalt-titanium alloy (CoTi).

Citation Information

Patent Citations

  • IC interconnect structures and methods for making same

    TW430966B

  • Interconnection structure of integrated circuit semiconductor device

    US12230568B2

  • Integrated circuit device including interconnection structure

    US20240071924A1