Process for fabricating a 3d-nand flash memory

Abstract

This invention relates to a method for preparing 3D-NAND flash memory, comprising a first step of electrodepositing an alloy of copper and a doped metal selected from manganese and zinc, followed by annealing the alloy, and a second step of layering the alloy to form a first layer of copper and a second layer containing zinc or manganese.

Description

[Technical Field]

[0001] This invention relates to the field of three-dimensional NAND flash memory devices and a method for generating copper wires in such devices. [Previous Technology]

[0002] 3D-NAND flash memory systems are formed by horizontally stacking alternating conductive metal layers (word lines, multiples of 8) and insulating layers. The entire height of the conductor / insulator stack is penetrated by several vertical polysilicon semiconductor channels (drains) to form a three-dimensional array of memory cells, each cell located at the intersection of the channel and the word line. The word lines are electrically connected to the bit lines and source lines. The contact between the bit lines and the polysilicon drains is typically provided by tungsten pads or tungsten wires.

[0003] The conductivity and reliability of metal contacts are crucial criteria for providing good electron transfer in memory. However, the copper diffusion barrier material that must be placed between the copper wire and the tungsten contact wire has high resistance and blocks part of the current, which reduces the information transmission speed from the word line to the bit line, reduces the power supply from the copper source line to the word line, and increases battery consumption.

[0004] More precisely, the copper diffusion barrier layer between tungsten and copper in current devices has many drawbacks. The barrier materials used (such as tantalum nitride or titanium nitride) do not adhere sufficiently to the copper, so a thin layer of tantalum or titanium is usually inserted between the nitride and the copper. On the other hand, since the tantalum layer is produced by physical vapor deposition (PVD), it is necessary to cover the tantalum layer with a copper seed layer without disrupting the vacuum in the chamber to prevent the tantalum layer from oxidizing into tantalum pentoxide, which has high electrical resistance.

[0005] Current methods for generating copper wires in 3D-NAND flash memory are therefore complex, and there is a desire to provide a simpler method that involves less material deposition at the interface between the tungsten contacts and the copper, and therefore fewer fabrication steps.

[0006] There is also a need for a method for fabricating 3D-NAND flash memory that reduces the resistance between the two metal layers and is easier to implement. 3D-NAND flash memory fabricated according to this method has lower fabrication costs, operates at higher speeds, and consumes less power.

[0007] Finally, in the prior art, the barrier layer deposited by a dry process (e.g., in the vapor phase) does not have a uniform thickness across the entire covering surface; its thickness is higher on concave surfaces or at the edges. Therefore, in the specific case of tungsten contacts placed between polysilicon channels and copper bit lines, tantalum nitride or titanium nitride layers deposited in the vapor phase (e.g., by CVD) will be thicker at the bottom of the copper-filled recess (more precisely, at the point of current flow). The difference in the thickness of the barrier material between the bottom of the copper recess and the wall, as well as the presence of overhangs at the recess edges, leads to a decrease in resistance in certain areas affecting device reliability and an increase in resistance in current-flowing areas.

[0008] To solve these problems, thinner, more conductive and flexible barriers will be needed to maximize trench filling space, reduce resistance in current flow areas and improve the reliability of 3D-NAND flash memory.

[0009] The present invention addresses these various requirements by replacing at least partially the barrier material (which has high resistance and uneven thickness) used in the prior art with a conformal, thinner and more conductive barrier layer.

[0010] The present invention also provides a method in which copper diffusion barrier material and copper are deposited in a groove in a single filling step to produce copper bit lines.

[0011] Finally, the present invention makes it possible to selectively form a copper diffusion barrier layer substantially on the insulating portion (most typically in silicon dioxide) and to a lesser extent on the interface between the copper and the metal contacts, thereby significantly reducing the resistance between these two metal layers and thus significantly reducing the resistance between the copper bit lines and the contacts that connect them to the polysilicon channels of the 3D-NAND flash memory. [Summary of the Invention]

[0012] This invention addresses these various needs by providing a method for fabricating 3D-NAND flash memory, wherein a copper diffusion barrier layer can be deposited on an insulating surface in a wet process step, rather than in a dry process as in the prior art. The method of this invention makes it possible to deposit a doped metal precursor onto the copper diffusion barrier layer to form word lines during the copper electrodeposition step. This step uses an electrolyte containing both copper ions and barrier material doped metal precursor ions.

[0013] The dry process described in this specification may be a process selected from the group consisting of: atomic layer deposition (ALD), physical vapor deposition (PVD) and chemical vapor deposition (CVD).

[0014] The present invention provides a method comprising a first step of electrodepositing an alloy of copper and a doped metal selected from manganese and zinc, followed by annealing the alloy to cause it to be layered and forming a first layer of copper and a second layer comprising the doped metal and / or its oxide.

Implementation Method

[0016] Therefore, the method of the present invention is a method for preparing 3D-NAND flash memory, the method comprising a first step of electrodepositing an alloy of copper and a doped metal selected from manganese and zinc, the first electrodeposition step comprising contacting a first surface of the metal layer with an electrolyte containing copper(II) ions and doped metal ions, and then polarizing the first surface for a time sufficient to allow the copper-doped metal alloy to cover the first surface, the first electrodeposition step being followed by a second step of annealing the alloy to cause it to be layered and form a first layer of copper and a second layer containing the doped metal and / or its oxide.

[0017] In detail, the first copper layer is intended to form the copper bit lines of 3D-NAND flash memory.

[0018] Advantageously, the electrolyte containing copper(II) ions and doped metal ions has a pH between 6.0 and 10.0, while the prior art electrolyte containing copper(II) ions for forming copper bit lines has a much lower pH.

[0019] As used herein, "electrodeposition" should be understood to mean any method in which a substrate is polarized and brought into contact with a liquid containing a metal precursor in order to deposit metal on the substrate surface. Electrodeposition is performed by transferring current between the anode and the substrate to be coated (which constitutes the cathode) in an electrolyte containing metal ions.

[0020] According to one embodiment, a copper-manganese alloy or a copper-zinc alloy is deposited on the surface of a conductive metal layer, the conductive layer being covered with a dielectric material, preferably an inorganic oxide. The alloy is then heat-treated to separate the copper from the doped metal, to obtain a second layer substantially comprising manganese, zinc and / or their oxides and a first layer substantially comprising copper.

[0021] "Substantially contains a layer of copper" means a copper deposit containing less than 1% by mass of impurities, which include any element other than copper.

[0022] "Substantially contains manganese, zinc and / or their oxides" means a deposit containing less than 1% by mass of impurities, which include any compound other than manganese, zinc and / or their oxides.

[0023] During alloy annealing, the alloy is delaminated to form a thin layer substantially comprising manganese, zinc, and / or their oxides, and a copper layer. This thin layer may then be inserted between the copper layer and the surface of the dielectric material. When the dielectric material is an inorganic oxide, the atoms of the doped metal may form oxides from oxygen atoms present in the dielectric and produce a layer with copper diffusion barrier properties, such as manganese oxide (MnO) or zinc oxide (ZnO).

[0024] The concentration of impurities in the copper deposit formed after alloy annealing can preferably be less than 1% by mass. Furthermore, the advantage of the layer substantially comprising manganese, zinc, and / or their oxides prepared according to the method of the present invention is that it is conformal (its thickness variation over the entire surface is preferably less than or equal to 10%). It is also extremely thin, for example, in the range of 0.1 nm to 3 nm.

[0025] Thus, it is possible to obtain copper bit lines separated from the dielectric material by a thin and regular layer substantially comprising manganese, zinc and / or their oxides. The method of the present invention also makes it possible to significantly reduce the thickness of the copper diffusion barrier layer used in the prior art, or even remove the copper diffusion barrier layer to separate the copper bit lines from the electrical contacts connected to the polysilicon channel.

[0026] According to a specific embodiment of the present invention, the metal layer includes a second surface that contacts a mixed surface comprising both an insulating region and a conductive region, the insulating region being made of a dielectric material and the conductive region being made of a contact metal selected from tungsten, molybdenum, cobalt and ruthenium, the contact metal being intended to connect the copper bit lines and polysilicon channels of the 3D-NAND flash memory.

[0027] Specifically, the dielectric material is selected from silicon dioxide, SiOC, SiOCH, SiN, or SiC. According to a preferred embodiment, the dielectric material contains oxygen. During the second step of annealing the alloy, the doped metal migrates to the mixed surface, and a second layer comprising the doped metal and / or its oxides at least covers the insulating region of the mixed surface. In an advantageous embodiment, the second layer comprises an oxide of the doped metal and functions as a copper diffusion barrier.

[0028] According to a first embodiment of the method of the present invention, referred to as the "filling" mode, the metal layer is a metal seed layer composed of copper, a copper alloy, or tantalum, which has been deposited during a step prior to the first electrodeposition step to contact a mixed surface with the insulating and conductive regions. The first surface of the metal layer in this case is the surface of the seed layer and may be concave, defined by a hollow area bounded by the walls and bottom of a trench. The hollow trench has an average width at the opening, for example, in the range of 15 nm to 700 nm, and an average depth in the range of 30 nm to 500 nm. In this first embodiment of the method of the present invention, the first step of electrodepositing a copper-doped metal alloy can be continued for a time sufficient to fill the hollow area with the alloy.

[0029] According to a second embodiment of the method of the present invention, the metal layer is a trench-filled copper deposit, and the first step of electrodepositing a copper-doped metal alloy can be carried out for a time sufficient to cover the trench-filled copper deposit in order to form an alloy deposit, which may be referred to as a "capping layer". The first copper layer formed as a result of the second annealing step is then polished in a third chemical mechanical polishing step. The trench-filled copper deposit can be formed by any method known to those skilled in the art, and the trench-filled copper deposit preferably does not contain doping metals selected from manganese and zinc.

[0030] The first copper alloy electrodeposition step of the method of the present invention may use an electrolyte, for example, a solution contained in water, that has: - copper(II) ions with a molar concentration between 1 mM and 120 mM; - a copper ion chelating agent selected from aliphatic polyamines having 2 to 4 amino groups (preferably ethylenediamine), with a molar concentration such that the ratio of the molar concentration of the chelating agent to the molar concentration of copper is in the range of 1:1 to 3:1; - a metal ion selected from manganese and zinc, with a molar concentration such that the ratio of the molar concentration of copper to the molar concentration of the metal is in the range of 1:10 to 10:1; - the pH of the electrolyte is between 6.0 and 10.0.

[0031] According to a particular embodiment, the electrolyte can be obtained by dissolving a copper(II) salt selected from copper sulfate, copper chloride, copper nitrate, and copper acetate, preferably copper sulfate, and more preferably copper sulfate pentahydrate, in water. The metal ions can be provided by dissolving organic salts, preferably carboxylates selected from gluconic acid, mucilage, tartaric acid, citric acid, and xylic acid. The metal ions are preferably substantially misculated in the electrolyte with a carboxylic acid or its carboxylate form.

[0032] According to a particular feature, copper ions are present in the electrodeposition composition at a concentration between 1 mM and 120 mM, preferably between 10 mM and 100 mM, and even more preferably between 40 mM and 90 mM.

[0033] The copper ion chelating agent is composed of one or more compounds selected from aliphatic polyamines having 2 to 4 amino groups (-NH2). Among the aliphatic polyamines that can be used, ethylenediamine, diethylenediamine, triethylenetetramine and dipropylenetriamine are mentioned, with ethylenediamine being preferred.

[0034] The ratio between the molar concentration of the misalignment agent and the molar concentration of copper ions is between 1:1 and 3:1, preferably between 1.5 and 2.5, and even more preferably between 1.8 and 2.2.

[0035] In the electrolyte, copper ions are essentially in the form of complexes with the complexing agent.

[0036] The molar concentration of the metal ions is such that the ratio between the molar concentration of copper and the molar concentration of the metal is in the range of 1:10 to 10:1.

[0037] In one specific embodiment of the invention, the metal is zinc. In this case, the ratio between the molar concentration of copper ions and the molar concentration of zinc ions is preferably 1:1 to 10:1.

[0038] When the metal is manganese, the ratio between the molar concentration of copper and the molar concentration of manganese can be in the range of 1:10 to 10:1.

[0039] The pH of the electrolyte may be between 6.0 and 10.0, more preferably between 6.5 and 10.0. According to a particular embodiment, the pH is between 6.5 and 7.5, more preferably between 6.8 and 7.2, for example, equal to 7.0 under preliminary measurement uncertainty. The pH of the composition may be adjusted to the desired range by means of one or more pH adjusting compounds, such as tetraalkylammonium salts (e.g., tetramethylammonium or tetraethylammonium). Tetraethylammonium hydroxide may be used.

[0040] Although there are no limitations in principle regarding the properties of the solvent (the limitation being that the solvent sufficiently dissolves the active material in the solution and does not interfere with electrodeposition), it is preferred to use water. According to one embodiment, the solvent mainly comprises water by volume.

[0041] According to a particular embodiment, the composition contains copper sulfate between 40 mM and 90 mM, ethylenediamine in a molar ratio to copper between 1.8 and 2.2, and zinc gluconate, at concentrations such that the molar ratio of copper to zinc is in the range of 2:1 to 3:1. The pH of the composition is preferably about 7.

[0042] The first step of electrodepositing an alloy of copper and a selected metal may include: - a step of contacting the conductive surface of the trench with an electrolyte as described above, - a step of polarizing the conductive surface for a time sufficient to achieve alloy deposition.

[0043] At the end of the first electrodeposition step, the manganese or zinc content in the deposited alloy is preferably between 0.5 atomic% and 10 atomic%.

[0044] The polarization step continues for a time sufficient to form the desired alloy thickness. The conductive surface can be polarized by a constant current mode (fixed applied current), a constant potential mode (applied and fixed potential, as appropriate, relative to a reference electrode), or a pulse mode (with current or voltage).

[0045] In a particular embodiment of the method for preparing the 3D-NAND flash memory according to the present invention, a copper-metal alloy is deposited on the surface of a copper layer. The copper layer may be a seed layer covering the bottom and walls of trenches that have been etched in a previous step, or a certain amount of copper that fills the trenches and has been previously deposited according to a method known to those skilled in the art.

[0046] In a first embodiment, an alloy is deposited to fill cavities that have been previously excavated on a substrate and whose surfaces have been covered with a dielectric material, and then, where appropriate, covered with a metallic material, specifically a copper and / or tantalum seed layer (the so-called "filling" mode). In this first embodiment, the alloy is deposited on the conductive surface of the trench to be filled.

[0047] In the second embodiment, an alloy is deposited on a layer of copper, with the copper filling the cavity opening to the surface of the substrate (a so-called "capping layer" pattern). The conductive surface then includes a portion of the copper deposit corresponding to the cavity and a portion of the substrate surface corresponding to the opening of the cavity thereon.

[0048] The cavity may have an average width at the opening in the range of 15 nm to 700 nm and an average depth in the range of 100 nm to 500 nm.

[0049] In the first embodiment, the method according to the present invention makes it possible to obtain copper filler of excellent quality without material defects and without generating a large amount of contaminants.

[0050] The surface of the cavity to be filled by the alloy is, for example, a first surface of a metal layer having a second surface, which is in contact with a dielectric material, preferably an inorganic oxide such as silicon dioxide, which is typically deposited by CVD.

[0051] The seed layer system is made of a single material such as copper or tantalum. Alternatively, the seed layer system consists of an assembly of two layers, including a copper layer and a so-called "pad" layer inserted between the copper layer and the dielectric material, which improves the adhesion of copper to the material. For example, the pad may be made of tantalum, ruthenium, cobalt, titanium or alloys thereof.

[0052] In a particular embodiment, the metal layer is a seed layer composed of copper with a thickness in the range of 4 nm to 20 nm, or a seed layer composed of a 1 nm thick pad and a 5 nm thick copper seed layer.

[0053] According to the second embodiment, the cavity is filled with pure copper by any method known to those skilled in the art, whether by physical deposition (PVD, CVD, ALD) or by a wet process (autocatalytic or electrolytic). In the context of this invention, "pure copper" means copper that does not contain other metallic elements, specifically copper that does not contain zinc or manganese. Specifically, in the context of this invention, "pure copper" can be understood as a copper deposit preferably containing less than 1 atomic percent of elements other than copper. Such impurities may particularly include oxygen, carbon, and nitrogen.

[0054] The first electrodeposition step may include one or more polarization steps, performed at a temperature between 20°C and 30°C. Those familiar with this technique should know how to select the variables of the steps based on common sense.

[0055] It can be performed using at least one polarization mode selected from the group consisting of: ramp mode, constant current mode and current pulse mode.

[0056] According to one embodiment, the polarization of the conductive surface is performed in a pulsed mode by applying a unit area current in the range of 3 mA / cm2 to 25 mA / cm2 at a frequency in the range of 5 kHz to 15 kHz, and by applying a zero current cycle at a frequency in the range of 1 kHz to 10 kHz.

[0057] The conductive surface can be brought into contact with the electrolyte before or after polarization. Preferably, the contact is made before energization.

[0058] The first electrodeposition step is stopped when the alloy deposit covers the flat surface of the substrate to a thickness between 50 nm and 400 nm, for example, between 125 nm and 300 nm. The alloy deposit corresponds to an alloy block deposited in the hollow volume of the cavity but not completely filling it, or a combination of an alloy block that fills the entire hollow volume of the cavity and an alloy block covering the surface of the substrate, or an alloy block that only corresponds to the upper half of the copper deposit covering the surface of the substrate and filling the cavity, which is generated in a step prior to the first electrodeposition step.

[0059] The deposition rate of the copper alloy can be between 0.1 nm / s and 6.0 nm / s, preferably between 1.0 nm / s and 3.0 nm / s, and even more preferably between 1 nm / s and 2.5 nm / s.

[0060] The method of the present invention includes a second step of annealing the copper alloy deposit obtained at the end of the first electrodeposition step.

[0061] This annealing heat treatment can be carried out at a temperature between 50°C and 550°C, preferably under a reducing gas such as N2 containing 4% H2.

[0062] The low impurity content, coupled with a very low porosity percentage, produces copper deposits with low resistivity.

[0063] During the annealing step, manganese or zinc atoms separate from copper, resulting in the formation of two layers: a first layer that substantially contains copper, and a second layer that substantially contains manganese, zinc and / or their oxides.

[0064] The conductive surface in contact with the electrolyte may be the surface of a metal seed layer, which is covered by an insulating dielectric material and itself is covered by polycrystalline silicon. In this embodiment, manganese or zinc atoms migrate via the seed layer to the interface between the seed layer and the dielectric insulating material during the annealing step.

[0065] The layer substantially comprising manganese, zinc and / or their oxides is preferably a continuous and conformal layer with an average thickness in the range of 0.5 nm to 2 nm. "Continuous" means that the layer covers the entire surface of the dielectric substrate without making it flush. "Conformal" means that the thickness of the layer is preferably ±10% relative to its average thickness.

[0066] At the end of the second annealing step, the total impurity content of the first copper layer obtained by the method of the present invention should preferably be less than 1 atomic%. The impurities mainly include oxygen, followed by carbon and nitrogen. The total carbon and nitrogen content is preferably less than 300 ppm.

[0067] The method of the present invention may include a preparatory step of reducing plasma treatment to reduce native metal oxides present on the surface of a metal layer. Preferably, the first electrodeposition step is performed immediately after the plasma treatment to minimize the recombination of native oxides.

[0068] The method of the present invention may also include the step of generating metal contacts selected from tungsten, molybdenum, cobalt and ruthenium, the contact generation step being performed before the deposition of the metal layer described above. This metal contact formation step can be performed by methods known to those skilled in the art.

[0069] A 3D-NAND device obtained using the method of the present invention may include at least one copper diffusion barrier material disposed between copper and an insulating material, the barrier material comprising zinc or manganese.

[0070] In the context of this invention, "3D-NAND flash memory" means vertically integrated memory, such as Bit-Cost Scalable® (BiCS) commercial reference memory, tubular Bit-Cost Scalable® (P-BiCS) commercial reference memory, Terabit Cell Array Transistor (TCAT) and vertical NAND (V-NAND) memory.

[0071] A 3D-NAND flash memory according to the prior art reproduced in FIG1 may include - a silicon substrate 10 covered by a stack 20 of layers located in a horizontal plane, the stack alternating between silicon dioxide layers 20a and conductive metal layers constituting word lines 20b, - at least one polysilicon channel 30 that vertically passes through the stack 20 of layers, and - at least one copper bit line 40 located in a plane parallel to and above the stack of layers, the polysilicon channel 30 and the copper bit line 40 being electrically connected by metal contacts 50, the polysilicon channel 30 and the word line 20b being separated by a charge storage region 60 typically containing silicon nitride (ONO), and the copper bit line 40 being separated from the metal contacts 50 by a copper diffusion barrier material 90 typically containing tantalum nitride or titanium nitride.

[0072] This invention relates to a method for replacing, at least partially, a copper diffusion barrier material 90 used in the prior art with another copper diffusion barrier material comprising zinc, manganese, or oxides thereof. This increases the conductivity between the copper bit line 40 and the polysilicon channel. Specifically, the method allows the removal of the barrier layer 90 of the prior art. In a particular embodiment, the method of the present invention allows the deposition of a layer comprising a zinc or manganese-based material at least on the vertical walls of the copper bit line, and, if applicable, on the bottom of the copper bit line, the properties of which can vary depending on its position on the surface of the copper wire. For example, the zinc or manganese-based material deposited on the walls of the copper wire may have a copper diffusion barrier function. For example, no zinc or manganese-based material will be deposited on the bottom of the copper wire so that the copper will contact the metal contact. Finally, the zinc or manganese-based material may be deposited on the bottom of the copper wire at the interface with the metal contact, and the layer does not provide a barrier function. All such options will depend on the chemical properties of the deposited zinc or manganese material. Specifically, zinc oxide or manganese oxide, when deposited to a sufficient thickness, will act as a copper diffusion barrier.

[0073] 3D-NAND flash memory (a schematic diagram of which is shown in Figure 1) can be fabricated using prior art methods comprising two series of steps. In the first series of steps, metal contacts 50 are generated on the upper half of a polysilicon channel 30, the metal contacts 50 typically being made of molybdenum, tungsten, cobalt, or ruthenium, most typically tungsten. According to a specific method of prior art, the first series of steps including generating the metal contacts comprises: - depositing a silicon dioxide layer on at least the upper half of the polysilicon channel 30 by CVD, followed by photolithography etching of the silicon dioxide to form at least one cavity; - continuously depositing a seed layer of titanium or tantalum on the surface of the cavity by PVD, and continuously depositing a copper diffusion barrier layer, such as titanium nitride or tantalum nitride, using a CVD method; - filling the cavity with tungsten by CVD, and over-depositing tungsten by chemical mechanical polishing (CMP) to obtain the metal contacts 50.

[0074] In the second series of steps of the prior art method, which is partially shown in Figures 2A to 2D, copper bit lines are deposited on the metal contacts obtained from the first series of steps.

[0075] The second series of steps including the formation of copper bit lines 40 on the metal contact 50 may particularly include: - a step of depositing a silicon dioxide layer 70 on the metal contact 50 by PECVD, followed by a step of etching at least one trench 80 in the silicon dioxide layer 70, the etching step causing the surface 50a of the metal contact to be flush with the bottom of the trench 80, as shown in FIG2A; and - a step of depositing a copper diffusion barrier layer 90 (typically tantalum nitride) on the walls and bottom of the trench 80 by PECVD, as shown in FIG2B; - a step of depositing a copper seed layer 100 on the copper diffusion barrier layer 90 by PECVD, as shown in FIG2C; and then - a step of filling the remaining void volume in the trench with copper by electrodeposition, followed by a step of chemical mechanical polishing to over-deposit copper to form the copper bit lines 40 shown in FIG2D.

[0076] Specific examples of the method for fabricating 3D-NAND flash memory according to the present invention are shown in Figures 3A to 3C. These figures illustrate a first variation of the method of the present invention described above, according to which a first step of electrodepositing a copper-doped metal alloy results in the complete filling of the trench volume.

[0077] In FIG. 3A, a substrate is provided comprising: - a stack 20 of layers in a horizontal plane, the stack alternating between silicon dioxide layers 20a and conductive metal layers constituting word lines 20b; - at least one polysilicon channel 30 vertically penetrating the stack 20 of layers; - metal contacts 50 located on the upper half of the polysilicon channel 30; and trenches cut into dielectric layers 70 to create a hybrid surface comprising dielectric surfaces 70a on the walls of the trenches, dielectric surfaces 70b outside the trenches, and surfaces 50a of the metal contacts. The hybrid surface is covered with a thin metal layer 101 to leave void volumes 80b in the trenches.

[0078] As shown in FIG3B, at the end of the first electrodeposition step of the method according to the present invention, an alloy 200 of copper and a doped metal selected from manganese and zinc is electrodeposited on the metal seed layer 101 to fill the volume 80b.

[0079] In Figure 3C, copper and doped metal have been separated by the second step of the method according to the present invention, annealing alloy 200, to form a first layer 110 of copper filling the trench and a second layer 300 containing doped metal and / or its oxide, the second layer 300 being located at the interface between dielectric surface 70a and the first layer 110 of copper.

[0080] Figures 4A to 4C illustrate a second variation of the method of the present invention described above, in which a first step of electrodepositing a copper-doped metal alloy is performed after the volume 80b of the trench is filled with copper according to the prior art method. In this variation, the prior pure copper filling step includes filling the trench with copper, for example by electrodeposition, and then depositing a copper-doped metal alloy on the trench-filled copper according to the aforementioned first electrodeposition step to form a copper-doped metal alloy deposit called a "capping layer".

[0081] A substrate conforming to the one shown in FIG4A and identical to the substrate shown in FIG3A is provided, wherein the substrate specifically includes a metal seed layer 101 and a void volume 80b in a trench.

[0082] As shown in FIG4B, the void volume 80b is filled with copper deposit 400 by a method known to those skilled in the art, for example by electrodeposition using an electrolyte containing copper(II) ions that is the same as or different from the electrolyte used in the first electrodeposition step, the electrolyte further containing doped metal ions, preferably an electrolyte containing only copper(II) ions.

[0083] In FIG4C, at the end of the first electrodeposition step of the method according to the present invention, an alloy 201 of copper and doped metal is deposited on copper deposit 400.

[0084] Next, in the second step of annealing the alloy according to the method of the present invention, the alloy 201 is annealed to cause it to layer and form a first copper layer 111 as shown in FIG. 4D. The first layer 111 includes the amount of copper contained in the seed layer 101 and a portion of the copper in the alloy 201. Annealing also allows the formation of a second layer 301 containing a doped metal and / or its oxide, located at the interface between the dielectric surface (including dielectric surface 70a and dielectric surface 70b) and the first copper layer 111. The second layer containing the doped metal and / or its oxide may or may not cover the surface 50a of the metal contact 50. In FIG. 4D, the dielectric 70 is silicon dioxide, and the second layer 301 containing the doped metal contains zinc oxide or manganese oxide and does not cover the surface 50a of the metal contact.

[0085] The method of the present invention is suitable for generating copper bit lines to fabricate 3D-NAND devices and may include steps for generating polysilicon channels, generating word lines, and generating metal contacts prior to the first electrodeposition step, these steps being performed according to methods known to those skilled in the art. According to an advantageous embodiment of the method of the present invention, at least one step of depositing copper diffusion barrier material by a prior art dry process is replaced by a step of depositing an alloy of copper and a doped metal selected from zinc or manganese, the deposition step being performed according to the first electrodeposition step described above.

[0086] Prior to the first step of electrodepositing a copper-metal alloy, the method of the present invention may include: - a step of depositing a layer of silicon dioxide, followed by - etching the layer to form at least one cavity having sidewalls made of silicon dioxide and a bottom made of a metal contact material, - a step of depositing a metal seed layer consisting of an assembly of a copper or metal adhesive layer (referred to as a "pad") and a copper layer on the walls and bottom of the cavity.

[0087] Another object of the present invention is a use of zinc or manganese in a method for fabricating 3D-NAND flash memory to suppress the insertion of copper diffusion barrier material (typically with high resistance) between metal contacts and copper bit lines. This barrier material is deposited by a dry process and is selected from, for example, tantalum nitride and titanium nitride. The metal contacts electrically connect the polysilicon channels and the copper bit lines in the 3D-NAND flash memory, and the metal contacts comprise contact metals selected from tungsten, molybdenum, cobalt, and ruthenium. The present invention is illustrated by the following examples.

[0088] Example 1: Electrodeposition and annealing of copper-zinc alloy to fill cavities covered with tantalum / copper seed layers and suspended tungsten contacts by electrodeposition on the tantalum / copper seed layer, filling trenches 300 nm wide and 600 nm deep with copper-zinc alloy. This deposition is carried out using a pH 7 composition of a sulfide containing copper(II) ions and an organic salt containing zinc(II) ions in the presence of ethylenediamine.

[0089] A.-Materials and Equipment: Substrate: The substrate used in this example consists of a 4×4 cm silicon sample on which trenches 300 nm wide and 600 nm deep were etched. On the sidewalls, silicon is covered with silicon oxide, which is also covered with a 1 nm thick tantalum layer and contacts a 5 nm thick copper metal layer. At the bottom of the trench, silicon is covered with a thick tungsten layer and contacts a 5 nm thick copper metal layer. The measured resistivity of the substrate is approximately 30 ohms / square. Electrodeposition Solution: In this solution, copper is provided by 16 g / L CuSO4(H2O)5 (64 mM Cu2+) with two molar equivalents of ethylenediamine. Zinc is provided by zinc gluconate to give 25 mM Zn2+. Tetraethylammonium hydroxide (TEAH) is added to adjust the pH of the solution to 7. Equipment: In this example, the electrodeposition equipment consists of two parts: a tank for containing the electrodeposition solution, equipped with a fluid recirculation system for controlling the hydrodynamics of the system, and a rotating electrode equipped with a sample holder suitable for the size of the sample used (4 cm × 4 cm). The electrodeposition tank has two electrodes: a copper anode and a silicon sample coated with a copper metal layer forming the cathode. A reference is connected to the anode. Connectors allow electrical connection of the electrodes, which are connected by wires to a constant potentiometer providing up to 20 V or 2 A.

[0090] B.-Experimental Procedure: Preparatory Steps: The substrate generally does not require any specific treatment unless the native copper oxide layer is significantly affected by the age of the wafer or poor storage. This storage is usually carried out under nitrogen. In this case, it is necessary to perform a hydrogen-containing plasma treatment. Pure hydrogen or a gas mixture containing 4% hydrogen and nitrogen can be used. First Step of Electrodeposition: Polarize the cathode in a current pulse mode with a current range of 10 mA (or 1.4 mA / cm2) to 200 mA (or 28.6 mA / cm2), for example 150 mA (or 21.4 mA / cm2), wherein the pulse duration during cathode polarization is between 5 and 1000 ms, and the zero polarization between two cathode pulses is between 5 and 1000 ms. This step is performed at 60 rpm for 5 minutes. The second step of annealing: Annealing is carried out at 100°C in a hydrogen atmosphere (nitrogen containing 4% hydrogen) for 30 minutes, followed by 350°C for 15 minutes, in order to induce zinc migration on the sidewalls of the trench (which is the interface between SiO2 and copper).

[0091] C-Results: Transmission electron microscopy (TEM) analysis performed after annealing showed defect-free filling of pores on the trench walls, reflecting good copper nucleation and a pore-free structure. The copper layer thickness on this structure was 200 nm. XPS analysis prior to annealing showed a uniform presence of approximately 2 atomic% zinc in the alloy. Similar analyses showed that after annealing, zinc migrated towards both the SiO2-Ta interface and the extreme surfaces, rather than towards the W-copper interface. Furthermore, the total contamination in oxygen, carbon, and nitrogen did not exceed 600 atomic ppm. This integration has the advantage of reducing line resistance and thus optimizing the memory.

[0092] Example 2: Electrodeposition and annealing of copper-zinc alloy to fill cavities covered with copper seed layers and suspended tungsten contacts by electrodeposition on a copper seed layer directly deposited on SiO2, filling trenches 300 nm wide and 600 nm deep with copper-zinc alloy. This deposition was carried out using a pH 7 composition of a sulfide containing copper(II) ions and an organic salt containing zinc(II) ions in the presence of ethylenediamine.

[0093] A.-Materials and Equipment: Substrate: The substrate used in this example consists of a 4×4 cm silicon sample on which trenches 300 nm wide and 600 nm deep were etched. On the sidewalls, the silicon is covered with silicon oxide, which is also in direct contact with a 5 nm thick copper metal layer. At the bottom of the trench, the silicon is covered with a thick tungsten layer and in contact with a 5 nm thick copper metal layer. The measured resistivity of the substrate is approximately 30 ohms / square. Electrodeposition Solution: The electrodeposition solution used is the same as in Example 1. Equipment: The equipment used is the same as in Example 1.

[0094] B. - Experimental Procedure: Preparatory Steps: The substrate does not require any special treatment. First Step of Alloy Electrodeposition: It is the same as in Example 1. Second Step of Annealing: This annealing is the same as in Example 1.

[0095] C - Results Obtained: Transmission electron microscopy (TEM) analysis performed after annealing showed defect-free filling of pores on the trench walls, reflecting good copper nucleation and a pore-free structure. The copper layer thickness on this structure was 200 nm. XPS analysis prior to annealing showed a uniform presence of 2 atomic percent zinc in the alloy. Compared to Example 1, the same type of analysis showed a more significant migration of zinc towards the SiO2-Cu interface after annealing. This integration is the optimal choice for reducing line resistance and thus optimizing the memory.

[0096] Example 3: A copper-filled structure was followed by electrodeposition and annealing of a copper-zinc alloy to achieve a 300 nm so-called "capping layer" deposit. The suspended tungsten contacts were electrodeposited on a copper seed layer, filling trenches 300 nm wide and 600 nm deep with copper. Deposition was performed using a pH 7 composition containing a copper(II) ion sulfide salt of ethylenediamine and thiodiglycolic acid. Next, a 300 nm thick copper-zinc alloy capping layer was electrodeposited onto the copper deposited in the first step. This capping layer was prepared from a pH 7 composition containing a copper(II) ion sulfide salt and an organic salt of zinc(II) ions in the presence of ethylenediamine. A.-Materials and Equipment: Substrate: The substrate used was the same as in Example 2. Electrodeposition Solutions: First Copper Solution: In this solution, copper is provided by 16 g / L CuSO4(H2O)5 (64 mM Cu2+), accompanied by two molar equivalents of ethylenediamine and 50 ppm thiodiglycolic acid for trench filling. TEAH is added to adjust the pH of the solution to 7. Second Copper and Zinc Solution for the Capping Layer: Copper is provided by 16 g / L CuSO4(H2O)5 (64 mM Cu2+), accompanied by two molar equivalents of ethylenediamine. Zinc is provided by zinc gluconate to obtain 25 mM Zn2+. TEAH is added to adjust the pH of the solution to 7.

[0097] Equipment: The equipment used is the same as in Example 1. B.-Experimental Procedure: Preparatory Steps: The substrate does not require any special treatment. 1-Copper Filling: The process is performed as follows: the cathode is polarized in a ramp mode within a current range of 20 mA (or 1.4 mA / cm2) to 120 mA (or 17.1 mA / cm2). For example, the current ramp is between 20 mA (or 2.9 mA / cm2) and 100 mA (or 14.3 mA / cm2), where the slope is between 0.5 and 2 mA / s.

[0098] 2- The conditions for the first electrolysis step of depositing the alloy to form a capping layer are the same as those in Example 1. 2- The second annealing step: This annealing is the same as in Example 1.

[0099] C-Results: Transmission electron microscopy (TEM) analysis performed after annealing showed defect-free filling of pores on the trench walls, reflecting good copper nucleation and a pore-free structure. The copper layer thickness on this structure was 300 nm. XPS analysis before annealing showed the presence of 2 atomic % zinc in the alloy, uniformly present in the thick copper layer. In the structure, the copper is pure copper. The same type of analysis showed, on the one hand, the migration of zinc to the SiO2-Cu interface via pure copper after annealing and towards the extreme surface. On the other hand, the total contamination in oxygen, carbon, and nitrogen did not exceed 600 atomic ppm. This method has the advantage of working with thinner trenches.

[0100] Example 4: Electroplating and annealing of copper-zinc alloy to fill cavities covered with copper seed layers, and suspended nickel-boron contacts by electrodeposition on a copper seed layer directly deposited on SiO2, filling trenches 300 nm wide and 600 nm deep with copper-zinc alloy. This deposition was performed using a pH 7 composition containing a sulfide salt of copper(II) ions and an organic salt of zinc(II) ions in the presence of ethylenediamine. A.-Materials and Equipment: Substrate: The substrate used in this example consisted of a 4 × 4 cm silicon sample on which trenches 300 nm wide and 600 nm deep were etched. On the sidewalls, silicon was coated with silicon oxide, which was also in direct contact with a 5 nm thick copper metal layer. At the bottom of the trench, silicon was covered with a thick NiB layer and in contact with a 5 nm thick copper metal layer. The measured resistivity of the substrate was approximately 30 ohms / square. Electrodeposition Solution: The electroplating solution used was the same as in Example 1. Equipment: The equipment used was the same as in Example 1. B. Experimental Procedure: Preparatory Steps: No special treatment was required for the substrate. 1- The conditions for the first electrolysis step were the same as in Example 1. 2- The second annealing step: This annealing was the same as in Example 1. C- Results: Transmission electron microscopy (TEM) analysis performed after annealing showed defect-free filling of pores on the trench walls, indicating good copper nucleation and a pore-free structure. The thick copper layer on this structure was 200 nm. XPS analysis prior to annealing showed the presence of approximately 2 atomic percent zinc in the alloy. This same type of analysis showed that zinc migrated to the SiO2-Cu interface rather than the NiB-Cu interface after annealing.

[0101] Example 5: A copper-filled structure was followed by electroplating and annealing of a copper-zinc alloy to achieve a 300 nm so-called "capping layer" deposit. Pendant nickel-boron contacts were electrodeposited on a copper seed layer, filling trenches 300 nm wide and 600 nm deep with copper. Deposition was performed using a pH 7 composition containing a copper(II) ion sulfide salt of ethylenediamine and thiodiglycolic acid. Next, a 300 nm thick copper-zinc alloy capping layer was electrodeposited onto the copper deposited in the first step. This capping layer was prepared using a pH 7 composition containing a copper(II) ion sulfide salt and an organic salt of zinc(II) ions in the presence of ethylenediamine. A.-Materials and Equipment: Substrate: The substrate used was the same as in Example 3. Electrodeposition Solution: The two solutions used were the same as in Example 4. Equipment: The equipment used was the same as in Example 1. B.-Experimental Procedure: It was the same as in Example 1. C-Results: Transmission electron microscopy (TEM) analysis performed after annealing showed defect-free filling of pores on the trench walls, indicating good copper nucleation and a pore-free structure. The thick copper layer on this structure is 300 nm. XPS analysis prior to annealing showed 2 atomic % zinc uniformly present in the alloy layer, while the copper in the structure is pure copper. After annealing, the same type of analysis showed zinc migrating through pure copper to the SiO2-Cu interface and towards the extreme surfaces. However, the Cu-NiB interface was intact and undamaged, with no Zn present in NiB. Furthermore, the total contamination of oxygen, carbon, and nitrogen did not exceed 600 atomic ppm. This solution has the advantage of producing copper wires with finer dimensions than previous techniques. [Simplified Explanation of the Diagram]

[0015] Figure 1 shows a perspective view of a prior art 3D-NAND flash memory comprising a barrier material based on tantalum nitride or titanium nitride. Figures 2A to 2D show the steps of a method for fabricating copper bit lines according to a prior art 3D-NAND flash memory. Figures 3A to 3C show a method for fabricating a 3D-NAND flash memory according to the present invention in a "fill" mode. Figures 4A to 4D show a method for fabricating a 3D-NAND flash memory according to the present invention in a "cover" mode.

Claims

1. A method for fabricating 3D-NAND flash memory, the method comprising a first step of electrodepositing an alloy of copper and a doped metal selected from manganese and zinc, the first electrodeposition step comprising contacting a first surface (101a) of a metal layer (101, 400) with an electrolyte containing copper(II) ions and doped metal ions, subsequently polarizing the first surface for a time sufficient to allow a copper-doped metal alloy (200, 201) to cover the first surface, the first electrodeposition step followed by annealing the alloy to delaminate it and form a first layer (110, 111) of copper and a second layer (300, 301) containing the doped metal and / or its oxides, a second step.

2. The method of claim 1, wherein the first layer (110, 111) of the copper forms the copper bit lines of the 3D-NAND flash memory.

3. The method of claim 1, wherein the electrolyte comprising copper(II) ions and doped metal ions has a pH between 6.0 and 10.

0.

4. The method of claim 1 or 2, wherein the metal layer (101, 400) includes a second surface in contact with a mixed surface comprising both insulating regions (70a, 70b) and conductive regions (50a), the insulating regions (70a, 70b) being made of a dielectric material and the conductive regions (50a) being made of a contact metal selected from tungsten, molybdenum, cobalt and ruthenium, the contact metal connecting the copper bit lines (40) and polysilicon channels (30) of the 3D-NAND flash memory.

5. The method of claim 4, wherein during the second step of annealing the alloy, the doped metal migrates to the mixed surface, and the second layer (300, 301) comprising the doped metal and / or its oxide at least covers the insulating region (70a, 70b) of the mixed surface.

6. The method of claim 5, wherein the second layer (300, 301) comprises an oxide of the doped metal and functions as a copper diffusion barrier.

7. The method of claim 4, wherein the metal layer (101) is a metal seed layer composed of copper, copper alloy or tantalum, which has been deposited in a step prior to the first electrodeposition step to contact the mixed surface of the insulating region (70a, 70b) and the conductive region (50a).

8. The method of claim 7, wherein a portion of the first surface (101a) of the metal seed layer is concave, defined by the hollow space (80b) demarcated by the walls and bottom of the trench.

9. The method of claim 8, wherein the hollow trench (80b) has an average width at the opening in the range of 15 nm to 700 nm and an average depth in the range of 30 nm to 500 nm.

10. The method of claim 8, wherein the first step of electrodepositing the copper-doped metal alloy is carried out for a time sufficient to fill the hollow (80b) with the alloy (200).

11. The method of claim 1, wherein the metal layer (400) is a trench-filled copper deposit, and wherein the first step of electrodepositing the copper-doped metal alloy is carried out for a time sufficient to cover the trench-filled copper deposit (400) to form an alloy deposit (201), and the first copper layer (111) formed as a result of the second annealing step is subsequently polished in a third chemical mechanical polishing step.

12. A method of using zinc or manganese to prepare 3D-NAND flash memory to suppress the insertion of copper diffusion barrier material (90) between metal contacts (50) and copper bit lines (40), the barrier material being deposited by a dry process and being selected from tantalum nitride and titanium nitride, the metal contacts (50) being electrically connected to polysilicon channels (30) and copper bit lines (40) in the 3D-NAND flash memory, and the metal contacts (50) comprising contact metals selected from tungsten, molybdenum, cobalt and ruthenium.

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