Light-emitting device

Abstract

A light-emitting element includes: a semiconductor stack comprising a first type semiconductor layer, an active region, and a second type semiconductor layer; a first insulating layer formed on the semiconductor stack and including a plurality of first insulating layer openings and contact holes; a reflective conductive structure formed on the first insulating layer and electrically connected to the second type semiconductor layer through the first insulating layer openings; a second insulating layer formed on the reflective conductive structure and including a plurality of second insulating layer openings, wherein each first insulating layer opening and each second insulating layer opening is staggered; a first bonding pad located on the second insulating layer, with contact holes electrically connected to the first type semiconductor layer; and a second bonding pad located on the second insulating layer and electrically connected to the second type semiconductor layer through the first insulating layer openings.

Description

Technical Field

[0001] This application relates to a light-emitting element, and more specifically, to a light-emitting element for enhancing brightness. Prior Technology

[0002] Solid-state light-emitting elements, such as light-emitting diodes (LEDs), have low power consumption, low heat generation, long lifespan, small size, fast response speed, and good photoelectric properties, such as stable emission wavelength. Therefore, they have been widely used in household appliances, indicator lights, and optoelectronic products.

[0003] A conventional light-emitting diode (LED) comprises a substrate, an n-type semiconductor layer, an active layer, and a p-type semiconductor layer formed on the substrate, and p- and n-electrodes formed on the p-type and n-type semiconductor layers, respectively. When an electric current is applied to the LED through the electrodes and a specific forward bias voltage is applied, holes from the p-type semiconductor layer and electrons from the n-type semiconductor layer recombine in the active region to emit light. However, as LEDs are applied to various optoelectronic products, the brightness specifications of LEDs are also increasing. Improving their brightness is one of the research and development goals of those skilled in the art. Summary of the Invention

[0004] This application discloses a light-emitting element comprising a first type semiconductor layer including a first portion and a second portion; a semiconductor platform including an active region formed on the first portion and a second type semiconductor layer formed on the active region; a peripheral exposed region not covered by the semiconductor platform, exposing the second portion and surrounding the semiconductor platform; a first insulating layer formed on the second type semiconductor layer and including an opening in the first insulating layer; a reflective conductive structure formed on the first insulating layer, filling the opening in the first insulating layer and electrically connected to the second type semiconductor layer; a second insulating layer formed on the reflective conductive structure and including a first group of second insulating layer openings, wherein, viewed from above, the first group of second insulating layer openings does not overlap with the opening in the first insulating layer; a first bonding pad located on the second insulating layer and electrically connected to the first type semiconductor layer; and a second bonding pad located on the second insulating layer and electrically connected to the second type semiconductor layer, wherein, viewed from above, the second bonding pad overlaps with the first group of second insulating layer openings.

[0005] This application discloses a light-emitting element comprising a first type semiconductor layer, including a first portion and a second portion; a semiconductor platform, including an active region formed on the first portion and a second type semiconductor layer formed on the active region; a peripheral exposed region, not covered by the semiconductor platform, exposing the second portion and surrounding the semiconductor platform; a first insulating layer formed on the second type semiconductor layer and including an opening in the first insulating layer; a reflective conductive structure formed on the first insulating layer, filling the opening in the first insulating layer and electrically connected to the second type semiconductor layer; a second insulating layer formed on the reflective conductive structure and having a contact region, wherein the contact region includes a plurality of covering portions and a first group of second insulating layer opening portions surrounding the plurality of covering portions; a first solder pad located on the second insulating layer and electrically connected to the first type semiconductor layer; and a second solder pad located on the second insulating layer and electrically connected to the second type semiconductor layer, wherein the first insulating layer opening includes a first group of openings located within the contact region, and from a top view, the plurality of covering portions are respectively disposed corresponding to the first group of openings, and the first group of second insulating layer opening portions surrounds the first group of openings and does not overlap with the first group of openings.

[0006] This application discloses a light-emitting element comprising a first type semiconductor layer including a first portion and a second portion; a semiconductor platform including an active region formed on the first portion and a second type semiconductor layer formed on the active region; a peripheral exposed area not covered by the semiconductor platform, exposing the second portion and surrounding the semiconductor platform; a first insulating layer formed on the second type semiconductor layer and including a trench; a reflective conductive structure formed on the first insulating layer, filling the trench and electrically connected to the second type semiconductor layer; a first pad located on the reflective conductive structure and electrically connected to the first type semiconductor layer; and a second pad located on the reflective conductive structure and electrically connected to the second type semiconductor layer, wherein the first pad and the second pad are arranged along a first direction, the trench has an extension length in the first direction greater than the length of the first pad or the second pad in the first direction, and the trench is not connected to the peripheral exposed area. Simple Explanation of the Diagram

[0007] [Figure 1A] shows a top view of a light-emitting element 10 according to an embodiment of this application. [Figure 1B] shows a magnified view of one of the upper parts marked C in Figure 1A. [Figure 2A] shows a cross-sectional view of the light-emitting element 10 of one embodiment of Figure 1 along line A-A' of this application. [Figure 2B] shows a cross-sectional view of the light-emitting element 10 of one embodiment of Figure 1 along line B-B' of this application. [Figures 3 to 18B] show top views and cross-sectional views at various stages of a method for manufacturing a light-emitting element 10 according to an embodiment of this application. [Figures 19A to 19E] show top views of light-emitting elements 11 to 15 in various embodiments of this application. [Figure 20A] shows a top view of a light-emitting element 20 according to an embodiment of this application. [Figure 20B] shows a cross-sectional view of the light-emitting element 20 of one embodiment of Figure 20A of this application along line A-A'. [Figures 21A and 21B] show top views of light-emitting elements 21 and 22 in various embodiments of this application. [Figure 22] shows a top view of a light-emitting element 30 according to an embodiment of this application. [Figure 23A] shows a cross-sectional view of the light-emitting element 30 of one embodiment of Figure 22 of this application along line A-A'. [Figure 23B] shows a cross-sectional view of the light-emitting element 30 of one embodiment of Figure 22 of this application along line B-B'. [Figure 24] shows a top view of a light-emitting element 31 according to an embodiment of this application. [Figure 25] shows a schematic diagram of a light-emitting package 1P according to an embodiment of this application. [Figure 26] shows a schematic diagram of a light-emitting package 2P according to an embodiment of this application. [Figure 27] shows a schematic diagram of a light-emitting package 3P according to an embodiment of this application. [Figure 28] shows a schematic diagram of a light-emitting device 1A according to an embodiment of this application. [Figure 29] shows a schematic diagram of a light-emitting device 2A according to an embodiment of this application. [Figure 30] shows a schematic diagram of a light-emitting device 3A according to an embodiment of this application. [Figure 31] shows a schematic diagram of a light-emitting device 4A according to an embodiment of this application. Implementation

[0008] The following detailed description of exemplary embodiments of the present invention, with reference to illustrations, is intended to enable those skilled in the art to fully understand the spirit of the invention. The present invention is not limited to the following embodiments, but may be implemented in other forms. Ordinal numbers used in this specification, such as "first," "second," and "third," are used to modify elements and do not inherently imply any prior ordinal number for that element, nor do they represent the order of one element with another, or the order of manufacturing methods. The use of these ordinal numbers is solely to clearly distinguish elements with the same name. Furthermore, the dimensions, materials, shapes, relative arrangements, etc., of the constituent parts described in the embodiments are not limited to these descriptions and are merely illustrative. The size or positional relationships of the components shown in the illustrations may be exaggerated for clarity. Additionally, other layers / structures or steps may be incorporated into the following embodiments. For example, the description "forming a second layer / structure on a first layer / structure" can include embodiments where the first layer / structure directly contacts the second layer / structure, or embodiments where the first layer / structure indirectly contacts the second layer / structure, i.e., other layers / structures exist between the first and second layers / structures. Furthermore, the spatial relationship between the first and second layers / structures can change depending on the operation or use of the device. The first layer / structure itself is not limited to a single layer or structure; the first layer can contain multiple sublayers, and the first structure can contain multiple substructures. In this specification, some identical symbols represent elements having the same or similar structure, function, or principle, and can be deduced by those skilled in the art based on the teachings of this specification. For the sake of brevity, elements with identical symbols will not be repeated.

[0009] Figure 1A shows a top view of a light-emitting element 10 according to an embodiment of this application. Figure 2A shows a cross-sectional view along line A-A' in Figure 1A. Figure 2A shows a cross-sectional view along line B-B' in Figure 1A. Figures 3 to 18B show top views and cross-sectional views at various stages of the manufacturing method of the light-emitting element 10 according to an embodiment of this application. The manufacturing method of the light-emitting element 1 is described in detail below. First, referring to Figures 3, 4A, and 4B, a first type semiconductor layer 110n is formed on a substrate 100, and an active region 110a and a second type semiconductor 110p are sequentially formed on the first type semiconductor layer 110n. Figure 3 is a top view after the above steps in the manufacturing method of the light-emitting element 10 are completed, and Figures 4A and 4B show cross-sectional views along line A-A' and line B-B' in Figure 3, respectively. The substrate 100 may be a wafer, and the first type semiconductor layer 110n, the active region 110a, and the second type semiconductor 110p formed thereon constitute a semiconductor wafer. The semiconductor wafer is separated into a plurality of light-emitting elements 10 after a subsequent dicing process. The following embodiment illustrations and descriptions will use a single light-emitting element 10 as an example.

[0010] The substrate 100 may be a growth substrate, including a gallium arsenide (GaAs) substrate and a gallium phosphide (GaP) substrate for growing gallium indium phosphide (AlGaInP), or a sapphire (Al₂O₃) substrate, a gallium nitride (GaN) substrate, a silicon carbide (SiC) substrate, and an aluminum nitride (AlN) substrate for growing indium gallium nitride (InGaN) or aluminum gallium nitride (AlGaN). The substrate 100 includes a substrate upper surface 100s. The substrate 100 may be a patterned substrate, i.e., the substrate upper surface 100s has a patterned structure (not shown). In one embodiment, light emitted from the active region 110a can be refracted by the patterned structure of the substrate 100, thereby increasing the brightness of the light-emitting element. In one embodiment, the patterned structure mitigates or suppresses misalignment caused by lattice mismatch between the substrate 100 and the first type semiconductor layer 110n, the active region 110a, and the second type semiconductor layer 110p, thereby improving epitaxial quality.

[0011] In one embodiment of this application, the method for forming a first type semiconductor layer 110n, an active region 110a, and a second type semiconductor layer 110p on a substrate 100 includes metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or ion plating, such as sputtering or evaporation.

[0012] In one embodiment, a buffer structure (not shown) may be formed before forming the first type semiconductor layer 110n on the substrate 100. The buffer structure can further reduce the lattice mismatch and suppress dislocations, thereby improving the epitaxial quality. The material of the buffer layer includes materials suitable for the epitaxial growth of the semiconductor stack, such as GaN, AlGaN, or AlN. The method for forming the buffer structure includes metal-organic chemical vapor deposition (MOCVD), molecular beam epitaxy (MBE), hydride vapor phase epitaxy (HVPE), or ion plating, such as sputtering or evaporation. In one embodiment, the buffer structure includes multiple sublayers (not shown). The sublayers may be made of the same material or different materials. In one embodiment, the buffer structure includes two sublayers, wherein the first sublayer is grown by sputtering and the second sublayer is grown by MOCVD. In one embodiment, the buffer layer further includes a third sublayer. The third sublayer is grown by MOCVD, and the growth temperature of the second sublayer is higher or lower than the growth temperature of the third sublayer. In one embodiment, the first, second, and third sublayers comprise the same material, such as AlN, or different materials, such as AN, GaN, or AlGaN. In one embodiment of this application, the first type semiconductor layer 110n and the second type semiconductor layer 110p, for example, cladding layers or confinement layers, have different conductivity types, electrical properties, polarities, or doping elements for providing electrons or holes. For example, the first type semiconductor layer 110n is an n-type semiconductor, and the second type semiconductor layer 110p is a p-type semiconductor. An active region 110a is formed between the first type semiconductor layer 110n and the second type semiconductor layer 110p. Electrons and holes combine in the active region 110a under the drive of current, converting electrical energy into light energy to emit light. The wavelength of the light emitted by the light-emitting element 10 can be adjusted by changing the physical properties and chemical composition of one or more of the layers.

[0013] The materials of the first type semiconductor layer 110n, the active region 110a, and the second type semiconductor layer 110p include group III-V semiconductor materials such as AlxInyGa(1-xy)N or AlxInyGa(1-xy)P, where 0≤x, y≤1; x+y≤1. Depending on the material of the active region 110a, when the material of the active region 110a is from the AlInGaP series, it can emit red light with wavelengths between 610nm and 650nm or yellow light with wavelengths between 550nm and 570nm. When the material of the active region 110a is from the InGaN series, it can emit blue or deep blue light with wavelengths between 400nm and 490nm or green light with wavelengths between 490nm and 550nm. When the material of the active region 110a is from the AlGaN series, it can emit UV light with wavelengths between 400nm and 250nm. The active region 110a can be a single heterostructure (SH), a double heterostructure (DH), a double-side double heterostructure (DDH), or a multi-quantum well (MQW). The material of the active region 110a can be an i-type, p-type, or n-type semiconductor.

[0014] Next, the exposed area formation step is performed, including the formation of a peripheral exposed area E. Figure 3 is a top view after the above steps are completed in the manufacturing method of the light-emitting element 10. Figures 4A and 4B show cross-sectional views along lines A-A' and B-B' in Figure 3, respectively. Referring to Figures 3, 4A, and 4B, two regions, a first portion P1 and a second portion P2, of the first type semiconductor layer 110n are defined. The second type semiconductor layer 110p and the active region 110a on the second portion P2 are removed downward from the upper surface of the second type semiconductor layer 110p, or a portion of the first type semiconductor layer 110n is further etched to a depth to expose the upper surface of the first type semiconductor layer 110n, forming the peripheral exposed area E. In one embodiment, the second portion P2 surrounds the first portion P1. Relative to the peripheral exposed area E, the active region 110a and the second type semiconductor layer 110p on the first portion P1 that have not been removed form a semiconductor platform 110. In one embodiment, the method of removing the second type semiconductor layer 110p and active region 110a on the second portion P2 includes defining the first portion P1 and the second portion P2 with a photomask, and then removing the second type semiconductor layer 110p and active region 110a on the second portion P2 by etching and developing. In this embodiment, the peripheral exposed area E is not covered by the semiconductor platform 110, exposing the second portion P2 of the first type semiconductor layer 110n. Surrounding the semiconductor platform 110, the peripheral exposed area E includes a bottom and sidewalls. The bottom is formed by the upper surface of the second portion P2 where the first type semiconductor layer 110n is exposed, and the sidewalls are formed by the side surfaces of the semiconductor platform 110 and the upper surface of the second portion P2. In one embodiment, the first type semiconductor layer 110n of the second portion P2 surrounding the semiconductor platform 110 can be further removed, exposing the upper surface of the substrate by 100s, forming a walkway area. The walkway divides and defines a plurality of light-emitting units 10, and serves as the location of the pre-dividing lines in the subsequent cutting process. In one embodiment, as shown in FIG3, the outline of the semiconductor platform 110 is wavy, sawtooth, square wave, or other non-linear pattern. The light extraction efficiency of the light-emitting element 10 can be improved by the pattern design of the outline of the semiconductor platform 110.

[0015] Next, referring to Figures 5, 6A, and 6B, a transparent conductive layer 130 is formed. Figure 5 is a top view after the above steps are completed in the manufacturing method of the light-emitting element 10. Figures 6A and 6B show cross-sectional views along lines A-A' and B-B' in Figure 5, respectively. The transparent conductive layer 130 covers the upper surface of the second type semiconductor layer 110p and is in electrical contact with the second type semiconductor layer 110p. In this embodiment, the edge of the transparent conductive layer 130 is recessed within the edge of the adjacent second type semiconductor layer 110p. The transparent conductive layer 130 can be a metal or a transparent conductive material, wherein the metal can be selected from a thin metal layer with light transmittance, such as gold (Au), aluminum (Al), titanium (Ti), nickel (Ni), chromium (Cr), or alloys or stacks of the above materials. Transparent conductive materials are transparent to the light emitted from the active region 110a, including materials such as graphene, indium tin oxide (ITO), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), zinc oxide (ZnO), or indium zinc oxide (IZO).

[0016] After the transparent conductive layer 130 is formed, referring to Figures 7, 8A, and 8B, a first insulating layer 120 is formed. Figure 7 is a top view after the above steps are completed in the method for manufacturing the light-emitting element 10, and Figures 8A and 8B show cross-sectional views along lines A-A' and B-B' in Figure 7, respectively. The first insulating layer 120 is formed on the second type semiconductor layer 110p. In one embodiment, the first insulating layer 120 is formed on the upper surface of the transparent conductive layer 130, extending to cover a portion of the second type semiconductor layer 110p, the side surface of the second portion P2 of the first type semiconductor layer 110n, a portion of the bottom and sidewalls in the peripheral exposed area E, and the upper surface 100s of the substrate 100 periphery. The first insulating layer 120 includes a first insulating layer opening 120c located on the second type semiconductor layer 110p, exposing a portion of the second type semiconductor layer 110p, and / or the transparent conductive layer 130. The first insulating layer 120 is transparent to light emitted from the active region 110a, and its material is a non-conductive material, including organic or inorganic materials. The organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, polyimide, or fluorocarbon polymer. Inorganic materials include, for example, silicone, glass, or dielectric materials. Dielectric materials include, for example, silicon oxide (SiNx), silicon nitride (SiOx), silicon oxynitride (SiOxNy), niobium oxide (Nb2O5), tantalum oxide (Ta2O5), hafnium oxide (HfO2), titanium oxide (TiOx), magnesium fluoride (MgF2), and aluminum oxide (Al2O3). The first insulating layer 120 can be formed by stacking multiple sublayers. In one embodiment, multiple sublayers are formed of dielectric materials, including silicon-containing materials such as silicon oxide (SiO₂x), silicon nitride (SiN₂x), or silicon oxynitride (SiOₓN₂y), metal oxides such as tantalum oxide (Ta₂O₅), niobium oxide (Nb₂O₅), hafnium oxide (HfO₂), titanium oxide (TiO₂x), or aluminum oxide (Al₂O₃), and metal fluorides such as magnesium fluoride (MgF₂). By selecting materials with different refractive indices and designing their thicknesses, a material stack is formed to create a reflective structure that provides reflection of light within a specific wavelength range emitted from the active region 110a, such as a distributed Bragg reflector (DBR).The first insulating layer 120 can be formed using methods such as atomic layer deposition (ALD), sputtering, evaporation, and spin-coating. In another embodiment, the first insulating layer 120 is formed only on the upper surfaces of the second type semiconductor layer 110p and the transparent conductive layer 130. Before forming the transparent conductive layer 130 and the first insulating layer 120, a protective insulating layer (not shown) is first formed to cover the side surfaces of the semiconductor platform 110. Specifically, the protective insulating layer covers a portion of the second type semiconductor layer 110p, the side surfaces of the second portion P2 of the first type semiconductor layer 110n, a portion of the bottom and sidewalls in the peripheral exposed area E, and the upper surface 100s of the substrate 100 periphery. Then, the transparent conductive layer 130 and the first insulating layer 120 are formed on the second type semiconductor layer 110p. In this embodiment, the transparent conductive layer 130 can extend onto the portion of the protective insulating layer it covers. Specifically, in one embodiment, the transparent conductive layer 130 may extend to cover a portion of the protective insulating layer, but not beyond the periphery of the semiconductor platform 110. In another embodiment, the transparent conductive layer 130 may extend to cover a portion of the protective insulating layer, and extend beyond the periphery of the semiconductor platform 110 to cover the protective insulating layer of the sidewalls of the semiconductor platform 110.

[0017] Referring to Figures 7, 8A, and 8B, in the step of forming the first insulating layer 120, an insulating material layer can be formed first, and then a first insulating layer opening 120c can be formed by dry etching, wet etching, or lift-off, exposing a portion of the second-type semiconductor layer 110p and / or the transparent conductive layer 130. In this embodiment, viewed from above, the first insulating layer opening 120c includes a trench that is not connected to the surrounding exposed area E. Specifically, the trench endpoints and edges of the first insulating layer opening 120c are spaced apart from the semiconductor platform 110 by a distance. Viewed from above, the trench extends in the first insulating layer 120 to form a fishbone pattern. Specifically, the trench includes a main trunk T1 and a plurality of branches B1, which extend from both sides of the main trunk T1 to form a fishbone pattern on the semiconductor platform 110. In one embodiment, the branches B1 branch from both sides of the main trunk T1 along a direction perpendicular to the extension of the main trunk T1. In one embodiment, the branches B1 on both sides of the main trunk T1 can extend symmetrically or asymmetrically. In one embodiment, the number, length, and / or width of the branches B1 on both sides of the main trunk T1 can be the same or different. The length and / or width of the main trunk T1 and the branches B1 can be the same or different. In one embodiment, the distance between two adjacent branches B1 can be the same or different. In one embodiment, the number of branches B1, the length and width of the main trunk T1 and the branches B1, the distance between two adjacent branches B1, and the ratio of the total top-view area of ​​the trench to the top-view area of ​​the substrate 100 can be designed and adjusted according to size and photoelectric characteristic requirements. In one embodiment, the width of the trench main trunk T1 and the branches B1 can be from 1 micrometer to 20 micrometers. In one embodiment, the distance between two adjacent branches B1 can be from 10 micrometers to 200 micrometers. In one embodiment, the ratio of the total top-view area of ​​the trench to the top-view area of ​​the substrate 100 can be from 1% to 20%. However, this is not limited to the aforementioned numerical range. For example, when applied to low current density products, such as current density less than or equal to 0.21 A / mm², the width of the trench trunk T1 and branch B1 can be smaller, and the spacing between two adjacent branches B1 can be larger. When applied to high current density products, such as current density greater than or equal to 0.42 A / mm², the width of the trench trunk T1 and branch B1 can be larger, and the spacing between two adjacent branches B1 can be smaller.

[0018] Referring to Figures 11, 12A, and 12B, a reflective conductive structure 140 is formed. Figure 11 is a top view after the above steps are completed in the manufacturing method of the light-emitting element 10. Figures 12A and 12B show cross-sectional views along lines A-A' and B-B' in Figure 11, respectively. The reflective conductive structure 140 is formed on the first insulating layer 120 and is electrically connected to the second type semiconductor layer 110p through an opening 120c in the first insulating layer. Externally injected current passes through the reflective conductive structure 140 and is then electrically connected to the second type semiconductor layer 110p via a trench to achieve a uniform current distribution. In one embodiment, the first insulating layer 120 covers the side surfaces of the first type semiconductor layer 110n and the semiconductor platform 110, which can protect the first type semiconductor layer 110n and the semiconductor platform 110 and prevent damage to the first type semiconductor layer 110n and the semiconductor platform 110 in subsequent processes, or short circuits caused by dissimilar electrical contacts. In one embodiment, the reflective conductive structure 140 may comprise a single metal layer or a stack of multiple metal layers, and the first insulating layer 120 may comprise a single layer or a stack of multiple layers, such as a distributed Bragg reflector. The reflective conductive structure 140 and the first insulating layer 120 form an omnidirectional reflector (ODR) to enhance light reflection and the brightness of the light-emitting element 10. In one embodiment, the ratio of the total top-view area of ​​the overlapping portion of the reflective conductive structure 140 and the first insulating layer 120 to the top-view area of ​​the semiconductor platform 110 may be 80% to 99%. In one embodiment, the reflective conductive structure 140 includes a barrier layer (not shown) and a reflective layer (not shown). The barrier layer is formed and covers the reflective layer, and the barrier layer can prevent the migration, diffusion, or oxidation of metal elements in the reflective layer. The reflective layer is made of a metallic material with high reflectivity to light emitted from the active region 110a, such as silver (Ag), gold (Au), aluminum (Al), titanium (Ti), chromium (Cr), copper (Cu), nickel (Ni), platinum (Pt), ruthenium (Ru), tungsten (W), or alloys or stacks of the above materials. The barrier layer is made of chromium (Cr), aluminum (Al), platinum (Pt), titanium (Ti), tungsten (W), zinc (Zn), or alloys or stacks of the above materials. In one embodiment, when the barrier layer is a metal stack, the barrier layer is formed by alternating stacks of two or more metals, such as Cr / Pt, Cr / Ti, Cr / TiW, Cr / W, Cr / Zn, Ti / Al, Ti / Pt, Ti / W, Ti / TiW, Ti / Zn, Pt / TiW, Pt / W, Pt / Zn, TiW / W, TiW / Zn, or W / Zn, etc. In one embodiment, the edge of the reflective conductive structure 140 is recessed within the edge of the adjacent second type semiconductor layer 110p, and the edge of the transparent conductive layer 130 is recessed within the edge of the adjacent reflective conductive structure 140.In other words, the edge of the reflective conductive structure 140 is spaced from the edge of the adjacent second-type semiconductor layer 110p, and the edge of the transparent conductive layer 130 is spaced from the edge of the adjacent reflective conductive structure 140.

[0019] In one embodiment, an adhesive layer 121 formation step may be performed before forming the reflective conductive structure 140. Refer to Figures 9, 10A, and 10B. Figure 9 is a top view after the above steps in the manufacturing method of the light-emitting element 10 are completed. Figures 10A and 10B show cross-sectional views along lines A-A' and B-B' in Figure 9, respectively. The adhesive layer 121 is formed on the first insulating layer 120 and fills the opening 120c of the first insulating layer, connecting the second type semiconductor layer 110p and / or the transparent conductive layer 130 via the opening 120c. In one embodiment, the adhesive layer 121 is formed on the first insulating layer 120, or formed on the first insulating layer 120 and extending into the sidewall of the opening 120c of the first insulating layer. In one embodiment, the adhesive layer 121 has an adhesive layer opening (not shown) corresponding to the first insulating layer opening 120c, exposing the second type semiconductor layer 110p and / or the transparent conductive layer 130 through the adhesive layer opening and the first insulating layer opening 120c. In one embodiment, the edge of the adhesive layer 121 is recessed within the edge of the adjacent second type semiconductor layer 110p, and the edge of the transparent conductive layer 130 is recessed within the edge of the adjacent adhesive layer 121. In other words, the edge of the adhesive layer 121 is located on the second type semiconductor layer 110p and spaced apart from the edge of the adjacent second type semiconductor layer 110p by a distance, and the edge of the transparent conductive layer 130 is located on the adhesive layer 121 and spaced apart from the edge of the adjacent adhesive layer 121 by a distance. The adhesive layer 121 can be a metal or a transparent conductive material, wherein the metal can be selected from a thin metal layer with light transmittance, such as gold (Au), aluminum (Al), titanium (Ti), nickel (Ni), chromium (Cr), or alloys or stacks of the above materials. The transparent conductive material is transparent to the light emitted from the active region 110a, and includes materials such as graphene, titanium nitride (TiN), indium tin oxide (ITO), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), zinc oxide (ZnO), or indium zinc oxide (IZO). In one embodiment, when the adhesive layer 121 has an adhesive layer opening (not shown), the adhesive layer 121 can be a dielectric material, such as titanium oxide (TiO₂x) or aluminum oxide (Al₂O₃). In one embodiment, the thickness of the adhesive layer 121 is less than the thickness of the transparent conductive layer 130 to avoid light absorption and affecting the luminous efficiency. In one embodiment, the reflective conductive structure 140 is located on the adhesive layer 121, thereby increasing the adhesion between the reflective conductive structure 140 and the first insulating layer 120.

[0020] Referring to Figures 13, 14A, and 14B, after forming the reflective conductive structure 140, a second insulating layer 150 is formed. Figure 13 is a top view after the above steps are completed in the manufacturing method of the light-emitting element 10. Figures 14A and 14B show cross-sectional views along lines A-A' and B-B' in Figure 13, respectively. The second insulating layer 150 is formed on the reflective conductive structure 140. In one embodiment, the second insulating layer 150 extends from the reflective conductive structure 140 and is formed on the first insulating layer 120, covering the peripheral exposed area E and / or the upper surface 100s of the substrate surrounding the substrate 100. In one embodiment, the second insulating layer 150 is formed on a portion of the reflective conductive structure 140. In one embodiment, the second insulating layer 150 includes a first group of second insulating layer openings 150c1 and / or a second group of second insulating layer openings 150c2 located on the reflective conductive structure 140, and exposes another portion of the reflective conductive structure 140 through the first group of second insulating layer openings 150c1 and / or the second group of second insulating layer openings 150c2. The second insulating layer 150 further includes one or more second peripheral contact holes 150a located on the peripheral exposed area E, and exposes a portion of the second portion P2 of the first type semiconductor layer 110n through the second peripheral contact holes 150a. In the step of forming the second insulating layer 150, an insulating material layer may first be formed on the reflective conductive structure 140, and then one or more first group of second insulating layer openings 150c1, second group of second insulating layer openings 150c2 and one or more second peripheral contact holes 150a may be formed by dry etching, wet etching or lift-off. In one embodiment, viewed from above, the first group of second insulating layer openings 150c1 and / or the second group of second insulating layer openings 150c2 are spaced apart from the first insulating layer opening 120c and do not overlap. In this embodiment, the size, number, and position of the second insulating layer openings can be adjusted according to the specifications of the light-emitting element. For example, the size and number of the second insulating layer openings can be adjusted according to electrical requirements. When the hole size of the second insulating layer openings is larger and the number is greater, the forward voltage of the element can be reduced. In addition, to avoid the overlap between the second insulating layer openings and the first insulating layer opening, which would increase the height difference between the layers, while maintaining the total area of ​​the second insulating layer openings, the height difference can be reduced by increasing the number of second insulating layer openings and reducing the hole size of each second insulating layer opening to avoid the position of the first insulating layer opening. For example, the contact area can be adjusted by forming a first group of second insulating layer openings 150c1 and a second group of second insulating layer openings 150c2.In another embodiment, during the step of forming one or more second peripheral contact holes 150a, the first peripheral contact holes 120a of the first insulating layer 120 can be formed simultaneously with the formation of the second peripheral contact holes 150a. Specifically, during the step of removing a portion of the second insulating layer to form the second peripheral contact holes 150a, the first insulating layer 120 directly below the second peripheral contact holes 150a is also removed to form the first peripheral contact holes 120a, exposing the second portion P2 of the first type semiconductor layer 110n. In one embodiment, a plurality of first peripheral contact holes 120a are disposed on the peripheral exposed area E, and a plurality of second peripheral contact holes 150a are respectively disposed on the peripheral exposed area E corresponding to the positions of the first peripheral contact holes 120a. The second insulating layer 150 is transparent to light emitted from the active area 110a, and its material is a non-conductive material, including organic or inorganic materials. Organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, polyimide, or fluorocarbon polymer. Inorganic materials include, for example, silicone, glass, or dielectric materials. Dielectric materials include, for example, silicon oxide (SiNx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), niobium oxide (Nb₂O₅), tantalum oxide (Ta₂O₅), hafnium oxide (HfO₂), titanium oxide (TiO₂), magnesium fluoride (MgF₂), and aluminum oxide (Al₂O₃). The second insulating layer 150 may be formed by stacking multiple sublayers. In one embodiment, the multiple sublayers are formed of dielectric materials, including silicon-containing materials such as silicon oxide (SiO₂x), silicon nitride (SiN₂x), or silicon oxynitride (SiOₓN₂y), metal oxides such as niobium oxide (Nb₂O₅), tantalum oxide (Ta₂O₅), hafnium oxide (HfO₂), titanium oxide (TiO₂x), or aluminum oxide (Al₂O₃), and metal fluorides such as magnesium fluoride (MgF₂). By selecting materials with different refractive indices and designing their thicknesses, stacking them into material layers constitutes a reflective structure that provides reflection of light within a specific wavelength range emitted by the active region 110a, such as a distributed Bragg reflector (DBR).The second insulating layer 150 can be formed using methods such as atomic layer deposition (ALD), sputtering, evaporation, and spin-coating. In one embodiment, since the second insulating layer 150 covers the side surfaces of the first semiconductor layer 110n and the semiconductor platform 110, it can protect the first semiconductor layer 110n and the semiconductor platform 110, preventing potential damage to the first semiconductor layer 110n and the semiconductor platform 110 in subsequent processes, or the formation of short circuits due to dissimilar electrical contacts.

[0021] After forming the second insulating layer 150, refer to Figures 15, 16A, and 16B to perform a contact layer 160 formation step. Figure 15 is a top view after the above steps in the manufacturing method of the light-emitting element 10 are completed. Figures 16A and 16B show cross-sectional views along lines A-A' and B-B' in Figure 15, respectively. The contact layer 160 is formed on the second insulating layer 150 and includes a first contact layer 161 and a second contact layer 162 separated from each other. The first contact layer 161 covers the first insulating layer 120 and the second insulating layer 150 and extends to the peripheral exposed area E. It contacts the second portion P2 of the first type semiconductor layer 110n through the first peripheral contact hole 120a and the second peripheral contact hole 150a to electrically connect the first type semiconductor layer 110n. The second contact layer 162 contacts the reflective conductive structure 140 via the first group of second insulating layer openings 150c1 and / or the second group of second insulating layer openings 150c2, and is electrically connected to the second type semiconductor layer 110p. In one embodiment, the contact layer 160 further includes a third contact layer 163 located between the first contact layer 161 and the second contact layer 162, and is separated from and electrically isolated from the first contact layer 161 and the second contact layer 162. In one embodiment, viewed from above, the first contact layer 161 surrounds the second contact layer 162 and / or the third contact layer 163. By having the first contact layer 161, which is electrically connected to the first type semiconductor layer 110n, surround the second contact layer 162, which is electrically connected to the second type semiconductor layer 110p, the effect of uniform current diffusion is achieved. In one embodiment, the third contact layer 163 is electrically floating and used as the pin area of ​​the light-emitting element 10, and has a buffer function of absorbing and dispersing welding force. In one embodiment, the third contact layer 163 is connected to the first contact layer 161 or the second contact layer 162, and the third contact layer 163 is electrically connected to the first contact layer 161 or the second contact layer 162. In one embodiment, the contact layer 160 comprises a metallic material, such as silver (Ag), aluminum (Al), chromium (Cr), platinum (Pt), gold (Au), titanium (Ti), tungsten (W), zinc (Zn), or alloys or stacks of the above materials. In one embodiment, the contact layer 160 comprises a reflective metallic layer, such as silver (Ag) or aluminum (Al), and an adhesive layer (not shown) is provided between the reflective metallic layer and the second insulating layer 150 to increase the adhesion between the reflective metallic layer and the second insulating layer 150. In one embodiment, the adhesive layer is formed on the second insulating layer 150 corresponding to the first contact layer 161 and the second contact layer 162, which are separated from each other. In one embodiment, a portion of the adhesive layer covers the first insulating layer 120 and the second insulating layer 150 and extends to the peripheral exposed area E, and contacts the second portion P2 of the first type semiconductor layer 110n via the first peripheral contact hole 120a and the second peripheral contact hole 150a to electrically connect the first type semiconductor layer 110n.In this embodiment, another portion of the adhesive layer contacts the reflective conductive structure 140 via the first group of second insulating layer openings 150c1 and / or the second group of second insulating layer openings 150c2, and is electrically connected to the second type semiconductor layer 110p. In one embodiment, the adhesive layer is formed on the second insulating layer 150 and extends into the sidewalls of the first peripheral contact hole 120a, the second peripheral contact hole 150a, and the second insulating layer openings 150c1 and 150c2, wherein the adhesive layer has an adhesive layer opening (not shown) corresponding to the first peripheral contact hole 120a, the second peripheral contact hole 150a, and the second insulating layer openings 150c1 and 150c2, and the contact layer 160 contacts the first type semiconductor layer 110n via the adhesive layer opening and the first peripheral contact hole 120a and the second peripheral contact hole 150a, and contacts the reflective conductive structure 140 via the adhesive layer opening and the second insulating layer openings 150c1 and 150c2. In one embodiment, the adhesive layer can be a metal or a transparent conductive material. The metal can be selected from a thin, light-transmitting metal layer, such as gold (Au), aluminum (Al), titanium (Ti), nickel (Ni), chromium (Cr), or alloys or stacks of these materials. The transparent conductive material is transparent to the light emitted from the active region 110a and includes materials such as graphene, titanium nitride (TiN), indium tin oxide (ITO), zinc aluminum oxide (AZO), zinc gallium oxide (GZO), zinc oxide (ZnO), or indium zinc oxide (IZO). In one embodiment, when the adhesive layer has an opening, the adhesive layer can be a dielectric material, such as titanium oxide (TiO₂x) or aluminum oxide (Al₂O₃). In one embodiment, the reflective metal layer is silver, and the adhesive layer is indium tin oxide. In one embodiment, the thickness of the adhesive layer is less than the thickness of the transparent conductive layer 130 to avoid light absorption and affecting the luminous efficiency.

[0022] Next, referring to Figures 17, 18A, and 18B, a third insulating layer 170 is formed. Figure 17 is a top view after the above steps in the manufacturing method of the light-emitting element 10 are completed. Figures 18A and 18B show cross-sectional views along lines A-A' and B-B' in Figure 17, respectively. The third insulating layer 170 is formed on the contact layer 160 and extends from the contact layer 160 to the second insulating layer 150, covering the peripheral exposed area E and / or the upper surface 100s of the substrate surrounding the substrate 100. In the step of forming the third insulating layer 170, an insulating material layer may be formed first, and then one or more first pad openings 170a may be formed to expose the first contact layer 161, and one or more second pad openings 170b may be formed to expose the second contact layer 162 by means of dry etching, wet etching, or lift-off. In one embodiment, viewed from above, the first group of second insulating layer openings 150c1 overlaps with and is located within the second solder pad opening 170b, while the second group of second insulating layer openings 150c2 does not overlap with and is located outside the second solder pad opening 170b. In this embodiment, in the top view, to avoid the second solder pad opening 170b cutting through the second insulating layer opening and causing a height difference at the junction, the first group of second insulating layer openings 150c1 and the second group of second insulating layer openings 150c2 are designed to reduce the aforementioned height difference. In one embodiment, the shapes of the first solder pad opening 170a and the second solder pad opening 170b are different. The third insulating layer 170 is transparent to light emitted from the active region 110a, and its material is a non-conductive material, including organic or inorganic materials. Organic materials include Su8, benzocyclobutene (BCB), perfluorocyclobutane (PFCB), epoxy resin, acrylic resin, cyclic olefin polymer (COC), polymethyl methacrylate (PMMA), polyethylene terephthalate (PET), polycarbonate (PC), polyetherimide, polyimide, or fluorocarbon polymer. Inorganic materials include, for example, silicone, glass, or dielectric materials. Dielectric materials include, for example, silicon oxide (SiNx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), niobium oxide (Nb₂O₅), tantalum oxide (Ta₂O₅), hafnium oxide (HfO₂), titanium oxide (TiO₂), magnesium fluoride (MgF₂), and aluminum oxide (Al₂O₃). The third insulating layer 170 may be composed of multiple sublayers stacked together.In one embodiment, multiple sublayers are formed of dielectric materials, including silicon-containing materials such as silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOₓNy), metal oxides such as niobium oxide (Nb₂O₅), tantalum oxide (Ta₂O₅), hafnium oxide (HfO₂), titanium oxide (TiO₂x), or aluminum oxide (Al₂O₃), and metal fluorides such as magnesium fluoride (MgF₂). By selecting materials with different refractive indices and designing their thicknesses, a material stack is formed to create a reflective structure that provides reflection of light emitted from the active region 110a within a specific wavelength range, such as a distributed Bragg reflector (DBR). The third insulating layer 170 is formed by methods such as atomic layer deposition (ALD), sputtering, evaporation, and spin-coating. In one embodiment, since the third insulating layer 170 covers the side surfaces of the first semiconductor layer 110n, the semiconductor platform 110, and the contact layer 160, it can protect the first semiconductor layer 110n, the semiconductor platform 110, and the contact layer 160, preventing potential damage to the first semiconductor layer 110n, the semiconductor platform 110, and the contact layer 160 in subsequent processes, or preventing short circuits caused by dissimilar electrical contacts.

[0023] After the third insulating layer 170 is formed, please refer to Figures 1A, 2A, and 2B. First pads 181 and 182 are formed at the first pad opening 170a and the second pad opening 170b, respectively, and are electrically connected to the first semiconductor layer 110n and the second semiconductor layer 110p via contact with the first contact layer 161 and the second contact layer 162, respectively. In one embodiment, the first pad 181 and / or the second pad 182 may further cover the third insulating layer 170 to increase the area of ​​the first pad 181 and the second pad 182, thereby increasing the bonding area during subsequent packaging processes. The first pad 181 and the second pad 182 comprise metallic materials, such as chromium (Cr), titanium (Ti), tungsten (W), gold (Au), aluminum (Al), indium (In), tin (Sn), nickel (Ni), platinum (Pt), or a stack or alloy of the above materials. The first bonding pad 181 and the second bonding pad 182 may be composed of a single layer or multiple layers. For example, the first bonding pad 181 and the second bonding pad 182 may include Ti / Al, Ti / Au, Ti / Pt / Au, Cr / Au, Cr / Pt / Au, Ni / Au, Ni / Pt / Au, or Cr / Al / Cr / Ni / Au. In one embodiment, the surfaces of the first bonding pad 181 and the second bonding pad 182 have a plurality of recesses (not shown) corresponding to the openings of the first insulating layer 120, the second insulating layer 150, and the third insulating layer 170. Through these recesses, the bonding force between the bonding pad and the carrier board can be improved in subsequent packaging processes, thereby improving process yield. Finally, the semiconductor wafer is diced along the walkway area to form a plurality of light-emitting elements 10.

[0024] Figure 1A shows a top view of a light-emitting element 10 according to an embodiment of this application. Figure 2A shows a cross-sectional view along line A-A' in Figure 1A. Figure 2B shows a cross-sectional view along line B-B' in Figure 1A. As shown in Figures 1, 2A, and 2B, the light-emitting element 10 includes a substrate 100, a first type semiconductor layer 110n, a semiconductor platform 110, a peripheral exposed area E, a first insulating layer 120, a reflective conductive structure 140, a second insulating layer 150, a contact layer 160, a third insulating layer 170, a first bonding pad 181, and a second bonding pad 182. In one embodiment, the light-emitting element 10 may include a transparent conductive layer 130 located between the semiconductor platform 110 and the first insulating layer 120. In one embodiment, the light-emitting element 10 may include an adhesive layer 121 located between the first insulating layer 120 and the reflective conductive structure 140.

[0025] Specifically, a first type semiconductor layer 110n is located on the substrate 100 and includes a first portion P1 and a second portion P2. In one embodiment, the second portion P2 surrounds the first portion P1. In one embodiment, the first type semiconductor layer 110n does not cover the upper surface 100s of the substrate surrounding the substrate 100. A semiconductor platform 110 is located on the first type semiconductor layer 110n and includes an active region 110a located on the first portion P1 of the first type semiconductor layer 110n and a second type semiconductor layer 110p located on the active region 110a. In this embodiment, the peripheral exposed region E is not covered by the semiconductor platform 110, exposing the second portion P2 of the first type semiconductor layer 110n. Surrounding the semiconductor platform 110, the peripheral exposed region E includes a bottom and a sidewall. The bottom is formed by the upper surface of the exposed second portion P2 of the first type semiconductor layer 110n, and the sidewall is formed by the side surface where the semiconductor platform 110 and the upper surface of the second portion P2 meet. A first insulating layer 120 is located on the second type semiconductor layer 110p. In one embodiment, the first insulating layer 120 is formed on the upper surface of the transparent conductive layer 130, extending to cover a portion of the second type semiconductor layer 110p, the side surface of the second portion P2 of the first type semiconductor layer 110n, a portion of the bottom and sidewalls in the peripheral exposed area E, and the upper surface 100s of the substrate 100 periphery. The first insulating layer 120 includes a first peripheral contact hole 120a and a first insulating layer opening 120c. The first peripheral contact hole 120a is located on the peripheral exposed area E and exposes the second portion P2 of the first type semiconductor layer 110n. The first insulating layer opening 120c is located on the second type semiconductor layer 110p and exposes the second type semiconductor layer 110p, and / or the transparent conductive layer 130. In one embodiment, viewed from above, the first insulating layer opening 120c includes a trench that is not connected to the peripheral exposed area E. Specifically, the trench is spaced a distance from the semiconductor platform 110. Specifically, the trench endpoints and edges of the first insulating layer opening 120c are spaced apart from the semiconductor platform 110 by a distance. The reflective conductive structure 140 is located on the second type semiconductor layer 110p or the transparent conductive layer 130, and is electrically connected to the second type semiconductor layer 110p and / or the transparent conductive layer 130 via the first insulating layer opening 120c. In one embodiment, the edge of the reflective conductive structure 140 is recessed within the edge of the adjacent second type semiconductor layer 110p, and the edge of the transparent conductive layer 130 is recessed within the edge of the adjacent reflective conductive structure 140. In other words, the edge of the reflective conductive structure 140 is located on the second type semiconductor layer 110p and spaced apart from the edge of the adjacent second type semiconductor layer 110p by a distance, the edge of the transparent conductive layer 130 is spaced apart from the edge of the adjacent reflective conductive structure 140, and the edge of the reflective conductive structure 140 is located between the edge of the adjacent second type semiconductor layer 110p and the edge of the adjacent transparent conductive layer 130.In one embodiment, the reflective conductive structure 140 is located on the adhesive layer 121, thereby increasing the adhesion between the reflective conductive structure 140 and the first insulating layer 120. In one embodiment, the adhesive layer 121 is located on the first insulating layer 120, or is located on the first insulating layer 120 and extends into the sidewall of the opening 120c of the first insulating layer, and is electrically connected to the second semiconductor layer 110p and / or the transparent conductive layer 130. In one embodiment, the adhesive layer 121 has an adhesive layer opening (not shown) corresponding to the opening 120c of the first insulating layer, through which the second semiconductor layer 110p and / or the transparent conductive layer 130 are exposed. In one embodiment, the edge of the adhesive layer 121 is recessed within the edge of the adjacent second semiconductor layer 110p, and the edge of the transparent conductive layer 130 is recessed within the edge of the adjacent adhesive layer 121. The second insulating layer 150 is located on the reflective conductive structure 140. In one embodiment, the second insulating layer 150 extends from the reflective conductive structure 140 onto the first insulating layer 120, covering the peripheral exposed area E and / or the upper surface 100s of the substrate surrounding the substrate 100. In one embodiment, the second insulating layer 150 is located on a portion of the reflective conductive structure 140. The second insulating layer 150 includes a first group of second insulating layer openings 150c1 and / or a second group of second insulating layer openings 150c2 located on the reflective conductive structure 140, and exposing a portion of the reflective conductive structure 140 via the first group of second insulating layer openings 150c1 and / or the second group of second insulating layer openings 150c2. In one embodiment, viewed from above, the first group of second insulating layer openings 150c1 and / or the second group of second insulating layer openings 150c2 are spaced apart from the first insulating layer opening 120c and do not overlap. In another embodiment, the second insulating layer 150 includes a second peripheral contact hole 150a located on the peripheral exposed area E and corresponding to the first peripheral contact hole 120a, exposing a second portion P2 of the first type semiconductor layer 110n. In one embodiment, a plurality of first peripheral contact holes 120a are disposed on the peripheral exposed area E, and a plurality of second peripheral contact holes 150a are respectively disposed on the peripheral exposed area E corresponding to the positions of the first peripheral contact holes 120a. In one embodiment, since the first insulating layer 120 and the second insulating layer 150 cover the side surfaces of the first type semiconductor layer 110n and the semiconductor platform 110, they can protect the first type semiconductor layer 110n and the semiconductor platform 110, preventing possible damage to the first type semiconductor layer 110n and the semiconductor platform 110 in subsequent processes, or the formation of short circuits due to dissimilar electrical contacts. The contact layer 160 is located on the second insulating layer 150 and includes a first contact layer 161 and a second contact layer 162 separated from each other.The first contact layer 161 covers the first insulating layer 120 and the second insulating layer 150 and extends to the peripheral exposed area E. It contacts the second portion P2 of the first type semiconductor layer 110n via the first peripheral contact hole 120a and the second peripheral contact hole 150a to electrically connect to the first type semiconductor layer 110n. The second contact layer 162 contacts the reflective conductive structure 140 via the first set of second insulating layer openings 150c1 and / or the second set of second insulating layer openings 150c2 to electrically connect to the second type semiconductor layer 110p. In one embodiment, the contact layer 160 further includes a third contact layer 163 located between the first contact layer 161 and the second contact layer 162, and is separated from and electrically isolated from the first contact layer 161 and the second contact layer 162. In one embodiment, viewed from above, the first contact layer 161 surrounds the second contact layer 162 and / or the third contact layer 163. The first contact layer 161, electrically connected to the first type semiconductor layer 110n, surrounds the second contact layer 162, which is electrically connected to the second type semiconductor layer 110p, to achieve uniform current diffusion. In one embodiment, the third contact layer 163 is electrically floating and serves as the pin area of ​​the light-emitting element 10, providing a buffer function to absorb and disperse welding force. In one embodiment, the third contact layer 163 is connected to the first contact layer 161 or the second contact layer 162, and is electrically connected to the first contact layer 161 or the second contact layer 162. A third insulating layer 170 is located on the contact layer 160 and extends from the contact layer 160 to the second insulating layer 150, covering the peripheral exposed area E and / or the upper surface 100s of the substrate surrounding the substrate 100. The third insulating layer 170 includes a first pad opening 170a exposing the first contact layer 161, and a second pad opening 170b exposing the second contact layer 162. The third insulating layer 170 further covers the sidewalls surrounding the semiconductor platform 110 and the first-type semiconductor layer 110n, and the upper surface 100s of the substrate. A first pad 181 is located in the first pad opening 170a and contacts the first contact layer 161. A second pad 182 is located in the second pad opening 170b and contacts the second contact layer 162. In one embodiment, the first pad 181 and the second pad 182 are located in the first pad opening 170a and the second pad opening 170b, respectively, and extend onto the third insulating layer 170. In one embodiment, viewed from above, the first group of second insulating layer openings 150c1 overlaps with and is located within the second solder pad opening 170b, while the second group of second insulating layer openings 150c2 does not overlap with and is located outside the second solder pad opening 170b. In one embodiment, the first solder pad opening 170a and the second solder pad opening 170b have different shapes.

[0026] In one embodiment, the first contact layer 161 is electrically connected to the first type semiconductor layer 110n via the second peripheral contact hole 150a and the first peripheral contact hole 120a, and the second contact layer 162 is electrically connected to the second type semiconductor layer 110p via the first group of second insulating layer openings 150c1 and the second group of second insulating layer openings 150c2. In one embodiment, the surfaces of the first solder pad 181 and the second solder pad 182 have a plurality of recesses (not shown) corresponding to the openings of the first insulating layer 120, the second insulating layer 150 and the third insulating layer 170. These recesses can improve the bonding force between the solder pad and the carrier board in subsequent packaging processes, thereby improving process yield. In one embodiment, viewed from above, the first solder pad 181 and the second solder pad 182 are arranged along a first direction D1. A first insulating layer opening 120c extends in the first insulating layer 120 along the first direction D1 to form a trench. The trench has an extension length in the first direction D1 greater than the length of the first solder pad 181 or the second solder pad 182 in the first direction D1. In one embodiment, viewed from above, the trench extends along the first direction D1 and overlaps with the first solder pad 181 and the second solder pad 182. Through the aforementioned extension trench design of the first insulating layer opening 120c, while the brightness is improved by forming a reflector of a certain area with the first insulating layer 120 and the reflective conductive structure 140, a uniform current distribution can also be achieved to reduce the positive voltage. Viewed from above, the trench extends in the first insulating layer 120 to form a fishbone pattern. The trench includes a main trunk T1 and a plurality of branches B1, each branch B1 extending from both sides of the main trunk T1 to form a fishbone pattern on the semiconductor platform 110. In one embodiment, the branches B1 branch from both sides of the main trunk T1 along a direction perpendicular to the extension of the main trunk T1. In one embodiment, the branches B1 on both sides of the main trunk T1 may extend symmetrically or asymmetrically. In one embodiment, the number, length, and / or width of the branches B1 on both sides of the main trunk T1 may be the same or different. The length and / or width of the main trunk T1 and the branches B1 may be the same or different. In one embodiment, the distance between two adjacent branches B1 may be the same or different. In one embodiment, the number of branches B1, the length and width of the trunk T1 and branches B1, the distance between adjacent branches B1, the ratio of the total top-view area of ​​the trench to the top-view area of ​​the substrate 100, and the ratio of the top-view area of ​​the overlapping portion of the reflective conductive structure 140 and the first insulating layer 120 to the top-view area of ​​the semiconductor platform 110 can be designed and adjusted according to size and photoelectric characteristic requirements. In one embodiment, the width of the trench trunk T1 and branches B1 can be from 1 micrometer to 20 micrometers. In one embodiment, the distance between adjacent branches B1 can be from 10 micrometers to 200 micrometers. In one embodiment, the ratio of the total top-view area of ​​the trench to the top-view area of ​​the substrate 100 can be from 1% to 20%. In one embodiment, the ratio of the total top-view area of ​​the overlapping portion of the reflective conductive structure 140 and the first insulating layer 120 to the top-view area of ​​the semiconductor platform 110 can be from 80% to 99%.However, this is not limited to the aforementioned numerical range. For example, when applied to low current density products, such as those with a current density less than or equal to 0.21 A / mm², the width of the trench trunk T1 and branch B1 can be smaller, and the spacing between adjacent branches B1 can be larger. Conversely, when applied to high current density products, such as those with a current density greater than or equal to 0.42 A / mm², the width of the trench trunk T1 and branch B1 can be larger, and the spacing between adjacent branches B1 can be smaller.

[0027] Figure 1B shows a magnified top view of a portion marked C in Figure 1A. A boundary O extends along a first direction D1 between the semiconductor platform 110 and the surrounding exposed area E, and the boundary O includes a first convex-concave pattern. Specifically, the outline of the semiconductor platform 110 includes the first convex-concave pattern. The trench formed by the first insulating layer opening 120c extending in the first insulating layer 120 includes an outer segment S1, which is adjacent to the boundary O and extends along the first direction D1, and has a distance d from the boundary O. The outer segment S1 includes a second convex-concave pattern that substantially corresponds to the first convex-concave pattern. Specifically, the protruding portion of the second convex-concave pattern corresponds to the protruding portion of the first convex-concave pattern, and the concave portion of the second convex-concave pattern corresponds to the concave portion of the first convex-concave pattern. The first convex-concave pattern of the boundary O can be wavy, sawtooth, square wave, or other non-linear patterns. The design of the first convex-concave pattern can improve the light extraction efficiency of the light-emitting element 10. In one embodiment, the edge of the first contact layer 161 includes a third convex-concave pattern. The protruding portion of the third convex-concave pattern corresponds to the concave portion of the first convex-concave pattern and / or the second convex-concave pattern. The concave portion of the third convex-concave pattern corresponds to the protruding portion of the first convex-concave pattern and / or the second convex-concave pattern. By designing the protruding portion of the third convex-concave pattern, the first contact layer 161 is electrically connected to the first type semiconductor layer 110n through the first peripheral contact hole 120a and the second peripheral contact hole 150a to achieve the effect of uniform current diffusion, and can also avoid short circuits caused by opposite electrical contacts. In one embodiment, the edge of the first contact layer 161 includes a third convex-concave pattern only in the portion surrounding the first solder pad 181, and the edge of the first contact layer 161 includes a fourth convex-concave pattern in the portion surrounding the second solder pad 182. The protruding portion of the fourth convex-concave pattern corresponds to the protruding portion of the first convex-concave pattern and / or the second convex-concave pattern, and the concave portion of the fourth convex-concave pattern corresponds to the concave portion of the first convex-concave pattern and / or the second convex-concave pattern. The concave portion of the fourth convex-concave pattern allows the first contact layer 161 to be electrically connected to the first semiconductor layer 110n via the first peripheral contact hole 120a and the second peripheral contact hole 150a, thereby achieving uniform current diffusion. In another embodiment, the edge of the first contact layer 161 in the portion surrounding the second solder pad 182 may be a straight line, and the first contact layer 161 is electrically connected to the first semiconductor layer 110n via the first peripheral contact hole 120a and the second peripheral contact hole 150a. With the aforementioned design, the edge of the first contact layer 161 can have a certain linewidth in the portion surrounding the second pad 182, thus avoiding the problem of current congestion.

[0028] Figures 19A to 19E show top views of light-emitting elements 11 to 15 according to various embodiments of this application. The manufacturing process and structure of light-emitting elements 11 to 15 are similar to those of light-emitting element 10. For similar manufacturing processes and structures, please refer to the description and drawings of light-emitting element 10, which will not be repeated here. The differences will be explained later. However, to clearly illustrate the differences, Figures 19A to 19E only show the first insulating layer 120, the first peripheral contact hole 120a, the first insulating layer opening 120c, the second insulating layer 150, the second peripheral contact hole 150a, the first group of second insulating layer openings 150c1, and the second group of second insulating layer openings 150c2. First, referring to Figure 19A, the difference between light-emitting element 11 and light-emitting element 10 is that the outer section S1 is a straight line pattern, which does not include the second concave-convex pattern corresponding to the first concave-convex pattern. Next, as shown in Figure 19B, the difference between light-emitting element 12 and light-emitting element 10 is that, compared to the fishbone pattern formed by the main trunk T1 of the groove formed by the opening 120c of the first insulating layer in the first insulating layer 120 extending perpendicularly to the first direction D1, and branches B1 extending from both sides of the main trunk T1 along the direction perpendicular to the extension of the main trunk T1 (i.e., parallel to the first direction D1), the fishbone pattern is formed by the main trunk T2 of the groove formed by the opening 120c of the first insulating layer in the first insulating layer 120 extending parallel to the first direction D1, and branches B2 extending from both sides of the main trunk T2 along the direction perpendicular to the extension of the main trunk T2 (i.e., perpendicular to the first direction D1). Because the main trunk T2 is located in the center of the light-emitting element 12, current injection can be increased. In one embodiment, the branches B2 on both sides of the main trunk T2 can extend symmetrically or asymmetrically. In one embodiment, the number, length, and / or width of the branches B2 on both sides of the main trunk T2 can be the same or different. The length and / or width of the trunk T2 and branches B2 may be the same or different. In one embodiment, the distance between two adjacent branches B2 may be the same or different. In one embodiment, the number of branches B2, the length and width of the trunk T2 and branches B2, the distance between two adjacent branches B2, the ratio of the total top-view area of ​​the trench to the top-view area of ​​the substrate 100, and the ratio of the total top-view area of ​​the overlapping portion of the reflective conductive structure 140 and the first insulating layer 120 to the top-view area of ​​the semiconductor platform 110 can be designed and adjusted according to size and photoelectric characteristic requirements. In one embodiment, the width of the trench trunk T2 and branches B2 may be from 1 micrometer to 20 micrometers. In one embodiment, the distance between two adjacent branches B2 may be from 10 micrometers to 200 micrometers. In one embodiment, the ratio of the total top-view area of ​​the trench to the top-view area of ​​the substrate 100 may be from 1% to 20%. In one embodiment, the ratio of the total top-view area of ​​the overlapping portion of the reflective conductive structure 140 and the first insulating layer 120 to the top-view area of ​​the semiconductor platform 110 can be 80% to 99%.However, this is not limited to the aforementioned numerical range. For example, when applied to low current density products, such as those with a current density less than or equal to 0.21 A / mm², the width of the trench trunk T2 and branches B2 can be smaller, and the spacing between adjacent branches B2 can be larger. Conversely, when applied to high current density products, such as those with a current density greater than or equal to 0.42 A / mm², the width of the trench trunk T2 and branches B2 can be larger, and the spacing between adjacent branches B2 can be smaller. Referring to Figure 19C, the difference between the light-emitting element 13 and the light-emitting element 10 is that the trench formed by the opening 120c of the first insulating layer extending in the first insulating layer 120 includes an outer frame F3 and a plurality of branches B3. The outer frame F3 is disposed near the edge of the semiconductor platform 110, and the branches B3 extend from the two sides of the outer frame F3 perpendicular to the first direction D1, parallel to the first direction D1, and are staggered to form a forked pattern on the semiconductor platform 110. In one embodiment, the length and / or width of the branches B3 can be the same or different. The widths of the outer frame F3 and branches B3 can be the same or different. In one embodiment, the distance between two adjacent branches B3 can be the same or different. In one embodiment, the number of branches B3, the length and width of the outer frame F3 and branches B3, the distance between two adjacent branches B3, the ratio of the total top-view area of ​​the trench to the top-view area of ​​the substrate 100, and the ratio of the total top-view area of ​​the overlapping portion of the reflective conductive structure 140 and the first insulating layer 120 to the top-view area of ​​the semiconductor platform 110 can be designed and adjusted according to size and photoelectric characteristic requirements. In one embodiment, the width of the trench outer frame F3 and branches B3 can be from 1 micrometer to 20 micrometers. In one embodiment, the distance between two adjacent branches B3 can be from 10 micrometers to 200 micrometers. In one embodiment, the ratio of the total top-view area of ​​the trench to the top-view area of ​​the substrate 100 can be from 1% to 20%. In one embodiment, the ratio of the total top-view area of ​​the overlapping portion of the reflective conductive structure 140 and the first insulating layer 120 to the top-view area of ​​the semiconductor platform 110 can be 80% to 99%. However, it is not limited to the aforementioned numerical range. For example, when applied to low current density products, such as current density less than or equal to 0.21 A / mm², the width of the trench outer frame F3 and the branch B3 can be smaller, and the spacing between two adjacent branches B3 can be larger. When applied to high current density products, such as current density greater than or equal to 0.42 A / mm², the width of the trench outer frame F3 and the branch B3 can be larger, and the spacing between two adjacent branches B3 can be smaller. In Figures 19D and 19E, the difference between the light-emitting elements 14 and 15 and the light-emitting element 10 is that the trenches formed by the opening 120c of the first insulating layer extending in the first insulating layer 120 are respectively a loop pattern and a grid pattern.Referring to Figure 19D, the difference between the light-emitting element 14 and the light-emitting element 10 is that the trench formed by the opening 120c of the first insulating layer extending in the first insulating layer 120 includes an outer frame F4 and an inner loop C4. The outer frame F4 is disposed near the edge of the semiconductor platform 110, and the inner loop C4 extends from the outer frame F4 to form a loop pattern on the semiconductor platform 110. By providing the inner loop C4 inside the outer frame F4, the uniformity of current injection can be improved. In one embodiment, the widths of the outer frame F4 and the inner loop C4 may be the same or different. In one embodiment, the widths of the outer frame F4 and the inner loop C4, the distance between the outer frame F4 and the inner loop C4, the ratio of the total top-view area of ​​the trench to the top-view area of ​​the substrate 100, and the ratio of the total top-view area of ​​the overlapping portion of the reflective conductive structure 140 and the first insulating layer 120 to the top-view area of ​​the semiconductor platform 110 can be designed and adjusted according to size and photoelectric characteristic requirements. In one embodiment, the width of the trench outer frame F4 and the inner back portion C4 can be from 1 micrometer to 20 micrometers. In one embodiment, the spacing between the outer frame F4 and the inner back portion C4 can be from 10 micrometers to 200 micrometers. In one embodiment, the ratio of the total top-view area of ​​the trench to the top-view area of ​​the substrate 100 can be from 1% to 20%. In one embodiment, the ratio of the total top-view area of ​​the overlapping portion of the reflective conductive structure 140 and the first insulating layer 120 to the top-view area of ​​the semiconductor platform 110 can be from 80% to 99%. However, this is not limited to the aforementioned numerical range. For example, when applied to low current density products, such as those with a current density less than or equal to 0.21 A / mm², the width of the trench outer frame F4 and the inner return portion C4 can be smaller, and the spacing between the outer frame F4 and the inner return portion C4 can be larger. Conversely, when applied to high current density products, such as those with a current density greater than or equal to 0.42 A / mm², the width of the trench outer frame F4 and the inner return portion C4 can be larger, and the spacing between the outer frame F4 and the inner return portion C4 can be smaller. In one embodiment, as shown in FIG19D, the trench extending in the first insulating layer 120 includes a fifth convex-concave pattern, wherein the fifth convex-concave pattern is formed corresponding to the position of the first convex-concave pattern of the semiconductor platform 110. In one embodiment, as shown in FIG19D, the tail portion of the extended trench includes a straight line segment extending parallel to the first direction D1, the straight line segment having an extension length in the first direction D1 greater than the length of the first pad 181 or the second pad 182 in the first direction D1. In one embodiment, as shown in FIG19D, the first group of second insulating layer openings 150c1 of the light-emitting element 14 is offset from the first insulating layer opening 120c, and the shape of the first group of second insulating layer openings 150c1 conforms to the groove extension shape of the first insulating layer opening 120c and extends to form one or more U-shapes.Referring to Figure 19E, the difference between the light-emitting element 15 and the light-emitting element 10 is that the trench formed by the opening 120c in the first insulating layer 120 includes an outer frame F5, a plurality of warp portions V5, and a plurality of weft portions H5. The outer frame F5 is disposed adjacent to the edge of the semiconductor platform 110. The warp portions V5 extend from the outer frame F5 perpendicular to the first direction D1, and the weft portions H5 extend from the outer frame F5 parallel to the first direction D1. The outer frame F5, the warp portions V5, and the weft portions H5 form a grid pattern on the semiconductor platform 110. By providing the warp portions V5 and the weft portions H5 within the outer frame F5, the current contact area can be increased. In one embodiment, the widths of the outer frame F5, the warp portions V5, and the weft portions H5 may be the same or different. In one embodiment, the distance between two adjacent warp portions V5 and / or two adjacent weft portions H5 may be the same or different. In one embodiment, the widths of the outer frame F5, warp portion V5, and weft portion H5, the distance between two adjacent warp portions V5 and two adjacent weft portions H5, the ratio of the total top-view area of ​​the trench to the top-view area of ​​the substrate 100, and the ratio of the total top-view area of ​​the overlapping portion of the reflective conductive structure 140 and the first insulating layer 120 to the top-view area of ​​the semiconductor platform 110 can be designed and adjusted according to size and photoelectric characteristic requirements. In one embodiment, the widths of the trench outer frame F5, warp portion V5, and weft portion H5 can be from 1 micrometer to 20 micrometers. In one embodiment, the distance between two adjacent warp portions V5 and two adjacent weft portions H5 can be from 10 micrometers to 200 micrometers. In one embodiment, the ratio of the total top-view area of ​​the trench to the top-view area of ​​the substrate 100 can be from 1% to 20%. In one embodiment, the ratio of the total top-view area of ​​the overlapping portion of the reflective conductive structure 140 and the first insulating layer 120 to the top-view area of ​​the semiconductor platform 110 can be from 80% to 99%. However, this is not limited to the aforementioned numerical ranges. For example, when applied to low current density products, such as those with a current density less than or equal to 0.21 A / mm², the widths of the groove frame F5, warp V5, and weft H5 can be smaller, while the spacing between two adjacent warp V5 sections and two adjacent weft H5 sections can be larger. Conversely, when applied to high current density products, such as those with a current density greater than or equal to 0.42 A / mm², the widths of the groove frame F5, warp V5, and weft H5 can be larger, while the spacing between two adjacent warp V5 sections and two adjacent weft H5 sections can be smaller.

[0029] Figures 20A and 20B show a top view and a cross-sectional view of the light-emitting element 20 according to an embodiment of this application, respectively. The manufacturing process and structure of the light-emitting element 20 are similar to those of the light-emitting element 10. For similar manufacturing processes and structures, please refer to the description and drawings of the light-emitting element 10, which will not be repeated here. The differences will be explained later. As shown in Figures 20A and 20B, the first type semiconductor layer 110n further includes one or more third portions P3. In one embodiment, the first portion P1 surrounds the third portion P3. The active region 110a and the first type semiconductor layer 110n on the third portion P3 are removed downward from the upper surface of the second type semiconductor layer 110p, or a portion of the first type semiconductor layer 110n is further etched to a depth to expose the upper surface of the first type semiconductor layer 110n, forming one or more semiconductor platform openings 210a, exposing the third portion P3 of the first type semiconductor layer 110n, which is surrounded by the semiconductor platform 110. The first insulating layer 120 and the second insulating layer 150 further include one or more first internal contact holes 220a and second internal contact holes 250a respectively, which are disposed corresponding to the semiconductor platform opening 210a, and expose the third portion P3 of the first type semiconductor layer 110n. In one embodiment, the first internal contact holes 220a and second internal contact holes 250a are formed in the same process as the first peripheral contact holes 120a and second peripheral contact holes 150a. In one embodiment, the first contact layer 160 is electrically connected to the first type semiconductor layer 110n via the first internal contact holes 220a and second internal contact holes 250 to achieve the effect of uniform current diffusion. The transparent conductive layer 130, the adhesive layer 121 and the reflective conductive structure 140 further include one or more transparent conductive layer openings 230a, adhesive layer openings 221a and reflective conductive structure openings 240a respectively, which are disposed corresponding to the semiconductor platform opening 210a, and expose the third portion P3 of the first type semiconductor layer 110n. In one embodiment, the transparent conductive layer opening 230a, the adhesive layer opening 221a, and the reflective conductive structure opening 240a can be formed by dry etching, wet etching, or lift-off methods after the transparent conductive layer 130, the adhesive layer 121, and the reflective conductive structure 140 are formed.

[0030] Referring to Figures 20A and 20B, the trench formed by the first insulating layer opening 120c extending in the first insulating layer 120 includes a main trunk T1 and an outer side segment S1, an inner side segment S2, and a connecting segment S3 extending from the main trunk T1. The inner side segment S2 extends along a first direction D1, the outer side segment S1 is located between the boundary O and the inner side segment S2, and the connecting segment S3 extends perpendicular to the first direction D1 to connect with the inner side segment S2. The area of ​​the trench can be adjusted by increasing or decreasing the connecting segment S3, thereby adjusting the forward voltage of the light-emitting element. In one embodiment, viewed from above, the inner side segment S2 does not overlap with the semiconductor platform opening 210a. In another embodiment, viewed from above, the inner side segment S2 is disconnected corresponding to the semiconductor platform opening 210a. In one embodiment, viewed from above, the first insulating layer opening 120c does not overlap with the reflective conductive structure opening 240a, and consequently, it also does not overlap with the transparent conductive layer opening 230a, adhesive layer opening 221a, first internal contact hole 220a, and second internal contact hole 250 within the reflective conductive structure opening 240a. As shown in Figures 20A and 20B, the second insulating layer 150 of the light-emitting element 20 includes one or more second sets of second insulating layer openings 150c2. In one embodiment, viewed from above, the second set of second insulating layer openings 150c2 does not overlap with the second solder pad 182. In one embodiment, viewed from above, the second set of second insulating layer openings 150c2 are arranged around the second solder pad 182 in a staggered manner with the first insulating layer opening 120c to form a dashed ring pattern. In one embodiment, the second insulating layer 150 of the light-emitting element 20 does not include second insulating layer openings that overlap with the second solder pad 182. In one embodiment, the area where the first pad 181 and / or the second pad 182 are located can avoid the semiconductor platform opening 210a, so as to avoid possible delamination between the pad and the interface of each layer due to the height difference.

[0031] Figures 21A and 21B show top views of light-emitting elements 21 and 22 in various embodiments of this application. The manufacturing process and structure of light-emitting elements 21 and 22 are similar to those of light-emitting elements 10 and 20. For similar manufacturing processes and structures, please refer to the description and drawings of light-emitting elements 10 and 20, which will not be repeated here. The differences will be explained later. However, to clearly illustrate the differences, Figures 21A and 21B only show the semiconductor platform 110, the first insulating layer 120, the first peripheral contact hole 120a, the first internal contact hole 220b, the first insulating layer opening 120c, the second insulating layer 150, the second peripheral contact hole 150a, the second internal contact hole 250b, and the second set of second insulating layer openings 150c2. Referring to Figures 21A and 21B, the difference between light-emitting elements 21 and 22 and light-emitting element 20 is that the grooves formed by the first insulating layer opening 120c extending in the first insulating layer 120 are respectively a fork pattern and a loop pattern. As shown in Figure 21A, viewed from above, the semiconductor platform opening 210a is positioned between the inner sections S2, ensuring that the inner sections S2 and the semiconductor platform opening 210a do not overlap. As shown in Figure 21B, viewed from above, the inner section S2 has an arc-shaped portion adjacent to the semiconductor platform opening 210a, thus avoiding the semiconductor platform opening 210a and ensuring that the inner section S2 and the semiconductor platform opening 210a do not overlap. In one embodiment, as shown in Figure 21B, the second set of second insulating layer openings 150c2 of the light-emitting element 22 is offset from the first insulating layer opening 120c, and the shape of the second insulating layer opening 150c2 extends in a U-shape conforming to the shape of the first insulating layer opening 120c.

[0032] Figure 22 shows a top view of a light-emitting element 30 according to an embodiment of this application. Figure 23A shows a cross-sectional view along line A-A' in Figure 22. Figure 23B shows a cross-sectional view along line B-B' in Figure 22. The manufacturing process and structure of the light-emitting element 30 are similar to those of the light-emitting elements 10 and 20. For similar manufacturing processes and structures, please refer to the description and drawings of the light-emitting elements 10 and 20, which will not be repeated here. The differences will be explained later. As shown in Figures 22, 23A and 23B, the difference between the light-emitting element 30 and the light-emitting elements 10 and 20 is that the first insulating layer opening 120c includes a plurality of openings distributed on the semiconductor platform 110. The second insulating layer 150 has a contact region R1 located on the reflective conductive structure 140. The contact region R1 includes a plurality of covering portions 351 and a first group of second insulating layer openings 350c surrounding the covering portions 351. A second contact layer 162 is formed on the second insulating layer 150, covering the first group of second insulating layer openings 350c and the covering portions 351 of the contact region R1, and electrically connecting the second type semiconductor layer 110p to the reflective conductive structure 140 via the first group of second insulating layer openings 350c. In one embodiment, the openings included in the first insulating layer opening 120c and the covering portions 351 and the first group of second insulating layer openings 350c included in the contact region R1 can be formed after the first insulating layer 120 and the second insulating layer 150 are formed, respectively, by dry etching, wet etching, or lift-off. In one embodiment, the aperture of the first insulating layer opening 120c can be from 1 micrometer to 20 micrometers. In one embodiment, the distance between two adjacent openings of the first insulating layer opening 120c can be from 1 micrometer to 50 micrometers. However, it is not limited to the aforementioned numerical range. For example, when applied to low current density products, such as current density less than or equal to 0.21 A / mm², the aperture of the first insulating layer opening 120c can be smaller, and the distance between two adjacent openings of the first insulating layer opening 120c can be larger. When applied to high current density products, such as current density greater than or equal to 0.42 A / mm², the aperture of the first insulating layer opening 120c can be larger, and the distance between two adjacent openings of the first insulating layer opening 120c can be smaller. In one embodiment, the light-emitting element 30 may include an adhesive layer 121 formed between the first insulating layer 120 and the reflective conductive structure 140, and may extend into the sidewall of the first insulating layer opening 120c. The adhesive layer 121 has an adhesive layer opening (not shown) corresponding to the first insulating layer opening 120c, through which the second type semiconductor layer 110p and / or the transparent conductive layer 130 are exposed. In one embodiment, the aperture of the adhesive layer opening can be from 1 micrometer to 20 micrometers. In one embodiment, the distance between two adjacent openings of the adhesive layer opening can be from 1 micrometer to 50 micrometers. In one embodiment, the aperture of the first insulating layer opening 120c can be the same as or different from the aperture of the adhesive layer opening.In one embodiment, the distance between two adjacent openings of the first insulating layer opening 120c may be the same as or different from the distance between two adjacent openings of the adhesive layer opening. In one embodiment, the aperture of the adhesive layer opening is smaller than the aperture of the first insulating layer opening 120c, thereby designing the adhesive layer 121 to cover the sidewall of the first insulating layer opening 120c, which can increase the adhesion between the reflective conductive structure 140 and the first insulating layer 120.

[0033] In one embodiment, viewed from above, the opening 120c of the first insulating layer includes a first group of openings located within the contact area R1. Cover portions 351 are respectively disposed corresponding to the first group of openings, and the first group of second insulating layer opening portions 350c surrounds the first group of openings and does not overlap with them. In one embodiment, the distance between two adjacent openings of the first group of openings within the contact area R1 may be the same as or different from the distance between two adjacent openings of the first insulating layer opening 120c outside the contact area R1. In one embodiment, the arrangement (array) of the openings of the first group of openings within the contact area R1 may be the same as or different from the arrangement of the openings of the first insulating layer opening 120c outside the contact area R1. In one embodiment, viewed from above, the contact area R1 is located between the first solder pad 181 and the second solder pad 182, and does not overlap with them. In one embodiment, viewed from above, the outline of the contact area R1 is a geometric pattern or an irregular pattern. In one embodiment, the contact area R1 has an irregular pattern outline with a concave-convex edge. This design of the contact area R1's position prevents short circuits caused by dissimilar electrical contacts. In one embodiment, the contact area R1 is spaced apart from the semiconductor platform opening 210a. In one embodiment, viewed from above, the contact area R1 is disposed around the second contact layer 162.

[0034] Figure 24 shows a top view of a light-emitting element 31 according to an embodiment of this application. The manufacturing process and structure of the light-emitting element 31 are similar to those of light-emitting elements 10, 20, and 30. For similar manufacturing processes and structures, please refer to the descriptions and drawings of light-emitting elements 10, 20, and 30, which will not be repeated here. The differences will be explained later. As shown in Figure 24, the difference between the light-emitting element 31 and the light-emitting element 30 is that the second insulating layer 150 has a contact area R2 located on the reflective conductive structure 140. From the top view, the contact area R2 overlaps with the second solder pad 182. Due to the aforementioned design of the position of the contact area R2, compared with the embodiment of the light-emitting element 30 where the second solder pad 182 does not overlap with the contact area R1, the contact area R2 of the light-emitting element 31 can have a larger contact area, which can improve the current injection and reduce the forward voltage of the light-emitting element. In one embodiment, the contact area R2 includes a plurality of covering portions 351' and a first group of second insulating layer opening portions 350c' surrounding the covering portions 351'. The second contact layer 162 is formed on the second insulating layer 150, covering the first group of second insulating layer opening portions 350c' and the covering portions 351' of the contact area R2, and electrically connecting the second type semiconductor layer 110p to the reflective conductive structure 140 via the first group of second insulating layer opening portions 350c'.

[0035] Figure 25 shows a schematic diagram of a light-emitting package 1P according to an embodiment of this application. As shown in Figure 25, the light-transmitting element 101P covers the side surface 100w of the substrate. Metal bumps 103a and 103b are respectively disposed corresponding to the first solder pad 181 and the second solder pad 182. Specifically, the metal bump 103a is connected to the first solder pad 181. The metal bump 103b is connected to the second solder pad 182. The reflector 102P covers a portion of the sidewalls of the metal bumps 103a and 103b. In one embodiment, the reflector 102P also covers a portion of the sidewalls of the first solder pad 181 and the second solder pad 182.

[0036] The metal bumps (103a, 103b) are lead-free solders comprising at least one material selected from the group consisting of tin, copper, silver, bismuth, indium, zinc, and antimony. The height of the metal bumps (e.g., H1) is between 20 and 150 μm. In one embodiment, the metal bumps are formed by a reflow soldering process. Solder paste is placed on the bonding pads and then heated in a reflow oven to melt the solder paste and create a joint. The solder paste may comprise tin-silver-copper, tin-antimony, or gold-tin and has a melting point greater than 215°C, greater than 220°C, or between 215 and 240°C (e.g., 217°C, 220°C, 234°C). In addition, the peak temperature during the reflow process (the peak temperature usually occurs in the reflow zone) is greater than 250°C, or greater than 260°C, or between 250 and 270°C (e.g., 255°C, 265°C).

[0037] The reflector 102P is an electrically insulator and comprises a first matrix and a plurality of reflective particles (not shown) mixed within the matrix. The first matrix has a silicon-based material or an epoxy-based material and has a refractive index (n) between 1.4 and 1.6 or 1.5 and 1.6. The reflective particles include titanium dioxide, silicon dioxide, aluminum oxide, zinc oxide, or zirconium dioxide. In one embodiment, when light emitted from the semiconductor stack 10a strikes the reflector 102P, the light is reflected, and this reflection is referred to as diffuse reflection. In addition to its reflective function, the reflector 102P can also serve as a mechanical support and withstand the stress generated by the light-emitting package 1P during operation.

[0038] The light-transmitting body 101P comprises a silicon-based matrix material or an epoxy resin-based matrix material. Alternatively, the light-transmitting body 101P may contain a plurality of wavelength-converting particles (not shown) and / or diffusing powder particles dispersed therein to absorb the first light emitted by the light-emitting element 1000 and convert it into a second light with a different spectrum from the first light, wherein the light-emitting element 1000 may be the light-emitting element in the aforementioned embodiments. The first light mixed with the second light will produce a third light. In this embodiment, the third light has a color point coordinate (x, y) in the CIE 1931 chromaticity diagram, where 0.27 ≤ x ≤ 0.285; 0.23 ≤ y ≤ 0.26. In another embodiment, the first light mixed with the second light will produce a third light, such as white light. Depending on the weight percentage concentration and type of wavelength conversion particles, the light-emitting encapsulation can emit white light under thermal stability, with a relative color temperature (CCT) of 2200K~6500K (e.g., 2200K, 2400K, 2700K, 3000K, 5000K, 5700K, 6500K). In the CIE 1931 chromaticity diagram, its color point coordinates (x, y) fall within the range of seven MacAdam ellipses, and it possesses a color rendering index (CRI) greater than 80 or greater than 90. In another embodiment, mixing the first light with the second light can produce violet, amber, green, yellow, or other non-white light.

[0039] Wavelength conversion particles have a particle size of 10 nm to 100 μm and may contain one or more types of inorganic phosphors, organic fluorescent colorants, semiconductors, or combinations thereof. Inorganic phosphors include, but are not limited to, yellow-green or red phosphors. Yellow-green phosphors may be composed of, for example, aluminum oxides (YAG or TAG), silicates, vanadates, alkaline earth metal selenides, or metal nitrides. Red phosphors may be composed of, for example, fluorides (K₂TiF₆:Mn⁴⁺, K₂SiF₆:Mn⁴⁺), silicates, vanadates, alkaline earth metal sulfides (CaS), metal nitrides, or mixtures of tungsten-molybdate groups. The weight percentage concentration (w / w) of the wavelength conversion particles in the matrix is ​​between 50% and 70%. Semiconductor materials include nano-sized crystals, such as quantum dot luminescent materials. Quantum dot luminescent materials can be selected from zinc sulfide (ZnS), zinc selenide (ZnSe), zinc telluride (ZnTe), zinc oxide (ZnO), cadmium sulfide (CdS), cadmium selenide (CdSe), cadmium telluride (CdTe), gallium nitride (GaN), gallium phosphide (GaP), gallium selenide (GaSe), gallium antimonide (GaSb), gallium arsenide (GaAs), aluminum nitride (AlN), aluminum phosphide (AlP), aluminum arsenide (AlAs), indium phosphide (InP), indium arsenide (InAs), tellurium (Te), lead sulfide (PbS), indium antimonide (InSb), lead telluride (PbTe), lead selenide (PbSe), antimony telluride (SbTe), zinc cadmium selenide (ZnCdSeS), copper indium sulfide (CuInS), cesium lead chloride (CsPbCl3), and cesium lead bromide (CsPbBr3). 3) and the group consisting of cesium lead iodide (CsPbI 3). The diffuser powder contains titanium dioxide, zirconium oxide, zinc oxide or aluminum oxide, and is used to scatter the light emitted by the light-emitting element 1000.

[0040] Figure 26 shows a schematic diagram of a light-emitting package 2P according to an embodiment of this application. The light-emitting element 1000 is mounted as a flip chip on the first pad 203P and the second pad 204P of the package substrate 202P. The first pad 203P and the second pad 204P are electrically insulated from each other by an insulating portion 205P containing insulating material. The flip chip mounting involves placing the substrate 100 side, opposite to the pad forming surface, upwards, making the substrate side the primary light extraction surface. To increase the light extraction efficiency of the light-emitting device, a reflective structure 201P can be provided around the light-emitting element 1000, wherein the light-emitting element 1000 can be the light-emitting element in the aforementioned embodiment.

[0041] Figure 27 shows a schematic diagram of a light-emitting package 3P according to an embodiment of this application. The light-emitting package 3P includes a support substrate 300, a light-emitting element 1000, a wavelength converter 305, and a lens 306. The light-emitting element 1000 can be flip-chip bonded to the support substrate 300, which is provided with a first pad 301 and a second pad 302, using a first bump 303 and a second bump 304. The support substrate 300 can be, for example, a printed circuit board. On the other hand, the lens 306 is disposed above the light-emitting element 1000. The lens 306 is a diffusion lens that disperses light, but it is not limited to this. Lenses 306 of various shapes can be combined with the light-emitting element 1000 to realize various light patterns, wherein the light-emitting element 1000 can be the light-emitting element in the aforementioned embodiment.

[0042] Figure 28 shows a schematic diagram of a light-emitting device 1A according to an embodiment of this application. The light-emitting device 1A includes a lampshade 401A, a reflector 402A, a light-emitting module 405A, a lamp holder 406A, a heat sink 407A, a connecting portion 408A, and an electrical connection element 409A. The light-emitting module 405A includes a carrier portion 403A, and a plurality of light-emitting units 404A located on the carrier portion 403A, wherein the plurality of light-emitting units 404A may be the light-emitting elements, light-emitting packages 1P, 2P, or 3P in the aforementioned embodiments.

[0043] Figure 29 shows a schematic diagram of a light-emitting device 2A according to an embodiment of this application. The light-emitting device 2A includes a display panel 500 and a backlight unit. The backlight unit includes a light-emitting element 1000, a bottom cover 501, a reflective sheet 502, a diffuser plate 503, and an optical sheet 504. The bottom cover 501 is open upwards to accommodate the light-emitting element 1000, the reflective sheet 502, the diffuser plate 503, and the optical sheet 504. The light-emitting element 1000 can be the light-emitting element or a light-emitting package as described in the previous embodiments. In one embodiment, a lens 505 is provided on each light-emitting element 1000 to improve the uniformity of light emitted from the multiple light-emitting elements 1000. The diffuser plate 503 and the optical sheet 504 are located on the light-emitting element 1000. Light emitted from the light-emitting element 1000 can be supplied to the display panel 500 as a surface light source through the diffuser plate 503 and the optical sheet 504.

[0044] Figure 30 shows a schematic diagram of a light-emitting device 3A according to an embodiment of this application. The light-emitting device 3A includes a display panel 600 and a backlight unit disposed below the display panel 600. Furthermore, the light-emitting device 3A includes a frame 601 supporting the display panel 600 and housing the backlight unit, and covers 602 and 603 covering the display panel 600. The display panel 600 can be fixed by the covers 602 and 603 located above and below it, and the lower cover 603 can be combined with the backlight unit. The backlight unit includes a light guide plate 604, an optical sheet 605, a reflective sheet 606, a carrier plate 607, and a plurality of light-emitting elements 1000. The optical sheet 605 is located on the light guide plate 604 to diffuse light, the reflective sheet 606 is arranged below the light guide plate 604 to reflect light traveling downwards from the light guide plate 604 towards the display panel 600, and the light-emitting elements 1000 are arranged at certain intervals on the carrier plate 607. In one embodiment, the carrier 607 may be a printed circuit board. The light-emitting element 1000 may be the light-emitting element or light-emitting package as described in the foregoing embodiments.

[0045] Figure 31 shows a schematic diagram of a light-emitting device 4A according to an embodiment of this application. The light-emitting device 4A includes a lamp body 700, a carrier plate 701, a light-emitting element 1000, a cover lens 702, a heat dissipation part 703, a support rib 704, and a connecting member 705. The carrier plate 701 is fixed and spaced apart on the lamp body 700 by the support rib 704. The carrier plate 701 can be a substrate with conductive patterns, such as a printed circuit board. The light-emitting element 1000 is located on the carrier plate 701 and can be electrically connected to an external power source through the conductive patterns of the carrier plate 701. The light-emitting element 1000 can be the light-emitting element or light-emitting package as described in the previous embodiments. The cover lens 702 is located on the light path emitted from the light-emitting element 1000 and can be used to adjust the direction angle and / or color of the light emitted by the light-emitting device 4A to the outside. The connecting member 705, while fixing the cover lens 702 to the carrier plate 701, also has a light-guiding function around the light-emitting element 1000. In one embodiment, the connecting member 705 may be formed of a light-reflective material or coated with a light-reflective material. The heat dissipation part 703 may include a heat sink 706 and / or a cooling fan 707 to dissipate heat generated when the light-emitting element 1000 is driven.

[0046] The above embodiments are merely illustrative of the principles and effects of this application and are not intended to limit this application. Anyone skilled in the art to which this application pertains may modify and vary the above embodiments without departing from the technical principles and spirit of this application. All equivalent variations and modifications made to the shape, structure, features, and spirit described in the claims of this application shall be included within the scope of the claims of this application.

[0047] 1A, 2A, 3A, 4A: Light-emitting devices 1P, 2P, 3P: Light-emitting encapsulation 10~15, 20~22, 30~31, 1000: Light-emitting elements 100:Substrate 100s: upper surface of substrate 100w: Substrate side surface 101P: Light-transmitting body 102P: Reflector 103a, 103b: Metal bumps 110: Semiconductor Platform 110n: Type I semiconductor layer 110a: Active Region 110p: Type II semiconductor layer 120: First insulating layer 120a: First peripheral contact hole 120c: Opening of the first insulating layer 121: Adhesive layer 130: Transparent conductive layer 140: Reflective conductive structure 150: Second insulation layer 150a: Second peripheral contact hole 150c1, 350c: Openings in the second insulating layer of the first group 150c2: Second group, second insulation layer opening 160: Contact layer 161: First contact layer 162: Second contact layer 163: Third contact layer 170: Third insulation layer 170a: First solder pad opening 170b: Second solder pad opening 181: First solder pad 182: Second solder pad 201P: Reflective Structure 202P: Packaging substrate 203P: First gasket 204P: Second gasket 205P: Insulation section 210a: Semiconductor platform opening 220a: First internal contact hole 221a: Adhesive layer opening 230a: Opening in transparent conductive layer 240a: Opening of the reflective conductive structure 250b: Second internal contact hole 300: Support substrate 301: First pad 302: Second pad 303: First bump 304: Second bump 305: Wavelength Converter 306, 505: Lenses 401A: Lampshade 402A: Reflector 403A: Bearing Unit 404A: Light-emitting unit 405A: Light-emitting module 406A: Lamp holder 407A: Heatsink 408A: Connecting part 409A: Electrical connection element 500, 600: Display panel 501: Bottom Cover 502, 606: Reflective sheets 503: Diffuser Plate 504, 605: Optical film 601: Framework 602, 603: Cover 604: Light guide plate 607, 701: Carrier Board 700: Lamp body 702: Cover Lens 703: Heat dissipation section 704: Support Rib 705: Connecting components 706: Heatsink 707: Cooling Fan 351: Covering section B1, B2, B3: Branches C4: Internal return part D1: First Direction d: interval E: Surrounding exposed areas F3, F4, F5: Outer frame H5: Latitude O: Boundary R1, R2: Contact area S1: Outer Section S2: Inner Section S3: Connecting Section T1, T2: Main trunk V5: Classics

Claims

1. A light-emitting element, comprising: a first type semiconductor layer including a first portion and a second portion, wherein the second portion surrounds the first portion; a semiconductor platform including an active region formed on the first portion and a second type semiconductor layer formed on the active region; a peripheral exposed region not covered by the semiconductor platform, exposing the second portion and surrounding the semiconductor platform; a first insulating layer formed on the second type semiconductor layer and including a first insulating layer opening; a reflective conductive structure formed on the first insulating layer, filling the first insulating layer opening and electrically connected to the second type semiconductor layer; a second insulating layer formed on the reflective conductive structure and including a first group of second insulating layer openings, wherein, viewed from above, the first group of second insulating layer openings does not overlap with the first insulating layer opening; A first solder pad is located on the second insulating layer and electrically connected to the first type semiconductor layer; and a second solder pad is located on the second insulating layer and electrically connected to the second type semiconductor layer, wherein the first solder pad and the second solder pad are arranged along a first direction, and when viewed from above, the second solder pad overlaps with the opening portion of the first group of second insulating layers.

2. A light-emitting element, comprising: a first type semiconductor layer including a first portion and a second portion, wherein the second portion surrounds the first portion; a semiconductor platform including an active region formed on the first portion and a second type semiconductor layer formed on the active region; a peripheral exposed region not covered by the semiconductor platform, exposing the second portion and surrounding the semiconductor platform; a first insulating layer formed on the second type semiconductor layer and including a first insulating layer opening; a reflective conductive structure formed on the first insulating layer, filling the first insulating layer opening and electrically connected to the second type semiconductor layer; a second insulating layer formed on the reflective conductive structure and having a contact region, wherein the contact region includes a plurality of covering portions and a first group of second insulating layer openings surrounding the covering portions; a first bonding pad located on the second insulating layer and electrically connected to the first type semiconductor layer; and a second bonding pad located on the second insulating layer and electrically connected to the second type semiconductor layer. The first solder pad and the second solder pad are arranged along a first direction. The opening of the first insulating layer includes a first set of openings located in the contact area. From a top view, the covering portions are respectively provided corresponding to the first set of openings. The first set of second insulating layer opening portions surround the first set of openings and do not overlap with the first set of openings.

3. The light-emitting element as claimed in claim 1, wherein the first insulating layer opening comprises a trench or a plurality of openings and is spaced apart from the semiconductor platform by a distance.

4. The light-emitting element as claimed in claim 3, wherein the trench extends in the first insulating layer along the first direction, and the trench has an extension length in the first direction greater than the length of the first pad or the second pad in the first direction.

5. The light-emitting element as claimed in claim 3, wherein the trench extends in the first insulating layer and includes an extending pattern, wherein, viewed from above, the extending pattern includes a herringbone pattern, a fork pattern, a wrapping pattern, or a grid pattern.

6. The light-emitting element as claimed in claim 3, wherein, viewed from above, a boundary extends along the first direction between the semiconductor platform and the peripheral exposed area, the boundary including a first embossed pattern, the trench extending in the first insulating layer including an outer segment adjacent to the boundary and extending along the first direction and spaced from the boundary, the outer segment including a second embossed pattern substantially corresponding to the first embossed pattern.

7. The light-emitting element as claimed in claim 3 further includes one or more semiconductor platform openings formed within the semiconductor platform, the first type semiconductor layer including a third portion, the one or more semiconductor platform openings exposing the third portion, wherein, viewed from above, the one or more semiconductor platform openings do not overlap with the trench or the plurality of openings.

8. The light-emitting element as claimed in claim 1, wherein the second insulating layer further includes a second set of openings, which, when viewed from above, do not overlap with the opening of the first insulating layer and the first and second solder pads, and are located between the first and second solder pads.

9. The light-emitting element as claimed in claim 2, wherein, viewed from above, the edge of the contact area includes a concave-convex edge.

10. The light-emitting element as claimed in claim 1 or 2 further includes a first contact layer formed between the second insulating layer and the first pad, wherein the first contact layer extends to the peripheral exposed area and contacts the second portion of the first type semiconductor layer to electrically connect the first type semiconductor layer.

11. The light-emitting element as claimed in claim 1 or 2 further includes a second contact layer formed between the second insulating layer and the second pad, wherein the second contact layer fills the opening portion of the first set of second insulating layers and is electrically connected to the second type semiconductor layer.

12. The light-emitting element as described in claim 1 or 2 further comprises an adhesive layer formed between the first insulating layer and the reflective conductive structure.

13. The light-emitting element as claimed in claim 12, wherein the material of the adhesive layer comprises a transparent metal oxide.