Static random-access memory (SRAM) array circuits including bilateral well tap cells with reduced width folded finger structure

Abstract

An SRAM array circuit is disclosed, wherein the horizontal N-wells of the header cells in the first column and the horizontal N-wells of the header cells in the second column are separated by a P-type substrate region. The header cells include bilateral P-type headers disposed in the P-type substrate region between the horizontal N-wells in the first and second columns, providing a ground voltage to the P-type substrates on both sides of the header cell row in the SRAM array circuit, instead of one P-type header on each side. The absence of vertical N-wells in the header cells reduces the width, corresponding to a reduction in the width of the SRAM array circuit. The bilateral P-type headers in the P-type injection region may include multiple folded fingers providing a ground voltage to the P-type substrates.

Description

[Technical Field]

[0001] The field of this disclosure generally relates to integrated circuits (ICs), and more specifically to arrays of memory devices in ICs. [Previous Technology]

[0002] Consumer electronics products require high performance at low cost. Most of this performance is provided by integrated circuits (ICs). One way to reduce IC costs is to reduce the IC area without compromising performance. A large portion of the area in many ICs is occupied by memory circuitry. Therefore, reducing the size of memory circuitry can significantly contribute to reducing the size and cost of ICs. Static Random Access Memory (SRAM) circuits are commonly used due to their fast access time and long lifespan. An SRAM circuit comprises several transistors formed in a semiconductor substrate. The transistors are arranged in an efficient pattern within memory bit cells, and the memory bit cells are arranged in a two-dimensional (2D) array on the semiconductor substrate. Each column of the SRAM array includes N-type and P-type regions of the semiconductor substrate. Proper operation of the SRAM circuit requires these regions to be at specific voltage levels (e.g., power supply voltage VDD and ground voltage VSS), thus the N-type and P-type regions are electrically coupled to corresponding voltages at the periphery of the array. Therefore, storage bits near the array periphery have low-resistance connections to VDD / VSS, but the VDD / VSS path resistance increases as it moves away from the array periphery.

[0003] In the presence of a high-resistance path through the semiconductor substrate from the memory bit cell to the nearest VDD / VSS connection, voltage anomalies such as voltage supply spikes or single-event disturbances (e.g., high-energy particles) can cause the voltage in the N-type or P-type region to become higher than VDD or lower than VSS. This voltage anomaly can trigger the conduction of parasitic transistors in the semiconductor substrate structure, resulting in a condition known as latch-up. During latch-up, a low-resistance path is created between VDD and VSS, and the SRAM circuit will not recover without a loop power supply in the SRAM circuit. The current generated by the latch-up condition can damage the SRAM circuit. Latch-up can be avoided by keeping the path resistance from VDD or VSS to the SRAM circuit below a threshold resistance. Therefore, for SRAM circuits located far from the array perimeter, a solution is needed where the path resistance through the substrate to VDD / VSS is high. To prevent SRAM circuits located far from the array perimeter (e.g., in the middle of the SRAM array) from being susceptible to latch-up, well tap cells are inserted in each column to reduce the distance to the VDD / VSS sources. The well tap cells provide VDD / VSS to the semiconductor substrate in the SRAM cells located in the middle of the SRAM array via a low-resistance path. The number of well taps is minimized due to the width of each column of the SRAM array to which the well tap cells are added. [Summary of the Invention]

[0004] The aspects disclosed herein include static random access memory (SRAM) array circuitry, which includes double-sided wellhead units with a reduced-width folded finger structure. Wellhead units inserted into each column of the SRAM array circuitry provide power and ground connections to the substrate to reduce latch-up in the SRAM bit cell circuitry. Wellhead units are disposed in rows between rows of the SRAM bit cell circuitry. The SRAM array circuitry includes a P-type substrate with horizontal N-wells disposed in each column. In conventional SRAM arrays, a row of wellhead units includes a vertical N-well and an N-type wellhead located at the intersection of a vertical N-well and a horizontal N-well. The vertical N-well is electrically coupled to the horizontal N-well in the corresponding column, but vertically separates the P-type substrate, decoupling the P-type substrate on a first side of the wellhead unit from the P-type substrate on a second side of the wellhead unit. Therefore, the wellhead unit includes a P-type wellhead on each side of the vertical N-well to provide ground connections to the first and second sides of the P-type substrate.

[0005] In an exemplary aspect, the horizontal N-wells of the header cells in the first column of the SRAM array circuit are separated from the horizontal N-wells of the header cells in the second column by a P-type substrate region. In the absence of vertical N-wells, the header cells include bilateral P-type headers disposed in the P-type substrate region between the horizontal N-wells in the first and second columns. The bilateral P-type headers provide a ground voltage to the P-type substrate parallel to both sides of the header cell row, instead of a separate P-type header on each side of the SRAM array circuit. In the absence of vertical N-wells, the width of the header cells is reduced, corresponding to a reduction in the width of the SRAM array circuit. The bilateral P-type headers may include a plurality of folded fingers that provide the ground voltage to the P-type substrate parallel to the ground voltage. The header cell row may also include P-type injection regions and N-type injection regions, the P-type injection regions including P-type headers for each column of the SRAM array circuit, and the N-type injection regions including N-type headers for each column of the SRAM array circuit. The SRAM array circuitry, including an exemplary well joint unit with a double-sided P-type well joint, has a reduced width, which lowers costs without altering performance.

[0006] In an exemplary aspect, an SRAM array circuit is disclosed. The SRAM array circuit includes a substrate; multiple columns of SRAM bit cell circuits disposed on the substrate, each column extending in a first axial direction; and multiple rows of SRAM bit cell circuits extending in a second axial direction orthogonal to the first axial direction. The SRAM array circuit also includes a wellhead cell row disposed between a first row and a second row of the multiple rows, the wellhead cell row including wellhead cells disposed in each column of the multiple columns. The substrate includes a P-type substrate, and the wellhead cell in each column includes an N-well located in the P-type substrate, the N-well extending in the first axial direction. The N-well of the wellhead cell in the first column of the multiple columns is separated from the N-well of the wellhead cell in the second column of the multiple columns by the P-type substrate. The P-type wellhead is disposed in the P-type substrate between the N-well of the wellhead cell in the first column and the N-well of the wellhead cell in the second column, and provides a ground voltage to the SRAM bit cell circuits on a first side of the wellhead cell row and to the SRAM bit cell circuits on a second side of the wellhead cell row.

[0007] In another exemplary aspect, an IC including an SRAM array circuit is disclosed. The SRAM array circuit includes a substrate; multiple columns of SRAM bit cell circuits disposed on the substrate, each column extending in a first axial direction; and multiple rows of SRAM bit cell circuits extending in a second axial direction orthogonal to the first axial direction. The SRAM array circuit includes a wellhead cell row disposed between a first row and a second row of the multiple rows, the wellhead cell row including wellhead cells disposed in each column of the multiple columns. The substrate includes a P-type substrate, and the wellhead cell in each column includes an N-well in the P-type substrate, the N-well extending in the first axial direction. The N-well of the wellhead cell in the first column of the multiple columns is separated from the N-well of the wellhead cell in the second column of the multiple columns by the P-type substrate, and the P-type wellhead is disposed in the P-type substrate between the N-well of the wellhead cell in the first column and the N-well of the wellhead cell in the second column, providing a ground voltage to the SRAM bit cell circuits on a first side of the wellhead cell row and to the SRAM bit cell circuits on a second side of the wellhead cell row.

Implementation Method

[0020] Several exemplary aspects of this disclosure are now described with reference to the accompanying drawings. The word "exemplary" is used herein to mean "as an example, instance, or illustration." Any aspect described herein as "exemplary" is not necessarily to be construed as superior to or exceeding the other aspects.

[0021] The aspects disclosed herein include a static random access memory (SRAM) array circuit, which includes a double-sided wellhead unit with a folded finger structure having reduced width. The wellhead unit, inserted into each column of the SRAM array circuit, provides power and ground connections to the substrate to reduce latch-up in the SRAM bit cell circuit. The wellhead units are disposed in rows between the rows of the SRAM bit cell circuit. The SRAM array circuit includes a P-type substrate with horizontal N-wells disposed in each column. In conventional SRAM arrays, a row of wellhead units includes a vertical N-well and an N-type wellhead located at the intersection of the vertical N-well and the horizontal N-well. The vertical N-well is electrically coupled to the horizontal N-well in the corresponding column, but vertically separates the P-type substrate, decoupling the P-type substrate on the first side of the wellhead unit from the P-type substrate on the second side of the wellhead unit. Therefore, the wellhead unit includes a P-type wellhead on each side of the vertical N-well to provide ground connections to the first and second sides of the P-type substrate.

[0022] In an exemplary aspect, the horizontal N-wells of the header cells in the first column of the SRAM array circuit are separated from the horizontal N-wells of the header cells in the second column by a P-type substrate region. In the absence of vertical N-wells, the header cells include bilateral P-type headers disposed in the P-type substrate region between the horizontal N-wells in the first and second columns. The bilateral P-type headers provide a ground voltage to the P-type substrate parallel to both sides of the header cell row, instead of a separate P-type header on each side of the SRAM array circuit. In the absence of vertical N-wells, the width of the header cells is reduced, corresponding to a reduction in the width of the SRAM array circuit. The bilateral P-type headers may include a plurality of folded fingers that provide the ground voltage to the P-type substrate parallel to the ground voltage. The header cell row may also include P-type injection regions and N-type injection regions, the P-type injection regions including P-type headers for each column of the SRAM array circuit, and the N-type injection regions including N-type headers for each column of the SRAM array circuit. The SRAM array circuitry, including an exemplary well joint unit with a double-sided P-type well joint, has a reduced width, which lowers costs without altering performance.

[0023] Latch-up is a condition in integrated circuitry caused by parasitic transistors in an IC substrate when voltage levels fluctuate and there is a high-resistivity path connected to the substrate's ground or power supply voltage. Latch-up can create a short circuit between the power supply and ground voltage rails of a field-effect transistor (FET) circuit. A short circuit can cause malfunctions and may result in high currents that could damage the IC. SRAM array circuitry can be susceptible to latch-up due to the high-resistivity paths between voltage sources around large SRAM array circuitry, especially in SRAM bit cell circuitry located far from the periphery in the middle of columns.

[0024] Figure 1 is a top view illustration of the SRAM array circuit 100 in IC 102. The SRAM array circuit 100 includes SRAM bit cell circuits 104 disposed in columns 106 and rows 108. Digital data can be written to each SRAM bit cell circuit 104, stored in each SRAM bit cell circuit 104, and read back from each SRAM bit cell circuit 104. The SRAM bit cell circuits 104 are formed in the substrate 110 of IC 102. Peripheral circuitry 112 couples the substrate 110 to the power supply voltage VDD and the ground voltage VSS for operating the SRAM bit cell circuits 104. The N-type region (not shown) of the substrate 110 is doped with pentavalent impurities and has electrons as the main charge carriers. The N-type region of the substrate 110 is coupled to VDD through the peripheral circuitry 112. The P-type region of substrate 110 is doped with trivalent impurities and has holes as the main charge carriers. The P-type region of substrate 110 is coupled to VSS through peripheral circuit 112.

[0025] Furthermore, each SRAM array circuit 100 includes a wellhead unit 116 in row 114 to directly supply the power supply voltage VDD and the ground voltage VSS to the substrate 110 in the SRAM bit cell circuit 104 located in the middle of column 106. The wellhead unit 116 supplies the power supply voltage VDD and the ground voltage VSS to the SRAM bit cell circuit 104 via a lower resistance than the path from the peripheral circuit 112 through the substrate 110. Row 114 is disposed between the first row 118A and the second row 118B of the SRAM bit cell circuit 104. Each SRAM bit cell circuit 104 may each include 5 to 12 or more transistors (e.g., field-effect transistors (FETs)). The benefits of the wellhead unit are independent of the specific design of the SRAM bit cell circuit. Therefore, details of the SRAM bit cell circuit 104 are beyond the scope of this application and will not be provided herein.

[0026] Details of an example of the well connector circuit 116 are presented herein. Figures 2-3 are illustrations of a conventional example of the well connector circuit 116. Examples in Figures 2-3 are presented for comparison with the exemplary aspects illustrated in Figures 4-10.

[0027] FIG2 is a top view illustration of the substrate 200 (also referred to as "P-type substrate 200") in which the wellhead unit 202 is formed, as further shown in FIG3. The substrate 200 and the wellhead unit 202 correspond to the substrate 110 and wellhead unit 116 in the SRAM array circuit 102 in FIG1, respectively. FIG2 shows two wellhead units 202, one in each column 204(1) and 204(2) (collectively referred to as column 204) in row 206 corresponding to row 114 in FIG1. ​​The two wellhead units 202 include a horizontal N-well 208 extending horizontally (i.e., in the X-axis direction) in each column 204 and a vertical N-well 210 (i.e., extending in the Y-axis direction) across column 204 in row 206. The vertical N-well 210 is coupled to the two horizontal N-wells 208 in column 204 in the form of an "N-well bend". The vertical N-well 210 divides the P-type substrate 200 in the wellhead unit 202 into a first P-type substrate region 214A on a first side of the vertical N-well 210 and a second P-type substrate region 214B on a second side of the vertical N-well 210. The first P-type substrate region 214A between the horizontal N-wells 208 in FIG2 and the second P-type substrate region 214B between the horizontal N-wells 208 are electrically decoupled so that the voltage directly coupled to the first P-type substrate region 214A is not coupled to the second P-type substrate region 214B through a low-resistance path.

[0028] Figure 3 is a top view illustration of the well connector unit 202 in the two columns 204 and row 206 of Figure 2. Features of Figure 2, also shown in Figure 3, have the same labels as in Figure 2. Each well connector unit 202 in each column 204 includes an N-type well connector 300 to supply power voltage VDD to the horizontal N-well 208 and the vertical N-well 210. The well connector unit 202 in each column 204 also includes two (2) P-type well connectors 302A-302B to supply ground voltage VSS to the first and second P-type substrate regions 214A and 214B. The well connector unit 202 has only one N-type well connector 300 because the horizontal N-well 208 extends in both directions of column 204. In this regard, when the wellhead unit 202 is used as the wellhead unit 116 in the SRAM array circuit 100 of FIG. 1, the horizontal N-well 208 extends through the first row 118A and the second row 118B (and additional rows) of the SRAM bit cell circuit 104 and provides a power supply voltage VDD to the first row 118A and the second row 118B (and additional rows) of the RAM bit cell circuit 104. Furthermore, the vertical N-well 210 overlaps or intersects with the horizontal N-well 208 in each column 204 such that the vertical N-well 210 is electrically coupled to each of the horizontal N-wells 208.

[0029] However, the first and second P-type substrate regions 214A and 214B are electrically separated from each other because the substrate 200 is divided into two in the Y-axis direction by the perpendicular N-well 210. Therefore, the first P-type well connector 302A provides the ground voltage VSS to the first P-type substrate region 214A, and the second P-type well connector 302B separately provides the ground voltage VSS to the second P-type substrate region 214B.

[0030] FIG3 illustrates additional features of the wellhead unit 202 formed on the substrate 200 of FIG2. The wellhead unit 202 includes an active region 304 formed on the substrate 200. The active region 304 extends in the column 204 parallel to the X-axis direction (e.g., the horizontal direction in FIG3). The active region 304 includes fins 306 spaced apart in the Y-axis direction by a fin pitch P306. FETs (not shown) in the SRAM bit cell circuit 104 of FIG1 are formed where the fins 306 extend through the SRAM array circuit 100. Therefore, FIG3 also includes a gate 308 disposed above the fins 306. The gates 308 extend parallel to the Y-axis direction and are spaced apart from each other in the X-axis direction at regular intervals according to the gate pitch P308.

[0031] The fin 306 extends discontinuously through the wellhead unit 202. Instead, fin cuts 310(1)-310(5) (collectively referred to as fin cuts 310(x)) are regions in which the fin 306 is removed from the substrate 200 such that the remaining fins 306 on either side of one of the fin cuts 310(x) are electrically insulated from each other. Thus, the fin cuts 310(x) divide the wellhead unit 202 in the Y-axis direction into portions 312(A), 312(B), 314(A), 314(B), 316(A) and 316(B), as described below.

[0032] Parts 312(A) and 312(B) are located on opposite sides of the well joint unit 202 in the X-axis direction. Part 312(A) is located between row 318(A) of the via 320 and fin cut 310(1). Part 312(A) includes the first unit termination 322(A) and the second unit termination 324(A) in column 204. Part 312(B) is located between row 318(B) of the via 320 and fin cut 310(5). Part 312(B) includes the first unit termination 322(B) and the second unit termination 324(B). Parts 312(A) and 312(B) may also be referred to as unit termination regions 312(A) and 312(B). The conventional example of the well joint unit 202 shown in Figure 3 extends horizontally from row 318 (A) to row 318 (B), with a total width W202 equal to eighteen (18) times the gate spacing PGATE.

[0033] Part 314(A) is located between fin cut 310(1) and fin cut 310(2). Part 314(B) is located between fin cut 310(4) and fin cut 310(5). Parts 314(A) and 314(B) include implanted P-type dopant material (e.g., boron, aluminum, and / or gallium) and are therefore also referred to as the first P-type implantation region 314(A) and the second P-type implantation region 314(B). The first P-type well joint 302A is formed in the overlap between the P-type substrate 200 and the first P-type implantation region 314(A) between the horizontal N-wells 208. The second P-type well joint 302B is formed in the overlap between the P-type substrate 200 and the second P-type implantation region 314(B) between the horizontal N-wells 208.

[0034] Part 316(A) is on the vertical N-well 210 between fin cuts 310(2) and fin cuts 310(3), and part 316(B) is on the vertical N-well 210 between fin cuts 310(3) and fin cuts 310(4). Therefore, parts 316(A) and parts 316(B) are located on opposite sides of fin cuts 310(3). N-type well joints 300 are formed in each column 204 at the overlap of the vertical N-well 210 and parts 316(B).

[0035] The vertical N-well 210 in Figure 3 provides electrical coupling between the horizontal N-wells 208, which is beneficial for the voltage distribution between the N-wells 208; however, the resistivity of the vertical N-well 210 reduces this benefit. The vertical N-well 208 and the associated fin cut 310(x) increase the width W202 of the wellhead unit 202 in the X-axis direction and also increase the width of the SRAM array circuit 100 in Figure 1. In addition, since the vertical N-well 210 separates the first and second P-type substrate regions 214A and 214B from each other, both P-type wellheads 302A-302B are required in each column.

[0036] An exemplary aspect of the well connector unit 400 is illustrated in FIG. 4, with a level of detail corresponding to FIG. 2. The well connector unit 400 is formed on a substrate 402 (also referred to as "P-type substrate 402"), and each well connector unit 400 includes an N-well 404 in the P-type substrate 402, wherein the N-well 404 extends in the X-axis direction. The N-well 404 in the first column 406 (1) and the N-well 404 in the second column 406 (2) are separated by the P-type substrate 402, which is partially located within the first well connector unit 400 in the first column 406 (1) and partially located within the second well connector unit 400 in the second column 406 (2). The well connector units 400 are arranged in a row 408 having multiple columns 406 (1)-406 (x) (only 406 (1) and 406 (2) are shown). In each of columns 406(1)-406(x), the N-well 404 in the well connector unit 400 extends in the X-axis direction on both sides of row 408 to the SRAM bit cell circuit 104 shown in FIG1. ​​The number "x" is the column number in the SRAM array circuit 100 in FIG1, wherein each column includes transistors for forming the SRAM bit cell circuit 104 in the N-well 404 and the P-type substrate 402.

[0037] The P-type substrate 402 extends uninterruptedly over a width W400 in the X-axis direction because the wellhead unit 400 does not include a vertical N-well (i.e., extending in the Y-axis direction) spanning columns 406(1) and 406(2) in row 408. The wellhead unit 400 may be employed in the wellhead unit 116 in FIG1, and the following description of some aspects of the wellhead unit 400 refers to its implementation in the SRAM array circuit 100, including the SRAM bit cell circuit 104 in FIG1. ​​FIG4 also indicates the positions of fin cuts 410(1)-410(3).

[0038] FIG5 illustrates a further exemplary aspect of the wellhead unit 400, with a level of detail corresponding to FIG3. Features of FIG4, also shown in FIG5, have the same labels in FIG5 as in FIG4. The wellhead unit 400 includes an active region 500. The active region 500 includes fins 502 in the P-type substrate 402 and N-well 404, but may instead include planar regions of the P-type substrate 402 and N-well 404. The fins 502 extend parallel to the X-axis direction and are spaced apart from each other according to the fin pitch PFIN. Gates 504 are disposed above the fins 502 and extend parallel to each other in the Y-axis direction. The gates 504 are spaced apart in the X-axis direction and are separated from each other by a gap according to the gate pitch PGATE. The gates 504 are, for example, polysilicon gates used in finned FETs.

[0039] The well connector unit 400 extends by a width W400 from the first row 506A to the second row 506B of the via 508. In the absence of a vertical N-well (vertical N-well 210 in FIG2) and the fin cut associated with the vertical N-well 210, the width W400 is equal to fourteen (14) times the gate pitch PGATE, which is narrower than the width W202 of the well connector unit 202 in FIG2 and FIG3. This width reduction achieved by the well connector unit 400 translates into a corresponding reduction in the width of the SRAM array circuit 100.

[0040] The fin 502 in the well connector unit 400 is divided into portions 510, 512, 514 and 516 by fin cuts 410(1)-410(3). Portions 510, 512, 514 and 516, as well as fin cuts 410(1)-410(3), extend longitudinally parallel to each other in a direction perpendicular to the Y-axis of the fin 502. Portion 510 is between the first row 506A of the via 508 and the fin cut 410(1). Portion 510 is also referred to as the bit cell termination portion 510 because it includes circuit structures 518(1) and 518(2) in columns 406(1) and 406(2) for the end termination of the SRAM bit cell circuit 104 in FIG. 1 on the first side of row 408. Portion 516 is between the fin cut 410(3) and the second row 506B of the via 508. Part 516 is also bit cell termination part 516, because part 516 includes circuit structures 520(1) and 520(2) in columns 406(1) and 406(2) for the end termination of the SRAM bit cell circuit 104 in FIG1 on the second side of row 408.

[0041] A portion 512 of the wellhead unit 400 is located between fin cuts 410 (1) and fin cuts 410 (2). Portion 512 is also a P-type injection region 512 implanted with P-type dopant material. A double-sided P-type wellhead 522 is disposed in the P-type injection region 512 of the P-type substrate 402 between the N-wells 404 in the first column 406 (1) and the N-wells 404 in the second column 406 (2), partially located within the wellhead unit 400 in each column 406 (1) and 406 (2). Specifically, the double-sided P-type wellhead 522 is located where the P-type injection region 512 and the P-type substrate 402 overlap or intersect. The P-type substrate 402 implanted with P-type dopant increases the conductivity of the P-type wellhead 522, which provides a low-resistance connection to the P-type substrate 402, to which a ground voltage VSS can be provided to avoid latch-up. Since the P-type substrate 402 extends uninterruptedly to both sides of row 408 of the wellhead unit 400, the double-sided P-type wellhead 522 provides a ground voltage VSS parallel to the P-type substrate 402 in the SRAM bit cell circuit 104 on the first side of the wellhead unit 400 and to the P-type substrate 402 in the SRAM bit cell circuit 104 on the second side of the wellhead unit 400. Therefore, for each column, a double-sided P-type wellhead 522 is used in the wellhead circuit 400 to replace the first and second P-type wellheads 302A and 302B in the wellhead unit 202 of FIG. 2 and FIG. 3. As noted above, the P-type wellhead 522 is located within the P-type substrate 402, which is partially located within the wellhead unit 400 in the first column 406 (1) and partially located within the wellhead unit 400 in the second column 406 (2). Similarly, another P-type well joint 522 is partially located within well joint unit 400 in the second column 406(2) and partially located within well joint unit 400 in the third column 406(3), and so on, so that row 408 includes P-type well joint units 522 corresponding to columns 406(1)-406(x-1).

[0042] A portion 514 of the wellhead unit 400 is also referred to as the N-type injection region 514 because a portion 514 of row 408 (extending in the Y-axis direction) is injected with N-type dopant material (e.g., phosphorus, arsenic, and / or antimony) between fin cuts 410 (2) and fin cuts 410 (3). An N-type wellhead 524 is disposed in the N-type injection region 514 of the N-well 404 in the first column 406 (1), and another N-type wellhead 524 is disposed in the N-type injection region 514 of the N-well 404 in the second column 406 (2). Specifically, the N-type wellhead 524 is located where the N-type injection region 514 and the N-well 404 overlap or intersect. In this regard, a low-resistance power supply voltage VDD is provided to the N-well 404 to avoid latch-up. N-well 404 extends into the SRAM array circuit 100 on both sides of row 408 and provides power supply voltage VDD to the SRAM bit cell circuit 104 on the first side of the well connector unit 400, which is connected in parallel with the SRAM bit cell circuit 104 on the second side of the well connector unit 400.

[0043] The N-wells 408 in corresponding columns 406(1) and 406(2) are electrically coupled to each other in one or more metal layers (not shown), which provides a lower resistance path between N-wells 404 than the vertical N-well 210 in FIG. 2. Furthermore, the well connector unit 400 in FIG. 5 is narrower in width (i.e., 14 times the gate spacing PGATE) than the well connector unit 202 in FIG. 3 (i.e., 18 times the gate spacing PGATE) because the well connector unit 400 does not include the vertical N-well 210. The reduction in the width W400 of the well connector unit 400 compared to the width W202 of the well connector unit 202 reduces the width of the SRAM array circuit 100 without compromising functionality and performance, which will reduce the cost of the IC containing the SRAM array circuit 100.

[0044] Figure 6 is a top view of one of the double-sided P-type well connectors 522, which includes three folded fingers 600 coupled together to provide a ground voltage VSS parallel to a P-type substrate 402. Figure 6 shows the fin 502 of Figure 5 extending in the X-axis direction. The folded fingers 600 are metal or other conductive materials disposed on the source / drain regions 602 of the plurality of fins 502 and extending in the Y-axis direction. The folded fingers 600 are electrically coupled to the source / drain regions 602 of the plurality of fins 502. The source / drain regions 602 are portions of the fins 502 between gates 504. The gate regions 604 of the plurality of fins 502 are disposed below the gates 504 in the P-type well connector 522. The gate regions 604 are formed of a non-conductive material 606, wherein the polycrystalline silicon material of the gate 502 above the gate portion 604 is removed to prevent activation of the gate regions 604 of the fins 502. In this example, each of the folded fingers 600 is coupled to two (2) source / drain regions 602. P-connectors 608 are formed at the source / drain regions 602 on either side of the gate region 604 where one of the folded fingers 600 is coupled to couple the P-type substrate 402 to the ground voltage VSS. Therefore, the double-sided P-type wellhead 522 in FIG. 6 includes four (4) P-connectors 608. Vias 610 couple the folded fingers 600 to a metal rail 612 that receives the ground voltage VSS. In this way, the folded fingers 600 couple the ground voltage VSS to the P-type substrate 402 in parallel via the P-connectors 608.

[0045] Figure 7 is a top view of an N-type well connector 524, which includes three folded fingers 700 coupled together to provide a power supply voltage VDD to an N-well 404 in parallel. Each folded finger 700 is coupled to a source / drain region 702 of a fin 502, and an N-connector 704 is formed at the source / drain regions 702 on either side of the gate region 706 of the fin 502 where the folded fingers 700 are coupled. The folded fingers 700 are coupled to a metal rail 710 receiving the power supply voltage VDD via a via 708. In this way, the folded fingers 700 couple the power supply voltage VDD to the N-well 404 in parallel via the N-connector 704. The N-type well connector 524 provides the power supply voltage 404 bilaterally (i.e., to the area of ​​the N-wells on both sides of the well connector unit 400 in Figure 5).

[0046] Detailed views of the double-sided P-type well joint 522 and N-type well joint 524 are shown in more detail in Figures 8 and 9, respectively. The features in Figures 8 and 9, also shown in Figures 4-7, have the same labels as in Figures 4-7.

[0047] FIG8 is an illustration of a cross-sectional end view of a fin 800 on a P-type substrate 402 in a P-type injection region 512 and a fin 802 on an N-type well 404 in an N-type injection region 514. Fins 800 and 802 correspond to fin 502 in FIGS. 5-7. FIG8 shows a side view of one of the folded fingers 600 of FIG. 6 coupled to fin 800 and a side view of one of the folded fingers 700 of FIG. 7 coupled to fin 802. Folded fingers 600 and 700 are formed of metal layers 804 and 806. FIG8 also shows a via 610 coupling folded fingers 600 to metal rail 612 and a via 708 coupling folded fingers 700 to metal rail 710. In FIG8, metal rails 612 and 710 are further coupled to the upper metal layer 808 through via 810.

[0048] Figure 9 is a cross-sectional side view of the fin 800 forming the P-connector 608 in the P-type well connector 522 and the fin 802 on the N-well 404 forming the N-connector 704 in the N-type well connector 524 in Figure 8. Figure 9 shows an end view of the folded fingers 600 and 700 coupled to the metal rails 612 and 710, the gate 504, and the via 806 coupled to the upper metal layer 804. The P-connector 608 is formed at the source / drain regions 602 on both sides of the gate region 604 on the metal rail 612, and the N-connector 704 is formed at the source / drain regions 702 on both sides of the gate region 706 on the metal rail 710.

[0049] FIG10 illustrates a well connector unit 1000, which corresponds in detail to the illustration of well connector unit 400 in FIG5. Exemplary aspects of well connector unit 1000 correspond to those aspects of well connector unit 400 discussed above. FIG10 shows a fin 1002 extending in the X-axis direction and a gate 1004 extending in the Y-axis direction, separated by a gate spacing PGATE. A double-sided P-type well connector 1006 provides a ground voltage VSS to a P-type substrate 1008 on both sides of the well connector unit 1000 in parallel. Each double-sided P-type well connector 1006 is partially disposed within a first well connector unit 1000 in a first column 1010 (1) and partially disposed within a second well connector unit 1000 in a second column 1010 (2). However, each P-type well connector 1006 includes eight (8) P-connectors 1012 instead of the four (4) P-connectors 608 of the double-sided P-type well connector 522. Well connector unit 1000 includes fin cuts 1014(1)-1014(3) dividing portions 1016, 1018, 1020 and 1022, which correspond to portions 510, 512, 514 and 516 of well connector unit 400, respectively. As the width W400 of well connector unit 400 is, the width W1000 of well connector unit 1000 is equal to fourteen (14) times the gate spacing PGATE. Well connector unit 1000 in Figure 10 includes an N-type well connector 1024(1) in an N-type injection region 1026 of an N-well 1028(1) in the first column 1010(1) and another N-type well connector 1024(2) in an N-type injection region 1026 of an N-well 1028(2) in the second column 1010(2). The N-type injection region 1026 is located in portion 1020 of well connector unit 1000. N-type well connectors 1024(1) and 1024(2) correspond to N-type well connector 524 in Figure 5.

[0050] FIG11 illustrates an exemplary wireless communication device 1100 including radio frequency (RF) elements formed by one or more integrated circuits (ICs) 1102, wherein any IC 1102 may include an exemplary SRAM array circuit, wherein, as illustrated in FIG4, FIG5 and FIG10 and according to any aspect disclosed herein, the P-type wellhead between horizontal N-wells provides a ground voltage VSS to the P-type substrate on both sides of the wellhead unit row to reduce latch-up. As an example, the wireless communication device 1100 may be included in or provided in any of the above-described devices. As shown in FIG11, the wireless communication device 1100 includes a transceiver 1104 and a data processor 1106. The data processor 1106 may include memory for storing data and code. The transceiver 1104 includes a transmitter 1108 and a receiver 1110 supporting bidirectional communication. Generally, the wireless communication device 1100 may include any number of transmitters 1108 and / or receivers 1110 for any number of communication systems and frequency bands. All or part of the transceiver 1104 can be implemented on one or more analog ICs, RFICs, mixed-signal ICs, etc.

[0051] The transmitter 1108 or receiver 1110 can be implemented using a superheterodyne architecture or a direct conversion architecture. In a superheterodyne architecture, the signal undergoes frequency conversion between RF and baseband in multiple stages, for example, conversion from RF to intermediate frequency (IF) in one stage and then from IF to baseband in another stage. In a direct conversion architecture, the signal undergoes frequency conversion between RF and baseband in one stage. Superheterodyne and direct conversion architectures can use different circuit blocks and / or have different requirements. In the wireless communication device 1100 in Figure 11, the transmitter 1108 and receiver 1110 are implemented using a direct conversion architecture.

[0052] In the transmission path, the data processor 1106 processes the data to be transmitted and provides I and Q analog output signals to the transmitter 1108. In the exemplary wireless communication device 1100, the data processor 1106 includes digital-to-analog converters (DACs) 1112(1) and 1112(2) for converting the digital signals generated by the data processor 1106 into I and Q analog output signals (e.g., I and Q output currents) for further processing.

[0053] Within transmitter 1108, low-pass filters 1114(1) and 1114(2) filter the I and Q analog output signals, respectively, to remove unwanted signals caused by the previous digital-to-analog conversion. Amplifiers (AMPs) 1116(1) and 1116(2) amplify the signals from low-pass filters 1114(1) and 1114(2), respectively, and provide I and Q baseband signals. Upconverter 1118 upconverts the I and Q baseband signals using I and Q transmit (TX) local oscillator (LO) signals from TX LO signal generator 1122 via mixers 1120(1) and 1120(2) to provide upconverted signal 1124. Filter 1126 filters upconverted signal 1124 to remove unwanted signals caused by upconversion and noise in the receive band. Power amplifier (PA) 1128 amplifies the up-converted signal 1124 from filter 1126 to obtain the desired output power level and provide a transmit RF signal. The transmit RF signal is routed through duplexer or switch 1130 and transmitted via antenna 1132.

[0054] In the receiving path, antenna 1132 receives the signal transmitted by the base station and provides the received RF signal, which is routed through duplexer or switch 1130 and provided to low noise amplifier (LNA) 1134. Duplexer or switch 1130 is designed to operate at a specific receive (RX) to TX duplexer frequency separation so that the RX signal is isolated from the TX signal. The received RF signal is amplified by LNA 1134 and filtered by filter 1136 to obtain the desired RF input signal. Downconversion mixers 1138(1) and 1138(2) mix the output of filter 1136 with the I and Q RX LO signals (i.e., LO_I and LO_Q) from RX LO signal generator 1140 to generate I and Q baseband signals. The I and Q baseband signals are amplified by AMPs 1142(1) and 1142(2) and further filtered by low-pass filters 1144(1) and 1144(2) to obtain I and Q analog input signals, which are provided to data processor 1106. In this example, data processor 1106 includes analog-to-digital converters (ADCs) 1146(1) and 1146(2) for converting the analog input signals into digital signals for further processing by data processor 1106.

[0055] In the wireless communication device 1100 of Figure 11, the TX LO signal generator 1122 generates I and Q TX LO signals for up-conversion, while the RX LO signal generator 1140 generates I and Q RX LO signals for down-conversion. Each LO signal is a periodic signal with a specific base frequency. The TX phase-locked loop (PLL) circuit 1148 receives timing information from the data processor 1106 and generates control signals used to adjust the frequency and / or phase of the TX LO signals from the TX LO signal generator 1122. Similarly, the RX PLL circuit 1150 receives timing information from the data processor 1106 and generates control signals used to adjust the frequency and / or phase of the RX LO signals from the RX LO signal generator 1140.

[0056] The wireless communication device 1100 can be provided or integrated into any processor-based device. Each of the wireless communication devices 1100 includes an exemplary SRAM array in which, as illustrated in Figures 4, 5 and 10 and according to any aspect disclosed herein, the P-type wellhead joints between horizontal N-wells provide a ground voltage connection parallel to the P-type substrates located on both sides of the wellhead joint cell row to reduce latch-up. Examples, but not limited to, include set-top boxes, entertainment units, navigation devices, communication devices, fixed location data units, mobile location data units, Global Positioning System (GPS) devices, mobile phones, cellular phones, smartphones, Session Initiation Protocol (SIP) phones, tablets, tablet phones, servers, computers, portable computers, mobile computing devices, wearable computing devices (e.g., smartwatches, health or fitness trackers, glasses, etc.), desktop computers, personal digital assistants (PDAs), monitors, computer monitors, televisions, tuners, radios, satellite radios, music players, digital music players, portable music players, digital video players, video players, digital video disc (DVD) players, portable digital video players, automobiles, vehicle components, avionics systems, drones, and multi-rotor aircraft.

[0057] In this regard, FIG12 illustrates an example of a processor-based system 1200 including an SRAM array, wherein, as illustrated in FIG4, FIG5, and FIG10 and according to any aspect disclosed herein, the P-type wellheads between horizontal N-wells provide a ground voltage connection to the P-type substrates on both sides of the wellhead unit row in parallel to reduce latch-up. In this example, the processor-based system 1200 includes one or more central processing unit (CPU) units 1202, which may also be referred to as CPUs or processor cores, each including one or more processors 1204. The CPU(s) 1202 may have cache memory 1206 coupled to the processor(s) 1204 for fast access to temporarily stored data. As an example, the processor(s) 1204 may include exemplary SRAM array circuitry, wherein, as illustrated in FIG4, FIG5, and FIG10 and according to any aspect disclosed herein, the P-type wellheads between horizontal N-wells provide a ground voltage VSS to the P-type substrates on both sides of the wellhead unit row to reduce latch-up. Multiple CPUs 1202 are coupled to system bus 1208 and can couple master and slave devices contained in processor-based system 1200 to each other. As is known, the multiple CPUs 1202 communicate with these other devices by exchanging address, control, and data information on system bus 1208. For example, the multiple CPUs 1202 can transmit bus transaction requests to memory controller 1210, which is an example of a slave device. Although not shown in Figure 12, multiple system buses 1208 may be provided, each with a different configuration.

[0058] Other master and slave devices may be connected to system bus 1208. As illustrated in FIG12, these devices may include memory system 1212, which, as an example, includes storage controller 1210 and one or more memory arrays 1214, one or more input devices 1216, one or more output devices 1218, one or more network interface devices 1220, and one or more display controllers 1222. Each of memory system 1212, one or more input devices 1216, one or more output devices 1218, one or more network interface devices 1220, and one or more display controllers 1222 may include exemplary SRAM array circuitry, wherein, as illustrated in FIG4, FIG5, and FIG10 and in accordance with any aspect disclosed herein, the P-type wellhead between horizontal N-wells provides a ground voltage VSS to the P-type substrates on both sides of the wellhead unit row to reduce latch-up. The input devices (multiple) 1216 may include any type of input device, including but not limited to input keys, switches, voice processors, etc. The (multiple) output devices 1218 may include any type of output device, including but not limited to audio, video, and other visual indicators. The (multiple) network interface devices 1220 may be any device configured to allow data exchange with the network 1224. The network 1224 may be any type of network, including but not limited to wired or wireless networks, private or public networks, local area networks (LANs), wireless local area networks (WLANs), wide area networks (WANs), BLUETOOTH™ networks, and the Internet. The (multiple) network interface devices 1220 may be configured to support any desired type of communication protocol.

[0059] The (multiple) CPUs 1202 may also be configured to access the (multiple) display controllers 1222 via system bus 1208 to control information sent to one or more displays 1226. The (multiple) display controllers 1222 send information to the (multiple) displays 1226 for display via one or more video processors 1228, which process the information to be displayed into a format suitable for the (multiple) displays 1226. The (multiple) displays 1226 may include any type of display, including but not limited to cathode ray tube (CRT), liquid crystal display (LCD), plasma display, light-emitting diode (LED) display, etc. The (multiple) display controllers 1222, the (multiple) displays 1226, and / or the (multiple) video processors 1228 may include exemplary SRAM array circuitry in which, as illustrated in Figures 4, 5, and 10 and according to any aspect disclosed herein, the P-type wellhead between horizontal N-wells provides a ground voltage VSS to the P-type substrates on both sides of the wellhead unit row to reduce latch-up.

[0060] Those skilled in the art will further appreciate that the various illustrative logic blocks, modules, circuits, and algorithms described in conjunction with the aspects disclosed herein can be implemented as electronic hardware, stored in memory or another computer-readable medium, and executed by a processor or other processing device, or a combination of both. As an example, the master and slave devices described herein can be employed in any circuit, hardware component, IC, or IC chip. The memory disclosed herein can be of any type and size and can be configured to store any type of information desired. To clearly illustrate this interchangeability, various illustrative elements, blocks, modules, circuits, and steps have been described above generally in terms of their functionality. How such functionality is implemented depends on the specific application, design choices, and / or design constraints imposed on the entire system. Those skilled in the art can implement the described functionality in different ways for each specific application, but such implementation decisions should not be construed as departing from the scope of this disclosure.

[0061] The various illustrative logic blocks, modules, and circuits described in connection with the aspects disclosed herein may be implemented or executed using a processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware element, or any combination thereof designed to perform the functions described herein. The processor may be a microprocessor, but alternatively, it may be any conventional processor, controller, microcontroller, or state machine. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors combined with a DSP core, or any other such configuration).

[0062] The aspects disclosed herein can be embodied in hardware and in instructions stored in hardware, and can reside in, for example, random access memory (RAM), flash memory, read-only memory (ROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM), registers, hard disks, removable disks, CD-ROMs, or any other form of computer-readable media known in the art. An exemplary storage medium is coupled to a processor such that the processor can read information from the storage medium and write information to the storage medium. Alternatively, the storage medium can be integrated into the processor. The processor and storage medium can reside in an ASIC. The ASIC can reside in a remote station. Alternatively, the processor and storage medium can reside as discrete components in a remote station, base station, or server.

[0063] It should also be noted that the operational steps described in any exemplary aspect of this document are described to provide examples and discussion. The described operations may be performed in many different orders other than those illustrated. Furthermore, the operations described in a single operational step may actually be performed in multiple different steps. In addition, one or more operational steps discussed in the exemplary aspects may be combined. It should be understood that many different modifications may be made to the operational steps illustrated in the flowcharts, which will be apparent to those skilled in the art. Those skilled in the art will also understand that information and signals can be represented using any of a variety of different techniques and technologies. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the above description may be represented by voltage, current, electromagnetic waves, magnetic fields or particles, light fields or particles, or any combination thereof.

[0064] The foregoing description of this disclosure is provided to enable any person skilled in the art to make or use this disclosure. Various modifications to this disclosure will be apparent to those skilled in the art, and the general principles defined herein can be applied to other variations. Therefore, this disclosure is not intended to be limited to the examples and designs described herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0065] Implementation examples are described in the following numbered clauses: 1. A static random access memory (SRAM) array circuit, comprising: a substrate; multiple columns of SRAM bit cell circuitry disposed on the substrate, each column of the multiple columns extending in a first axial direction; multiple rows of SRAM bit cell circuitry extending in a second axial direction orthogonal to the first axial direction; and a wellhead cell row disposed between a first row and a second row of the multiple rows, the wellhead cell row comprising wellhead cells disposed in each column of the multiple columns; wherein: the substrate comprises a P-type substrate; the wellhead cell in each column comprises an N-well in the P-type substrate, the N-well extending in the first axial direction; The N-well of the wellhead unit in the first column of the plurality of columns is separated from the N-well of the wellhead unit in the second column of the plurality of columns by the P-type substrate; and the P-type wellhead is disposed in the P-type substrate between the N-well of the wellhead unit in the first column and the N-well of the wellhead unit in the second column, and provides a ground voltage to the SRAM bit cell circuit on the first side of the row of wellhead units and to the SRAM bit cell circuit on the second side of the row of wellhead units. 2. The SRAM array circuit according to claim 1, wherein the wellhead unit in the first column further includes an N-type wellhead disposed in the N-well of the wellhead unit in the first column, the N-type wellhead providing a power supply voltage to the SRAM bit cell circuit on the first side of the row of wellhead units and to the SRAM bit cell circuit on the second side of the row of wellhead units. 3. The SRAM array circuit according to claim 2, wherein each wellhead unit further comprises: a P-type injection region extending in the second axial direction; and an N-type injection region extending in the second axial direction; wherein: the P-type wellhead is disposed in the P-type injection region; and the N-type wellhead is disposed in the N-type injection region. 4. The SRAM array circuit according to any one of claims 2 and 3, wherein the P-type wellhead comprises: a plurality of P-connectors on the P-type substrate, each P-connector including a first source / drain region on a first side of the gate region and a second source / drain region on a second side of the gate region, the first source / drain region being electrically coupled to the second source / drain region. 5. The SRAM array circuit according to claim 4, wherein the first source / drain region, the second source / drain region, and the gate region of each of the plurality of P-connectors comprise a fin region on the P-type substrate.6. The SRAM array circuit according to any one of claims 4 and 5, wherein the P-type wellhead further comprises: a first finger including a first portion of a first metal layer coupled to a first source / drain region of a first plurality of P-connectors; a second finger including a second portion of the first metal layer coupled to a second source / drain region of the first plurality of P-connectors; and a second metal layer electrically coupled to the first finger and the second finger. 7. The SRAM array circuit according to claim 6, wherein the P-type wellhead further comprises: a third finger including a third portion of the first metal layer; the second source / drain region of the first plurality of P-connectors including the first source / drain region of a second plurality of P-connectors; and the third finger coupled to the second source / drain region of the second plurality of P-connectors. 8. The SRAM array circuit according to any one of claims 4 to 7, wherein the P-type wellhead comprises eight (8) P-connectors. 9. The SRAM array circuit according to any one of Clauses 4 to 7, wherein the P-type wellhead comprises sixteen (16) P-connectors. 10. The SRAM array circuit according to any one of Clauses 4 to 9, wherein the N-type wellhead of the wellhead unit in the first column comprises: a plurality of N-connectors on the N-well, each N-connector comprising a first source / drain region on a first side of the gate region and a second source / drain region on a second side of the gate region, the first source / drain region being electrically coupled to the second source / drain region. 11. The SRAM array circuit according to Clause 10, wherein the N-type wellhead comprises eight (8) N-connectors. 12. The SRAM array circuit according to any one of Clauses 3 to 11, each wellhead unit further comprising: a fin extending in the first axial direction; and an intermediate fin cut extending in the second axial direction, the intermediate fin cut comprising a fin gap between the fin in the P-type injection region and the fin in the N-type injection region.13. The SRAM array circuit according to Clause 12, each wellhead unit further includes: a first side bit cell termination, the first side bit cell termination being between a first row of the plurality of rows of the SRAM bit cell circuit and the P-type injection region; a first side fin cut, the first side fin cut being between the first side bit cell termination and the P-type injection region, the first side fin cut including a fin gap between the fin in the first side bit cell termination and the fin in the P-type injection region; a second side bit cell termination, the second side bit cell termination being between a second row of the plurality of rows of the SRAM bit cell circuit and the N-type injection region; and a second side fin cut, the second side fin cut being between the second side bit cell termination and the N-type injection region, the second side fin cut including a fin gap between the fin in the second side bit cell termination and the fin in the N-type injection region. 14. The SRAM array circuit according to any one of clauses 12 and 13, further comprising gates extending over the fin in the second axial direction and spaced apart by a gate pitch in the first axial direction; wherein: the wellhead unit row is between a first SRAM bit cell circuit in the first row of the plurality of rows and a second SRAM bit cell circuit in the second row of the plurality of rows; and the width of the wellhead unit row is equal to fourteen (14) times the gate pitch in the first axial direction. 15. The SRAM array circuit of any one of clauses 1 to 14 is integrated into a radio frequency (RF) front-end module. 16. An SRAM array circuit according to any one of Clauses 1 to 14, integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; Global Positioning System (GPS) devices; mobile phones; cellular phones; smartphones; Session Initiation Protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft.17. An integrated circuit (IC) including a static random access memory (SRAM) array circuit, the SRAM array circuit comprising: a substrate; multiple columns of SRAM bit cell circuits disposed on the substrate, each column of the multiple columns extending in a first axial direction; multiple rows of SRAM bit cell circuits extending in a second axial direction orthogonal to the first axial direction; and a wellhead cell row disposed between a first row and a second row of the multiple rows, the wellhead cell row including wellhead cells disposed in each column of the multiple columns; wherein: the substrate comprises a P-type substrate; the wellhead cell in each column includes an N-well in the P-type substrate, the N-well extending in the first axial direction; The N-well of the wellhead unit in the first column of the plurality of columns is separated from the N-well of the wellhead unit in the second column of the plurality of columns by the P-type substrate; and the P-type wellhead is disposed in the P-type substrate between the N-well of the wellhead unit in the first column and the N-well of the wellhead unit in the second column, and provides a ground voltage to the SRAM bit cell circuit on the first side of the row of wellhead units and to the SRAM bit cell circuit on the second side of the row of wellhead units. 18. The IC according to claim 17, wherein the wellhead unit in the first column further includes an N-type wellhead disposed in the N-well of the wellhead unit in the first column, the N-type wellhead providing a power supply voltage to the SRAM bit cell circuit on the first side of the row of wellhead units and to the SRAM bit cell circuit on the second side of the row of wellhead units. 19. The IC according to claim 18, each wellhead unit further includes: a P-type injection region extending in the second axial direction; and an N-type injection region extending in the second axial direction; wherein: the P-type wellhead is disposed in the P-type injection region; and the N-type wellhead is disposed in the N-type injection region. 20. The IC according to any one of claims 17 to 19, the SRAM array circuit further includes gates extending over the fin in the second axial direction and spaced apart by a gate pitch in the first axial direction; wherein: the wellhead unit row is between a first SRAM bit cell circuit in the first row of the plurality of rows and a second SRAM bit cell circuit in the second row of the plurality of rows; and the width of the wellhead unit row is equal to fourteen (14) times the gate pitch in the first axial direction. [Simplified Explanation of the Diagram]

[0008] Figure 1 is a top view illustration of a static random access memory (SRAM) array circuit in two memory array architecture configurations, wherein each SRAM array circuit includes a row of wellhead cells to reduce latch-up.

[0009] Figure 2 is a top view illustration of the substrate region in the well header cell of the SRAM array circuit, wherein the vertical N-well divides the region of the P-type substrate into a first side and a second side.

[0010] Figure 3 is a top view of the well connector unit in Figure 2, which includes a circuit layer and shows a P-type well connector on each side of the vertical N-well in each column of the SRAM array circuit to provide a ground voltage to the P-type substrate.

[0011] FIG4 is a top view illustration of a substrate region in an exemplary well joint unit, which includes a P-type substrate extending uninterruptedly between N wells in each column.

[0012] FIG5 is a top view illustration of the substrate in FIG4 including the circuit layer of the exemplary well joint unit, wherein the double-sided P-type well joint disposed between horizontal N wells provides ground voltage to the P-type substrate on both sides of the well joint unit row in parallel.

[0013] Figure 6 is a top view illustration of a P-type well connector, in which three folded fingers are coupled together to provide a grounding voltage to the P-type substrate in parallel.

[0014] Figure 7 is a top view illustration of the N-type well joint area, in which three folded fingers are coupled together to provide power voltage to the N-well in parallel.

[0015] Figure 8 is a diagram of a cross-sectional end view of the fin, wherein the P-connector and the N-connector are formed in the well joint unit.

[0016] Figure 9 is a schematic diagram of a cross-sectional side view of the fin, wherein the P-connector and the N-connector are formed in the well joint unit.

[0017] Figure 10 is a top view illustration of another exemplary well connector unit in an SRAM array circuit, wherein a double-sided P-type well connector disposed in a horizontal P-type substrate provides a ground voltage to the P-type substrate on both sides of the well connector unit row in parallel.

[0018] FIG11 is a block diagram of an exemplary wireless communication device including a radio frequency (RF) module, which includes an SRAM array containing the wellhead unit shown in FIG4, FIG5 and FIG10.

[0019] As illustrated in Figures 4, 5 and 10 and according to any aspect disclosed herein, Figure 12 is a block diagram of an exemplary integrated circuit (IC) package including an exemplary SRAM array circuit, wherein a P-type well header between horizontal N-wells provides a ground voltage VSS to the P-type substrate on both sides of the well header cell row to reduce latch-up.

Claims

1. A static random access memory (SRAM) array circuit, comprising: substrate; A multi-column SRAM bit cell circuit is disposed on the substrate, each of the multiple columns extending in a first axial direction; The SRAM bit cell circuit has multiple rows, which extend along a second axis orthogonal to the first axis direction; A row of well connector units is disposed between a first row and a second row of the plurality of rows, the row of well connector units comprising well connector units disposed in each of the plurality of columns; wherein: the substrate comprises a P-type substrate; the well connector unit in each column comprises an N-well in the P-type substrate, the N-well extending in the first axial direction to SRAM bit circuitry in both the first and second rows of the plurality of rows; the N-well of the well connector unit in the first column of the plurality of columns is separated from the N-well of the well connector unit in the second column of the plurality of columns by the P-type substrate; A double-sided P-type well connector is disposed in the P-type substrate between the N-well of the well connector unit in the first column and the N-well of the well connector unit in the second column, such that the double-sided P-type well connector is partially located within the well connector unit in the first column and partially located within the well connector unit in the second column, and provides a ground voltage to the SRAM bit cell circuit on the first side of the row of well connector units and to the SRAM bit cell circuit on the second side of the row of well connector units.

2. The SRAM array circuit according to claim 1, wherein the well connector unit in the first column further includes an N-type well connector disposed in the N wells of the well connector unit in the first column, the N-type well connector providing a power supply voltage to the SRAM bit cell circuit on the first side of the row of the well connector unit and to the SRAM bit cell circuit on the second side of the row of the well connector unit.

3. The SRAM array circuit according to claim 2, wherein each wellhead unit further comprises: The P-type injection region extends in the direction of the second axis; and an N-type injection region extending in the direction of the second axis; wherein: the bilateral P-type well joint is disposed in the P-type injection region; The N-type well joint is located in the N-type injection area.

4. The SRAM array circuit according to claim 2, wherein the bilateral P-type well connector comprises: A plurality of P-connectors are provided on the P-type substrate. Each P-connector includes a first source / drain region on a first side of the gate region and a second source / drain region on a second side of the gate region, wherein the first source / drain region is electrically coupled to the second source / drain region.

5. The SRAM array circuit according to claim 4, wherein the first source / drain region, the second source / drain region, and the gate region of each of the plurality of P-connectors include regions of fins on the P-type substrate.

6. The SRAM array circuit according to claim 4, wherein the bilateral P-type well connector further comprises: A first folded finger, the first folded finger including a first portion of a first metal layer, the first portion of the first metal layer being coupled to the first source / drain region of a first plurality of P-connectors; a second folded finger, the second folded finger including a second portion of the first metal layer, the second portion of the first metal layer being coupled to the second source / drain region of the first plurality of P-connectors. And a second metal layer, which is electrically coupled to the first folded finger and the second folded finger.

7. The SRAM array circuit according to claim 6, wherein the bilateral P-type well connector further comprises: The third folded finger includes a third portion of the first metal layer; The second source / drain region of the first plurality of P-connectors includes the first source / drain region of the second plurality of P-connectors; and the third folded finger is coupled to the second source / drain region of the second plurality of P-connectors.

8. The SRAM array circuit according to claim 4, wherein the bilateral P-type wellhead includes eight (8) P-connectors.

9. The SRAM array circuit according to claim 4, wherein the bilateral P-type wellhead comprises sixteen (16) P-connectors.

10. The SRAM array circuit according to claim 4, wherein the N-type well connector of the well connector unit in the first column comprises: The N-well has a plurality of N-connectors, each N-connector including a first source / drain region on a first side of the gate region and a second source / drain region on a second side of the gate region, the first source / drain region being electrically coupled to the second source / drain region.

11. The SRAM array circuit according to claim 10, wherein the N-type well connector comprises eight (8) N-connectors.

12. The SRAM array circuit according to claim 3, each wellhead unit further includes: The fin extends in the direction of the first axis; And an intermediate fin cut extending in the second axial direction, the intermediate fin cut including a fin gap between the fin in the P-type injection region and the fin in the N-type injection region.

13. The SRAM array circuit according to claim 12, each wellhead unit further includes: The first side bit cell terminates between the first row of the multiple rows of the SRAM bit cell circuit and the P-type injection region. A first side fin cut, the first side fin cut being between the first side bit cell termination and the P-type injection region, the first side fin cut including a fin gap between the fin in the first side bit cell termination and the fin in the P-type injection region; a second side bit cell termination, the second side bit cell termination being between the second row of the multiple rows of the SRAM bit cell circuit and the N-type injection region. And a second lateral fin cut, the second lateral fin cut being between the second lateral bit cell termination and the N-type injection region, the second lateral fin cut including a fin gap between the fin in the second lateral bit cell termination and the fin in the N-type injection region.

14. The SRAM array circuit according to claim 12, further comprising gates extending over the fin in the second axial direction and spaced apart by a gate pitch in the first axial direction; wherein: The well joint unit row is between the first SRAM bit cell circuit in the first row of the plurality of rows and the second SRAM bit cell circuit in the second row of the plurality of rows; and the width of the well joint unit row is equal to fourteen (14) times the gate spacing in the first axial direction.

15. The SRAM array circuitry described in claim 1 is integrated into a radio frequency (RF) front-end module.

16. The SRAM array circuitry of claim 1 is integrated into a device selected from the group consisting of: set-top boxes; entertainment units; navigation devices; communication devices; fixed location data units; mobile location data units; Global Positioning System (GPS) devices; mobile phones; cellular phones; smartphones; Session Initiation Protocol (SIP) phones; tablet computers; tablet phones; servers; computers; portable computers; mobile computing devices; wearable computing devices; desktop computers; personal digital assistants (PDAs); monitors; computer monitors; televisions; tuners; radios; satellite radios; music players; digital music players; portable music players; digital video players; video players; digital video disc (DVD) players; portable digital video players; automobiles; vehicle components; avionics systems; unmanned aerial vehicles; and multi-rotor aircraft.

17. An integrated circuit (IC) comprising the SRAM array circuit described in any one of claims 1 to 16.

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