Interposer, integrated circuit package, method for fabricating an interposer, and package

Abstract

An integrated circuit (IC) package includes: a die having a first set of interconnects with a first spacing; and an intermediary including an organic substrate having a second set of interconnects with a second spacing. The intermediary also includes an inorganic layer above the organic substrate. The inorganic layer includes conductive traces electrically coupling the second set of interconnects to the first set of interconnects. The die is attached to the intermediary via the first set of interconnects. In some embodiments, the intermediary further includes an embedded die. The IC package further includes a package support and a second inorganic layer above a surface of the intermediary opposite to the die, the package support having a third set of interconnects with a third spacing. The second inorganic layer includes conductive traces electrically coupling the third set of interconnects to the second set of interconnects.

Description

[Technical Field]

[0001] Field of Invention

[0002] This disclosure relates to techniques, methods and apparatus involving an inorganic redistribution layer (RDL) over an organic substrate in an integrated circuit (IC) package. [Previous Technology]

[0003] Background of the Invention

[0004] Electronic circuits fabricated on wafers of semiconductor materials such as silicon are commonly referred to as ICs. Wafers containing such ICs are typically diced into multiple individual dies. These dies can be packaged into an IC package containing one or more dies along with other electronic components, such as resistors, capacitors, and inductors. The IC package can then be integrated into electronic systems such as consumer electronics systems. Over the past few decades, the reduction in feature structures and spacing in ICs has been a driving force in the semiconductor industry, allowing for increased density of functional units on a limited semiconductor wafer substrate. [Summary of the Invention]

[0005] According to one embodiment of the present invention, an intermediary is specifically provided, comprising: an organic substrate including a first set of interconnects having a first spacing; an inorganic layer including a second set of interconnects having a second spacing; and a conductive trace electrically coupling the first set of interconnects to the second set of interconnects, wherein: the inorganic layer is above the organic substrate, and the second spacing is different from the first spacing.

Implementation Method

[0024] Detailed Description of Preferred Embodiments

[0025] For the purpose of illustrating the IC package described herein, it is important to understand the phenomena that can function during the assembly and packaging of the IC. The following basic information can be considered as the basis for properly interpreting the contents of this disclosure. This information is provided for illustrative purposes only and therefore should not be considered as limiting the scope of this disclosure and its possible applications in any way.

[0026] In a general sense, as transistor density increases with each new silicon processing node, package architecture must expand accordingly. Current packaging challenges relate to reducing the spacing between first-level interconnects (FLI) (e.g., interconnects between the die and the package substrate) to below the spacing achievable with solder joints. Additionally, wiring density is also a challenge, as it varies with the trace width, trace spacing, and via size required for wiring between layers. For example, silicon interposers using 65 nm copper back-end (BEOL) technology are typically wired with trace spacings ranging from 1 micrometer to 4 micrometers, posing a challenge to solder-based interconnect technologies.

[0027] Furthermore, as transistor density increases with each new silicon processing node, producing monolithic dies becomes extremely difficult, leading to the increasing use of die decomposition to address the shortcomings of pure 3D stacking solutions in terms of yield, thermal management, and redesign of each silicon node. One example of a die decomposition scheme is the Omnidirectional Interconnect (ODI) architecture, which uses larger copper pillars in a base composite intermediate (also referred to as the "base composite" or simply the "intermediate," used interchangeably herein) directly connected to the die from the package. This base composite intermediate includes one or more embedded dies within the substrate and localized embedded through-silicon vias (or through-substrate vias) (TSVs). In a general sense, the base composite interconnect is a micro logic bump (MLB) (also referred to herein as a "micro bump") at the base composite to top die interface or a package-side bump (PSB) at the base composite to package interface.

[0028] However, a spacing mismatch exists between the MLB and PSB on either side of the base complex, where the MLB spacing is much smaller than the PSB spacing. If there is no RDL at the MLB, the interconnects of the top die, embedded TSV die, and copper pillars in the base complex will be constrained to have a common spacing, significantly limiting the top die pitch and restricting design flexibility and manufacturability. If there is no RDL at the PSB, the spacing between PSBs in the base complex will be constrained to match the top die pitch. As the base complex size increases and the top die pitch decreases, this makes it difficult to attach the base complex to a PCB or another package substrate. Current solutions to the spacing mismatch use redundant MLBs, such as dummy or floating bumps.

[0029] In existing packaging architectures, the most commonly used FLI material is copper bump, where the solder cap is on the die and the pad is on the package substrate, or gold-plated copper pad is on the die and solder paste or solder balls are on the package substrate. Lead-based solder with a melting point of approximately 185°C and lead-free solder with a melting point of 235°C are widely used in these architectures. However, these solder-based interconnects cannot achieve the extremely fine pitch (e.g., less than 10 micrometers) required for new silicon-processed nodes.

[0030] Hybrid direct bonding, including dielectric bonding and metal-to-metal (e.g., Cu-Cu) bonding, offers a promising solution, but faces significant integration challenges due to stringent manufacturing requirements (particularly at the packaging level, such as manufacturing hybrid direct interconnects in wafer-level packages) and the lower temperatures required by complementary metal-oxide-semiconductor (CMOS) processes and typical packaging materials. For example, manufacturing processes often have to balance high-yield bonding processes for dielectric and metal interfaces with maintaining low processing temperatures to ensure package integrity. Many studies have shown that silicon carbonitride (SiCN) dielectrics have advantages over silicon oxide (SiO2) in reducing bonding temperatures, particularly lowering annealing temperatures to below or equal to 250 degrees Celsius. However, these studies utilize plasma-enhanced chemical vapor deposition (PECVD), which requires high deposition temperatures (i.e., 370 degrees Celsius) and precursors.

[0031] Furthermore, these films require pre-bonding densification above the deposition temperature to prevent voids at the bonding interface. Physical vapor deposition (PVD) is a superior method for silicon nitride (SiN) dielectric deposition, allowing bonding at low deposition temperatures. PVD processes do not require densification pre-bonding and can achieve considerable bond strength at low post-bonding annealing temperatures. However, SiN layers are typically formed over inorganic dielectric materials, such as silicon oxides and similar materials, used in back-to-the-line (BEOL) monolithic semiconductor processes, which are not used in packaging materials during packaging-level manufacturing processes.

[0032] Another solution is to use an RDL on the die, which can accommodate different line spacings between the die and the package substrate. Generally, redistribution layers are used to redistribute contacts from the surface of the die or package substrate to different layers, which allows for higher contact density and different spacings between layers. For example, RDLs are typically positioned above the die to achieve finer spacing at the die interface and coarser spacing at the package substrate and / or solder balls interface. In such configurations, the RDL is typically an organic material compatible with the underlying dielectric of the die (e.g., SiN and SiO2). In some packages where the RDL is disposed on a package substrate (e.g., a thin film on a molding compound), the RDL is an organic material compatible with the underlying organic dielectric of the package substrate. For example, WPR® (a registered trademark of JSR Corporation, Tokyo, Japan) is a typical photosensitive dielectric material used to form RDLs, and is also used as an outer coating layer in wafer-level chip-scale packages (WL-CSPs) and an organic passivation layer in semiconductor devices. It has a low curing temperature (≤ 200 degrees Celsius), excellent adhesion to silicon nitride and silicon oxide, and low residual stress. However, it cannot support RDL thicknesses smaller than 5 micrometers, as well as the corresponding feature sizes and spacings.

[0033] Furthermore, a feasible manufacturing process for generating sub-5-micron pitch feature sizes in organic RDL layers remains an ongoing challenge and has not yet been satisfactorily resolved. For example, laser ablation of organic dielectric materials removed from the surface can provide feature sizes smaller than 5 microns; however, this process is messy and slow. Another approach is to use stencil-printed organic films on a molding compound; however, this technology is still in its early stages. In another approach, ultra-fine pitch organic substrates (uFOS) achieve linewidths / pitches as low as 2 microns, but require multiple redistribution layers. Moreover, this high-density fan-out (HDFO) organic intermediate is best suited for applications requiring trace pitches of 3 to 10 microns, which is higher than the trace pitches of some silicon-processed nodes, and therefore less suitable for such nodes.

[0034] Compared to organic RDL layers, inorganic passivation layers used in semiconductor manufacturing provide a protective barrier for the active semiconductor surface, shielding it from the influence of the surrounding environment. Their thickness is sufficient to allow vias and features with extremely low pitch. Passivation layers made of silicon nitride and similar materials used in semiconductor manufacturing typically exhibit good adhesion to the underlying silicon and are chemically inert, corrosion-resistant dielectrics, providing a barrier against water diffusion. Depending on the requirements, they can be formed to a thickness of less than 100 nanometers and fabricated using several known techniques, including atomic layer deposition (ALD), spin coating, electrochemical deposition, sputtering, electron beam evaporation, float transfer, and dip casting. In some typical semiconductor manufacturing processes, passivation layers are formed by depositing silicon oxide and silicon nitride layers on the semiconductor substrate using PECVD. Capping layers are another type of barrier layer typically formed on the surface above interconnects. Silicon nitride, silicon carbide, silicon carbonitride, and silicon oxide are commonly used as capping layers for interconnects because these materials act as a barrier to copper diffusion and as an etch stop layer for any subsequent bimetallic damascene etching process.

[0035] Compared to such inorganic passivation layers over inorganic substrates such as silicon, the various embodiments of this disclosure comprise inorganic passivation layers over organic substrates such as epoxy resins. In a general sense, known techniques exist for passivating flexible plastic substrates such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), and polyethersulfone (PES) with thinner silicon nitride (Si3N4) films as effective diffusion barriers. However, such thin inorganic layers over plastic substrates are ineffective in any RDL capacity. Furthermore, depositing silicon nitride films with high density, good uniformity, and good adhesion onto flexible plastic substrates is challenging at low temperatures. The embodiments disclosed herein differ from such films over a flexible plastic substrate in the nature of the underlying substrate (e.g., epoxy-based, or mold-based, rather than PET-based), the process used to deposit such inorganic layers (e.g., low temperature), and the function of the inorganic layers (e.g., RDL, rather than simply a protective barrier in flexible PET applications).

[0036] In one embodiment of this disclosure, an example of a mediator includes a substrate comprising an organic insulator and an inorganic layer above the organic insulator. As used herein, the term "mediator" refers to a structure comprising a substrate having electrical paths therein for guiding electrical energy (e.g., power, ground, and / or signals) from one surface to an opposite surface. In some embodiments, the mediator may be coupled to one or more dies on one surface and a package support on an opposite surface. In other embodiments, the mediator may be coupled to one or more dies on one surface and to one or more dies on an opposite surface. In still other embodiments, the mediator may be coupled to one or more dies on one surface and to a printed circuit board (PCB) on an opposite surface. In still other embodiments, a plurality of such mediators may be stacked one on top of another. In some embodiments, the mediator further includes dies embedded therein. Although intermediates may generally comprise organic materials (e.g., silica-filled epoxy resin) and inorganic materials (e.g., ceramics), the embodiments described herein refer to a substrate comprising an organic insulator. The organic insulator has interconnects with a first spacing therein, and the inorganic layer has interconnects with a second spacing therein, the second spacing being smaller than the first spacing.

[0037] Each of the structures, assemblies, packages, methods, apparatuses, and systems disclosed herein may have several innovative forms, and none of them is solely responsible for all the desired properties disclosed herein. Details of one or more embodiments of the subject matter described in this specification are set forth in the following description and accompanying drawings.

[0038] In the following detailed description, various exemplary embodiments may be described using terminology commonly used by those skilled in the art to convey the essence of their work to others skilled in the art. For example, the term "connection" means a direct connection between connected things without any intermediate means (which may be one or more of a mechanical connection, electrical connection, and / or thermal connection), while the term "coupled" means a direct connection between connected things, or an indirect connection via one or more passive or active intermediate means. The term "circuit" means one or more passive and / or active components configured to cooperate with each other to provide a desired function. The term "interconnect" may be used to describe any element formed of conductive material for providing electrical connections to one or more components associated with an IC or / or providing electrical connections between various such components. Generally, "interconnect" may refer to two conductive traces (sometimes also called "wires") and conductive vias. Generally, in the context of interconnects, the term "conductive trace" can be used to describe a conductive element isolated by an insulating material (e.g., a low-k dielectric material) provided in the plane of the IC die. Such traces are typically stacked across several layers of a metallization stack. On the other hand, the term "via" can be used to describe a conductive element that interconnects two or more traces across different layers. For this purpose, a via can be positioned substantially perpendicular to the plane of the IC die and can interconnect two traces in adjacent layers or two traces in non-adjacent layers. The term "metallization stack" can be used to refer to a stack of one or more interconnects used to provide connections to different circuit components of an IC chip. Sometimes, traces and vias can be referred to as "conductive traces" and "conductive vias," respectively, to emphasize the fact that these elements include conductive materials such as metals.

[0039] Interconnects as described herein, and especially interconnects of IC structures as described herein, can be used to provide electrical connections to one or more components associated with the IC and / or to provide electrical connections between various such components. In various embodiments, components associated with the IC may include, for example, transistors, diodes, power supplies, resistors, capacitors, inductors, sensors, transceivers, receivers, antennas, etc. Components associated with the IC may include components mounted on the IC or connected to the IC. The IC may be analog or digital and can be used in many applications, such as microprocessors, optoelectronic devices, logic blocks, audio amplifiers, etc., depending on the components associated with the IC. The IC may be used as part of a chipset for performing one or more related functions in a computer. In another instance, the terms "package" and "IC package" are synonymous, as are the terms "die" and "IC die," the term "insulation" means "electrically insulating," and the term "conductivity" means "conductive," unless otherwise specified.

[0040] In yet another instance, if used, the terms “oxide,” “carbide,” “nitride,” etc. refer to compounds that respectively contain oxygen, carbon, nitrogen, etc., the term “high-k dielectric” refers to a material with a dielectric constant higher than that of silicon oxide, and the term “low-k dielectric” refers to a material with a dielectric constant lower than that of silicon oxide.

[0041] The terms “substantially,” “near,” “approximately,” “close to,” and “about” generally refer to a target value within + / - 20% (e.g., within + / - 5 or 10% of the target value) in the context of a specific value as described herein or known in the art. Similarly, terms indicating the orientation of various elements, such as “coplanar,” “perpendicular,” “orthogonal,” “parallel,” or any other angle between elements, generally refer to a target value within + / - 5 to 20% in the context of a specific value as described herein or known in the art.

[0042] As used herein, the terms “above,” “below,” “between,” and “on” refer to the relative position of a material layer or component with respect to other layers or components. For example, a layer disposed above or below another layer may be in direct contact with that other layer or may have one or more intervening layers. Furthermore, a layer disposed between two layers may be in direct contact with one or both of the two layers or may have one or more intervening layers. In contrast, a first layer described as “on” a second layer refers to a layer in direct contact with that second layer. Similarly, unless otherwise explicitly stated, a feature disposed between two features may be in direct contact with an adjacent feature or may have one or more intervening layers. Additionally, as used herein, the term “disposed” refers to location, position, placement, and / or arrangement, and not any particular method of formation.

[0043] For the purposes of this disclosure, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this disclosure, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C). The term "between" when used in reference measurement ranges includes the ends of the measurement range. When used herein, the notation "A / B / C" means (A), (B), and / or (C).

[0044] The description uses the phrases "in one embodiment" or "in an embodiment," which may each refer to one or more of the same or different embodiments. Furthermore, as used with respect to embodiments of this disclosure, the terms "comprising," "including," "having," and the like are synonymous. This disclosure may use perspective-based descriptive terms such as "above," "below," "top," "bottom," and "side"; these descriptions are used for ease of discussion and are not intended to limit the application of the disclosed embodiments. The drawings are not necessarily drawn to scale. Unless otherwise specified, the use of ordinal adjectives such as "first," "second," and "third" to describe common objects only indicates reference to different examples of similar objects and is not intended to imply that the objects described must be in a given sequence, whether temporally, spatially, hierarchically, or in any other way.

[0045] In the following detailed description, reference is made to the accompanying drawings, which form part of this document and illustrate practical embodiments by way of illustration. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of this disclosure. Therefore, the following detailed description should not be considered limiting.

[0046] In the figures, the same reference numerals refer to the same or similar elements / materials shown, such that, unless otherwise stated, the interpretation of an element / material having a given reference numeral provided in the context of one of the figures may be applied to other figures in which elements / materials having the same reference numerals may be shown. Furthermore, in the figures, some schematic illustrations of example structures of the various devices and assemblies described herein may be shown with precise right angles and straight lines; however, it should be understood that such schematic illustrations may not reflect actual process limitations, which may produce less "ideal" features when any of the structures described herein is examined using images (such as scanning electron microscopy (SEM) images, transmission electron microscopy (TEM) images, or non-contact profilometers) with appropriate characterization tools. In such images of real structures, possible processing and / or surface defects may also be visible, such as surface roughness, curvature or profile deviations, pits or scratches, imperfectly straight edges of the material, tapered through-holes or other openings, unintentional rounding or thickness variations at corners of different material layers, accidental spiral misalignments within crystalline regions, edge misalignments or combined misalignments, and / or accidental misalignment defects of single atoms or clusters of atoms. Other defects not listed here but common to the fields of device manufacturing and / or packaging may also exist.

[0047] In the figures, for illustrative purposes, a particular number and arrangement of structures and components are shown, and any desired number or arrangement of such structures and components may exist in various embodiments. Furthermore, the structures shown in the figures may take any suitable form or shape depending on the material properties, manufacturing process, and operating conditions.

[0048] Various operations can be described in a manner most conducive to understanding the claimed subject matter as a series of discrete actions or operations arranged sequentially. However, the order of description should not be construed as implying that such operations must depend on the order. Specifically, these operations may not be performed in the order presented. The described operations may be performed in an order different from the described embodiments. Various additional operations may be performed, and / or the described operations may be omitted in additional embodiments. Example Embodiments

[0049] FIG1 is a schematic cross-sectional illustration of an IC package 100 according to some embodiments of the present disclosure. An interposer 101 includes a die 102 embedded within a substrate 104, which includes an organic insulator. An inorganic layer 106 is located on a surface 108 of the substrate 104. In an exemplary embodiment, the inorganic layer 106 includes a silicon nitride (e.g., SixNy). In other embodiments, the inorganic layer 106 may include silicon, carbon, and nitrogen (e.g., SiCN), or silicon and oxygen (e.g., SiO2). The substrate 104 may contain any suitable organic material, including epoxy molding compounds (EMC), epoxy resins, silica-filled epoxy resins, polyimides, polyesters, vinyl polyesters, silica, or glass fibers filled with various additives such as dicis-butenediamide and anti-exudants.

[0050] A through-connector 110 in the substrate 104 provides electrical coupling from the die 102 to the surface 108 of the substrate 104 or between the surface 108 and the opposing surface 112. For example, through-connector 110A provides coupling from the die 102 to the surface 108, and through-connector 110B provides electrical coupling between surfaces 108 and 112. In some embodiments, through-connector 110B may be referred to as a through-hole (TMV). A via 114 within the inorganic layer 106 provides electrical coupling from the through-connector 110 to the surface 116 of the inorganic layer 106. In various embodiments, a conductive trace 118 comprising one or more metal layers may be disposed on the surface 116. For example, conductive trace 118A comprises a single metal layer; conductive trace 118B comprises three metal layers. Within the scope of this disclosure, any number of metal layers may be included in the conductive trace 118. Any of the conductive trace 118, via 114, and / or through connector 110 may be formed of any suitable conductive material such as copper, silver, nickel, gold, aluminum, or other metals or alloys. The conductive trace 118, via 114, and through connector 110 may provide electrical coupling to the die 102 or surface 112, such as providing power, ground, and signal connections to or from the die or surface. In various embodiments, the conductive trace 118 may be suitably interconnected to direct power, ground, and / or signals to / from various components of the IC package 100. In some embodiments, the conductive trace 118 may include bonding pads for electrical coupling to solder balls or other interconnects.

[0051] In various embodiments, the minimum spacing 120 between the vias 114 in the inorganic passivation layer 106 facilitates die-to-die (DTD) interconnects within the IC package 100. In some embodiments, the minimum spacing 120 may be 1 micrometer or less. In other embodiments, the minimum spacing 120 may be less than, for example, 10 micrometers to support DTD interconnects. In still other embodiments, the minimum spacing 120 may be, for example, 100 micrometers or greater to support die-to-package substrate (DTPS) interconnects. In some embodiments, the DTPS interconnects disclosed herein may have a spacing between about 80 micrometers and 300 micrometers, and the DTD interconnects disclosed herein may have a spacing between about 0.7 micrometers and 100 micrometers, both of which may be supported by the inorganic layer 106. Compared to organic redistribution or passivation layers, the inorganic layer 106 in various embodiments can support any spacing that can be manufactured using semiconductor processing techniques. For example, any manufacturing technique that can place a silicon nitride layer over silicon can be used to place an inorganic layer 106 over a substrate 104 containing an organic dielectric. In various embodiments, the spacing 120 can be scalable to accommodate any desired interconnect density, constrained only by the general manufacturing limitations of silicon-processed nodes.

[0052] In some embodiments, the inorganic layer 106 may serve as a single-layer RDL. This application provides design flexibility, allowing top die interconnects or substrate interconnects to be separated from embedded die interconnects by appropriate redistribution of traces. The RDL can reduce any unused areas created by embedding the die 102 in the substrate 104 (e.g., restricted areas near the through-connector 110B) to allow for additional routing for top die connections. Additionally, the inorganic layer 106 overcomes the drawbacks of organic RDLs (such as organic photodefinable dielectrics, including polyimide (PI), polybenzoxazole (PBO), and WPR®, which cannot support extremely fine pitches). In some embodiments, an organic passivation and / or RDL layer (not shown) may be added, for example, on top of the inorganic layer 106 to provide further redistribution.

[0053] A single-layer RDL can also extend the architecture of the IC package 100 by loosening the spacing on the surface 112 to achieve coupling with components having coarser spacing. In embodiments where the die 102 is placed on a mold holder or cavity inside the substrate 104 (e.g., at a controlled height, such as using thermocompression bonding (TCB)), thereby creating a non-routable area below the mold holder, the inorganic layer 106 disposed on the surface 112 (not shown) can act as an RDL layer, appropriately fanning out to interconnects in this area. In some embodiments, the inorganic layer 106 can additionally act as, for example, a passivation and / or barrier layer, preventing electromigration risks and dendrite formation in solder-based interconnects, and acting as a hermetically sealed layer to prevent moisture ingress. In some embodiments, the inorganic layer 106 provides a “reset” of the surface 108 by using vias 114 to provide additional and new areas for rerouting. In some embodiments, the configuration shown in the figure can be used in advanced packaging architectures, such as omnidirectional interconnects (ODI) and similar technologies.

[0054] In some embodiments, the grain 102 may comprise a substrate formed of a substantially single-crystal semiconductor such as silicon or germanium. In some other embodiments, the substrate may be formed using alternative materials, which may or may not be combined with silicon, including but not limited to germanium, indium antimonide, lead telluride, indium arsenide, indium phosphide, gallium arsenide, indium gallium arsenide, gallium antimonide, or other combinations of Group III-V, Group II-VI, or Group IV materials. In still other embodiments, the substrate may comprise, for example, a compound semiconductor having a first sublattice of at least one element from Group III of the periodic table (e.g., Al, Ga, In) and a second sublattice of at least one element from Group V of the periodic table (e.g., P, As, Sb). In still other embodiments, the substrate may comprise an intrinsically IV or III-V semiconductor material or alloy that is not intentionally doped with any electrically active impurities; in alternative embodiments, a nominal impurity dopant level may be present. In other embodiments, the substrate may comprise an organic material, such as a silicon dioxide-filled epoxy resin. In other embodiments, the substrate may comprise a high-mobility oxide semiconductor material, such as tin oxide, antimony oxide, indium oxide, indium tin oxide, titanium oxide, zinc oxide, indium zinc oxide, indium gallium zinc oxide (IGZO), gallium oxide, titanium oxynitride, ruthenium oxide, or tungsten oxide. Generally, the matrix may include one or more of the following: tin oxide, cobalt oxide, copper oxide, antimony oxide, ruthenium oxide, tungsten oxide, zinc oxide, gallium oxide, titanium oxide, indium oxide, titanium oxynitride, indium tin oxide, indium zinc oxide, nickel oxide, niobium oxide, copper peroxide, IGZO, indium telluride, molybdenite, molybdenum diselenide, tungsten diselenide, tungsten disulfide, N- or P-type amorphous or polycrystalline silicon, germanium, indium gallium arsenide, silicon germanium, gallium nitride, aluminum gallium nitride, indium phosphide, and black phosphorus, each of which may be doped with one or more of gallium, indium, aluminum, fluorine, boron, phosphorus, arsenic, nitrogen, tantalum, tungsten, and magnesium.

[0055] In various embodiments, die 102 may include one or more of, or a portion thereof, of the following: interconnect bridges, central processing units, memory devices such as high-bandwidth memory devices, logic circuits, input / output circuit systems, transceivers such as field-programmable gate array transceivers, gate array logic such as field-programmable gate array logic in power delivery circuit systems, III-V or III-N devices such as III-N or III-N amplifiers (e.g., GaN amplifiers), peripheral component high-speed interconnect circuit systems, dual data rate transmission circuit systems, or other electronic components known in the art. In some embodiments, die 102 may include active circuit systems; in other embodiments, die 102 may include only passive circuit systems without any active components. In some embodiments, die 102 may include TSVs; in other embodiments, die 102 may not have TSVs.

[0056] It should be noted that FIG1 is intended to illustrate the relative arrangement of components within its assembly, and in general, such assemblies may include other components not described (e.g., various interface layers or other components related to optical functionality (if applicable), electrical connectivity, or thermal mitigation). For example, in some other embodiments, the assembly shown in FIG1 may include additional dies and other electrical components. Furthermore, although some components of such assemblies are illustrated in FIG1 as planar rectangles or formed of rectangular solids, this is merely for illustrative purposes, and embodiments of such assemblies may be bent, rounded, or otherwise irregularly shaped, as determined by and sometimes unavoidable by the manufacturing processes used to manufacture the various components.

[0057] FIG2 is a schematic cross-sectional illustration of an IC package 100 according to some embodiments of the present disclosure. Intermediate 101 includes bonding pads 202 on surface 108, which are aligned, for example, with through connector 110. At least some conductive traces 118, such as 118A, may also be formed on surface 108 of substrate 104 instead of surface 116 of inorganic layer 106. In some embodiments, inorganic layer 106 provides a “reset” of surface 108 by using bonding pads 202 and conductive traces 118A to provide additional and new areas for redistribution. In some embodiments, inorganic layer 106 acts as a capping layer, for example, to protect conductive traces 118A from environmental influences. In some embodiments, organic passivation and / or RDL layers (not shown) may be added on top of inorganic layer 106.

[0058] FIG3 is a schematic cross-sectional illustration of an IC package 100 according to some embodiments of the present disclosure. Intermediate 101 includes a first inorganic layer 106 (1) above a surface 108 of a substrate 104. A via 114 (1) between a surface 116 (1) of the inorganic layer 106 (1) and a surface 108 of the substrate 104 provides electrical coupling for a through connector 110 in the substrate 104. A second inorganic layer 106 (2) may be on a surface 116 (1) of the inorganic layer 106 (1). A conductive trace 118 may be on a surface 116 (2) of the inorganic layer 106 (2). A via 114 (2) in the inorganic layer 106 (2) provides electrical coupling from the via 114 (1) and the through connector 110 to the conductive trace 118. In such embodiments, the inorganic layer 106, which includes layers 106(1) and 106(2), can be used as a single RDL layer and an additional capping layer. In some embodiments, an organic passivation and / or RDL layer (not shown) can be added on top of the inorganic layer 106.

[0059] FIG4A is a schematic cross-sectional illustration of an IC package 100 according to some embodiments of the present disclosure. A plurality of dies 102 may be stacked and / or otherwise configured in the IC package 100 above a mediator 101, the mediator comprising a substrate 104 and one or more dies 102 embedded therein. In some embodiments, a bottom filler 402 between the top die 102 and the substrate 104 may provide additional thermomechanical support for the top die 102. In some embodiments, an organic die layer may be formed around one or more dies 102 to form a reconfigured wafer (e.g., an embedded wafer-level ball grid array (e-WLB)) or a reconfigured panel (e.g., an embedded panel-level ball grid array (e-PLB)), which is then unified to form the mediator 101. An inorganic RDL may then be disposed above the surface of the die layer to allow interconnects to terminals to fan out beyond the edges of such embedded dies.

[0060] For ease of explanation, a portion 403 is extended in more detail in FIG. 4B. Interconnects, such as solder-based interconnects 404, may be located on the bottom of the IC package 100. In some embodiments, the die 102 closest to the solder interconnect 404 may be located inside the substrate 104; in other embodiments, a layer of organic material comprising an epoxy-based molding compound may be disposed on the die 102, thereby forming the substrate 104 for the purposes of this disclosure. An inorganic layer 106 may be suitably disposed on the substrate 104. For example, a first inorganic layer may be disposed, followed by the formation of metallization and vias thereon, and then a second inorganic layer may be disposed. An organic polyimide RDL 406 may be additionally disposed on the inorganic layer 106, for example as an additional RDL. The organic polyimide RDL 406 may include another set of conductive traces with a different spacing from the conductive traces in the inorganic layer 106. In various embodiments, the configurations depicted in Figures 4A and 4B can be used in high-performance 3D ICs based on face-to-face packaging architectures, such as Foveros™, which have extremely fine pitch (e.g., 36 micrometers) at the die-to-die interface using microbump-based DTD interconnects. Through the inorganic layer 106 as described herein, the extremely fine pitch at the die-to-die interface can be replicated at the package level, for example, between the substrate 104 and the package substrate or PCB where solder-based interconnects 404 are replaced with DTD interconnects such as microbumps, thereby allowing for stacking and reduced footprint and / or higher performance.

[0061] FIG5A is a simplified exploded oblique projection of an exemplary IC package 100 according to some embodiments of the present disclosure. A plurality of dies 102 (e.g., 102A and 102B, etc.) may be coupled to a medium 101 using DTD interconnects 502. The medium 101 includes a substrate 104 and an inorganic layer 106 disposed on at least one surface 108 of the substrate 104, adjacent to and facing the plurality of dies 102. In some embodiments, the inorganic layer 106 may be disposed on an opposing surface 112. In some embodiments (e.g., as shown), the inorganic layer 106 may be disposed on both surface 108 and surface 112, the inorganic layers being identified as 106(1) and 106(2), respectively. The medium 101 may be coupled to a PCB 504 using DTPS interconnects 506 adjacent to the surface 112 opposite to the dies 102. In some embodiments, the DTPS interconnect 506 may have a coarser pitch than the DTD interconnect 502.

[0062] In some embodiments, the intermediary 101 may be coupled to another intermediary 101 instead of the PCB 504. In such embodiments, the DTPS interconnect 506 may be suitably replaced by a DTD interconnect 502. In other such embodiments, the DTPS interconnect 506 may be used to couple two intermediaries together. In some other embodiments, another plurality of dies 102 may be coupled to a substrate 104 on surface 112 instead of the PCB 504. In such embodiments, the DTPS interconnect 506 may be suitably replaced by a DTD interconnect 502. Any such combination is possible within the broad scope of this disclosure.

[0063] The inorganic layer 106 can serve as an RDL on the surface 108 to accommodate different pitches of the DTD interconnects 502, including: extremely fine pitch, such as a hybrid direct bond 510 with a minimum pitch of less than 10 micrometers; extremely fine pitch, such as a microbump 512 with a minimum pitch between 20 micrometers and 80 micrometers; and fine pitch, such as a flip chip 514 with a minimum pitch of about 100 micrometers. Similarly, the inorganic layer 106 can serve as another RDL on the surface 112 to accommodate different pitches of the DTPS interconnects 506.

[0064] Figure 5B shows a simplified cross-section of the IC package 100 of Figure 5A along segment BB' for further explanation. For ease of explanation and to avoid confusion, only a few components shown in Figure 5A are illustrated in Figure 5B. The selected components are for illustrative / explanatory purposes only and are not intended to limit the scope of the embodiments described herein.

[0065] In some embodiments, the die 102A may be coupled to the substrate 104 using a hybrid direct bonding member 510. Conductive traces 118(1) on the surface 108 of the substrate 104 may electrically couple the DTD interconnect 502 (e.g., the hybrid direct bonding member 510) to an interconnect including a through-connector 110 (e.g., 110B) in the substrate 104. Suitable vias disposed in the inorganic layer 106(1) may also enable electrical coupling between the DTD interconnect 502 (e.g., the hybrid direct bonding member 510), the conductive traces 118(1), and / or the through-connector 110 (e.g., 110B). In some embodiments, the hybrid direct bonding member 510 may have a finer pitch than the through-connector 110. The redistributed conductive trace 118(1) can be fanned out from coarser pitch interconnects (e.g., 110) to finer pitch interconnects (e.g., 510) in a single-layer RDL containing inorganic layer 106(1).

[0066] Conductive traces 118(2) on surface 112 can similarly provide electrical coupling between through-connectors 110 (e.g., 110B) and DTPS interconnects 506. Suitable vias disposed in inorganic layer 106(2) can also enable electrical coupling between DTPS interconnects 506, conductive traces 118(2), and / or through-connectors 110 (e.g., 110B). In some embodiments, hybrid direct connectors 510 may have a finer pitch than through-connectors 110. Redistribution of conductive traces 118(2) can achieve fan-out from coarser pitch interconnects (e.g., 506) to finer pitch interconnects (e.g., 110) in a single-layer RDL containing inorganic layer 106(2).

[0067] In the embodiment shown in the figures, die 102B may be coupled to intermediary 101 via microbumps 512 and flip-chip 514. Intermediary 101 may include embedded die 102C within substrate 104. In some embodiments, die 102C may act as a bridging die, thereby interconnecting die 102B with adjacent dies. In other embodiments, die 102C may act as a substrate die, which, for example, provides various IC functionalities used by one or more of the plurality of dies 102 on substrate 104. Conductive traces 118(1) on the surface 108 of the substrate 104 can electrically couple DTD interconnects 502 (e.g., microbumps 512 and flip chips 514) to interconnects including through-connectors 110 (e.g., 110A, 110B) in the substrate 104, thereby providing electrical coupling between dies 102B and 102C and other components of the IC package 100. Suitable vias disposed in the inorganic layer 106(1) can also enable electrical coupling between microbumps 512 and flip chips 514 and conductive traces 118(1) and / or through-connectors 110 (e.g., 110A, 110B).

[0068] When describing a DTD or DTPS interconnect (e.g., 502, 506) at an interface, a first surface of the interface may include a first set of conductive contacts, and a second surface may include a second set of conductive contacts. One or more of the conductive contacts in the first set may then be electrically and mechanically coupled to some of the conductive contacts in the second set via the DTD or DTPS interconnect. In some embodiments, the DTD interconnect 502 may be used as a data transmission simplex channel, while the DTPS interconnect 506 may be used as a power line and ground wire, etc.

[0069] In various embodiments, the DTD interconnect 502 disclosed herein may take any suitable form, including microbumps, direct bonding interconnects (DBI), hybrid direct bonding interconnects, and flip-chip, etc. In some embodiments, conductive contacts on either side of the DTD interconnect may be bonded together (e.g., under high voltage and / or high temperature) without the use of intervening solder or anisotropic conductive material. In some embodiments, a thin cap of solder may be used in the metal-to-metal interconnect to accommodate flatness, and this solder may become an intermetallic compound during processing. In some metal-to-metal interconnects utilizing hybrid direct bonding, a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, or an organic layer) may be present between the bonded metals (e.g., between copper pads or copper pillars providing associated conductive contacts). In some embodiments, one side of the DTD interconnect may include metal pillars (e.g., copper pillars), and the other side of the DTD interconnect may include metal contacts (e.g., copper contacts) recessed in a dielectric. In some embodiments, metal-to-metal interconnects (e.g., copper-to-copper interconnects) may comprise a noble metal (e.g., gold) or its oxide as a conductive metal (e.g., silver). In some embodiments, metal-to-metal interconnects may comprise metal nanostructures (e.g., nanorods) that may have a reduced melting point. Metal-to-metal interconnects may be able to reliably conduct higher currents than other types of interconnects; for example, some solder interconnects may form brittle intermetallic compounds when current flows, and the maximum current delivered via such interconnects may be constrained to mitigate mechanical failure.

[0070] In some embodiments, the die on any side of a set of DTD interconnects 502 may be an unpackaged die, and / or the DTD interconnects 502 may include small conductive bumps or pillars (e.g., copper bumps or pillars) attached to individual conductive contacts by solder. In some embodiments, some or all of the DTD interconnects 502 may be solder interconnects, including solder with a higher melting point than the solder included in some or all of the DTPS interconnects 506. For example, when the DTD interconnects 502 are formed prior to the formation of the DTPS interconnects 506, the solder-based DTD interconnects may use a higher temperature solder (e.g., having a melting point above 200 degrees Celsius), while the DTPS interconnects may use a lower temperature solder (e.g., having a melting point below 200 degrees Celsius). In some embodiments, the higher temperature solder may include: tin; tin and gold; or tin, silver and copper (e.g., 96.5% tin, 3% silver and 0.5% copper). In some embodiments, the lower temperature solder may include tin and bismuth (e.g., eutectic tin-bismuth) or tin, silver, and bismuth. In some embodiments, the lower temperature solder may include indium, indium, and tin, or gallium.

[0071] The DTPS interconnects 506 disclosed herein may take any suitable form. In some embodiments, a set of DTPS interconnects 506 may include solder (e.g., solder bumps or solder balls that undergo heat reflow to form the DTPS interconnects). DTPS interconnects including solder may include any suitable solder material, such as lead / tin, tin / bismuth, eutectic tin / silver, ternary tin / silver / copper, eutectic tin / copper, tin / nickel / copper, tin / bismuth / copper, tin / indium / copper, tin / zinc / indium / bismuth, or other alloys. In some embodiments, a set of DTPS interconnects may include anisotropic conductive materials, such as anisotropic conductive films or anisotropic conductive pastes. Anisotropic conductive materials may include conductive materials dispersed in non-conductive materials. In some embodiments, anisotropic conductive materials may include microscopic conductive particles embedded in an adhesive or thermosetting adhesive film (e.g., thermosetting biphenyl-type epoxy resin or acrylic-based material). In some embodiments, conductive particles may include polymers and / or one or more metals (e.g., nickel or gold). For example, the conductive particles may include nickel-plated gold or silver-plated copper, which are then coated with a polymer. In another example, the conductive particles may include nickel. When an anisotropic conductive material is not compressed, there may be no conductive path from one side of the material to the other. However, when the anisotropic conductive material is sufficiently compressed (e.g., by means of conductive contacts on either side of the anisotropic conductive material), the conductive material near the compression zone may come into contact with each other to form a conductive path from one side of the film to the other in the compression zone. In some embodiments, a set of DTD interconnects may also include any suitable solder material, such as any of the materials discussed above for DTPS interconnects. In some embodiments, a set of DTD interconnects may include anisotropic conductive materials, such as any of the materials discussed above for DTPS interconnects.

[0072] In some embodiments, the spacing between DTD interconnects 502 may differ from the spacing between DTPS interconnects 506, but in other embodiments, these spacings may be substantially the same. In the package as described herein, some or all of the DTD interconnects 502 may have a finer spacing than the DTPS interconnects 506. In some embodiments, where the DTD interconnects 502 may have too fine a spacing to be directly coupled to the substrate 104, the inorganic layer 106 may be used to achieve this coupling by providing a surface 116 and a suitable material in which fine-pitch vias with a spacing as fine as that on the die 102 may be formed.

[0073] Generally, DTD interconnects can have a smaller pitch than DTPS interconnects because the similarity of the materials of different dies on either side of a set of DTD interconnects is greater than the similarity of the materials between the die and the package support on either side of a set of DTPS interconnects. The difference in the material composition of the die and the package support can cause differential expansion and contraction of the die and the package support due to heat generated during operation (and heat applied during various manufacturing operations). To mitigate damage caused by this differential expansion and contraction (e.g., cracking, solder bridging, etc.), DTPS interconnects are typically larger and more widely spaced than DTD interconnects, which can experience less thermal stress due to the greater material similarity of the dies on either side of the DTD interconnects.

[0074] On the other hand, in various embodiments, the inorganic layer 106 on either side of the DTD interconnect 502 (e.g., the die side and the interposer side) can have the same surface material on both sides, because the die 102 is typically also coated with a passivation layer of silicon nitride or a similar inorganic material. Compared to the case where there is no inorganic layer 106 on the substrate 104, this material symmetry allows for the reduction of differential stress and promotes finer-pitch interconnects between the die 102 and the organic dielectric-based substrate 104. The inorganic layer 106 can further implement any suitable via pitch on the surfaces 108 and / or 112, such that any pitch constraints on the DTD interconnect 502 and the DTPS interconnect 506 are caused by the limitations of the die 102 and the PCB 504, respectively, rather than by the limitations of the substrate 104. In some embodiments, the underfill 516 between the intermediary 101 and the PCB 504 can be used to provide additional thermomechanical integrity and reliability to the IC package 100.

[0075] FIG6A is a simplified top view of a portion of an IC package 100 according to an exemplary embodiment. An inorganic layer 106 may be situated above a substrate 104 comprising an organic insulator. The substrate 104 may include interconnects comprising through-connects 110 with a minimum pitch 602. Interconnects comprising pads 604 may be formed on the inorganic layer 106 with a minimum pitch 606. In various embodiments, the pitch 606 may be smaller than the pitch 602. Additional interconnects comprising conductive traces 118 may electrically couple vias 114 above the through-connects 110 to the pads 604 to achieve fan-out from the fine pitch (e.g., 606) of the pads 604 on the inorganic layer 106 to the coarser pitch (e.g., 602) of the through-connects 110 in the substrate 104.

[0076] Features can be formed to have any desired size, shape, and spacing that can be accommodated by the inorganic layer 106. For example, via 114A may have a diameter similar to (or larger / smaller than) that of the through connector 110 in the substrate 104. Thus, the inorganic layer 106 enables a single-layer RDL. In various embodiments, pads 604 with fine pitch 606 can be used to form fine-pitch interconnects, such as hybrid direct-attachments connected to a die. In other embodiments, the spacing 606 between pads 604 may be larger than the spacing 602 between through connectors 110 (or vias 114), for example, to achieve electrical coupling with a package substrate or PCB (such as a ball grid array (BGA)) having coarser-pitch interconnects. In some embodiments, for example, a coplanar die / die interface on the surface 108 of the substrate 104 may achieve lower stress on the conductive traces 118 wired on the surface 108. In embodiments where an inorganic layer 106 is present above a substrate 104, direct electroplating on a small grain pad (e.g., 602) on a surface 108 can achieve high interconnect density.

[0077] Figure 6B is a simplified cross-sectional view along segment BB' of Figure 6A, showing the electrical coupling between the through connector 110, through-hole 114, conductive trace 118, and pad 604 (which is not obviously discernible in the cross-section because it is essentially seamlessly connected to the conductive trace 118). The through-hole 114 may be disposed above the surface 108 of the substrate 104; the conductive trace 118 may be disposed above the surface 116 of the inorganic layer 106 in a manner similar to that shown in the embodiment of Figure 1. Other embodiments may include a similar fan-out from fine-pitch pads to coarse-pitch through-holes and vice versa in a structure similar to that shown in Figures 2 or 3.

[0078] FIG6C is a simplified cross-sectional view along segment CC' of FIG6A, showing the electrical coupling between the through connector 110, the via 114A, the conductive trace 118, and the pad 604. The via 114A may be disposed above the surface 108 of the substrate 104 and has a similar size and shape to the through connector 110. In some embodiments, the via 114A may include an engagement pad (e.g., 202 in FIG2) on the through connector 110. The conductive trace 118 may be disposed above the surface 116 of the inorganic layer 106 in a manner similar to that shown in FIG1. ​​Other embodiments may include a similar fan-out from fine-pitch pads to coarse-pitch vias and vice versa in a structure similar to that shown in FIG2 or FIG3.

[0079] Figures 7A and 7B are schematic cross-sectional views of surfaces in an example IC package architecture according to some embodiments of the present disclosure. Figure 7A shows surface 108 of substrate 104, which is polished to have a low surface roughness. Figure 7A shows surface 108 of substrate 104 after undergoing a soft etching process, resulting in a certain surface roughness. In advanced packaging applications, it is common practice to pretreat substrates such as substrate 104 before organic film deposition in sequence of degassing and soft etching processes. The main application is degassing to remove surface moisture from the organic film and substrate by typically heating the substrate to 120°C to 150°C. Subsequent soft etching is performed in a dedicated chamber such as an inductively coupled plasma (ICP) module. Bombarding the substrate with low-energy, high-density argon plasma effectively removes surface contaminants and native oxides, thereby enhancing the adhesion of subsequent films. Soft etching using the ICP etching process offers high etching rates, high selectivity, and low-damage processing, along with excellent profile control over low-voltage plasma. In the ICP plasma process, gases such as argon and nitrogen are introduced above an inductor coil, surrounding a ceramic tube. The substrate containing the wafer is placed on a RF-powered chuck. RF pulses are applied to both the coil and the chuck to generate plasma. The wafer possesses a potential that promotes the orientation of etchants extracted from the plasma toward the surface to be etched. Introducing different gases can produce chemical reactions, resulting in anisotropic etch profiles.

[0080] While typical packaging applications employ soft etching without considering any specific target surface roughness of surface 108, embodiments of this disclosure use a controlled soft etching process that provides a regulated surface roughness measure 702 over surface 108. In a general sense, surface roughness is a series of microscopic "peaks and valleys" across a surface such as surface 108. Surface roughness is typically calculated using the root mean square (RMS) of the surface peaks and valleys across that surface. In some embodiments, surface roughness measure 702 may include an RMS (also referred to as Rq) value. In other embodiments, surface roughness measure 702 may include an average roughness (also referred to as Ra) value. In various embodiments, the surface roughness measure 702 of surface 108 after the soft etching process may be 0.4 nm larger than the surface roughness measure before the soft etching process.

[0081] Furthermore, the surface roughness measure 702 may vary depending on the material type of the substrate 104. In an example embodiment, the surface roughness measure 702 of the granular mold material without soft etching is 3.1 nm, while the surface roughness measure 702 of the same material after soft etching is 3.4 nm. In another example embodiment, the surface roughness measure 702 of the liquid mold material after curing without soft etching is 3.3 nm, while the surface roughness measure 702 of the same material after soft etching is 4.0 nm. In various embodiments, subjecting the substrate 104 to a soft etching process to increase the surface roughness by a small amount (e.g., about 10%) achieves better adhesion between the inorganic layer 106 and the substrate 104 (compared to no etching) and has the resulting improved reliability, for example, without delamination or cracking under the following conditions: after 168 hours of 10 reflow cycles at 260 degrees Celsius and 60% humidity; after 216 hours of 3 reflow cycles at 260 degrees Celsius and 30 degrees Celsius and 60% humidity; and after 1000 hours at 150 degrees Celsius.

[0082] Figure 8 is a graph 800 showing the film stress as a function of the inorganic layer thickness according to some embodiments of the present disclosure. The residual film stress can be calculated using the Stoney formula: where Es / (1-) is the biaxial Young's modulus of the substrate (180.5 GPa for (100) oriented silicon wafers), and ts and tf represent the thicknesses of the substrate 104 and the inorganic layer 106, respectively. R0 and R1 are the radii of curvature of the inorganic layer 106 before and after deposition. The inorganic layer 106 comprises silicon nitride deposited in a single step in plot 802. The inorganic layer 106 comprises silicon nitride deposited in a separation process in plot 804. In some embodiments, the separation process comprises a 100 nm alternative deposition step (equivalent to a process time of 47.0 seconds), followed by a 60-second cooling step. The inorganic layer 106 comprises silicon carbonitride deposited in a single step as shown in plot 806. Both the silicon nitride and silicon carbonitride films exhibit compressive stress levels, which become more moderate with increasing thickness of the inorganic layer 106. The residual compressive stress level refers to the dense and compressed film produced by the deposition process, which tends to expand to alleviate its internal energy. Stabilization is observed when the film thickness exceeds 1.0 µm. In the case of silicon nitride, a plateau is reached at -65 ± 5 MPa, while the stress level of the silicon carbonitride film tends to plateau around -280 ± 20 MPa.

[0083] Figure 9 is a graph 900 illustrating the peak wafer temperature during the deposition of inorganic layer 106 as a function of inorganic layer thickness, according to some embodiments of the present disclosure. Prior to the deposition of inorganic layer 106, substrate 104 may be pretreated using degassing and soft etching processes, which may result in a peak temperature of approximately 150 degrees Celsius. The peak temperature after deposition shows an increase to approximately 180 degrees Celsius for a 100 nm silicon nitride layer, an increase to approximately 270 degrees Celsius for a 500 nm layer, and then stabilizes to approximately 228 degrees Celsius for all other thicker films, as shown in plot 902. This behavior indicates the efficiency of the deposition and cooling schemes used to stabilize the peak temperature. Silicon nitride deposition at 300 nm and 500 nm is carried out in a single step and cooling does not require temperatures as high as approximately 40 to 50 degrees Celsius, as shown in plot 904, while the 1.0-micron process exceeds the upper limit of 260 degrees Celsius, as shown by the dashed extension line. Silicon carbonitride processes (e.g., inorganic layer 106 containing silicon carbonitride) indicate a stable temperature of approximately 100 degrees Celsius independent of film thickness, as shown in plot 906.

[0084] In various embodiments, any of the features discussed herein with reference to any of Figures 1 through 7B may be combined with any other feature to form a package having one or more ICs as described herein, for example, to form a modified IC package 100. Some such combinations have been described above, but other combinations and modifications are possible in various embodiments. Example Methods

[0085] Figure 10 is a flowchart of an example method 1000 for manufacturing an IC package 100 according to various embodiments of the present disclosure. Although Figure 10 illustrates various operations performed in a specific order, this is merely illustrative, and the operations discussed herein may be appropriately rearranged and / or repeated. Furthermore, additional processes not described may be performed without departing from the scope of the present disclosure. Moreover, various operations discussed herein with respect to Figure 10 may be modified according to the present disclosure to manufacture other microelectronic assemblies 200 disclosed herein.

[0086] At 1002, the substrate 104 can be planarized, for example, using a chemical mechanical polishing (CMP) process. At 1004, the surface 108 of the substrate 104 can be subjected to a soft etching process, such as ICP etching, to slightly increase the surface roughness (e.g., by 10%). In some embodiments, a degassing process can be performed before (or in combination with) the soft etching process in other embodiments. Degassing is primarily used to remove surface moisture from the organic substrate 104 by typically heating the wafer to 120 to 150°C. The subsequent soft etching can be performed in a dedicated chamber, such as an ICP module, where, in addition to increasing surface roughness, the bombardment of the substrate 104 by a low-energy, high-density argon plasma can effectively remove surface contaminants and native oxides, thereby enhancing the adhesion of the subsequent inorganic layer 106.

[0087] At 1006, an inorganic layer 106 may be disposed on surface 108. In various embodiments, a low-temperature PVD process using magnetron sputtering can be used to produce layer thicknesses of approximately 1.5 micrometers to 2 micrometers. Compared to chemical vapor deposition (CVD) and PECVD counterparts, the main benefits of magnetron sputtering include high deposition rates, excellent thickness uniformity, stringent defect control, and low deposition temperatures. In various embodiments, amorphous thin films of silicon nitride (a-SixNy) and silicon carbonitride (a-SiCxNy) can be deposited on an exposed silicon substrate by direct current (DC) magnetron sputtering in a mixed atmosphere of nitrogen and argon.

[0088] In embodiments where silicon nitride is the material of inorganic layer 106, the main hardware features and key process conditions of the process module are as follows. A polycrystalline silicon target with a diameter of 400 mm can be used to sputter silicon nitride in a PVD tool. In some embodiments, the PVD tool may include high-volume manufacturing tools for 300 mm wafers and specifically designed for mature back-side metallization (BSM) processes. In some embodiments, the PVD tool for silicon nitride deposition may use a "recessed chuck" to prevent direct contact between the undeposited wafer side and the chuck surface. In a recessed setup, only the wafer circumference is located on a metal support ring positioned around the top of the chuck. The additional requirements for full deposition in BSM applications prohibit any mechanical fixation of the substrate edges. Therefore, with the recessed chuck, the substrate can dissipate the heat generated by the growth of the inorganic layer solely through radiation. To facilitate this heat dissipation (e.g., to limit the temperature rise during deposition), a "separation process" comprising alternating deposition and cooling steps can be performed in some embodiments.

[0089] The known best method (BKM) deposition conditions for silicon nitride, such as power density, N2:argon ratio, and process pressure, are as follows: a pulsed DC power supply at a frequency of 350 kHz and a pulse stop time of 1100 nanoseconds; a power density of 6.37 W / cm2; a nitrogen (N2) to argon (Ar) gas ratio of 1; and a sputtering pressure (pump throttling) of 1.3 e-2 mbar. Among these process parameters, two important tuning knobs for reducing stress on the silicon nitride film include using DC power in pulse mode and the increased process pressure obtained by operating the pump in throttling mode.

[0090] In embodiments using silicon carbonitride as the material for the inorganic layer 106, a 200 mm wafer-sized PVD tool can be used, for example, equipped with a 300 mm diameter powder-pressed silicon carbide target, wherein the silicon / carbon ratio is 1:1. The process conditions for establishing the silicon carbonitride BKM are as follows: continuous DC power supply; 4.95 W / cm² power density; N₂:Ar gas ratio of 1.2; and sputtering pressure of 9.7e-4 mbar. In various embodiments, a multi-chamber PVD tool that can be configured to have up to six process modules can be used, which are clustered around a central vacuum transport section. This multi-chamber architecture allows a series of processes to be performed in different modules without disrupting the vacuum. Furthermore, for deposited inorganic layers thicker than 1.0 µm, using more than one PVD chamber helps to multiply the achievable operating rate by a factor proportional to the number of chambers used. In some embodiments, the PVD tool for depositing silicon carbonitride may be equipped with a clamping configuration to mechanically hold the wafer edge by the mass of the clamping mask. Thus, the entire undeposited wafer surface can contact the water-cooled pedestal. Argon gas applied through a dedicated inlet at the center of the chuck can be distributed via a grooved network that provides efficient wafer cooling through conduction.

[0091] At 1008, vias can be formed in the inorganic layer 106 using any suitable process such as laser cutting or etching. In some embodiments, the vias may have a size of 4 µm × 6 µm. At 1010, a seed metal (e.g., titanium or copper) can be deposited on the surface 116 of the inorganic layer 106. In some embodiments, the surface 116 may be etched to improve the adhesion of the seed metal. At 1012, the surface 116 of the inorganic layer may be patterned and electroplated with metal to form conductive traces 118. In some embodiments, more than one metal layer may be electroplated. For example, copper may be electroplated across the entire seed metal, followed by nickel (Ni) electroplated at selected locations (e.g., bonding pads), followed by an alloy of tin (Sn) and silver (Ag) electroplated on the nickel. In some embodiments, solder is used as an interconnect, and the solder may also be electroplated on the bonding pads. At 1014, an interconnect (e.g., 118B) may be formed, for example, to couple the substrate 104 to other components of the IC package 100. At 1016, the seed metal may be etched away. The resulting structure may be similar to the structure shown with respect to FIG1.

[0092] Figure 11 is a flowchart of an example method 1100 for manufacturing an IC package 100 according to various embodiments of the present disclosure. At 1102, a CMP process may be used, for example, to planarize the substrate 104. At 1104, the surface 108 of the substrate 104 may be subjected to a soft etching process, such as ICP etching, to slightly increase the surface roughness (e.g., by 10%). In some embodiments, a degassing process may be performed before (or in combination with) the soft etching process. At 1106, a seed metal (e.g., titanium or copper) may be disposed on the surface 108 of the substrate 104. At 1108, the surface 108 may be patterned and electroplated with a metal such as copper to create a portion of the bonding pad 202 and conductive trace 118, such as 118A. In some embodiments, the minimum spacing for the electroplated metal may be 25 µm. At 1110, the seed metal may be etched away.

[0093] At 1112, an inorganic layer 106 may be disposed on surface 108 and on electroplated metal (e.g., a portion of bonding pad 202 and conductive trace 118A). The process for disposing of the inorganic layer 106 may be the same as that disclosed with respect to FIG. 10. In some embodiments, the resulting thickness of the inorganic layer 106 may be 3 μm to 5 μm. At 1114, vias may be formed in the inorganic layer 106, for example, by laser cutting or etching. At 1116, a seed metal (e.g., titanium or copper) may be deposited on surface 116 of the inorganic layer 106. In some embodiments, surface 116 may be etched to improve the adhesion of the seed metal. At 1118, interconnects (e.g., 118B) may be formed, for example, by further patterning and metal plating on surface 116. At 1120, the seed metal deposited on surface 116 may be etched away. The resulting structure can be similar to the structure shown in Figure 2.

[0094] FIG12 is a flowchart of an example method 1200 for manufacturing an IC package 100 according to various embodiments of the present disclosure. At 1202, a CMP process may be used, for example, to planarize the substrate 104. At 1204, the surface 108 of the substrate 104 may be subjected to a soft etching process, for example, ICP etching, to slightly increase the surface roughness (e.g., by 10%). In some embodiments, a degassing process may be performed before the soft etching process (or in combination with it in other embodiments). At 1206, an inorganic layer 106 (1) may be disposed on the surface 108. The process for disposing of the inorganic layer 106 (1) may be the same as that disclosed with respect to FIG10. In some embodiments, the resulting thickness of the inorganic layer 106 (1) may be 1.5 µm to 2 µm. At 1208, vias may be formed in the inorganic layer 106 (1), for example, by laser cutting or etching.

[0095] At 1210, a seed metal (e.g., titanium or copper) may be disposed on the surface 116(1) of the inorganic layer 106(1). At 1212, the surface 116(1) may be patterned and electroplated with a metal such as copper to create a portion of the bonding pad 202 and the conductive trace 118, such as 118A. In some embodiments, the minimum spacing for the electroplated metal may be 25 µm. At 1214, the seed metal deposited on the surface 116(1) may be etched away.

[0096] At 1216, another inorganic layer 106 (2) may be disposed on the surface 116 (1) of the previously disposed inorganic layer 106 (1) and on electroplated metal (e.g., a portion of bonding pad 202 and conductive trace 118A). The process for disposing the inorganic layer 106 (2) may be the same as the process for disposing the inorganic layer 106 (1). In some embodiments, the resulting thickness of the inorganic layer 106 (2) may be 3 µm to 5 µm. At 1218, vias may be formed in the inorganic layer 106 (2), for example by laser cutting or etching. At 1220, a seed metal (e.g., titanium or copper) may be deposited on the surface 116 (2) of the inorganic layer 106 (2). In some embodiments, the surface 116 (2) may be etched to improve the adhesion of the seed metal. At 1222, interconnects (e.g., 118B) can be formed, for example, by further patterning and metal plating on surface 116(2). At 1224, the seed metal deposited on surface 116(2) can be etched away. The resulting structure can be similar to the structure shown with respect to FIG3.

[0097] Although the operations of methods 1000, 1100, and 1200 are illustrated one at a time and in a specific order in Figures 10 to 12, the operations can be performed in any suitable order and repeated as needed. For example, one or more operations can be performed in parallel to substantially manufacture multiple IC packages simultaneously. In another instance, the operations can be performed in a different order to reflect the structure of a particular IC package, which may include one or more IC packages 100 as described herein. Several other variations are also possible to achieve the desired structure of the IC package 100.

[0098] Furthermore, the operations illustrated in Figures 10 to 12 may be combined or may include more details than those described herein. Additionally, methods 1000, 1100, and 1200 shown in Figures 10 to 12 may further include other manufacturing operations related to the manufacture of other components of the assembly described herein or any means that may include the assembly as described herein. For example, methods 1000, 1100, and 1200 may include various cleaning operations, surface planarization operations (e.g., using CMP), operations for surface roughening, operations including barriers and / or adhesive layers as needed, and / or operations for incorporating or integrating packages as described herein into IC components, computing devices, or any desired structure or device. Example devices and components

[0099] The packages disclosed herein, such as any of the embodiments shown in Figures 1 through 7 or any other embodiments described herein, may be included in any suitable electronic component. Figures 13 through 15 illustrate various examples of packages, assemblies, and devices that may be used with or include any of the IC packages disclosed herein.

[0100] FIG13 is a cross-sectional side view of an illustrative IC package 2200, which may include an IC package according to any of the embodiments disclosed herein. In some embodiments, the IC package 2200 may be a system-in-package (SiP).

[0101] As shown in FIG. 13, the package support 2252 may be formed of an insulator (e.g., ceramic, stacked thin film, epoxy resin film having filler particles therein, etc.) and may have conductive paths extending through the insulator between the first surface 2272 and the second surface 2274, or between different locations on the first surface 2272 and / or between different locations on the second surface 2274. These conductive paths may take the form of any of the interconnect structures, which include, for example, lines and / or vias as discussed above with reference to FIG. 1.

[0102] The package support 2252 may include conductive contacts 2263, which are coupled to conductive paths 2262 via the package support 2252, thereby allowing the circuitry within the die 2256 and / or the intermediate 2257 to be electrically coupled to various conductive contacts in the conductive contacts 2264 (or electrically coupled to other devices not shown included in the package support 2252).

[0103] The IC package 2200 may include an interposer 2257, which is coupled to the package support 2252 via conductive contacts 2261 of the interposer 2257, a first-level interconnect 2265, and conductive contacts 2263 of the package support 2252. The first-level interconnect 2265 illustrated in FIG13 is a solder bump, but any suitable first-level interconnect 2265, such as a solder bump, a solder post, or a bonding wire, may be used.

[0104] The IC package 2200 may include one or more dies 2256 coupled to the intermediary 2257 via conductive contacts 2254 of die 2256, first-level interconnects 2258, and conductive contacts 2260 of intermediary 2257. The conductive contacts 2260 may be coupled to conductive paths (not shown) via the intermediary 2257, thereby allowing the circuitry within the die 2256 to be electrically coupled to various conductive contacts in the conductive contacts 2261 (or electrically coupled to other devices (not shown) included in the intermediary 2257). The first-level interconnect 2258 illustrated in FIG13 is a solder bump, but any suitable first-level interconnect 2258, such as a solder bump, solder post, or bonding wire, may be used. As used herein, "conductive contact" may refer to a portion of a conductive material (e.g., a metal) that serves as an interface between different components; a conductive contact may be recessed into the surface of a component, flush with the surface of a component, or extend outward from the surface of a component, and may take any suitable form (e.g., a conductive pad or a socket).

[0105] In some embodiments, underfill material 2266 may be disposed around first-level interconnect 2265 between package support 2252 and intermediate 2257, and mold 2268 may be disposed around die 2256 and intermediate 2257 and in contact with package support 2252. In some embodiments, underfill material 2266 may be the same as mold 2268. Example materials that can be used for underfill material 2266 and mold 2268 are suitable epoxy resins. Second-level interconnect 2270 may be coupled to conductive contact 2264. The second-level interconnect 2270 illustrated in FIG13 is a solder ball (e.g., for BGA configuration), but any suitable second-level interconnect 2270 (e.g., a pin in a pin grid array configuration or a pad in a pad grid array configuration) may be used. The second-level interconnect 2270 can be used to couple the IC package 2200 to another component, such as a circuit board (e.g., a motherboard), an intermediary, or another IC package, as known in the art and discussed below with reference to FIG14.

[0106] In various embodiments, any of the dies 2256 may include die 102 as described herein. In embodiments in which the IC package 2200 includes a plurality of dies 2256, the IC package 2200 may be referred to as a multi-chip package (MCP). Dies 2256 may include circuitry for performing any desired functionality. For example, in addition to one or more dies 2256 being die 102 as described herein, one or more dies 2256 may also be logic dies (e.g., silicon-based dies), one or more dies 2256 may be memory dies (e.g., high-bandwidth memory), etc. In some embodiments, at least some of the dies 2256 may include an inorganic layer 106 as described herein. In some embodiments, at least some of the dies 2256 may not include an inorganic layer 106 as described herein.

[0107] Although the IC package 2200 illustrated in FIG. 13 is a flip-chip package, other package architectures may be used. For example, the IC package 2200 may be a BGA package, such as an embedded wafer-level ball grid array (eWLB) package. In another example, the IC package 2200 may be a wafer-level wafer-scale package (WLCSP) or a panel fan-out (FO) package. Although two dies 2256 are illustrated in the IC package 2200, the IC package 2200 may include any desired number of dies 2256. The IC package 2200 may include additional passive components, such as surface-mount resistors, capacitors, and inductors disposed over the first side 2272 or the second side 2274 of the package support 2252 or disposed on either side of the interposer 2257. More generally, the IC package 2200 may include any other active or passive components known in the art.

[0108] In some embodiments, the intermediary 2257 may not be included in the IC package 2200; alternatively, the die 2256 may be directly coupled to the conductive contact 2263 at the first surface 2272 via the first-level interconnect 2265.

[0109] FIG14 is a cross-sectional side view of an IC device assembly 2300 that may include components having one or more microelectronic assemblies 200 according to any of the embodiments disclosed herein. The IC device assembly 2300 includes several components disposed above a circuit board 2302 (which may be, for example, a motherboard). The IC device assembly 2300 includes components disposed above a first surface 2340 and an opposite second surface 2342 of the circuit board 2302; typically, components may be disposed above one or both surfaces 2340 and 2342. In particular, any suitable component of the IC device assembly 2300 may include any of one or more microelectronic assemblies 200 according to any of the embodiments disclosed herein; for example, any of the IC packages discussed below with reference to the IC device assembly 2300 may take the form of any of the embodiments of the IC package 2200 discussed above with reference to FIG13.

[0110] In some embodiments, the circuit board 2302 may be a PCB comprising a plurality of metal layers separated from each other by insulating layers and interconnected by conductive vias. Any one or more of these metal layers may be patterned to route electrical signals between components coupled to the circuit board 2302 (optionally combined with other metal layers). In other embodiments, the circuit board 2302 may be a non-PCB package support.

[0111] Figure 14 illustrates that, in some embodiments, the IC device assembly 2300 may include an intermediary-on-package structure 2336 coupled to a first surface 2340 of a circuit board 2302 via a coupling assembly 2316. The coupling assembly 2316 may electrically and mechanically couple the intermediary-on-package structure 2336 to the circuit board 2302, and may include solder balls (as shown), protrusions and recesses of sockets, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structures.

[0112] The on-middle package structure 2336 may include an IC package 2320 coupled to the middleman 2304 via a coupling component 2318. Depending on the desired functionality, the coupling component 2318 may take any suitable form, such as that discussed above with reference to coupling component 2316. In some embodiments, the IC package 2320 may be or include an IC package 2200, for example, as described above with reference to FIG13. In some embodiments, the IC package 2320 may include at least one inorganic layer 106 over an organic substrate 104, as described herein. The inorganic layer 106 is not specifically shown in FIG14 to avoid obscuring the diagram.

[0113] Although a single IC package 2320 is shown in Figure 14, multiple IC packages can be coupled to the interposer 2304; in fact, additional interposers can be coupled to the interposer 2304. The interposer 2304 provides an interposer package support for bridging the circuit board 2302 and the IC package 2320. Typically, the interposer 2304 can redistribute connections to wider spacing or redirect connections to different connections. For example, the interposer 2304 can couple the IC package 2320 to the BGA of the coupling assembly 2316 for coupling to the circuit board 2302.

[0114] In the embodiment illustrated in FIG. 14, the IC package 2320 and the circuit board 2302 are attached to opposite sides of the intermediary 2304. In other embodiments, the IC package 2320 and the circuit board 2302 may be attached to the same side of the intermediary 2304. In some embodiments, three or more components may be interconnected by means of the intermediary 2304.

[0115] Intermediate 2304 may be formed of epoxy resin, glass fiber reinforced epoxy resin, ceramic material, or polymeric material such as polyimide. In some embodiments, intermediate 2304 may be formed of alternative rigid or flexible materials, including the same materials described above for semiconductor substrates, such as silicon, germanium, and other Group III-V and Group IV materials. Intermediate 2304 may include metal interconnects 2308 and vias 2310, including but not limited to TSV 2306. Intermediate 2304 may further include embedded devices 2314, including both passive and active devices. Such devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. More complex devices (such as RF devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices) may also be formed on intermediate 2304. The intermediate on-package structure 2336 may take the form of any of the intermediate on-package structures known in this art.

[0116] In some embodiments, the IC device assembly 2300 may include an IC package 2324 coupled to a first side 2340 of the circuit board 2302 via a coupling component 2322. The coupling component 2322 may take the form of any of the embodiments discussed above with reference to coupling component 2316, and the IC package 2324 may take the form of any of the embodiments discussed above with reference to IC package 2320.

[0117] In some embodiments, the IC device assembly 2300 may include a stacked package structure 2334 coupled to a second side 2342 of the circuit board 2302 via a coupling component 2328. The stacked package structure 2334 may include an IC package 2326 and an IC package 2332 coupled together via a coupling component 2330, such that the IC package 2326 is disposed between the circuit board 2302 and the IC package 2332. The coupling components 2328 and 2330 may take the form of any of the embodiments of the coupling component 2316 discussed above, and the IC package 2326 and / or 2332 may take the form of any of the embodiments of the IC package 2320 discussed above. The stacked package structure 2334 may be assembled according to any of the stacked package structures known in the art.

[0118] FIG15 is a block diagram of an example computing device 2400 that may include one or more components having one or more IC packages, according to any of the embodiments disclosed herein. For example, according to any of the embodiments disclosed herein, any suitable component of the computing device 2400 may include an inorganic layer 106 over an organic substrate 104. In another example, any or more components of the computing device 2400 may include any embodiment of an IC package 2200 (e.g., as shown in FIG13). In yet another example, any or more components of the computing device 2400 may include an IC device assembly 2300 (e.g., as shown in FIG14).

[0119] Several components are illustrated in FIG. 15 as included in the computing device 2400, but any one or more of these components may be omitted or repeated as appropriate for the application. In some embodiments, some or all of the components included in the computing device 2400 may be attached to one or more motherboards. In some embodiments, some or all of these components are manufactured on a single system-on-a-chip (SoC) die.

[0120] Additionally, in various embodiments, the computing device 2400 may not include one or more of the components illustrated in FIG. 15, but the computing device 2400 may include interface circuitry systems for coupling to one or more components. For example, the computing device 2400 may not include the display device 2406, but may include display device interface circuitry systems (e.g., connector and driver circuitry systems) to which the display device 2406 may be coupled. In another set of examples, the computing device 2400 may not include the audio input device 2418 or the audio output device 2408, but may include audio input or output device interface circuitry systems (e.g., connector and support circuitry systems) to which the audio input device 2418 or the audio output device 2408 may be coupled.

[0121] The computing device 2400 may include a processing device 2402 (e.g., one or more processing devices). As used herein, the terms "processing device" or "processor" may refer to any device or part of a device that processes electronic data from a register and / or memory to convert that electronic data into other electronic data that can be stored in the register and / or memory. The processing device 2402 may include one or more digital signal processors (DSPs), ASICs, CPUs, GPUs, cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, or any other suitable processing devices. The computing device 2400 may include a memory 2404, which itself may include one or more memory devices, such as electrically dependent memory (e.g., dynamic random access memory (DRAM)), non-electrically dependent memory (e.g., read-only memory (ROM)), flash memory, solid-state memory, and / or hard disk drives. In some embodiments, the memory 2404 may include memory sharing a die with the processing device 2402. This memory can be used as cache memory and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0122] In some embodiments, the computing device 2400 may include a communication chip 2412 (e.g., one or more communication chips). For example, the communication chip 2412 may be configured to manage wireless communications for transmitting data to and from the computing device 2400. The term "wireless" and its derivatives may be used to describe circuits, devices, systems, methods, technologies, communication channels, etc., which may transmit data by using modulated electromagnetic radiation that passes through a non-solid medium. This term does not imply that the associated device does not contain any wires, but in some embodiments such devices may contain wires.

[0123] The communication chip 2412 can implement any of a number of wireless standards or protocols, including but not limited to Institute of Electrical and Electronics Engineers (IEEE) standards, including Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) initiatives, and any amendments, updates, and / or revisions (e.g., Advanced LTE initiatives, Ultra Mobile Broadband (UMB) initiatives (also known as "3GPP2"), etc.). IEEE 802.16 compliant broadband wireless access (BWA) networks are generally referred to as WiMAX networks (an acronym for Global Microwave Access), which is a mark of a product that has passed the conformance and interoperability testing of the IEEE 802.16 standard. The communication chip 2412 may operate according to Global System for Mobile Communications (GSM), Universal Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. The communication chip 2412 may operate according to Enhanced GSM Evolved Data (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). The communication chip 2412 may operate according to Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Wireless Telecommunications (DECT), Evolved Data Optimization (EV-DO), and derivatives thereof, as well as any other wireless protocols designated as 3G, 4G, 5G, and beyond. In other embodiments, the communication chip 2412 may operate according to other wireless protocols. The computing device 2400 may include an antenna 2422 to facilitate wireless communication and / or receive other wireless communications (such as AM or FM radio transmissions).

[0124] In some embodiments, the communication chip 2412 may manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., Ethernet). As mentioned above, the communication chip 2412 may include multiple communication chips. For example, a first communication chip 2412 may be dedicated to shorter-range wireless communications, such as Wi-Fi or Bluetooth, and a second communication chip 2412 may be dedicated to longer-range wireless communications, such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, or other longer-range wireless communications. In some embodiments, the first communication chip 2412 may be dedicated to wireless communications, and the second communication chip 2412 may be dedicated to wired communications.

[0125] The computing device 2400 may include a battery / power circuit system 2414. The battery / power circuit system 2414 may include one or more energy storage devices (e.g., batteries or capacitors) and / or a circuit system for coupling components of the computing device 2400 to a power source (e.g., AC line power) separate from the power source of the computing device 2400.

[0126] The computing device 2400 may include a display device 2406 (or a corresponding interface circuit system, as discussed above). The display device 2406 may include any visual indicator, such as a head-up display, computer monitor, projector, touch screen display, liquid crystal display (LCD), light-emitting diode display, or flat panel display.

[0127] The computing device 2400 may include an audio output device 2408 (or a corresponding interface circuit system, as discussed above). The audio output device 2408 may include any device that generates audible indicators, such as a speaker, headphones, or earphones.

[0128] The computing device 2400 may include an audio input device 2418 (or a corresponding interface circuit system, as discussed above). The audio input device 2418 may include any device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output).

[0129] The computing device 2400 may include a GPS device 2416 (or a corresponding interface circuit system, as discussed above). The GPS device 2416 may communicate with a satellite-based system and may receive the location of the computing device 2400, as known in the art.

[0130] The computing device 2400 may include another output device 2410 (or a corresponding interface circuit system, as discussed above). Examples of the other output device 2410 may include an audio codec, a video codec, a printer, a wired or wireless transmitter for providing information to other devices, or an additional storage device.

[0131] The computing device 2400 may include another input device 2420 (or a corresponding interface circuit system, as discussed above). Examples of the other input device 2420 may include an accelerometer, a gyroscope, a compass, an image capturing device, a keyboard, a cursor control device such as a mouse, a stylus, a touchpad, a barcode reader, a quick-response (QR) code reader, any sensor, or a radio frequency identification (RFID) reader.

[0132] The computing device 2400 may have any desired form factor, such as a handheld or mobile computing device (e.g., a cell phone, smartphone, mobile internet device, music player, tablet computer, laptop, mini-notebook, ultrabook, personal digital assistant (PDA), super mobile PC, etc.), a desktop computing device, a server or other networked computing component, a printer, a scanner, a monitor, a set-top box, an entertainment control unit, a vehicle control unit, a digital camera, a digital video recorder, or a wearable computing device. In some embodiments, the computing device 2400 may be any other electronic device for processing data. (Selected Example)

[0133] The following paragraphs provide various examples of the embodiments disclosed herein.

[0134] Example 1 provides an intermediary (e.g., 101) comprising: an organic substrate (e.g., 104) including a first set of interconnects (e.g., 110) having a first spacing (e.g., 602); an inorganic layer (e.g., 106) including a second set of interconnects (e.g., 604) having a second spacing (e.g., 606); and a conductive trace (e.g., 118) electrically coupling the first set of interconnects to the second set of interconnects. The inorganic layer is situated above the organic substrate (e.g., Figures 1 to 6), and the second spacing differs from the first spacing (e.g., Figure 6A).

[0135] Example 2 provides the intermediate of Example 1, wherein the surface of the organic substrate adjacent to the inorganic layer undergoes a soft etching process (e.g., Figures 10 to 12) before the inorganic layer is placed.

[0136] Example 3 provides an intermediary of any of Examples 1 to 2, wherein the second set of interconnects and conductive traces are located above the inorganic layer (e.g., Figure 6B).

[0137] Example 4 provides an intermediary of any of Examples 1 to 2, wherein the second set of interconnects and conductive traces are within an inorganic layer (e.g., Figure 2).

[0138] Example 5 provides an intermediary of any of Examples 1 to 2, wherein the second set of interconnects (e.g., 114) is within the inorganic layer and the conductive traces are above the inorganic layer (e.g., Figure 1).

[0139] Example 6 provides a middleware of any of Examples 1 to 5, wherein the second spacing is smaller than the first spacing.

[0140] Example 7 provides a middleware of any one of Examples 1 to 5, wherein the second spacing is greater than the first spacing.

[0141] Example 8 provides an intermediary of any of Examples 1 to 7, wherein the first set of interconnects includes through connectors (e.g., 110B) that extend between a surface of the substrate near the inorganic layer (e.g., 108) and an opposite surface of the substrate (e.g., 112).

[0142] Example 9 provides an intermediary of any of Examples 1 to 8, which further includes a grain embedded in the substrate (e.g., 102 in Figure 1).

[0143] Example 10 provides the intermediate of Example 9, wherein the die contains an active circuit system.

[0144] Example 11 provides the intermediate of Example 9, wherein the die contains only a passive circuit system without any active components.

[0145] Example 12 provides an intermediary of any of Examples 9 to 11, wherein the first set of interconnects includes a through connection (e.g., 110A) extending between the surface and the die.

[0146] Example 13 provides an intermediary of any of Examples 1 to 8, wherein an inorganic layer is attached above a first surface (e.g., 108) of a substrate, and a second surface (e.g., 112) of the substrate opposite to the first surface includes a third set of interconnects (e.g., 506) having a third spacing, and the third spacing is different from the first spacing (e.g., Figures 5A to 5B).

[0147] Example 14 provides the medium of Example 13, wherein the inorganic layer includes a first inorganic layer (e.g., 106(1)) and the medium is further included above a second inorganic layer (e.g., 106(2)) on a second surface of the substrate (e.g., FIG5B).

[0148] Example 15 provides the intermediate of Example 14, which further includes conductive traces coupled to a second inorganic layer, the conductive traces electrically coupling the first set of interconnects to the third set of interconnects.

[0149] Example 16 provides a middleware of any of Examples 13 to 15, wherein the third spacing is greater than the first spacing.

[0150] Example 17 provides an intermediary for any of Examples 1 to 16, wherein the inorganic layer provides a protective barrier over the organic substrate.

[0151] Example 18 provides a medium of any of Examples 1 to 17, wherein the inorganic layer is a first inorganic layer (e.g., 106(1)) and the medium is contained in a second inorganic layer above the first inorganic layer (e.g., 106(2)) (e.g., Figure 3).

[0152] Example 19 provides the intermediary of Example 18, wherein the conductive trace (e.g., 118A) is located within the second inorganic layer.

[0153] Example 20 provides an intermediary of any of Examples 18 to 19, wherein the second inorganic layer includes a third set of interconnects (e.g., 114(2)) coupled to the second set of interconnects (e.g., 114(1)) and a conductive trace (e.g., 118B) is located above the second inorganic layer.

[0154] Example 21 provides an intermediary of any of Examples 1 to 20, which further includes an organic layer (e.g., 406 in Figure 4) above the inorganic layer, such that the inorganic layer is between the organic layer and the organic matrix.

[0155] Example 22 provides the intermediate of Example 21, wherein the organic layer includes a third set of interconnects with a third pitch.

[0156] Example 23 provides the middleware of Example 21, wherein the organic layer comprises polyimide.

[0157] Example 24 provides an intermediary of any of Examples 1 to 23, wherein the inorganic layer comprises silicon nitride or silicon carbonitride.

[0158] Example 25 provides an IC package comprising: a die (e.g., 102A or 102B in FIG. 5B) having a first set of interconnects (e.g., 510, 512 or 514) having a first pitch; and an intermediary (e.g., 101) having an organic substrate (e.g., 104) and an inorganic layer (e.g., 106(1)) above the organic substrate, the organic substrate having a second set of interconnects (e.g., 110A, 110B) having a second pitch. The inorganic layer includes conductive traces (e.g., 118(1)) electrically coupling the second set of interconnects to the first set of interconnects, and the die is attached to the intermediary via the first set of interconnects.

[0159] Example 26 provides the IC package of Example 25, which further includes: a package support (e.g., 504) having a third set of interconnects (e.g., 506) having a third pitch; and another inorganic layer (e.g., 106(2)) over the die-opposite surface (e.g., 112) of the interposer. The other inorganic layer includes conductive traces (e.g., 118(2)) electrically coupling the third set of interconnects to the second set of interconnects.

[0160] Example 27 provides an IC package of any of Examples 25 to 26, which further includes another die (e.g., 102C) embedded in a substrate. A third set of interconnects (e.g., 110A) in the substrate electrically couples the die (e.g., 102B) to the other die.

[0161] Example 28 provides an IC package of any of Examples 25 to 27, wherein the inorganic layer contains an RDL.

[0162] Example 29 provides an IC package of any of Examples 25 to 27, wherein the inorganic layer includes a cover layer.

[0163] Example 30 provides an IC package of any of Examples 25 to 29, wherein the inorganic layer is a first inorganic layer (e.g., 106(1)) and the intermediate is contained in a second inorganic layer above the first inorganic layer (e.g., 106(2)) (e.g., FIG3).

[0164] Example 31 provides an IC package of any of Examples 25 to 30, which further includes a plurality of dies coupled to an interposer using interconnects with different pitches (e.g., FIG. 5A). Conductive traces in the inorganic layer electrically couple the interconnects with different pitches to a second set of interconnects.

[0165] Example 32 provides an IC package of any of Examples 25 to 31, wherein the first set of interconnects includes die-to-die (DTD) interconnects.

[0166] Example 33 provides an IC package of any of Examples 25 to 31, wherein the first pitch is smaller than the second pitch and the third pitch is larger than the second pitch.

[0167] Example 34 provides the IC package of Example 26, wherein the third set of interconnects includes a die-to-package substrate (DTPS) interconnect.

[0168] Example 35 provides a method for manufacturing an intermediary (e.g., Figures 10 to 11), which includes providing a substrate comprising an organic insulator, polishing the surface of the substrate to form a polished surface (e.g., 1002, 1102, 1202), increasing the surface roughness of the polished surface to form a roughened surface (e.g., 1004, 1104, 1204), and disposing an inorganic layer on the roughened surface (e.g., 1006, 1112, 1206).

[0169] Example 36 provides the method of Example 35, wherein the inorganic layer system is placed using physical vapor deposition (PVD) at a temperature of less than 250 degrees Celsius.

[0170] Example 37 provides a method of any of Examples 35 to 36, wherein increasing the surface roughness of the polished surface includes soft etching in an inductively coupled plasma (ICP) module.

[0171] Example 38 provides a method of any of Examples 35 to 37, wherein the polishing comprises chemical mechanical polishing.

[0172] Example 39 provides a method of any of Examples 35 to 38, which further includes: forming a via (e.g., 1008, 1114, 1208) in an inorganic layer, and patterning the inorganic layer and electroplating the inorganic layer with a metal to form a conductive trace (e.g., 1012, 1118, 1212) over the inorganic layer.

[0173] Example 40 provides a method of any of Examples 35 to 39, which further includes patterning the organic layer before placing the inorganic layer and electroplating the organic layer with a metal to form conductive traces over the organic substrate (e.g., 1108).

[0174] Example 41 provides a method of any of Examples 35 to 40, which further includes placing another inorganic layer on top of the inorganic layer (e.g., 1216).

[0175] Example 42 provides the method of Example 41, which further includes forming a via (e.g., 1208) in the inorganic layer before placing another inorganic layer.

[0176] Example 43 provides the method of Example 41, which further includes forming a via (e.g., 1218) in another inorganic layer.

[0177] Example 44 provides a method of any of Examples 41 to 43, which further includes patterning another inorganic layer and electroplating the other inorganic layer with a metal to form a conductive trace (e.g., 1222) over the other inorganic layer.

[0178] Example 45 provides a method of any of Examples 35 to 44, which further includes placing an organic RDL (e.g., 406) over an inorganic layer.

[0179] The above description of the embodiments described in this disclosure (including the description in the abstract of the invention) is not intended to be exhaustive or to limit the disclosure to the precise form disclosed. Although specific embodiments and examples of the disclosure are described herein for illustrative purposes, those skilled in the art will recognize that various equivalent modifications are possible within the scope of this disclosure. [Simplified Explanation of the Diagram]

[0006] The embodiments will be readily understood from the following detailed description taken in conjunction with the accompanying drawings. For the purpose of this description, similar reference numerals designate similar structural elements. The embodiments are illustrated in the accompanying drawings by way of example rather than limitation.

[0007] Figure 1 is a schematic cross-sectional view of an exemplary IC package having an inorganic RDL over an organic substrate according to some embodiments of the present disclosure.

[0008] Figure 2 is a schematic cross-sectional illustration of another example of an IC package having an inorganic RDL over an organic substrate, according to some embodiments of the present disclosure.

[0009] Figure 3 is a schematic cross-sectional illustration of another example of an IC package having an inorganic RDL over an organic substrate, according to some embodiments of the present disclosure.

[0010] Figures 4A and 4B are schematic cross-sectional illustrations of another example of an IC package having an inorganic RDL over an organic substrate, according to some embodiments of the present disclosure.

[0011] Figure 5A is a schematic exploded perspective view of an IC package having an inorganic RDL over an organic substrate according to some embodiments of the present disclosure.

[0012] FIG5B is a cross-sectional schematic diagram of a portion of the IC package of FIG5A according to some embodiments of the present disclosure.

[0013] FIG6A is a schematic top view of an example surface of an IC package according to some embodiments of the present disclosure.

[0014] Figures 6B and 6C are schematic cross-sectional views of a portion of the IC package of Figure 6A according to some embodiments of the present disclosure.

[0015] Figures 7A and 7B are schematic cross-sectional views of surfaces in an example IC package architecture according to some embodiments of the present disclosure.

[0016] Figure 8 is a graph showing the film stress as a function of the inorganic layer thickness according to some embodiments of the present disclosure.

[0017] Figure 9 is a graph showing the peak wafer temperature as a function of the inorganic layer thickness according to some embodiments of the present disclosure.

[0018] Figure 10 is a flowchart of an example method for manufacturing an IC package according to various embodiments of the present disclosure.

[0019] Figure 11 is a flowchart of another example method for manufacturing an IC package according to various embodiments of the present disclosure.

[0020] Figure 12 is a flowchart of another example method for manufacturing an IC package according to various embodiments of the present disclosure.

[0021] Figure 13 is a cross-sectional view of a device package that may include one or more IC packages according to any of the embodiments disclosed herein.

[0022] Figure 14 is a cross-sectional side view of a device assembly that may include one or more IC packages according to any of the embodiments disclosed herein.

[0023] Figure 15 is a block diagram of an example computing device that may include one or more IC packages according to any of the embodiments disclosed herein.

Claims

1. An intermediary comprising: a first inorganic layer including a first set of interconnects having a first spacing; an organic substrate above the first inorganic layer, the organic substrate including a set of vias coupled to the first set of interconnects and disposed at the first spacing; a die embedded in the organic substrate; a second inorganic layer including a second set of interconnects having a second spacing; and conductive traces electrically coupling the set of vias to the second set of interconnects, wherein: The second spacing is different from the first spacing.

2. The medium as claimed in claim 1, wherein, prior to the placement of the second inorganic layer, one surface of the organic substrate adjacent to the second inorganic layer undergoes a soft etching process.

3. The medium as claimed in claim 1, wherein the second set of interconnects and the conductive traces are located above the organic substrate.

4. The medium as claimed in claim 1, wherein the second set of interconnects and the conductive traces are located within the second inorganic layer.

5. The medium as claimed in claim 1, wherein the set of through holes comprises a through connector extending between one surface of the organic substrate near the first inorganic layer and one opposite surface of the organic substrate.

6. The medium as claimed in claim 1, wherein the set of through holes comprises a through connector extending between one surface of the organic substrate and the grain.

7. The medium as claimed in claim 1, wherein the organic matrix further includes a second set of vias coupled to one of the grains embedded in the organic matrix.

8. The medium as claimed in claim 7, wherein the second set of vias is configured with the second spacing, and one of the second set of vias is coupled to one of the second set of interconnects.

9. The intermediary as requested in claim 1, wherein the intermediary further includes a third inorganic layer above the second inorganic layer.

10. The medium of claim 1 further includes an organic layer above the second inorganic layer, such that the second inorganic layer is located between the organic layer and the organic matrix.

11. The medium as claimed in claim 10, wherein the organic layer comprises polyimide.

12. An intermediary as claimed in any of claims 1 to 11, wherein the second inorganic layer comprises silicon nitride or silicon carbonitride.

13. An IC package comprising: a die having a first set of interconnects having a first spacing; and an intermediary comprising a first substrate, an organic substrate above the first substrate, and a second inorganic layer above the organic substrate, the first substrate having a second set of interconnects having a second spacing, wherein: The second inorganic layer includes conductive traces that electrically couple the organic substrate to the first set of interconnects, and the grain is attached to the intermediary via the first set of interconnects.

14. The IC package of claim 13, further comprising: a package support having a third set of interconnects having a third spacing, the package support being coupled to the first substrate-free layer.

15. The IC package of claim 13, further comprising another die embedded in the organic substrate, wherein a third set of interconnects in the organic substrate electrically couples the die to the other die.

16. The IC package of claim 13, wherein the interposer includes a third inorganic layer above the second inorganic layer.

17. The IC package of claim 13 further includes a plurality of dies coupled to the interposer using interconnects with different spacings, wherein the conductive traces in the second inorganic layer electrically couple the interconnects with different spacings to the organic substrate.

18. A method for manufacturing an intermediary, comprising: providing a substrate comprising an organic insulator; polishing a surface of the substrate to form a polished surface; increasing the surface roughness of the polished surface to form a roughened surface; and disposing an inorganic layer above the roughened surface.

19. The method of claim 18, wherein the inorganic layer is deposited using physical vapor deposition (PVD) at a temperature of less than 250 degrees Celsius.

20. The method of claim 18, wherein increasing the surface roughness of the polished surface is included in a soft etching process within an inductively coupled plasma (ICP) module.

21. The method of claim 18, further comprising: forming a via in the inorganic layer; and patterning the inorganic layer and electroplating the inorganic layer with a metal to form a conductive trace over the inorganic layer.

22. The method of claim 18, further comprising patterning the organic layer before placing the inorganic layer and electroplating the organic layer with a metal to form conductive traces over the organic substrate.

23. The method of claim 18, further comprising placing an organic RDL over the inorganic layer.

24. A package comprising: a first inorganic layer including a first set of interconnects having a first spacing; an organic substrate above the first inorganic layer, the organic substrate including a set of vias coupled to the first set of interconnects and configured with respect to the first spacing; a die embedded in the organic substrate; a second inorganic layer including a second set of interconnects having a second spacing; and conductive traces electrically coupling the set of vias to the second set of interconnects, wherein the second spacing is different from the first spacing.

25. The package of claim 24, wherein, prior to the placement of the second inorganic layer, one surface of the organic substrate adjacent to the second inorganic layer undergoes a soft etching process.

26. The package of claim 24, wherein the second set of interconnects and the conductive traces are located within the second inorganic layer.

27. The package of claim 24, wherein the set of through holes includes a through connector extending between one surface of the organic substrate adjacent to the first inorganic layer and one opposing surface of the organic substrate.

28. The package of claim 24, the organic substrate further comprising a second set of vias coupled to one of the dies embedded in the organic substrate, wherein one of the second set of vias is coupled to one of the second set of interconnects.

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