Semiconductor wafer and method of fabricating the same

Abstract

A method is provided for manufacturing a semiconductor wafer having a device side, a back side opposite to the device side, and an outer peripheral edge. Suitably, the method includes: forming a top conductive layer on the device side of the semiconductor wafer; forming a passivation layer over the top conductive layer, the passivation layer being formed such that the passivation layer does not extend to the outer peripheral edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin-coated over the passivation layer such that the protective layer has a smooth top surface at least in a region near the outer peripheral edge of the semiconductor wafer.

Description

[Technical Field]

[0001] This disclosure relates to a semiconductor wafer and a method for manufacturing a semiconductor wafer. [Previous Technology]

[0002] This disclosure relates to semiconductor technology, and in particular to semiconductor devices and methods and / or apparatus for manufacturing semiconductor devices. [Summary of the Invention]

[0003] This disclosure discloses a method for manufacturing a semiconductor wafer having a component side, a back side opposite to the component side, and an outer peripheral edge. The method includes: forming a top conductive layer on the component side of the semiconductor wafer; forming a passivation layer over the top conductive layer, the passivation layer being formed such that the passivation layer does not extend to the outer peripheral edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin-coated over the passivation layer such that the protective layer has a smooth top surface at least in a region near the outer peripheral edge of the semiconductor wafer.

[0004] This disclosure discloses a method for manufacturing a semiconductor wafer having a first side, a second side opposite to the first side, and an outer peripheral edge. The method includes: performing a front-end process on the semiconductor wafer, the front-end process including creating a plurality of individual semiconductor elements in a plurality of individual element regions on the first side of the semiconductor wafer, the plurality of individual element regions being separated by a plurality of dicing channels located between the plurality of individual element regions; performing a back-end process on the semiconductor wafer, the back-end process including forming a top conductive layer on the first side of the semiconductor wafer; depositing a passivation layer over the top conductive layer, the passivation layer being configured not to extend to the outer peripheral edge of the semiconductor wafer; and spin-coating a protective layer over the passivation layer such that the material forming the protective layer accumulates in the space between the passivation layer stop and the outer peripheral edge of the semiconductor wafer, thereby forming the protective layer with a smooth top surface at least in the region near the outer peripheral edge of the semiconductor wafer.

[0005] A semiconductor wafer having a first side, a second side opposite to the first side, and an outer peripheral edge according to an embodiment of the present disclosure, the semiconductor wafer comprising: a plurality of individual semiconductor elements formed in a plurality of individual element regions on the first side of the semiconductor wafer, the plurality of individual element regions being separated by a plurality of dicing channels located between the plurality of individual element regions; a top conductive layer located on the first side of the semiconductor wafer; a passivation layer located above the top conductive layer, the passivation layer not extending to the outer peripheral edge of the semiconductor wafer; and a polyimide layer spin-coated on the passivation layer such that the material forming the polyimide layer accumulates in the space between the stop of the passivation layer and the outer peripheral edge of the semiconductor wafer, thereby such that the polyimide layer is formed with a smooth top surface at least in the region near the outer peripheral edge of the semiconductor wafer.

Implementation Method

[0007] The following discloses numerous different embodiments or examples for implementing various features of the provided object. Specific examples of components and arrangements are described below to simplify the invention. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of the invention. Such repetition is for the purpose of brevity and clarity, and not in itself to indicate a relationship between the various embodiments and / or configurations discussed.

[0008] Furthermore, for ease of explanation, spatially relative terms such as "left," "right," "side," "back," "rear," "behind," "front," "below," "lower," "above," and "upper" may be used herein to describe the relationship between one element or feature shown in the figures and another (other) element or feature. In addition to the orientations shown in the figures, these spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative terms used herein may be interpreted accordingly.

[0009] Generally, according to some embodiments of this disclosure, a semiconductor wafer may have a plurality of individual semiconductor elements formed thereon. For example, semiconductor elements, such as metal-oxide-semiconductor field-effect transistors (MOS-FETs), integrated circuits (ICs), etc., are manufactured and / or fabricated on semiconductor wafers in a semiconductor manufacturing plant (often referred to as a FAB or foundry). A number of process steps are typically applied to the semiconductor wafer to produce the desired semiconductor elements and / or a plurality of semiconductor elements on the wafer. For example, semiconductor manufacturing may be a multi-step sequence of lithography, mechanical and / or chemical process steps (e.g., surface passivation, thermal oxidation, planar diffusion, junction isolation, etc.), during which electronic circuits and / or semiconductor elements are progressively created on the semiconductor wafer.

[0010] According to some embodiments of this disclosure, a semiconductor manufacturing process is considered to include a front-end-of-line (FEOL) portion, an optional middle-end-of-line (MEOL) portion, and a back-end-of-line (BEOL) portion. FEOL is the first part of a semiconductor manufacturing process (e.g., including IC manufacturing processes), where, for example, individual active components are patterned on a semiconductor wafer. In some embodiments, the FEOL process includes, but is not limited to, selecting the type of semiconductor wafer to be used, chemical mechanical planarization and cleaning of the wafer, shallow trench isolation (STI), well formation, gate module formation, and source and drain creation. In some embodiments, the FEOL process does not include the deposition of metal interconnect layers. In some embodiments, an optional MEOL process follows the FEOL process and includes, but is not limited to, gate contact formation and under-bump metallization (UBM) processes. Appropriately, according to some embodiments, the BEOL is the final part of the semiconductor manufacturing process (after the FEOL and / or MEOL sections). For example, in some embodiments, the BEOL section is where individual components (e.g., transistors, capacitors, resistors, etc.) are interconnected with vias and conductive traces, but is not limited thereto.

[0011] In some suitable embodiments, scribe streets (sometimes also referred to as "scribe streets") are defined between individual components or between die regions of a semiconductor wafer. For example, individual components or die regions are where individual ICs are formed on a semiconductor wafer. Ultimately, the semiconductor wafer is sawed, broken, or otherwise cut along the scribe streets to divide the wafer into individual dies and / or semiconductor components. In some suitable embodiments, these scribe streets are naturally defined and / or formed during the FEOL and / or BEOL portions of the manufacturing process because material deposited and / or built-up in the individual component and / or die regions is not deposited between them, and therefore the scribe streets are naturally formed, defined, and / or otherwise established (e.g., as trenches or troughs between build-up layers of material deposited in the component and / or die regions where individual semiconductor components and / or ICs are formed).

[0012] Generally speaking, the surface on which the element is formed or one side of the semiconductor wafer is called the element side, and the opposite surface on the other side of the wafer is called the back side.

[0013] In some embodiments, the semiconductor wafer typically begins at a first thickness (e.g., about 680 μm or some other suitable thickness), which provides the wafer with adequate strength to prevent accidental breakage at inappropriate times during the manufacturing process and / or handling. According to some embodiments of this disclosure, before the semiconductor wafer is diced into individual dies, but after the formation of the semiconductor elements and / or the structure on the element side (i.e., after the BEOL process), the semiconductor wafer is thinned to a second thickness (e.g., about 300 μm to about 380 μm or other suitable thickness) by grinding the back side of the wafer. This back-side grinding typically generates silicon dust particles and / or other small debris that are removed from the back side of the wafer during wafer thinning. Advantageously, some embodiments of this disclosure help protect the element side of the semiconductor wafer from potential defects caused by the flow or migration of debris from the outer periphery of the wafer inward toward the center of the wafer during back-side grinding.

[0014] According to some suitable embodiments of this disclosure, FIG1 illustrates a semiconductor wafer W having a plurality of grains or device regions 10, in which individual semiconductor devices and / or ICs are formed. As shown, in some embodiments, the semiconductor wafer W will have a generally circular shape with an outer periphery or edge 12. The wafer W may not have a perfectly circular shape. For example, although not shown, the wafer W may include a wafer flat on a peripheral portion, which is sometimes aligned with the semiconductor crystal orientation and / or may encode other information such as dopant type. According to some embodiments of this disclosure, cleavage paths (i.e., cut paths) 14 are defined between the individual grains or device regions 10. In some embodiments, the cleavage paths 14 are naturally formed and / or defined in FEOL and / or BEOL processes, wherein material deposition and / or uplayering occurs in the individual grains or device regions 10 to form individual semiconductor devices and / or ICs, while no such material deposition or uplayering is formed between the individual grains or device regions 10.

[0015] According to some suitable embodiments of the present disclosure, FIG2 shows a partial cross-sectional view of a semiconductor wafer W taken along the section line XX shown in FIG1. ​​As will be described below, this cross-sectional view illustrates the state of the wafer after the formation of the passivation layer and the protective polyimide layer. As will also be described below, the wafer state shown in FIG2 is ready for back-side wafer thinning.

[0016] As shown in FIG2, in some embodiments, the BEOL process includes forming a top conductive layer or a top metal layer, sometimes referred to herein as a TME (top metal) layer 20. Suitably, the TME layer 20 is formed by depositing and / or patterning electrical conductors, such as metals or metal alloys (e.g., aluminum (Al), copper (Cu), silver (Ag), etc.), metal silicides, etc., on a generated semiconductor product (e.g., a product obtained where FEOL and BEOL processes have been completed). In some embodiments, the TME layer 20 may be deposited by physical vapor deposition (PVD), such as sputtering deposition or any other suitable deposition method. In some suitable embodiments, the TME layer 20 is formed of AlCu.

[0017] In some suitable embodiments, the TME layer 20 does not extend to the periphery or edge 12 of the semiconductor wafer W. In some suitable embodiments, the TME layer 20 will be located at a distance D2 from the outer periphery or edge 12 of the semiconductor wafer W, said distance D2 may be, for example, about 1.8 mm or more. For example, the TME layer 20 may be formed only in the region of the device dies, and these dies typically stop at the outer periphery or edge 12. Suitablely, the TME layer 20 will have a relatively large thickness. For example, according to some embodiments, the TME layer 20 typically has a thickness greater than or equal to about 20 kÅ (2.0 micrometers).

[0018] According to some suitable embodiments of this disclosure, a passivation layer 22 is deposited, patterned, and / or otherwise formed on top of the TME layer 20. The passivation layer 22 is typically deposited and / or formed after metallization, and it helps protect the underlying semiconductor device. In some suitable embodiments, the passivation layer 22 is an oxide layer that can be deposited by, for example, chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), or any other suitable deposition method.

[0019] In some suitable embodiments, the passivation layer 22 will have a relatively large thickness, for example, typically greater than or equal to about 15 kÅ (1.5 micrometers). In some suitable embodiments, the passivation layer 22 will have a thickness of about 32 kÅ or 3.2 μm. According to some suitable embodiments, the passivation layer 22 is positioned at a distance D1 from the outer periphery or edge 12 of the semiconductor wafer W, said distance D1 being, for example, about 1.0 mm or more.

[0020] As shown in FIG. 2, according to some embodiments of the present disclosure, a polyimide or other spin-coated protective layer 24 is deposited and / or otherwise formed on the passivation layer 22. Suitably, the polyimide layer 24 is formed on the semiconductor wafer W by, for example, spin coating or other similar suitable methods. In some suitable embodiments, the polyimide layer 24 will have a thickness of, for example, typically about 5.0 μm.

[0021] According to some suitable embodiments of the present disclosure, FIG3 shows a flowchart illustrating a method and / or process 1000 for manufacturing the semiconductor structure shown in FIG1 and 2.

[0022] As shown in the figure, the method or process 1000 begins with step 100, in which the FEOL portion of the semiconductor manufacturing process is performed. Suitably, in the FEOL process step 100, a plurality of individual semiconductor devices and / or ICs are progressively formed on the semiconductor wafer W (e.g., in the die or device region 10). In some embodiments, the FEOL process includes, but is not limited to, selecting the type of semiconductor wafer to be used, chemical mechanical planarization and cleaning of the wafer, shallow trench isolation (STI), well formation, gate module formation, and source and drain creation, etc.

[0023] The BEOL process step 200 is performed after the FEOL process step 100. For example, in some embodiments, the BEOL portion is where individual components (e.g., transistors, capacitors, resistors, etc.) are interconnected with vias and conductive traces, but is not limited thereto. Generally, there may be a number of metallization layers (sometimes referred to as metal layers M0, M1, M2, ..., TME, where TME represents the top metal layer) and intermetallic dielectric (IMD) material and interconnecting vias formed between the components and the various metal layers. As shown, the BEOL process step 200 suitably includes a sub-step 210 of depositing, patterning, and / or otherwise forming the TME layer 20. Suitably, the TME layer 20 may be deposited by, for example, PVD, sputtering deposition, or any other suitable deposition method.

[0024] As shown in FIG3, in step 300, a passivation layer 22 is deposited, patterned, and / or otherwise formed. According to some embodiments of this disclosure, step 300 suitably includes a series of sub-steps as more fully described in FIG4. Notably, step 300 includes performing wafer edge exposure (WEE) (sub-step) 330 to remove the outermost annular ring of the passivation layer at the periphery of the semiconductor wafer W. As discussed further hereafter, this provides protection against dust or other contaminants entering via the dicing path 14 during subsequent back-side wafer thinning processes.

[0025] According to some suitable embodiments of the present disclosure, FIG4 illustrates exemplary methods, processes and / or steps 300 for depositing, patterning and / or otherwise forming a passivation layer 22.

[0026] Suitably, as shown in FIG4, the method, process, or step 300 begins with sub-step 310, which is to deposit material (e.g., oxide material or other suitable material forming passivation layer 22) on the TME layer 20 on the semiconductor wafer W. In some embodiments, the passivation layer 22 may be deposited by, for example, CVD, PECVD, or any other suitable deposition method. In practice, the deposited passivation layer 22 may extend or substantially extend to the periphery or edge 12 of the semiconductor wafer W. For example, FIG5A shows an example configuration of the semiconductor wafer W after sub-step 310 and before sub-step 320.

[0027] After sub-step 310, a photoresist layer 26 of photoresist material is deposited on the passivation layer 22 (see also Figure 5B). In some embodiments, the photoresist layer 26 is a layer formed of a positive photoresist material. Therefore, the photoresist material is sensitive to light or radiation, and thus, when exposed to light or radiation, the photoresist material becomes selectively soluble or removable by the subsequent application of a suitable developer, while unexposed photoresist material remains largely unaffected by the developer (i.e., to avoid being substantially or otherwise removed by the developer). In some embodiments, the photoresist layer 26 is applied by spin coating or other suitable deposition techniques. For example, Figure 5B shows a configuration example of the semiconductor wafer W after sub-step 320 and before sub-step 330. As shown in Figure 5B, at this time, the photoresist layer 26 may extend or substantially extend to the periphery or edge 12 of the semiconductor wafer W.

[0028] After sub-step 320, according to some embodiments of the present disclosure, wafer edge exposure (WEE) is applied in sub-step 330.

[0029] Referring again to FIG6, the WEE step (sub-step) 330 exposes the outer annular ring 26a of the photoresist layer 26 near the periphery or edge 12 of the semiconductor wafer W to a beam 32a of light or radiation (e.g., UV light or radiation) emitted from a light or radiation source 32. According to some suitable embodiments of this disclosure, the light or radiation source 32 may be a laser or optical focusing illumination source or other similar illumination source whose output produces a beam (light / radiation beam) 32a of light or radiation with the desired spot size on the photoresist layer 26. In practice, the spot size corresponds to the desired width of the outer annular ring 26a removed from the photoresist layer 26. In some suitable embodiments, the effective spot size may have, for example, a diameter of about 1.0 mm or greater. Instead of using a focusing light source 32, or in addition to using a focusing light source 32, a suitable light shield (not shown, e.g., a metal plate) may be provided to block stray light and thus ensure that the beam 32a illuminates only over the width corresponding to the outer annular ring 26a.

[0030] Appropriately, the photoresist layer 26 of the photoresist material is sensitive to the received light / radiation beam 32a, so that when exposed to such light or radiation, the photoresist material becomes selectively soluble or dissolvable or otherwise removed by the subsequent application of a suitable developer, while the unexposed photoresist material remains largely unaffected by the developer.

[0031] In some embodiments, the WEE exposure sub-step 330 is suitably performed using the WEE technique shown in FIG. 6. Specifically, a photoresist-coated semiconductor wafer W is appropriately positioned and / or fixed on a rotatable chuck 30, such as a vacuum chuck or an electrostatic chuck. In some embodiments, a light / radiation source 32 is located above or near the photoresist layer 26 at or near the periphery or edge 12 of the semiconductor wafer W. The chuck 30 rotates the semiconductor wafer W when the source 32 emits a beam 32a toward and / or emits a beam 32a onto the photoresist layer 26. Therefore, as the chuck 30 and / or the fixed semiconductor wafer W rotate below it, the outer annular ring 26a of the photoresist layer 26 near the periphery or edge 12 of the semiconductor wafer W is exposed to light emitted from or radiated by the light / radiation source 32.

[0032] In some suitable embodiments, the outer annular ring 26a of the exposed photoresist layer 26 has a width w (measured radially relative to the semiconductor wafer W) of, for example, about 1.0 mm or more.

[0033] In some suitable alternative embodiments, the exposure sub-step 330 can be performed using any suitable lithography technique. For example, a stepper or scanner or other suitable projection and / or illumination source can be used with a suitable photomask to form patterned light or radiation exposure on the photoresist layer 26, wherein the outer annular ring 26a is exposed, while the remaining central portion of the photoresist layer 26 remains unexposed. In some other alternative embodiments, the photoresist layer 26 may comprise a negative photoresist material, so that patterned illumination allows the central portion of the photoresist layer 26 to receive exposure, while the outer annular ring 26a of the photoresist layer remains unexposed.

[0034] Turning now to FIG. 4, according to some suitable embodiments of this disclosure, an exposure sub-step 330 is followed by a development sub-step 340. Suitably, during the development sub-step 340, a developer is applied to the photoresist layer 26 to selectively remove portions of the photoresist layer 26. In particular, the developer serves to dissolve or otherwise remove the outer annular portion 26a of the photoresist layer 26 near the periphery or edge 12 of the semiconductor wafer W, while the central portion of the photoresist layer 26 remains completely or substantially unremoved by the applied developer. Thus, at this point, as shown in FIG. 5C, the photoresist layer 26 no longer extends to the periphery or edge 12 of the semiconductor wafer W. Instead, the photoresist layer 26 is separated from the periphery or edge 12 of the semiconductor wafer W by a radial distance w, such as about 1.0 mm or more. FIG. 5C shows an example configuration of the semiconductor wafer W after sub-step 340 and before sub-step 350.

[0035] According to some suitable embodiments of this disclosure, the developing sub-step 340 is followed by an etching sub-step 350. Referring to FIG5C, it can be understood that after the developing sub-step 340, the annular portion of the passivation layer 22, which previously rested on the removed outer annular portion 26a of the photoresist layer 26, has been exposed and / or is not covered by the photoresist layer 26. Therefore, during the etching sub-step 350, the uncovered annular portion of the passivation layer 22 is removed, while the remaining portion of the passivation layer 22, still covered and / or protected by the unremoved photoresist layer 26, remains substantially intact. In practice, any suitable etching or other similar material removal process can be used in sub-step 350, such as liquid (i.e., wet) or plasma (i.e., dry) etching processes. In some suitable embodiments, the etching process is anisotropic etching, which avoids severe undercutting of the photoresist. Figure 5D shows an example of the configuration of semiconductor wafer W after sub-step 350 and before sub-step 360.

[0036] As can be seen from Figure 5D, at this point, the passivation layer 22 no longer extends to the periphery or edge 12 of the semiconductor wafer W. Instead, consistent with the outer annular ring 26a of the removed photoresist layer 26, after the etching step 350, the passivation layer 22 is also separated from the periphery or edge 12 of the semiconductor wafer W by a radial distance w, for example, about 1.0 mm or more.

[0037] Returning to Figure 4, according to some suitable embodiments of this disclosure, an additional sub-step 360 may follow the etching sub-step 350. Since the photoresist layer 26 is no longer needed, the remaining photoresist layer 26 is appropriately removed (i.e., stripped) in sub-step 360. In some embodiments, the remaining photoresist layer 26 may be removed using a liquid or other suitable photoresist stripper that chemically or otherwise alters the photoresist material so that it no longer adheres to the underlying material. In some embodiments, the remaining photoresist layer 26 may be removed using a process known as ashing, in which an oxygen-containing plasma, for example, is applied to the photoresist layer 26 to oxidize it. In some other embodiments, a suitable solvent may be used to dissolve the remaining portion of the photoresist layer 26. In any case, Figure 5E shows an example configuration of the semiconductor wafer W after the removal of the remaining photoresist layer 26 (i.e., after sub-step 360).

[0038] Returning to FIG. 3, the passivation layer 22 is formed, for example, by deposition, patterning, and / or other means, such that the passivation layer 22 no longer extends all the way to or substantially all the way to the periphery or edge 12 of the semiconductor wafer W. In some suitable embodiments of this disclosure, a polyimide layer 24 may be deposited and / or otherwise formed on the passivation layer 22. For example, as shown in FIG. 3, step 400 in method or process 1000 is to deposit and / or form the polyimide layer 24. FIG. 7 shows a cross-sectional view of the semiconductor wafer W after deposition of the polyimide layer 24 according to some suitable embodiments of this disclosure.

[0039] In some suitable embodiments, after the passivation layer 22 is formed (and / or before the dicing process), physical failure analysis (PFA) may be performed, for example, at least at or near the periphery or edge 12 of the semiconductor wafer. Suitablely, such PFA allows or helps to detect the presence of the passivation layer 22 at or near the periphery or edge 12 of the wafer. For example, PFA may include optical microscopy, scanning electron microscopy (SEM), etc., performed at or near the periphery or edge 12 to confirm and / or otherwise determine that it does not contain the passivation layer 22 (that is, if necessary, the passivation layer 22 does not extend all the way to the periphery or edge 12 of the semiconductor wafer W), or alternatively, some of the passivation layer 22 has not been sufficiently removed from or is otherwise left at or near the periphery or edge 12 of the semiconductor wafer W (e.g., some unwanted residual thickness of the passivation layer remains at or near the periphery or edge 12 of the semiconductor wafer W).

[0040] According to some suitable embodiments of this disclosure, a polyimide layer 24 can be deposited and / or formed by a spin coating process to produce a uniform film. In practice, a spin coating process typically requires applying a relatively small amount of polyimide coating material to the center or vicinity of the semiconductor wafer W, and then rotating or turning (e.g., by rotating a chuck that holds the semiconductor wafer W) to disperse the coating material outward toward the periphery or edge 12 of the semiconductor wafer W by centrifugal force. For example, as shown in FIG2, when the polyimide material forming the polyimide layer 24 is dispersed and close to the periphery or edge 12 of the semiconductor wafer W, the polyimide material tends to accumulate near the periphery or edge 12 (e.g., filling the annular space left by the etched-removed passivation layer 22). It is noteworthy that such accumulation of polyimide material near the periphery or edge 12 tends to produce a relatively smooth, uniform, and / or uniform top surface 24a of the polyimide layer 24.

[0041] As shown in FIG3, according to some suitable embodiments of the present disclosure, the method or process 1000 includes a back-side polishing step 500 performed after step 400 of depositing and / or otherwise forming polyimide layer 24.

[0042] According to some embodiments, the back-side polishing step 500 includes first applying a protective tape to the device side of the semiconductor wafer W. In practice, the protective tape is applied to and / or covers the top surface 24a of the polyimide layer 24. After the protective tape is applied, the semiconductor wafer W is positioned and secured on the device side, for example, by means of a vacuum chuck, an electrostatic chuck, or other suitable holding device. Once the semiconductor wafer W is thus secured, the back side of the semiconductor wafer W is then mechanically polished, for example, to thin the semiconductor wafer W substrate to the desired thickness.

[0043] Generally, in practice, mechanical polishing is performed with a large amount of water supplied or introduced while abrasive or other suitable polishing tools rub against the back surface of the semiconductor wafer W. The applied polishing removes material from the back surface of the semiconductor wafer W. During the process, small dust particles and / or debris are generated, for example, removed from the back surface of the semiconductor wafer W during the polishing process.

[0044] It is worth noting that, when the passivation layer 22 is allowed to extend all the way or substantially all the way to the periphery or edge 12 of the semiconductor wafer W, a groove or other similar recess (at or near the periphery or edge 12 of the semiconductor wafer W) is often left on the top surface 24a of the polyimide layer 24 when the polyimide material is spin-coated over the passivation layer 22. For example, such a groove or recess typically tends to cover or correspond to the location of the dicing 14 and extends from the outer periphery or edge 12 of the semiconductor wafer W toward the interior or central region of the semiconductor wafer W (e.g., along the dicing 14). It is worth noting that in this case, the protective tape may not be able to adequately seal the top surface 24a of the polyimide layer 24. That is, the protective tape may not be able to adequately extend and / or cover the groove or recess, which may tend to be substantially narrow. Therefore, in this case, the groove or recess remains an open channel or passageway, allowing small dust particles and / or debris generated during the back-side polishing step to flow in and / or otherwise move (e.g., carried by water used in the polishing process or otherwise) from the outer periphery or edge 12 of the semiconductor wafer W into the interior or central region of the semiconductor wafer W, where the small dust particles and / or debris may cause defects.

[0045] However, as disclosed in this specification, according to some embodiments, the passivation layer 22 is not allowed to extend all the way to the periphery or edge 12 of the semiconductor wafer W. Instead, the passivation layer 22 is located at a distance from the outer periphery or edge 12 of the semiconductor wafer W, for example, about 1.0 mm or more. In some suitable embodiments, the passivation layer 22 may indeed extend all the way to the outer periphery or edge 12 of the semiconductor wafer W during the initial deposition of the passivation layer 22, but after the initial deposition of the passivation layer 22, the outer annular portion of the passivation layer 22 near the periphery or edge 12 of the semiconductor wafer W (e.g., having a width of about 1.0 mm or more measured radially relative to the semiconductor wafer W) is etched away or otherwise removed. For example, according to some suitable embodiments, the outer annular ring of the passivation layer 22 may be removed by using a WEE process during step 300, particularly during the etching sub-step 350.

[0046] According to some suitable alternative embodiments, the passivation layer 22 may be initially formed and / or patterned such that the passivation layer 22 does not extend all the way to the periphery or edge 12 of the semiconductor wafer W. For example, suitable photomasks and / or suitable lithography techniques and / or other suitable methods may be used such that the passivation layer 22 does not extend all the way to the periphery or edge 12 of the semiconductor wafer W when initially deposited.

[0047] In any case, referring to FIG8, it should be understood that the annular outer region 40 of the semiconductor wafer W remains free of the passivation layer 22. In some suitable embodiments, the annular outer region 40 has, for example, a width w relative to the semiconductor wafer W measured radially, of about 1.0 mm or greater. In some suitable embodiments, the semiconductor wafer has, for example, a diameter of about 99 mm or greater. Therefore, the annular outer region 40 without the passivation layer has a relatively small surface area compared to the surface area of ​​the entire semiconductor wafer W.

[0048] One advantage of having an annular outer region 40 without a passivation layer is that when the polyimide layer 24 is spin-coated onto the passivation layer 22, the polyimide layer 24 tends to accumulate and / or build up in the space without the passivation layer 22, thereby keeping the top surface 24 of the polyimide layer 24 substantially smooth, uniform, and / or homogeneous at least at or near the periphery or edge 12 of the semiconductor wafer W (e.g., see FIG2). That is, the aforementioned grooves and / or recesses (e.g., which may tend to be formed in the top surface 24a of the polyimide layer 24 above the dicing 14 when the passivation layer 22 is allowed to extend all the way to or substantially all the way to the periphery or edge 12 of the semiconductor wafer W) are eliminated and / or substantially reduced (e.g., in depth and / or other aspects). Therefore, when the protective tape is applied to the top surface 24a of the polyimide layer 24 for back-side polishing, the protective tape and the top surface 24a of the polyimide layer 24 maintain good and consistent contact around and near the periphery or edge 12 of the semiconductor wafer W, thereby preventing or inhibiting the inflow and / or movement of small dust particles and / or debris generated during back-side polishing into the interior or central region of the semiconductor wafer W, thereby limiting potential defects that may result therefrom.

[0049] Some further illustrative embodiments are described below.

[0050] In some further embodiments, a method of manufacturing a semiconductor wafer is provided, the semiconductor wafer having a device side, a back side opposite to the device side, and an outer peripheral edge. Suitably, the method includes: forming a top conductive layer on the device side of the semiconductor wafer; forming a passivation layer over the top conductive layer, the passivation layer being formed such that the passivation layer does not extend to the outer peripheral edge of the semiconductor wafer; and forming a protective layer over the passivation layer, the protective layer being spin-coated over the passivation layer such that the protective layer has a smooth top surface at least in a region near the outer peripheral edge of the semiconductor wafer.

[0051] In some other embodiments, the passivation layer is 1.0 mm or more away from the outer peripheral edge of the semiconductor wafer.

[0052] In an additional embodiment, the semiconductor wafer has a diameter of 99.0 mm or greater.

[0053] In some embodiments, the method further includes: performing a front-end process on the semiconductor wafer prior to forming the top conductive layer, the front-end process including creating a plurality of individual semiconductor devices in a plurality of individual device regions on the device side of the semiconductor wafer, the plurality of individual device regions being separated by a plurality of dicing channels located between the plurality of individual device regions.

[0054] In a further embodiment, the method further includes: applying a protective tape to the top surface of the protective layer; and grinding the back side of the semiconductor wafer to thin the substrate of the semiconductor wafer.

[0055] In some further embodiments, the applied grinding generates debris removed from the substrate of the semiconductor wafer, and the protective tape is in full contact with the smooth top surface of the protective layer to prevent the debris from moving from the outer peripheral edge of the semiconductor wafer toward the center portion of the semiconductor wafer between the protective tape and the top surface of the protective layer.

[0056] In some embodiments, forming a passivation layer includes: depositing a passivation layer over a top conductive layer such that the passivation layer extends to the outer peripheral edge of the semiconductor wafer; and removing an outer annular portion of the deposited passivation layer near the outer peripheral edge of the semiconductor wafer such that the remaining portion of the passivation layer no longer extends to the outer peripheral edge of the semiconductor wafer.

[0057] In a further embodiment, removing the outer annular portion of the deposited passivation layer includes: depositing a photoresist layer on top of the deposited passivation layer; exposing the outer annular portion of the photoresist layer to radiation; developing the photoresist layer to remove the exposed outer annular portion of the photoresist layer, thereby leaving the outer annular portion of the underlying passivation layer uncovered, and without removing the remaining portion of the photoresist layer covering the remaining portion of the passivation layer; and applying etching to remove the uncovered outer annular portion of the passivation layer, the remaining portion of the passivation layer being covered by the remaining portion of the photoresist layer to prevent etching.

[0058] In some embodiments, the exposure includes: positioning a radiation source near an outer annular portion of the photoresist layer; generating a radiation beam from the radiation source, the beam being directed and impacting the outer annular portion of the photoresist layer; and rotating the semiconductor wafer as the beam impacts the outer annular portion of the photoresist layer.

[0059] In some further embodiments, the formation of the top conductive layer is performed during the back-end process portion of the semiconductor manufacturing process.

[0060] In a further embodiment, the top conductive layer does not extend to the outer peripheral edge of the semiconductor wafer, but is located at a distance of 1.8 mm or greater from the outer peripheral edge of the semiconductor wafer.

[0061] In an additional embodiment, the protective layer is a polyimide layer.

[0062] In some further embodiments, a method for manufacturing a semiconductor wafer is provided. The semiconductor wafer suitably has a first side, a second side opposite to the first side, and an outer peripheral edge. The method includes: performing a front-end process on the semiconductor wafer, the front-end process including creating a plurality of individual semiconductor devices in a plurality of individual device regions on a first side of the semiconductor wafer, the plurality of individual device regions being separated by a plurality of dicing channels located between the plurality of individual device regions; performing a back-end process on the semiconductor wafer, the back-end process including forming a top conductive layer on the first side of the semiconductor wafer; depositing a passivation layer over the top conductive layer, the passivation layer being configured not to extend to the outer peripheral edge of the semiconductor wafer; and spin-coating a protective layer over the passivation layer such that the material forming the protective layer accumulates in the space between the passivation layer stop and the outer peripheral edge of the semiconductor wafer, thereby forming the protective layer with a smooth top surface at least in the region near the outer peripheral edge of the semiconductor wafer.

[0063] In some embodiments, the passivation layer is 1.0 mm or more away from the outer peripheral edge of the semiconductor wafer.

[0064] In some further embodiments, the method further includes: applying a protective tape to the top surface of the protective layer; applying grinding to a second side of the semiconductor wafer to thin the substrate of the semiconductor wafer; wherein the applied grinding produces debris removed from the substrate of the semiconductor wafer, and the protective tape is in sufficient contact with the smooth top surface of the protective layer to prevent debris from moving between the protective tape and the top surface of the protective layer from the outer peripheral edge of the semiconductor wafer toward the central portion of the semiconductor wafer.

[0065] In some additional embodiments, the passivation layer is formed by depositing a passivation layer on a top conductive layer such that the passivation layer extends to the outer peripheral edge of the semiconductor wafer; and removing an outer annular portion of the deposited passivation layer near the outer peripheral edge of the semiconductor wafer such that the remaining portion of the passivation layer no longer extends to the outer peripheral edge of the semiconductor wafer.

[0066] In some embodiments, removing the outer annular portion of the deposited passivation layer includes: depositing a photoresist layer on top of the deposited passivation layer; irradiating the photoresist layer with a light pattern; developing the photoresist layer to remove the outer annular portion of the photoresist layer, thereby leaving the outer annular portion of the underlying passivation layer uncovered, and not removing the remaining portion of the photoresist layer covering the remaining portion of the passivation layer; and applying etching to remove the uncovered outer annular portion of the passivation layer, the remaining portion of the passivation layer being covered by the remaining portion of the photoresist layer to prevent etching.

[0067] In a further embodiment, the irradiation includes: generating a light beam with a light source, the beam being guided and striking an outer annular portion of a photoresist layer; and rotating a semiconductor wafer as the beam strikes the outer annular portion of the photoresist layer.

[0068] In yet another embodiment, a semiconductor wafer is provided having a first side, a second side opposite to the first side, and an outer peripheral edge. The semiconductor wafer includes: a plurality of individual semiconductor elements formed in a plurality of individual element regions on the first side of the semiconductor wafer, the plurality of individual element regions being separated by a plurality of cleavages located between the plurality of individual element regions; a top conductive layer located on the first side of the semiconductor wafer; a passivation layer located above the top conductive layer, the passivation layer not extending to the outer peripheral edge of the semiconductor wafer; and a polyimide layer spin-coated on the passivation layer such that the material forming the polyimide layer accumulates in the space between the stop of the passivation layer and the outer peripheral edge of the semiconductor wafer, thereby forming the polyimide layer with a smooth top surface at least in the region near the outer peripheral edge of the semiconductor wafer.

[0069] In yet another embodiment, the passivation layer is 1.0 mm or more away from the outer peripheral edge of the semiconductor wafer.

[0070] The foregoing outlines features of many embodiments, enabling those skilled in the art to better understand the embodiments disclosed herein. Those skilled in the art should understand that other processes and structures can be easily designed or modified based on the embodiments disclosed herein to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that these equivalent structures do not depart from the spirit and scope of the invention disclosed. Various changes, substitutions, or modifications can be made to the embodiments disclosed herein without departing from the spirit and scope of the invention disclosed. [Simplified Explanation of the Diagram]

[0006] The following detailed description, taken in conjunction with the accompanying drawings, will provide the best understanding of the various aspects of this disclosure. It should be noted that, according to standard practice in the industry, the various features in the drawings are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or decreased for clarity of explanation. Figure 1 schematically shows a top view of a semiconductor wafer according to some embodiments of this disclosure. Figure 2 schematically shows a partial cross-sectional view of the semiconductor wafer shown in Figure 1 taken along section line XX according to some embodiments of this disclosure. Figure 3 is a flowchart illustrating a semiconductor manufacturing method and / or process according to some embodiments of this disclosure. Figure 4 is a flowchart illustrating in more detail the passivation layer formation steps of the semiconductor manufacturing method and / or process shown in Figure 3 according to some embodiments of this disclosure. Figures 5A to 5E schematically show cross-sectional views of a semiconductor wafer at various stages of the manufacturing process according to some embodiments of this disclosure. Figure 6 is a schematic diagram illustrating the wafer edge exposure technology used according to some embodiments of this disclosure. Figure 7 schematically shows a cross-sectional view of a semiconductor wafer according to some embodiments of this disclosure. Figure 8 is a further schematic top view illustrating a semiconductor wafer according to some embodiments of the present disclosure.

Claims

1. A method for manufacturing a semiconductor wafer having a component side, a back side opposite to the component side, and an outer peripheral edge, the method comprising: A plurality of patterned metallization layers and an inter-metal dielectric are formed on the device side of the semiconductor wafer, wherein the plurality of patterned metallization layers include a top patterned metallization layer; a passivation layer is formed on the top patterned metallization layer, and the passivation layer directly contacts and covers the top surface and side surface of the top patterned metallization layer, and the passivation layer is formed such that the passivation layer does not extend to the outer peripheral edge of the semiconductor wafer; and a protective layer is formed on the passivation layer, and the protective layer directly contacts and covers the top surface and side surface of the passivation layer, the protective layer extends to the outer peripheral edge of the semiconductor wafer, and is spin-coated on the passivation layer so that the protective layer has a smooth top surface at least in the region near the outer peripheral edge of the semiconductor wafer.

2. The method of claim 1, wherein the passivation layer is located at a distance of 1.0 mm or greater from the outer peripheral edge of the semiconductor wafer.

3. A method for manufacturing a semiconductor wafer having a first side, a second side opposite to the first side, and an outer peripheral edge, the method comprising: The semiconductor wafer is subjected to a front-end process, the front-end process including creating a plurality of individual semiconductor devices in a plurality of individual device regions on a first side of the semiconductor wafer, the plurality of individual device regions being separated by a plurality of dicing channels located between the plurality of individual device regions; the semiconductor wafer is subjected to a back-end process, the back-end process including forming a plurality of patterned metallization layers on the device regions on the first side of the semiconductor wafer and inter-metal dielectrics between the plurality of patterned metallization layers, wherein forming the plurality of patterned metallization layers includes a last formed top patterned metallization layer; A passivation layer is deposited on top of the patterned metallization layer, and the passivation layer directly contacts and covers the top surface and side surface of the top patterned metallization layer, the passivation layer being configured not to extend to the outer peripheral edge of the semiconductor wafer; and a protective layer is spin-coated on top of the passivation layer, and the protective layer directly contacts and covers the top surface and side surface of the passivation layer, such that the material forming the protective layer accumulates in the space between the stop of the passivation layer and the outer peripheral edge of the semiconductor wafer, thereby forming the protective layer with a smooth top surface at least in the region near the outer peripheral edge of the semiconductor wafer, and the protective layer extending to the outer peripheral edge of the semiconductor wafer.

4. The method as described in claim 3 further includes: Apply protective tape to the top surface of the protective layer; Grinding is applied to the second side of the semiconductor wafer to thin the substrate of the semiconductor wafer; The applied grinding generates debris removed from the substrate of the semiconductor wafer, and the protective tape is in full contact with the smooth top surface of the protective layer to prevent the debris from moving from the outer peripheral edge of the semiconductor wafer toward the central portion of the semiconductor wafer between the protective tape and the top surface of the protective layer.

5. A method for manufacturing a semiconductor wafer having a component side and a back side opposite to said component side, the method comprising: A top conductive layer is formed on the element side of the semiconductor wafer; A passivation layer is deposited, contacting and covering the top and side surfaces of the top conductive layer, the passivation layer extending to the outer edge of the semiconductor wafer; a photoresist layer is deposited on the passivation layer; the photoresist layer is exposed to radiation and developed to remove annular portions of the photoresist layer; etching is performed to remove the outer annular portions of the passivation layer that were not covered after the removal of the annular portions of the photoresist layer. And a spin-coated protective layer that directly contacts and covers the top and side surfaces of the passivation layer and the outer annular portion of the semiconductor wafer exposed due to the removal of the outer annular portion of the passivation layer, wherein the protective layer extends to the outer edge of the semiconductor wafer and is the outermost layer on the element side of the semiconductor wafer.

6. A semiconductor wafer having a first side, a second side opposite to the first side, and an outer peripheral edge, the semiconductor wafer comprising: A plurality of individual semiconductor elements are formed in a plurality of individual element regions on the first side of the semiconductor wafer, the plurality of individual element regions being separated by a plurality of dicing channels located between the plurality of individual element regions; a plurality of patterned metallization layers are located on the first side of the semiconductor wafer, wherein an intermetallic dielectric is disposed between the plurality of patterned metallization layers, and the plurality of patterned metallization layers include a top patterned metallization layer; a passivation layer is located above the top patterned metallization layer and directly contacts and covers the upper surface of the top patterned metallization layer, wherein the passivation layer does not extend to the outer peripheral edge of the semiconductor wafer; and a polyimide layer is spin-coated on the passivation layer and directly contacts the passivation layer, wherein the material of the polyimide layer is formed to accumulate in the space between the stop of the passivation layer and the outer peripheral edge of the semiconductor wafer, thereby forming the polyimide layer with a smooth top surface at least in the region near the outer peripheral edge of the semiconductor wafer.

7. The semiconductor wafer as claimed in claim 6, wherein the passivation layer comprises an oxide layer.

8. A semiconductor wafer, comprising: A plurality of individual semiconductor elements are formed in a plurality of individual element regions on the element side of the semiconductor wafer, the plurality of individual element regions being separated by a plurality of dicing channels located between the plurality of individual element regions; a plurality of patterned metallization layers are disposed on the element side of the semiconductor wafer, wherein an inter-metal dielectric is disposed between the plurality of patterned metallization layers, and the plurality of patterned metallization layers include a top patterned metallization layer, wherein the top patterned metallization layer is not disposed on an outer annular ring on the element side of the semiconductor wafer, the outer annular ring extending to the outer peripheral edge of the semiconductor wafer; a passivation layer is disposed on the top patterned metallization layer and on the inner portion of the outer annular ring on the element side of the semiconductor wafer, wherein the passivation layer directly contacts and covers the top surface and side surface of the top patterned metallization layer, the passivation layer is not disposed on the outer portion of the outer annular ring, the outer portion of the outer annular ring extending to the outer peripheral edge of the semiconductor wafer; And a polyimide layer, disposed on the passivation layer and on the outer portion of the outer annular ring, and directly contacting and covering the top and side surfaces of the passivation layer.

9. The semiconductor wafer as claimed in claim 8, wherein the width of the outer portion of the outer annular ring is 1.0 mm or greater.

10. A semiconductor wafer, comprising: A semiconductor device formed in a component region on the component side of the semiconductor wafer, the component region being separated by cleavages extending between the component regions; A back-end metallization layer is disposed on the device side of the semiconductor wafer and includes a top metallization layer; a passivation layer is disposed on the device side of the semiconductor wafer and directly contacts and covers the top metallization layer of the back-end metallization layer, wherein the passivation layer is not disposed on the outer annular ring portion of the semiconductor wafer extending to the outer peripheral edge of the semiconductor wafer on the device side; And a polyimide layer disposed on the passivation layer and on the outer annular ring portion on the element side of the semiconductor wafer, wherein the polyimide layer directly contacts and covers the upper surface of the portion of the passivation layer that overlaps and contacts the top metallization layer, and the bottom surface of the polyimide layer is at the same level as the bottom surface of the passivation layer.

Images