Package comprising stacked integrated devices with overhang

Abstract

A package includes: a substrate, a first integrated element coupled to the substrate, and a second integrated element coupled to the first integrated element. A portion of the second integrated element hangs over the first integrated element. The second integrated element is configured to be coupled to the substrate. The second integrated element includes a front side and a back side. The front side of the second integrated element faces the substrate.

Description

Technical Field

[0001] This patent application claims priority and benefit to non-provisional application No. 17 / 375,931 filed on July 14, 2021, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as fully set forth herein in their entirety and for all applicable purposes.

[0002] Various features relate to packages with integrated components. Prior Technology

[0003] A package may include a substrate and integrated components. These components are coupled together to provide a package capable of performing various electrical functions. How the integrated components and the substrate are coupled together affects the overall performance of the package. There has always been a need to provide packages with better performance and reduce the overall size of the package. Summary of the Invention

[0004] Various features relate to packages with integrated components.

[0005] One example provides a package including: a substrate, a first integrated element coupled to the substrate, and a second integrated element coupled to the first integrated element. A portion of the second integrated element hangs over the first integrated element. The second integrated element is configured to be coupled to the substrate. The second integrated element includes a front side and a back side. The front side of the second integrated element faces the substrate.

[0006] Another example provides an apparatus comprising: a substrate, a first integrated element coupled to the substrate, and a second integrated element coupled to the first integrated element. A portion of the second integrated element hangs over the first integrated element. The second integrated element is configured to be coupled to the substrate. The second integrated element includes a front side and a back side. The front side of the second integrated element faces the substrate.

[0007] Another example provides a method for manufacturing a package. The method provides a substrate. The method couples a first integrated element to the substrate. The method couples a second integrated element to the first integrated element such that a portion of the second integrated element hangs over the first integrated element. The second integrated element is configured to be coupled to the substrate. The second integrated element includes a front side and a back side. The front side of the second integrated element faces the substrate. Simple Explanation of the Diagram

[0008] In understanding the detailed description elaborated below in conjunction with the drawings, the various features, essences and advantages will become apparent, in the drawings, similar component symbols are always marked accordingly.

[0009] 1 illustrates a cross-sectional cross-sectional view of a package including an overhanging stacked integrated element.

[0010] 2 illustrates a cross-sectional cross-sectional view of a package including an overhanging stacked integrated element.

[0011] 3 illustrates a cross-sectional cross-sectional view of a package including an overhanging stacked integrated element.

[0012] 4 illustrates a cross-sectional cross-sectional view of a package including an overhanging stacked integrated element.

[0013] 5 illustrates a cross-sectional cross-sectional view of a package including an overhanging stacked integrated element.

[0014] Figure 6 illustrates a cross-sectional cross-sectional view of a package including an overhanging stacked integrated element.

[0015] Figures 7A-7B illustrate an exemplary process for fabricating a package having a stacked integrated element containing an overhang.

[0016] Figures 8A-8B illustrate an exemplary process for fabricating a package having a stacked integral element containing an overhang.

[0017] Figures 9A-9B illustrate an exemplary process for fabricating a package having a stacked integrated element containing an overhang.

[0018] 10 illustrates an exemplary flowchart of a method for fabricating a package having a stacked integrated element containing an overhang.

[0019] Figures 11A-11B illustrate an exemplary process for fabricating a substrate.

[0020] Figure 12 illustrates an exemplary flowchart of a method for fabricating a substrate.

[0021] Figure 13 illustrates various electronic devices that can integrate the chips, electronic circuits, integrated components, integrated passive components (IPDs), passive components, packages, and / or component packages described herein. Implementation

[0022] In the following description, specific details are provided to offer a thorough understanding of the various forms of this application. However, those skilled in the art will understand that these forms can be practiced without such specific details. For example, circuits may be illustrated using block diagrams to avoid obscuring the forms in unnecessary detail. In other instances, well-known circuits, structures, and techniques may not be illustrated in detail to avoid obscuring the forms of this application.

[0023] This application describes a package including a substrate, a first integrated element coupled to the substrate, and a second integrated element coupled to the first integrated element. A portion of the second integrated element hangs over the first integrated element. The second integrated element is configured to be coupled to the substrate. The second integrated element includes a front side and a back side. The front side of the second integrated element faces the substrate. The second integrated element is coupled to the substrate via at least one solder interconnect, at least one solder interconnect, and / or an intermediary. This package can bypass the use of wire bonding, which helps reduce the overall package size and improve package performance by reducing the interconnect length between integrated elements. A package configuration that includes placing one integrated element on top of another integrated element can also reduce package size and / or footprint while still providing improved package performance. An exemplary package including stacked integrated components with overhangs.

[0024] Figure 1 illustrates a cross-sectional view of a package 100 including stacked integrated components with overhangs. The package 100 includes a substrate 102, integrated components 104 and 106, and an encapsulation layer 108. Integrated component 104 may be a first integrated component. Integrated component 106 may be a second integrated component. The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder mask layer 126. A plurality of solder interconnects 130 may be coupled to the substrate 102.

[0025] Integrated element 104 is coupled to substrate 102 via a plurality of solder interconnects 140. Integrated element 106 is located on integrated element 104. Integrated element 106 may be coupled to integrated element 104 via adhesive (not shown). A portion 180 of integrated element 106 may hang over integrated element 104. At least one solder pillar interconnect 160 may be coupled to the front side of substrate 102 and portion 180 of integrated element 106. The at least one solder pillar interconnect 160 may be coupled to the plurality of interconnects 122 via at least one solder interconnect (not shown). Integrated element 106 may be coupled to substrate 102 via at least one solder pillar interconnect 160. At least one solder pillar interconnect 160 may be located between substrate 102 and portion 180 of integrated element 106. Integrated element 106 may be configured to be electrically coupled to integrated element 104 via at least one solder pillar interconnect 160, a plurality of interconnects 122, and / or a plurality of solder interconnects 140. For example, an electrical path for at least one signal between integrated element 104 and integrated element 106 may include at least one solder pad interconnect 160, at least one interconnect from a plurality of interconnects 122, and / or at least one solder interconnect from a plurality of solder interconnects 140. In an example where there is a solder interconnect between the at least one solder pad interconnect 160 and the plurality of interconnects 122, the electrical path may also include a solder interconnect between the at least one solder pad interconnect 160 and the plurality of interconnects 122.

[0026] Integrated element 104 may include a front side and a back side. Similarly, integrated element 106 may include a front side and a back side. The front side of integrated element 104 may face substrate 102. The back side of integrated element may include the die substrate (e.g., silicon) side of integrated element. The front side of integrated element 106 may face the back side of integrated element 104 and / or substrate 102. For example, the front side of a portion 180 of integrated element 106 may face substrate 102. The front side of integrated element 106 may be coupled to the back side of integrated element 104 (e.g., mechanically coupled via adhesive).

[0027] Encapsulation layer 108 may be located over substrate 102, integrated component 104, and integrated component 106. Encapsulation layer 108 may at least partially encapsulate integrated component 104, integrated component 106, and at least one solder post interconnect 160. Encapsulation layer 108 may include a molding compound, resin, and / or epoxy resin. Encapsulation layer 108 may be a component for encapsulation. Encapsulation layer 108 may be provided via compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0028] The configuration of package 100 helps to bypass the use of wire bonds. Bypassing the use of wire bonds helps to reduce the overall size of package 100 and helps to improve the performance of package 100 by reducing the interconnect length between integrated components (e.g., 104, 106). Since the front side of integrated component 106 faces the substrate 102, there is a shorter and more direct electrical path between substrate 102 and integrated component 106, which helps to improve the signal speed between integrated components. Packages using wire bonds may require more space between the integrated components and the edges of the package to accommodate the placement of the wire bonds. Since no wire bonds are required in package 100, the edges of package 100 can be closer to the edges of integrated components (e.g., 104, 106), which helps to reduce the overall form factor of package 100. The same benefits and advantages can be found for other packages described in this application.

[0029] Different implementations can have packages with different configurations of integrated components. Figure 2 illustrates a package 200 including stacked integrated components with overhangs. Package 200 is similar to package 100 and includes similar components, identical components, and / or similar arrangements as package 100. Therefore, the description of package 100 can be applied to package 200. Figure 2 illustrates that package 200 includes at least one pillar interconnect 160 and at least one solder interconnect 260. The at least one solder interconnect 260 is coupled to integrated component 106 and the at least one pillar interconnect 160. The at least one solder interconnect 260 may be coupled to the front side of a portion 180 of integrated component 106. The at least one pillar interconnect 160 may be coupled to substrate 102. In some implementations, the at least one pillar interconnect 160 may be considered part of substrate 102. Integrated component 106 may be coupled to substrate 102 via the at least one solder interconnect 260 and the at least one pillar interconnect 160. The at least one solder interconnect 260 and the at least one solder pillar interconnect 160 may be located between the substrate 102 and a portion 180 of the integrated element 106. The integrated element 106 may be configured to be electrically coupled to the integrated element 104 via the at least one solder interconnect 260, the at least one solder pillar interconnect 160, the plurality of interconnects 122, and / or the plurality of solder interconnects 140. For example, an electrical path for at least one signal between the integrated element 104 and the integrated element 106 may include at least one solder interconnect 260, at least one solder pillar interconnect 160, at least one interconnect from the plurality of interconnects 122, and / or at least one solder interconnect from the plurality of solder interconnects 140.

[0030] Figure 3 illustrates a package 300 including stacked integrated components with overhangs. Package 300 is similar to package 100 and includes similar components, identical components, and / or similar arrangements as package 100. Therefore, the description of package 100 can be applied to package 300. Figure 3 illustrates that package 300 includes an intermediary 302, at least one solder interconnect 260, and at least one solder interconnect 360. The at least one solder interconnect 260 is coupled to integrated component 106 and intermediary 302. The at least one solder interconnect 260 may be coupled to the front side of a portion 180 of integrated component 106. The at least one solder interconnect 360 may be coupled to substrate 102 and intermediary 302. Integrated component 106 may be coupled to substrate 102 via the at least one solder interconnect 260, intermediary 302, and the at least one solder interconnect 360. Intermediary 302 may be a substrate. The intermediate 302 includes at least one dielectric layer 320 and at least one interconnect 322 (e.g., an intermediate interconnect). The at least one solder interconnect 260, the intermediate 302, and / or the at least one solder interconnect 360 may be located between the substrate 102 and a portion 180 of the integrated element 106.

[0031] Integrated element 106 may be configured to be electrically coupled to integrated element 104 via the at least one solder interconnect 260, intermediary 302, the at least one solder interconnect 360, the plurality of interconnects 122, and / or the plurality of solder interconnects 140. For example, an electrical path for at least one signal between integrated element 104 and integrated element 106 may include at least one solder interconnect 260, at least one interconnect 322, at least one solder interconnect 360, at least one interconnect from the plurality of interconnects 122, and / or at least one solder interconnect from the plurality of solder interconnects 140.

[0032] Figures 1-3 illustrate that at least one solder post interconnect 160, at least one solder interconnect 260, intermediary 302, and / or at least one solder interconnect 360 may be located between the substrate 102 and the portion 180 of the integrated element 106 that is overhanging the integrated element 104.

[0033] Different implementations may include different numbers of integrated elements. For example, a package may include more than one integrated element that hangs over one or more integrated elements.

[0034] Figure 4 illustrates a package 400 including stacked integrated components with overhangs. Package 400 is similar to package 100 and includes similar components, identical components, and / or similar arrangements as package 100. Therefore, the description of package 100 can be applied to package 400. Figure 4 illustrates two integrated components overhanging the integrated components. Figure 4 illustrates that package 400 includes a substrate 102, integrated component 104 (e.g., a first integrated component), integrated component 106 (e.g., a second integrated component), integrated component 406 (e.g., a third integrated component), encapsulation layer 108, at least one solder interconnect 160 (e.g., at least one first solder interconnect), and at least one solder interconnect 460 (e.g., at least one second solder interconnect).

[0035] Integrated element 406 is located on integrated element 104. Integrated element 406 can be coupled to integrated element 104 via an adhesive (not shown). A portion 480 of integrated element 406 can hang over integrated element 104. The front side of integrated element 406 may face the back side of integrated element 104 and / or substrate 102. For example, the front side of portion 480 of integrated element 406 may face substrate 102. The front side of integrated element 406 may be coupled to the back side of integrated element 104 (e.g., mechanically coupled via adhesive).

[0036] At least one solder pad interconnect 460 may be coupled to the front side of a portion 480 of the substrate 102 and the integrated element 406. The at least one solder pad interconnect 460 may be coupled to the plurality of interconnects 122 via at least one solder interconnect (not shown). The integrated element 406 may be coupled to the substrate 102 via at least one solder pad interconnect 460. The integrated element 406 may be configured to be electrically coupled to the integrated element 104 via at least one solder pad interconnect 460, the plurality of interconnects 122, and / or the plurality of solder interconnects 140. For example, an electrical path for at least one signal between the integrated element 104 and the integrated element 406 may include at least one solder pad interconnect 460, at least one interconnect from the plurality of interconnects 122, and / or at least one solder interconnect from the plurality of solder interconnects 140. In the example where there is a solder interconnect between the at least one solder pad interconnect 460 and the plurality of interconnects 122, the electrical path may also include a solder interconnect between the at least one solder pad interconnect 460 and the plurality of interconnects 122.

[0037] The portion 480 of the integrated element 406 that hangs over the integrated element 104 may have a different size and / or length than the portion 180 of the integrated element 106 that hangs over the integrated element 104. Different implementations may have similar or different overhangs for different integrated elements. Note that the at least one solder pad interconnect 160 may originate from a plurality of solder pad interconnects (e.g., rows of solder pad interconnects) coupled between the integrated element 106 and the substrate 102. Similarly, the at least one solder pad interconnect 460 may originate from a plurality of solder pad interconnects (e.g., rows of solder pad interconnects) coupled between the integrated element 406 and the substrate 102.

[0038] Figure 5 illustrates a package 500 including stacked integrated components with overhangs. Package 500 is similar to package 200 and / or 400 and includes components similar to, identical to, and / or arranged similarly to those in package 200 and / or 400. Therefore, the descriptions of packages 200 and 400 can be applied to package 500. Figure 5 illustrates two integrated components overhanging another integrated component. Figure 5 illustrates that package 500 includes a substrate 102, integrated component 104, integrated component 106, integrated component 406, encapsulation layer 108, at least one solder interconnect 160 (e.g., at least one first solder interconnect), at least one solder interconnect 460 (e.g., at least one second solder interconnect), at least one solder interconnect 260 (e.g., at least one first solder interconnect), and at least one solder interconnect 560 (e.g., at least one second solder interconnect).

[0039] A portion 480 of integrated element 406 may hang above integrated element 104. The at least one solder interconnect 560 is coupled to integrated element 406 and the at least one pillar interconnect 460. The at least one solder interconnect 560 may be coupled to the front side of the portion 480 of integrated element 406. The at least one pillar interconnect 460 may be coupled to substrate 102. In some implementations, the at least one pillar interconnect 460 may be considered part of substrate 102. Integrated element 406 may be coupled to substrate 102 via the at least one solder interconnect 560 and the at least one pillar interconnect 460. Integrated element 406 may be configured to be electrically coupled to integrated element 104 via the at least one solder interconnect 560, the at least one pillar interconnect 460, the plurality of interconnects 122, and / or the plurality of solder interconnects 140. For example, an electrical path for at least one signal between integrated element 104 and integrated element 406 may include at least one solder interconnect 560, at least one solder post interconnect 460, at least one interconnect from a plurality of interconnects 122, and / or at least one solder interconnect from a plurality of solder interconnects 140.

[0040] Note that the at least one solder interconnect 160 and the at least one solder interconnect 260 may originate from a plurality of solder interconnects (e.g., rows of solder interconnects) and a plurality of solder interconnects (e.g., rows of solder interconnects) coupled between the integrated element 106 and the substrate 102. Similarly, the at least one solder interconnect 460 and the at least one solder interconnect 560 may originate from a plurality of solder interconnects (e.g., rows of solder interconnects) and a plurality of solder interconnects (e.g., rows of solder interconnects) coupled between the integrated element 406 and the substrate 102.

[0041] Figure 6 illustrates a package 600 including stacked integrated components with overhangs. Package 600 is similar to packages 300 and / or 400 and includes components similar to, identical to, and / or arranged similarly to those in packages 300 and / or 400. Therefore, the descriptions of packages 300 and 400 can be applied to package 600. Figure 6 illustrates two integrated components overhanging another integrated component. Figure 6 illustrates that package 600 includes a substrate 102, integrated components 104, 106, 406, an encapsulation layer 108, an intermediary 302 (e.g., a first intermediary), an intermediary 602 (e.g., a second intermediary), at least one solder interconnect 260, at least one solder interconnect 360, at least one solder interconnect 660, and at least one solder interconnect 670.

[0042] A portion 480 of integrated element 406 may hang above integrated element 104. At least one solder interconnect 670 is coupled to integrated element 406 and intermediary 602. The at least one solder interconnect 670 may be coupled to the front side of portion 480 of integrated element 406. The at least one solder interconnect 660 may be coupled to substrate 102 and intermediary 602. Integrated element 406 may be coupled to substrate 102 via the at least one solder interconnect 670, intermediary 602, and the at least one solder interconnect 660. Intermediary 602 may be a substrate. Intermediary 602 includes at least one dielectric layer 620 and at least one interconnect 622 (e.g., intermediary interconnect). Intermediary 602 may be similar to intermediary 302.

[0043] Integrated element 406 may be configured to be electrically coupled to integrated element 104 via the at least one solder interconnect 670, intermediary 602, the at least one solder interconnect 660, the plurality of interconnects 122, and / or the plurality of solder interconnects 140. For example, an electrical path for at least one signal between integrated element 104 and integrated element 406 may include at least one solder interconnect 670, at least one interconnect 622, at least one solder interconnect 660, at least one interconnect from the plurality of interconnects 122, and / or at least one solder interconnect from the plurality of solder interconnects 140.

[0044] Note that the at least one intermediary 302, the at least one solder interconnect 260, and the at least one solder interconnect 360 may originate from a plurality of intermediaries (e.g., rows of intermediaries) and a plurality of solder interconnects (e.g., rows of solder interconnects) coupled between the integrated element 106 and the substrate 102. Similarly, the at least one intermediary 602, the at least one solder interconnect 670, and the at least one solder interconnect 660 may originate from a plurality of intermediaries (e.g., rows of intermediaries) and a plurality of solder interconnects (e.g., rows of solder interconnects) coupled between the integrated element 406 and the substrate 102.

[0045] Note that the orientation of intermediary 302 and / or intermediary 602 shown in this case is exemplary. Intermediary 302 and / or intermediary 602 may be oriented in different ways. Intermediary 302 and / or intermediary 602 may include a substrate. Intermediary 302 and / or intermediary 602 may be manufactured using the process described in Figures 11A-11B. Figures 4-6 illustrate that at least one solder interconnect 160, at least one solder interconnect 260, intermediary 302, and / or at least one solder interconnect 360 may be located between substrate 102 and a portion 180 of integrated element 106 overhanging above integrated element 104. Figures 4-6 also illustrate that at least one solder interconnect 460, at least one solder interconnect 560, intermediary 602, and / or at least one solder interconnect 660 may be located between substrate 102 and a portion 480 of integrated element 406 overhanging above integrated element 104. Note that a package may include integrated components coupled to a substrate using different combinations of pillar interconnects, solder interconnects, and / or intermediaries. For example, one integrated component may be coupled to the substrate via a pillar interconnect, while another integrated component may be coupled to the substrate via an intermediary. Figures 1-6 illustrate examples of integrated components stacked on top of each other, wherein one or more integrated components (e.g., 106, 406) are coupled (e.g., mechanically, electrically) to a substrate (e.g., 102) via at least one non-leaded connection. Examples of non-leaded connections include pillar interconnects, solder interconnects, and / or intermediaries. Non-leaded connections provide at least one electrical path between the integrated component and the substrate. Non-leaded connections may also provide structural support for portions of an integrated component that overhang another integrated component.

[0046] Integrated components (e.g., 104, 106, 406) may include dies (e.g., semiconductor bare dies). Integrated components may include power management integrated circuits (PMICs). The integrated component may include an application processor. The integrated component may include a modem. Integrated components may include radio frequency (RF) components, passive components, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated components, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated components, silicon (Si)-based integrated components, silicon carbide (SiC)-based integrated components, memory, power management processors, and / or combinations thereof. Integrated components (e.g., 104, 106, 406) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.).

[0047] In some implementations, integrated element 104 (e.g., the first integrated element) may include a processor and / or a modem. In some implementations, integrated element 106 (e.g., the second integrated element) and / or integrated element 406 (e.g., the third integrated element) may include memory. Integrated element 106 and integrated element 406 may be planar with each other. Integrated element 106 and integrated element 406 may have similar or different thicknesses.

[0048] Various packages have been described; now, several methods for manufacturing packages will be described below. Exemplary process for manufacturing a package including stacked integrated components with overhangs.

[0049] In some implementations, manufacturing a package includes several procedures. Figures 7A-7B illustrate exemplary procedures for providing or manufacturing a package. In some implementations, the procedures of Figures 7A-7B can be used to provide or manufacture the package 100 of Figure 1. However, the procedures of Figures 7A-7B can be used to manufacture any package (e.g., 400) described in this case.

[0050] It should be noted that the processes in Figures 7A-7B can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this application.

[0051] As shown in Figure 7A, stage 1 illustrates the state after substrate 102 has been provided. Substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder mask layer 126. Different implementations may use different substrates with different numbers of metal layers. The substrate may include a coreless substrate, a cored substrate, or an embedded wire substrate (ETS). Figures 11A-11B illustrate and describe examples of substrate fabrication.

[0052] Phase 2 illustrates the state after at least one bond interconnect 160 has been formed on substrate 102. The at least one bond interconnect 160 can be formed using a plating process. The at least one bond interconnect 160 can be coupled to at least one interconnect from a plurality of interconnects 122. Note that in some implementations, the at least one bond interconnect 160 may be provided together with substrate 102 when substrate 102 is provided in Phase 1. In some implementations, the at least one bond interconnect 160 may be considered part of substrate 102.

[0053] Phase 3 illustrates the state after the integrated component 104 (e.g., the first integrated component) is coupled to the substrate 102. The integrated component 104 may be coupled to the substrate 102 via a plurality of solder interconnects 140. A solder reflow process can be used to couple the integrated component 104 to the substrate 102.

[0054] Phase 4 illustrates the state after integrating element 106 (e.g., a second integrating element) is coupled to integrating element 104, such that a portion (e.g., 180) of integrating element 106 hangs over integrating element 104. Adhesive may be used to couple integrating element 106 to integrating element 104. For example, the front side of integrating element 106 may be coupled to the back side of integrating element 104 via adhesive. Integrating element 106 may be coupled to substrate 102 via at least one solder post interconnect 160. A solder reflow process may be used to couple integrating element 106 to at least one solder post interconnect 160, which may include the use of solder interconnects.

[0055] In some implementations, integrated element 106 may include at least one solder pillar interconnect 160. That is, in some implementations, the at least one solder pillar interconnect 160 may be formed and / or coupled to integrated element 106 before being coupled to substrate 102. In such examples, it may not be necessary to form at least one solder pillar interconnect 160 (in stage 2). A solder reflow process may be used to couple at least one solder pillar interconnect 160 (e.g., of integrated element 106) to substrate 102. In such examples, at least one solder interconnect may be coupled to at least one solder pillar interconnect 160 and at least one interconnect from a plurality of interconnects 122. Different implementations may couple different integrated elements to integrated element 104 and / or substrate 102. For example, integrated element 406 may be coupled to integrated element 104.

[0056] As illustrated in Figure 7B, stage 5 illustrates the state after an encapsulation layer 108 has been provided (e.g., formed) on the substrate 102 and the integrated components (e.g., 104, 106). The encapsulation layer 108 may encapsulate the integrated components and / or elements. The encapsulation layer 108 may include a molding compound, resin, and / or epoxy resin. Compression molding, transfer molding, or liquid molding processes may be used to form the encapsulation layer 108. The encapsulation layer 108 may be photoetchable. The encapsulation layer 108 may be a component for encapsulation.

[0057] Phase 6 illustrates the state after a plurality of solder interconnects 130 have been coupled to the substrate 102. A solder reflow process can be used to couple the plurality of solder interconnects 130 to interconnects of a plurality of interconnects 122 from the substrate 102. Phase 6 may illustrate an example of a package 100 including stacked integrated components with overhangs. Exemplary process for manufacturing a package including stacked integrated components with overhangs.

[0058] In some implementations, manufacturing a package includes several procedures. Figures 8A-8B illustrate exemplary procedures for providing or manufacturing a package. In some implementations, the procedures of Figures 8A-8B can be used to provide or manufacture the package 200 of Figure 2. However, the procedures of Figures 8A-8B can be used to manufacture any package (e.g., 500) described in this case.

[0059] It should be noted that the processes in Figures 8A-8B can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this application.

[0060] As shown in Figure 8A, stage 1 illustrates the state after substrate 102 has been provided. Substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder mask layer 126. Different implementations may use different substrates with different numbers of metal layers. The substrate may include a coreless substrate, a cored substrate, or an embedded wire substrate (ETS). Figures 11A-11B illustrate and describe examples of substrate fabrication.

[0061] Phase 2 illustrates the state after at least one bond interconnect 160 has been formed on substrate 102. The at least one bond interconnect 160 can be formed using a plating process. The at least one bond interconnect 160 can be coupled to at least one interconnect from a plurality of interconnects 122. Note that in some implementations, the at least one bond interconnect 160 may be provided together with substrate 102 when substrate 102 is provided in Phase 1. In some implementations, the at least one bond interconnect 160 may be considered part of substrate 102.

[0062] Phase 3 illustrates the state after at least one solder interconnect 260 has been formed on at least one solder pillar interconnect 160. A solder reflow process can be used to couple at least one solder interconnect 260 to at least one solder pillar interconnect 160.

[0063] Phase 4 illustrates the state after the integrated component 104 (e.g., the first integrated component) is coupled to the substrate 102. The integrated component 104 may be coupled to the substrate 102 via a plurality of solder interconnects 140. A solder reflow process can be used to couple the integrated component 104 to the substrate 102.

[0064] As shown in Figure 8B, stage 5 illustrates the state after integrating element 106 (e.g., a second integrating element) is coupled to integrating element 104, such that a portion (e.g., 180) of integrating element 106 hangs over integrating element 104. Adhesive may be used to couple integrating element 106 to integrating element 104. For example, the front side of integrating element 106 may be coupled to the back side of integrating element 104 via adhesive. Integrating element 106 may be coupled to substrate 102 via the at least one solder interconnect 260 and the at least one solder pillar interconnect 160. A solder reflow process may be used to couple integrating element 106 to the at least one solder pillar interconnect 160 via the at least one solder interconnect 260. Different implementations may couple different integrating elements to integrating element 104 and / or substrate 102. For example, integrating element 406 may be coupled to integrating element 104.

[0065] Phase 6 illustrates the state after an encapsulation layer 108 has been provided (e.g., formed) on the substrate 102 and the integrated components. The encapsulation layer 108 may encapsulate the integrated components and / or components. The encapsulation layer 108 may include a molded part, resin, and / or epoxy resin. Compression molding, transfer molding, or liquid molding processes may be used to form the encapsulation layer 108. The encapsulation layer 108 may be photoetchable. The encapsulation layer 108 may be a component used for encapsulation.

[0066] Phase 7 illustrates the state after a plurality of solder interconnects 130 have been coupled to the substrate 102. A solder reflow process can be used to couple the plurality of solder interconnects 130 to interconnects of a plurality of interconnects 122 from the substrate 102. Phase 7 may illustrate an example of a package 200 including stacked integrated components with overhangs. Exemplary process for manufacturing a package including stacked integrated components with overhangs.

[0067] In some implementations, manufacturing a package includes several procedures. Figures 9A-9B illustrate exemplary procedures for providing or manufacturing a package. In some implementations, the procedures of Figures 9A-9B can be used to provide or manufacture the package 300 of Figure 3. However, the procedures of Figures 9A-9B can be used to manufacture any package (e.g., 600) described in this case.

[0068] It should be noted that the processes in Figures 9A-9B can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this application.

[0069] As shown in Figure 9A, stage 1 illustrates the state after substrate 102 has been provided. Substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder mask layer 126. Different implementations may use different substrates with different numbers of metal layers. The substrate may include a coreless substrate, a cored substrate, or an embedded wire substrate (ETS). Figures 11A-11B illustrate and describe examples of substrate fabrication.

[0070] Phase 2 illustrates the state after the integrated component 104 (e.g., the first integrated component) is coupled to the substrate 102. The integrated component 104 may be coupled to the substrate 102 via a plurality of solder interconnects 140. A solder reflow process can be used to couple the integrated component 104 to the substrate 102.

[0071] Phase 3 illustrates the state after the intermediary 302 has been coupled to the substrate 102. The intermediary 302 can be coupled to the substrate 102 via at least one solder interconnect 360. The at least one solder interconnect 360 can be coupled to interconnects from a plurality of interconnects 122. A solder reflow process can be used to couple the intermediary 302 to the substrate 102.

[0072] Phase 4 illustrates the state after at least one solder interconnect 260 has been formed on the intermediary 302. A solder reflow process can be used to couple at least one solder interconnect 260 to the intermediary 302.

[0073] As shown in Figure 9B, stage 5 illustrates the state after integrating element 106 (e.g., a second integrating element) is coupled to integrating element 104, such that a portion (e.g., 180) of integrating element 106 hangs over integrating element 104. Adhesive may be used to couple integrating element 106 to integrating element 104. For example, the front side of integrating element 106 may be coupled to the back side of integrating element 104 via adhesive. Integrating element 106 may be coupled to substrate 102 via intermediary 302. A solder reflow process may be used to couple integrating element 106 to intermediary 302 via at least one solder interconnect 260. Different implementations may couple different integrating elements to integrating element 104 and / or substrate 102. For example, integrating element 406 may be coupled to integrating element 104.

[0074] Phase 6 illustrates the state after an encapsulation layer 108 has been provided (e.g., formed) on the substrate 102 and the integrated components. The encapsulation layer 108 may encapsulate the integrated components and / or components. The encapsulation layer 108 may include a molded part, resin, and / or epoxy resin. Compression molding, transfer molding, or liquid molding processes may be used to form the encapsulation layer 108. The encapsulation layer 108 may be photoetchable. The encapsulation layer 108 may be a component used for encapsulation.

[0075] Phase 7 illustrates the state after a plurality of solder interconnects 130 have been coupled to the substrate 102. A solder reflow process can be used to couple the plurality of solder interconnects 130 to interconnects of a plurality of interconnects 122 from the substrate 102. Phase 7 may illustrate an example of a package 300 including stacked integrated components with overhangs. An exemplary flowchart of a method for manufacturing a package including stacked integrated components with overhangs.

[0076] In some implementations, manufacturing a package including a substrate and stacked integrated components with overhangs comprises several procedures. Figure 10 illustrates an exemplary flowchart of a method 1000 for providing or manufacturing a package. In some implementations, method 1000 of Figure 10 can be used to provide or manufacture the package 100 of Figure 1 described herein. However, method 1000 can be used to provide or manufacture any package described herein (e.g., 200, 300, 400, 500, 600).

[0077] It should be noted that the method of Figure 10 can combine one or more procedures to simplify and / or clarify the method used to provide or manufacture the package. In some implementations, the order of the procedures can be changed or modified.

[0078] This method (at 1005) provides a substrate (e.g., 102). The substrate 102 may be supplied by a vendor or manufactured. The substrate 102 may be manufactured using a process similar to that shown in Figures 11A-11B. However, different implementations may use different processes to manufacture the substrate 102. Examples of processes that may be used to manufacture the substrate 612 include semi-additive process (SAP) and modified semi-additive process (mSAP). The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder mask layer 126. The substrate 102 may include an embedded wire substrate (ETS). In some implementations, at least one dielectric layer 120 may include a prepreg layer. In some implementations, the substrate 102 may include at least one solder post interconnect (e.g., 160). Stage 1 of Figure 7A illustrates and describes an example of providing a substrate.

[0079] This method (at 1010) couples at least one integrated element (e.g., a first integrated element) to a substrate. For example, integrated element 104 is coupled to a first surface (e.g., the top surface) of substrate 102. Integrated element 104 may be coupled to substrate 102 via a plurality of solder interconnects 140. In some implementations, integrated element 104 may be coupled to substrate 102 via a plurality of solder pillar interconnects (not shown) and a plurality of solder interconnects 140. A solder reflow process may be used to couple integrated element 104 to substrate 102 via the plurality of solder interconnects 140. Stage 2 of Figure 7A illustrates and describes an example of coupling at least one integrated element to a substrate.

[0080] The method (at 1015) couples another integrated element to the integrated element. For example, integrated element 106 (e.g., a second integrated element) is coupled to integrated element 104 such that a portion (e.g., 180) of integrated element 106 hangs over integrated element 104. An adhesive may be used to couple integrated element 106 to integrated element 104. For example, the front side of integrated element 106 may be coupled to the back side of integrated element 104 via an adhesive. Integrated element 106 may include at least one solder pillar interconnect 160. Integrated element 106 may be coupled to substrate 102 via at least one solder pillar interconnect 160. A solder reflow process may be used to couple at least one solder pillar interconnect 160 to substrate 102. In such examples, at least one solder interconnect may be coupled to at least one solder pillar interconnect 160 and at least one interconnect from a plurality of interconnects 122. Note that at least one solder pillar interconnect 160 may be a portion of substrate 102 and / or a portion of integrated element 106 before integrated element 106 is coupled to substrate 102. Phase 4 of Figure 7A illustrates and describes an example of coupling integrated components via at least one solder post interconnect.

[0081] In some implementations, the integrated element 106 may be coupled to the substrate 102 via the at least one solder interconnect 260 and the at least one solder pillar interconnect 160. In some implementations, the at least one solder pillar interconnect 160 may be considered part of the integrated element 106. In some implementations, the at least one solder pillar interconnect 160 may be considered part of the substrate 102. A solder reflow process may be used to couple the integrated element 106 to the at least one solder pillar interconnect 160 via the at least one solder interconnect 260. Phase 5 of FIG8B illustrates and describes an example of coupling an integrated element via at least one solder pillar interconnect and at least one solder interconnect.

[0082] In some implementations, the integrated component 106 may be coupled to the substrate 102 via an intermediary 302. A solder reflow process may be used to couple the integrated component 106 to the intermediary 302 via at least one solder interconnect 260. The intermediary 302 may be coupled to the substrate 102 via a solder reflow process. Stage 5 of Figure 9B illustrates and describes an example of coupling an integrated component via at least one intermediary.

[0083] This method (at 1020) forms an encapsulation layer (e.g., 108) on a substrate (e.g., 102). The encapsulation layer 108 may be provided and formed on the substrate 102 and integrated components (e.g., 104, 106). The encapsulation layer 108 may encapsulate integrated components and / or elements. The encapsulation layer 108 may include a molded part, resin, and / or epoxy resin. Compression molding, transfer molding, or liquid molding processes may be used to form the encapsulation layer 108. The encapsulation layer 108 may be photoetchable. The encapsulation layer 108 may be a component for encapsulation. Stage 5 of Figure 7B illustrates and describes an example of forming an encapsulation layer.

[0084] This method (at 1025) couples a plurality of solder interconnects (e.g., 130) to a second surface of a substrate (e.g., 102). The plurality of solder interconnects 130 can be coupled to an interconnect (e.g., 122) located on the second surface of at least one dielectric layer 120. A solder reflow process can be used to couple the plurality of solder interconnects 130 to the substrate 102. Stage 6 of Figure 7B illustrates and describes an example of coupling solder interconnects to a substrate.

[0085] The package described in this case (e.g., 100) can be manufactured one at a time, or it can be manufactured together (as part of one or more wafers) and then diced into individual packages. Exemplary process for manufacturing a substrate

[0086] In some implementations, manufacturing the substrate includes several processes. Figures 11A-11B illustrate exemplary processes for providing or manufacturing the substrate. In some implementations, the processes of Figures 11A-11B can be used to provide or manufacture the substrate 102 of Figure 1. However, the processes of Figures 11A-11B can be used to manufacture any substrate described in this case.

[0087] It should be noted that the processes in Figures 11A-11B can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this application.

[0088] As shown in Figure 11A, stage 1 illustrates the state after a carrier 1100 is provided and a metal layer is formed on the carrier 1100. This metal layer can be patterned to form interconnects 1102. Plating and etching processes can be used to form the metal layer and the interconnects. In some implementations, the carrier 1100 may be provided with a metal layer that is patterned to form the interconnects 1102.

[0089] Stage 2 illustrates the state after the dielectric layer 1120 is formed over the carrier 1100 and interconnect 1102. Deposition and / or lamination processes can be used to form the dielectric layer 1120. The dielectric layer 1120 may include polyimide. However, different implementations may use different materials for the dielectric layer.

[0090] Stage 3 illustrates the state after a plurality of cavities 1110 have been formed in the dielectric layer 1120. The plurality of cavities 1110 can be formed using an etching process (e.g., a photolithography process) or a laser process.

[0091] Stage 4 illustrates the state after interconnects 1112 are formed in and on dielectric layer 1120 (including in and on the plurality of cavities 1110). For example, vias, pads, and / or traces may be formed. Plating processes may be used to form the interconnects.

[0092] Stage 5 illustrates the state after another dielectric layer 1122 is formed on top of dielectric layer 1120. Deposition and / or lamination processes can be used to form dielectric layer 1122. Dielectric layer 1122 can be made of the same material as dielectric layer 1120. However, different implementations may use different materials for the dielectric layer.

[0093] As shown in Figure 11B, stage 6 illustrates the state after a plurality of cavities 1130 have been formed in the dielectric layer 1122. The cavities 1130 can be formed using an etching process or a laser process.

[0094] Stage 7 illustrates the state after interconnects 1114 are formed in and on dielectric layer 1122 (including in and on the plurality of cavities 1130). For example, vias, pads, and / or traces may be formed. Plating processes may be used to form the interconnects.

[0095] Note that stages 5 to 7 can be repeatedly performed to form additional metal layers and additional dielectric layers. Some or all of interconnects 1102, 1112, and / or 1114 can define a plurality of interconnects 122 of substrate 102. Dielectric layers 1120 and 1122 can be represented by at least one dielectric layer 120.

[0096] Phase 8 illustrates the state after the carrier 1100 is decoupled from the dielectric layer 120 (e.g., removed, ground away) to leave the substrate 102 comprising at least one dielectric layer 120 and a plurality of interconnects 122.

[0097] Stage 9 illustrates the state after solder mask 124 and solder mask 126 are formed on substrate 102. A deposition process can be used to form solder mask 124 and solder mask 126. In some implementations, a solder mask layer may not be formed or may be formed on at least one dielectric layer 120.

[0098] Different implementations may use different processes to form the metal layers. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form the metal layers. For example, sputtering, spraying, and / or plating processes may be used to form the metal layers. Exemplary flowchart of a method for manufacturing a substrate

[0099] In some implementations, manufacturing the substrate includes several procedures. Figure 12 illustrates an exemplary flowchart of a method 1200 for providing or manufacturing a substrate. In some implementations, the method 1200 of Figure 12 can be used to provide or manufacture the substrate(s) of Figure 1. For example, the method of Figure 12 can be used to manufacture substrate 102.

[0100] It should be noted that method 1200 of Figure 12 can combine one or more procedures to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the procedures can be changed or modified.

[0101] The method (at 1205) provides a carrier 1100. Different implementations may use different materials for the carrier. The carrier may include a substrate, glass, quartz, and / or carrier strips. Figure 11A illustrates and describes an example of the carrier provided in stage 1.

[0102] The method (at 1210) forms a metal layer on a carrier 1100. This metal layer can be patterned to form interconnects. A plating process can be used to form the metal layer and the interconnects. In some implementations, the carrier may include the metal layer. The metal layer on the carrier can be patterned to form interconnects (e.g., 1102). Stage 1 of Figure 11A illustrates and describes an example of a metal layer and interconnects formed on a carrier.

[0103] The method (at 1215) forms a dielectric layer 1120 over a carrier 1100 and an interconnect 1102. The dielectric layer can be formed using deposition and / or lamination processes. The dielectric layer 1120 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1110) within the dielectric layer 1120. These cavities can be formed using etching processes (e.g., photolithography) or laser processes. Stages 2-3 of Figure 11A illustrate and depict examples of forming a dielectric layer and creating cavities within it.

[0104] This method (at 1220) forms interconnects within and over the dielectric layer. For example, interconnect 1112 may be formed within and over the dielectric layer 1120. A plating process may be used to form the interconnects. Forming interconnects may include providing a patterned metal layer on and / or within the dielectric layer. Forming interconnects may also include forming interconnects within cavities of the dielectric layer. Stage 4 of Figure 11A illustrates and describes an example of forming interconnects within and over the dielectric layer.

[0105] The method (at 1225) forms a dielectric layer 1122 over a dielectric layer 1120 and an interconnect. The dielectric layer can be formed using deposition and / or lamination processes. The dielectric layer 1122 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 1130) within the dielectric layer 1122. These cavities can be formed using etching or laser processes. Stages 5-6 of Figures 11A-11B illustrate and describe examples of forming a dielectric layer and forming cavities within it.

[0106] This method (at 1230) forms interconnects within and / or on the dielectric layer. For example, interconnect 1114 may be formed. A plating process may be used to form the interconnects. Forming interconnects may include providing a patterned metal layer on and within the dielectric layer. Forming interconnects may also include forming interconnects within cavities of the dielectric layer. Stage 7 of Figure 11B illustrates and describes an example of forming interconnects within and on the dielectric layer.

[0107] This method can form additional dielectric layers and additional interconnects, as described in 1225 and 1230.

[0108] Once all dielectric layers and additional interconnects are formed, the method can decouple (e.g., remove, grind away) the carrier (e.g., 1100) from dielectric layer 1120, leaving the substrate. In some implementations, the method may form one or more solder mask layers (e.g., 124, 126) on the substrate.

[0109] Different implementations may use different processes to form the metal layers. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form the metal layers. For example, sputtering, spraying, and / or plating processes may be used to form the metal layers. Exemplary electronic devices

[0110] Figure 13 illustrates various electronic devices that can integrate any of the aforementioned components, integrated components, integrated circuit (IC) packages, integrated circuit (IC) components, semiconductor components, integrated circuits, dies, intermediaries, packages, stacked packages (PoP), system-in-package (SiP), or systems-on-a-chip (SoC). For example, mobile phone device 1302, laptop device 1304, fixed-location terminal device 1306, wearable device 1308, or motor vehicle 1310 may include components 1300 as described herein. Component 1300 may be any of the components and / or integrated circuit (IC) packages described herein. The devices 1302, 1304, 1306, and 1308 and vehicle 1310 illustrated in Figure 13 are merely exemplary. Other electronic devices may also feature element 1300, including but not limited to the group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablets, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0111] One or more of the elements, programs, features and / or functions illustrated in Figures 1-6, 7A-7B, 8A-8B, 9A-9B, 10, 11A-11B and / or 12-13 may be rearranged and / or combined into a single element, program, feature or function, or may be implemented in several elements, programs, or functions. Additional elements, components, programs and / or functions may also be added without departing from this invention. It should also be noted that Figures 1-6, 7A-7B, 8A-8B, 9A-9B, 10, 11A-11B and / or 12-13 and their corresponding descriptions in this invention are not limited to chips and / or ICs. In some implementations, Figures 1-6, 7A-7B, 8A-8B, 9A-9B, 10, 11A-11B, and / or 12-13 and their corresponding descriptions may be used to manufacture, build, provide, and / or produce components and / or integrated components. In some implementations, components may include dies, integrated components, integrated passive components (IPDs), die packages, integrated circuit (IC) components, component packages, integrated circuit (IC) packages, wafers, semiconductor components, stacked package (PoP) components, thermal components, and / or intermediaries.

[0112] Note that the accompanying drawings in this application may represent actual and / or conceptual representations of various components, elements, objects, devices, packages, integrated components, integrated circuits, and / or transistors. In some instances, the drawings may not be to scale. In some instances, not all elements and / or components are illustrated for clarity. In some instances, the positioning, location, size, and / or shape of the various components and / or elements in the drawings may be exemplary. In some implementations, the various components and / or elements in the drawings may be optional.

[0113] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or manner described herein as "exemplary" need not be construed as superior to or better than other manners in this case. Similarly, the term "manner" does not require that all manners in this case include the features, advantages, or modes of operation discussed. The term "coupling" is used herein to refer to direct or indirect coupling (e.g., mechanical coupling) between two objects. For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered coupled to each other—even if objects A and C are not in direct physical contact with each other. An object coupled to another object may be coupled to a part or all of that object. The term "electrical coupling" may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can be transmitted between the two objects. Electrically coupled objects may or may not have current transmitted between them. The use of the terms "first," "second," "third," and "fourth" (and / or anything higher than fourth) is arbitrary. Any element described can be a first element, a second element, a third element, or a fourth element. For example, an element referred to as a second element can be a first element, a second element, a third element, or a fourth element. The term "enclosure" means that an object can partially or completely enclose another object. The terms "top" and "bottom" are arbitrary. An element located at the top can be situated on top of an element located at the bottom. A top element can be considered a bottom element, and vice versa. As described in this case, a first element situated "above" a second element can mean that the first element is located above or below the second element, depending on how the bottom or top is arbitrarily defined. In another instance, a first element can be situated above (e.g., above) a first surface of a second element, while a third element can be situated above (e.g., below) a second surface of a second element, where the second surface is opposite the first surface. Further note that the term "above," as used in this case in the context of an element being above another element, can be used to mean that an element is on and / or in another element (e.g., on the surface of an element or embedded in an element). Thus, for example, "first element on second element" can mean: (1) the first element is on the second element but does not directly contact the second element; (2) the first element is on the second element (e.g., on the surface of the second element); and / or (3) the first element is in the second element (e.g., embedded in the second element). A first element located "in" the second element can be partially or completely located in the second element. As used in this case, the terms "about "value X" or "approximately value X" mean within ten percent of "value X". For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0114] In some implementations, an interconnect is a component or assembly in a device or package that allows or facilitates an electrical connection between two points, elements, and / or assemblies. In some implementations, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one element or assembly. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or steps to form interconnects. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or plating processes may be used to form interconnects.

[0115] It should also be noted that the various disclosures contained herein can be described as programs illustrated as flowcharts, schematic diagrams, block diagrams, or block diagrams. Although flowcharts can describe operations as a sequential procedure, many operations can be executed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The program terminates when its operations are completed.

[0116] Further examples are described below to facilitate understanding of this case.

[0117] Example 1: A package includes: a substrate; a first integrated element coupled to the substrate; and a second integrated element coupled to the first integrated element. A portion of the second integrated element hangs over the first integrated element. The second integrated element is configured to be coupled to the substrate. The second integrated element includes a front side and a back side. The front side of the second integrated element faces the substrate.

[0118] State 2: Package as in State 1, wherein the second integrated element is interconnected to the substrate via at least one solder post.

[0119] State 3: The package as in State 1, wherein the second integrated element is coupled to the substrate via an intermediary and at least one solder interconnect.

[0120] State 4: Package as in State 3, wherein the intermediary includes a dielectric layer and at least one intermediary interconnect.

[0121] Version 5: Package as in versions 3 to 4, wherein the intermediary is located between the substrate and the portion of the second integrated element that is suspended above the first integrated element.

[0122] State 6: Packages as in states 1 to 5, wherein the second integrated element is coupled to the first integrated element via an adhesive.

[0123] Type 7: Packages as in Types 1 to 6, wherein the first integrated element includes a first front side and a first back side, and wherein the front side of the second integrated element faces the first back side of the first integrated element.

[0124] Type 8: Packages as in Types 1 to 7, wherein the first integrated element is coupled to the substrate via a plurality of solder interconnects.

[0125] Type 9: The package as in Types 1 to 8 further includes a third integrated element coupled to the first integrated element, wherein a portion of the third integrated element hangs over the first integrated element, and wherein the third integrated element is configured to be coupled to the substrate.

[0126] Type 10: Package as in Type 9, wherein the third integrated element is coupled to the substrate via at least one post interconnect, at least one solder interconnect, and / or an intermediary.

[0127] Example 11: An apparatus comprising: a substrate; a first integrated element coupled to the substrate; and a second integrated element coupled to the first integrated element. A portion of the second integrated element hangs over the first integrated element. The second integrated element is configured to be coupled to the substrate. The second integrated element includes a front side and a back side. The front side of the second integrated element faces the substrate.

[0128] State 12: The device as in State 11, wherein: the second integrated element is coupled to the substrate via at least one solder interconnect, at least one solder interconnect, and / or an intermediary.

[0129] State 13: A device as in State 12, wherein: the intermediary includes a dielectric layer and at least one intermediary interconnect.

[0130] Version 14: The device as in versions 12 to 13, wherein the intermediary is located between the substrate and the portion of the second integrated element that is suspended above the first integrated element.

[0131] Version 15: A device as in versions 11 to 14, wherein the second integrated element is coupled to the first integrated element via an adhesive.

[0132] Version 16: The apparatus of versions 11 to 15, wherein the first integrated element includes a first front side and a first back side, and wherein the front side of the second integrated element faces the first back side of the first integrated element.

[0133] State 17: A device as in States 11 to 16, wherein a first integrated element is coupled to a substrate via a plurality of solder interconnects.

[0134] Version 18: The apparatus of versions 11 to 17 further includes a third integrated element coupled to the first integrated element, wherein a portion of the third integrated element hangs over the first integrated element, and wherein the third integrated element is configured to be coupled to a substrate.

[0135] State 19: The device as in State 18, wherein: the third integrated element is coupled to the substrate via at least one solder interconnect, at least one solder interconnect, and / or an intermediary.

[0136] Type 20: Devices of types 11 to 19, wherein the device includes equipment selected from the group comprising: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptops, servers, Internet of Things (IoT) devices, and equipment in motor vehicles.

[0137] Sample 21: A method for manufacturing a package. The method provides a substrate. The method couples a first integrated element to the substrate. The method couples a second integrated element to the first integrated element such that a portion of the second integrated element hangs over the first integrated element. The second integrated element is configured to be coupled to the substrate. The second integrated element includes a front side and a back side. The front side of the second integrated element faces the substrate.

[0138] State 22: The method of State 21, wherein the second integrated element is coupled to the substrate via at least one solder interconnect, at least one solder interconnect, and / or an intermediary.

[0139] State 23: The method of states 21 to 22, wherein the second integrated element is coupled to the first integrated element via an adhesive.

[0140] State 24: The method of states 21 to 23, wherein the method further includes forming an encapsulation layer on the substrate.

[0141] Version 25: The method of versions 21 to 24 further includes the step of coupling a third integrated element to a first integrated element, wherein a portion of the third integrated element hangs over the first integrated element, and wherein the third integrated element is configured to be coupled to a substrate.

[0142] State 26: The method of State 25, wherein the third integrated element is coupled to the substrate via at least one solder interconnect, at least one solder interconnect, and / or an intermediary.

[0143] The various features of this case described herein can be implemented in different systems without departing from this case. It should be noted that the above examples are merely illustrative and should not be construed as limiting this case. The descriptions of the various forms of this case are intended to be illustrative, not to limit the scope of the appended claims. Therefore, the teachings of this case can be readily applied to other types of devices, and many substitutions, modifications, and variations will be readily apparent to those skilled in the art.

[0144] Phase 1: Phase 2 Phase 3 4: Stage 5: Stage 6: Stage 7: Stage 8: Stage 9: Stage 100: Package 102:Substrate 104: Integrated Components 106: Integrated Components 108: Encapsulation layer 120: Dielectric layer 122: Interconnection 124: Solder mask layer 126: Solder mask layer 130: Solder interconnect 140: Solder interconnect 160: Welded column interconnection 180: Part 200: Package 260: Solder interconnect 300: Package 302:Mediator 320: Dielectric layer 322: Interconnection 360: Solder Interconnect 400: Package 406: Integrated Components 460: Welded column interconnection 480: Part 500: Package 560: Solder Interconnect 600: Package 602:Intermediary 620: Dielectric layer 622: Interconnection 660: Solder Interconnect 670: Solder interconnect 1000: Method 1005: Steps 1010: Steps 1015: Steps 1020: Steps 1025: Steps 1100: Carrier 1102: Interconnection 1110: cavity 1112: Interconnection 1114: Interconnection 1120: Dielectric layer 1122: Dielectric layer 1130: cavity 1200: Method 1205: Steps 1210: Steps 1215: Steps 1220: Steps 1225: Steps 1230: Steps 1300: Components 1302: Mobile phone equipment 1304: Laptop devices 1306: Fixed-location terminal equipment 1308: Wearable devices 1310: Motor vehicles Y: axis Z: Axis

[0145] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A packaged integrated component, comprising: One substrate; A first integrated element includes a first front side and a first back side, wherein the first back side includes a first die substrate, and wherein the first front side of the first integrated element is coupled to a first side of the substrate via a first plurality of solder interconnects; an adhesive is coupled to the first back side of the first integrated element. A second integrated element coupled to the first integrated element via the adhesive, wherein a portion of the second integrated element hangs over the first integrated element, wherein the second integrated element is configured to be electrically coupled to the substrate, wherein the second integrated element includes a second front side and a second back side, wherein the second back side includes a second die substrate, and wherein the adhesive directly contacts (i) the first back side of the first integrated element and (ii) the second front side of the second integrated element; an encapsulation layer at least partially encapsulating the first integrated element and the second integrated element, wherein the encapsulation layer is different from the adhesive, wherein the second integrated element is coupled to the substrate via at least one solder interconnect and at least one solder post interconnect, wherein the at least one solder interconnect is independent of the first plurality of solder interconnects, wherein the at least one solder post interconnect is coupled to and contacts the substrate, and wherein the at least one solder interconnect is coupled to and contacts the second integrated element and the at least one solder post interconnect.

2. The packaged integrated element of claim 1 further includes an intermediary (i) located vertically between the second integrated element and the substrate, and (ii) located laterally to the first integrated element, wherein the second integrated element is coupled to the substrate via the intermediary and at least one additional solder interconnect, the at least one additional solder interconnect being independent of the first plurality of solder interconnects.

3. The packaged integrated element as claimed in claim 2, wherein the intermediary includes a dielectric layer and at least one intermediary interconnect.

4. The packaged integrated element as claimed in claim 2, wherein the intermediary is located between the substrate and the portion of the second integrated element that is suspended above the first integrated element.

5. The packaged integrated element as claimed in claim 1, wherein the adhesive comprises a material different from the solder interconnects in the first plurality of solder interconnects, and wherein the second front side of the second integrated element faces the first side of the substrate.

6. The packaged integrated element of claim 1, wherein the second integrated element is coupled to the substrate via at least one additional post interconnect and at least one additional solder interconnect, wherein the at least one additional post interconnect contacts the substrate, wherein the at least one additional solder interconnect contacts the at least one additional post interconnect and the second front side of the second integrated element, and wherein the at least one additional solder interconnect is independent of the first plurality of solder interconnects.

7. The packaged integrated element of claim 1, wherein the first plurality of solder interconnects are coupled to and contact the first front side of the first integrated element and a plurality of interconnects from the substrate, wherein the second integrated element is coupled to the substrate via an intermediary and at least one additional solder interconnect, the at least one additional solder interconnect being independent of the first plurality of solder interconnects, and wherein the at least one additional solder interconnect is coupled to and contact the second front side of the second integrated element.

8. The packaged integrated element of claim 1, further comprising a third integrated element coupled to the first integrated element, wherein a portion of the third integrated element hangs over the first integrated element, and wherein the third integrated element is configured to be electrically coupled to the substrate.

9. The packaged integrated element of claim 8, wherein the third integrated element is coupled to the substrate via (i) at least one additional post interconnect, (ii) at least one additional post interconnect and at least one additional solder interconnect, or (iii) an intermediary and at least one additional solder interconnect, and wherein the at least one additional solder interconnect is independent of the first plurality of solder interconnects.

10. A packaged integrated component, comprising: One substrate; A first integrated element includes a first front side and a first back side, wherein the first back side includes a first die substrate, and wherein the first front side of the first integrated element is coupled to a first side of the substrate via a first plurality of solder interconnects. A second integrated element coupled to the first integrated element, wherein a portion of the second integrated element hangs over the first integrated element, wherein the second integrated element is configured to be electrically coupled to the substrate, wherein the second integrated element includes a second front side and a second back side, wherein the second back side includes a second die substrate, and wherein the first back side of the first integrated element directly contacts the second front side of the second integrated element; wherein the second integrated element is coupled to the substrate via at least one solder interconnect and at least one solder pillar interconnect, wherein the at least one solder interconnect is independent of the first plurality of solder interconnects, wherein the at least one solder pillar interconnect is coupled to and contacts the substrate, and wherein the at least one solder interconnect is coupled to and contacts the second integrated element and the at least one solder pillar interconnect; an encapsulation layer at least partially encapsulates the first integrated element and the second integrated element.

11. The packaged integrated element of claim 10 further includes an intermediary (i) located vertically between the second integrated element and the substrate, and (ii) located laterally to the first integrated element, wherein the intermediary includes a dielectric layer and at least one intermediary interconnect, wherein the second integrated element is electrically coupled to the substrate via the intermediary and at least one additional solder interconnect, the at least one additional solder interconnect being independent of the first plurality of solder interconnects.

12. The packaged integrated element as claimed in claim 11, wherein the intermediary is located between the substrate and the portion of the second integrated element that is suspended above the first integrated element.

13. The packaged integrated element of claim 10, wherein the first back side of the first integrated element contacts the second die substrate of the second front side of the second integrated element.

14. The packaged integrated element of claim 10, wherein the second integrated element is coupled to the substrate via at least one additional post interconnect and at least one additional solder interconnect, wherein the at least one additional post interconnect contacts the substrate, wherein the at least one additional solder interconnect contacts the at least one additional post interconnect and the second front side of the second integrated element, and wherein the at least one additional solder interconnect is independent of the first plurality of solder interconnects.

15. The packaged integrated element of claim 10, wherein the first plurality of solder interconnects are coupled to and contact the first front side of the first integrated element and a plurality of interconnects from the substrate, and wherein the second front side of the second integrated element faces the first side of the substrate.

16. The packaged integrated element of claim 10 further includes a third integrated element coupled to the first integrated element, wherein a portion of the third integrated element hangs over the first integrated element, and wherein the third integrated element is configured to be electrically coupled to the substrate.

17. The packaged integrated element of claim 16, wherein the third integrated element is coupled to the substrate via (i) at least one additional post interconnect, (ii) at least one additional post interconnect and at least one additional solder interconnect, or (iii) an intermediary and at least one additional solder interconnect, and wherein the at least one additional solder interconnect is independent of the first plurality of solder interconnects.

18. The packaged integrated element as claimed in claim 10, wherein the device includes an apparatus selected from at least one of the following: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and an apparatus in a motor vehicle.

19. A method for manufacturing a package having an integrated element, comprising the steps of: providing a substrate; coupling a first integrated element to the substrate via a plurality of solder interconnects, wherein the first integrated element includes a first front side and a first back side, wherein the first back side includes a first die substrate, and wherein the first back side of the first integrated element is coupled to a first side of the substrate via the plurality of solder interconnects; and coupling a second integrated element to the first integrated element such that a portion of the second integrated element hangs over the first integrated element, wherein the second integrated element is coupled to the first integrated element via an adhesive, wherein the second integrated element is configured to be coupled to the substrate, wherein the second integrated element includes a second front side and a second back side, wherein the second back side includes a second die substrate, and wherein the adhesive directly contacts (i) the first back side of the first integrated element and (ii) the second front side of the second integrated element; wherein the second integrated element is coupled to the substrate via (i) at least one solder post interconnect and (ii) at least one solder interconnect. The at least one solder interconnect is independent of the first plurality of solder interconnects, the at least one solder post interconnect is coupled to and contacts the substrate, and the at least one solder interconnect is coupled to and contacts the second integrated element and the at least one solder post interconnect, forming an encapsulation layer that at least partially encapsulates the first integrated element and the second integrated element, wherein the encapsulation layer is different from the adhesive.

20. The method of claim 19, wherein the adhesive contacts the second die substrate on the second front side of the second integrated element, and wherein the adhesive comprises a material different from the solder interconnects in the first plurality of solder interconnects.

21. The method of claim 19, wherein the encapsulation layer is coupled to the substrate.

22. The method of claim 19 further includes the steps of: coupling a third integrated element to the first integrated element, wherein a portion of the third integrated element hangs over the first integrated element, and wherein the third integrated element is configured to be coupled to the substrate.

23. The method of claim 22, wherein the third integrated element is coupled to the substrate via at least one solder interconnect, at least one solder interconnect, and / or an intermediary.

Images