Package comprising a block device with a shield

Abstract

A package includes a substrate, a first integrated device coupled to the substrate, a first bulk device coupled to the substrate, and a second encapsulation layer encapsulating the first integrated device and the first bulk device. The first bulk device includes a first electrical component, a second electrical component, a first encapsulation layer at least partially encapsulating the first electrical component and the second electrical component, and a first metal layer coupled to the first encapsulation layer.

Description

Technical Field

[0001] Cross-references to related applications

[0002] This patent application claims priority and benefit to non-provisional application No. 17 / 383,241, filed July 22, 2021, with the United States Patent and Trademark Office, the entire contents of which are incorporated herein by reference as fully set forth herein in their entirety and for all applicable purposes.

[0003] Various features relate to the packaging of integrated devices. Prior Technology

[0004] A package may include a substrate and an integrated device. These components are coupled together to provide a package capable of performing a variety of electrical functions. Electromagnetic interference (EMI) can affect the overall performance of components and the package. There has always been a need to provide better-performing packages and reduce the impact of EMI within and around the package. Summary of the Invention

[0005] Various features relate to the packaging of integrated devices.

[0006] One example provides a package including a substrate, a first integrated device coupled to the substrate, a first bulk device coupled to the substrate, and a second encapsulation layer that at least partially encapsulates the first integrated device and the first bulk device. The first bulk device includes a first electrical component, a second electrical component, the first encapsulation layer encapsulating the first electrical component and the second electrical component, and a first metal layer coupled to the first encapsulation layer.

[0007] Another example provides an apparatus including a substrate, a first integrated device coupled to the substrate, a first block device coupled to the substrate, and a second encapsulation member configured to at least partially encapsulate the first integrated device and the first block device. The first block device includes a first electrical component, a second electrical component, the first encapsulation member configured to encapsulate the first electrical component and the second electrical component, and a first metal layer coupled to the first encapsulation member.

[0008] Another example provides a method for fabricating a package. The method provides a substrate. The method couples the first integration device to the substrate. The method couples the first lump-like device to the substrate. The first block-like device includes a first electrical element, a second electrical component, a first packing layer encapsulating the first electrical element and the second electrical element, and a first metal layer coupled to the first packing layer. The method forms a second packet sealing layer that at least partially encapsulates the first integral device and the first block-like device. Brief explanation of the schema

[0009] In combination with the accompanying figures to understand the detailed descriptions articulated below, the various features, essences and advantages will become apparent, in the accompanying figures, similar component symbols throughout are always marked accordingly.

[0010] A cross-sectional view of a package including at least one block-like device having a mask is explained in FIG.

[0011] 2 explains a cross-sectional plan view of a package including at least one block-like device having a mask.

[0012] A cross-sectional side-sectional view of a block-like device with a mask is explained in Figure 3 .

[0013] Another cross-sectional side-sectional view of a block-like device with a mask is explained in Figure 4 .

[0014] Figure 5 explains the up-view plan view of a block device with a mask.

[0015] Figure 6 explains the overhead plan view of a block device with a mask.

[0016] A cross-sectional side-sectional view of a block device with a mask and block substrate is explained in Figure 7 .

[0017] Another cross-sectional side-sectional view of a block device with a mask and block substrate is explained in Figure 8 .

[0018] Figure 9 explains the upward plan view of a block device with a mask and block substrate.

[0019] Figure 10 explains the overhead plan view of a block device with a mask and block substrate.

[0020] Figure 11 illustrates a cross-sectional side view of a block-shaped device with a shielding element.

[0021] Figure 12 illustrates another cross-sectional side view of the block-shaped device with a shield.

[0022] Figure 13 illustrates a bottom plan view of a block-shaped device with a shielding element.

[0023] Figure 14 illustrates a top plan view of a block-shaped device with a shielding element.

[0024] Figures 15A–15B illustrate exemplary steps for manufacturing an encapsulation comprising at least one block-shaped device and a shield.

[0025] Figure 16 illustrates an exemplary process for manufacturing an encapsulation comprising at least one block-shaped device and a shield.

[0026] Figures 17A–17B illustrate exemplary processes for manufacturing a block-shaped device with a shield.

[0027] Figures 18A–18C illustrate exemplary processes for manufacturing bulk devices, bulk substrates, and masking components.

[0028] Figure 19 illustrates an exemplary flowchart of a method for manufacturing a block-shaped device with a mask.

[0029] Figures 20A–20B illustrate exemplary processes for manufacturing a substrate.

[0030] Figure 21 illustrates an exemplary flowchart of a method for manufacturing a substrate.

[0031] Figure 22 illustrates various electronic devices that can integrate the chips, electronic circuits, integrated devices, integrated passive devices (IPDs), passive components, packages, and / or device packages described herein. Implementation

[0032] In the following description, specific details are provided to offer a thorough understanding of the various forms of this application. However, those skilled in the art will understand that these forms can be practiced without these specific details. For example, circuits may be shown in block diagrams to avoid obscuring these forms in unnecessary detail. In other cases, well-known circuits, structures, and techniques may not be shown in detail to avoid obscuring these forms of this application.

[0033] This application describes a package including a substrate, a first integrated device coupled to the substrate, a first bulk device coupled to the substrate, and a second encapsulation layer that at least partially encapsulates the first integrated device and the first bulk device. The first bulk device includes a first electrical component (e.g., a first electrical device), a second electrical component (e.g., a second electrical device), the first encapsulation layer encapsulating the first electrical component and the second electrical component, and a first metal layer coupled to the first encapsulation layer, wherein the first metal layer is configured as a shielding element (e.g., an electromagnetic interference (EMI) shielding element) for the first bulk device. Examples of electrical components (e.g., electrical devices) include passive components (e.g., capacitors) and / or integrated devices (e.g., semiconductor dies). The use of a bulk device with a shielding element helps to provide shielding for the bulk device and / or other components (e.g., the first integrated device) within the package. For example, the shielding element of the first bulk device may be configured as a shielding element for the first integrated device, thereby helping to prevent current through the first bulk device from interfering with current through the packaged first integrated device, and / or helping to prevent current through the packaged first integrated device from interfering with current through the first bulk device. In addition, this packaging configuration can help reduce package size and / or footprint while still providing improved packaging performance. Exemplary package including block-shaped device and shielding member

[0034] Figure 1 illustrates a cross-sectional view of a package 100 including at least one bulk device with an electromagnetic interference (EMI) shielding element. The package 100 includes a substrate 102, an integrated device 104, a bulk device 105, a bulk device 107, an encapsulation layer 108, and a metal layer 109. Bulk devices 105 and / or 107 may be examples of shielded bulk devices.

[0035] The substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder resist layer 126. The substrate 102 may include a first surface (e.g., a top surface) and a second surface (e.g., a bottom surface). A plurality of solder interconnects 130 may be coupled to the substrate 102. For example, the plurality of solder interconnects 130 may be coupled to the plurality of interconnects 122.

[0036] Integrated device 104 is coupled to a first surface of substrate 102 via a plurality of solder interconnects 140. Block device 105 may be a first block device. Block device 105 is coupled to the first surface of substrate 102 via a plurality of solder interconnects 151 and / or a plurality of solder interconnects 153. Block device 105 is coupled to a plurality of interconnects 122 via a plurality of solder interconnects 151 and / or a plurality of solder interconnects 153. Block device 107 may be a second block device. Block device 107 is coupled to the first surface of substrate 102 via a plurality of solder interconnects 178. Block device 107 is coupled to a plurality of interconnects 122 via a plurality of solder interconnects 178.

[0037] Encapsulation layer 108 may be a second encapsulation layer. Encapsulation layer 108 may be located on and / or around integrated device 104, block device 105, block device 107 and / or substrate 102. Encapsulation layer 108 may at least partially encapsulate integrated device 104, block device 105 and block device 107. Encapsulation layer 108 may include molding materials, resin and / or epoxy resin. Encapsulation layer 108 may be an encapsulation member (e.g., a second encapsulation member). Encapsulation layer 108 may be provided using compression and transfer molding processes, sheet molding processes, or liquid molding processes.

[0038] Metal layer 109 may be a second metal layer. Metal layer 109 is located on and coupled to the outer surface of encapsulation layer 108. For example, metal layer 109 may be located on the top and / or sides of the outer surface of encapsulation layer 108. Metal layer 109 may be located on the sides of substrate 102. Metal layer 109 may include one or more metal layers. As will be further described below, metal layer 109 may be coupled to the metal layers of bulk device 105 and / or bulk device 107. Metal layer 109 may be configured to be coupled to ground. Metal layer 109 may be configured as an EMI shield (e.g., EMI shielding member) of package 100. For example, metal layer 109 may be configured as a conformal shield of package 100. Metal layer 109 may help prevent external signals from interfering with the current and / or signals traveling inside package 100.

[0039] Block device 105 includes at least two electrical components (e.g., at least two electrical devices). Block device 107 includes at least two electrical components (e.g., at least two electrical devices). Examples of electrical components (e.g., electrical devices) include passive components (e.g., capacitors) and / or integrated devices (e.g., semiconductor chips).

[0040] The block device 105 includes a passive element 150 (e.g., a first capacitor), a passive element 152 (e.g., a second capacitor), an encapsulation layer 154, and a metal layer 156. The passive element 150 may be an example of a first electrical element. The passive element 152 may be an example of a second electrical element. The encapsulation layer 154 may encapsulate the passive elements 150 and 152. The encapsulation layer 154 may be a first encapsulation layer. The encapsulation layer 154 may include a molding compound, resin, and / or epoxy resin. The encapsulation layer 154 may be an encapsulation member (e.g., a first encapsulation member).

[0041] Metal layer 156 may be coupled to encapsulation layer 154. Metal layer 156 may be coupled to a side surface of bulk device 105. Metal layer 156 may be a first metal layer. Metal layer 156 may be configured to be coupled to ground. Metal layer 156 may be configured as an EMI shield (e.g., EMI shielding member) of bulk device 105. Metal layer 156 may be configured as an EMI shield of package 100. Metal layer 156 may provide shielding for passive element 150 and / or passive element 152. Metal layer 156 may also provide shielding for integrated device 104 (and / or any other element in package 100). For example, metal layer 156 may help prevent current traveling through passive element 150 and / or passive element 152 from interfering with current and / or signals traveling through integrated device 104, and vice versa. Metal layer 156 may be configured as a conformal shield of package 100. Metal layer 156 helps prevent external signals from interfering with current and / or signals traveling inside the bulk device 105. Metal layer 156 may be coupled to metal layer 109.

[0042] The bulk device 107 includes a bulk substrate 175, a passive element 170 (e.g., a first capacitor), an integrated device 172, an encapsulation layer 174, and a metal layer 176. The passive element 170 may be an example of a first electrical element. The integrated device 172 (e.g., a semiconductor die) may be an example of a second electrical element. The encapsulation layer 174 may encapsulate the passive element 170 and the integrated device 172. The encapsulation layer 174 may be a third encapsulation layer. The encapsulation layer 174 may include molding materials, resin, and / or epoxy resin. The encapsulation layer 174 may be an encapsulation member (e.g., a third encapsulation member). The encapsulation layer 174 may be located on the bulk substrate 175, the passive element 170, and the integrated device 172.

[0043] The bulk substrate 175 includes at least one dielectric layer 177 and a plurality of interconnects 179 (e.g., bulk substrate interconnects). Different implementations may use different materials for the at least one dielectric layer 177. For example, the at least one dielectric layer 177 may include glass, quartz, and / or a prepreg layer. Passive component 170 is coupled to bulk substrate 175 via a plurality of solder interconnects 171. Integrated device 172 is coupled to bulk substrate 175 via a plurality of solder interconnects 173. Bulk substrate 175 may be configured to at least partially provide EMI shielding. That is, some of the interconnects 179 may be configured as EMI shielding elements. Some of the interconnects 179 may be configured to be coupled to ground. Some of the interconnects 179 may be coupled to metal layer 176. Bulk device 107 is coupled to a plurality of interconnects 122 of substrate 102 via a plurality of solder interconnects 178. A plurality of solder interconnects 178 may be coupled to a plurality of interconnects 179 of a bulk substrate 175.

[0044] Metal layer 176 may be coupled to encapsulation layer 174. Metal layer 176 may be coupled to a side surface of bulk device 107. Metal layer 176 may be coupled to some of the interconnects 179 of a plurality of interconnects 179 of bulk substrate 175. Metal layer 176 may be a first metal layer. Metal layer 176 may be configured to be coupled to ground. Metal layer 176 may be configured as an EMI shielding element (e.g., EMI shielding member) of bulk device 107. Metal layer 176 may be configured as an EMI shielding element of package 100. Metal layer 176 may provide shielding for passive component 170 and / or integrated device 172. Metal layer 176 may also provide shielding for integrated device 104 (and / or any other component in package 100). For example, metal layer 176 may help prevent current traveling through passive component 170 and / or integrated device 172 from interfering with current and / or signals traveling through integrated device 104, and vice versa. Metal layer 176 can be configured as a compartmentalized shielding element for package 100. Metal layer 176 helps prevent external signals from interfering with current and / or signals traveling within the bulk device 107. Metal layer 176 can be coupled to metal layer 109.

[0045] Figure 2 illustrates a cross-sectional plan view of package 100. As shown in Figure 2, package 100 includes an integrated device 104, a bulk device 105, a bulk device 107, a passive element 270, a passive element 272, an encapsulation layer 108, and a metal layer 109. The integrated device 104, bulk device 105, bulk device 107, passive element 270, and passive element 272 are coupled to a substrate 102 (not shown in Figure 2). The encapsulation layer 108 at least partially encapsulates the integrated device 104, bulk device 105, bulk device 107, passive element 270, and passive element 272. The encapsulation layer 108 may be located on the substrate 102, the integrated device 104, bulk device 105, bulk device 107, passive element 270, and / or passive element 272.

[0046] The block device 105 includes passive element 150, passive element 152, passive element 250, passive element 252, encapsulation layer 154, and metal layer 156. Encapsulation layer 154 encapsulates passive element 150, passive element 152, passive element 250, and passive element 252.

[0047] The block device 107 includes a passive element 170 and an integrated device 172, an encapsulation layer 174 and a metal layer 176.

[0048] Metal layer 156 laterally surrounds encapsulation layer 154, passive element 150, passive element 152, passive element 250, and passive element 252. Metal layer 156 can shield passive element 150, passive element 152, passive element 250, and passive element 252 from integrated device 104, bulk device 107, passive element 270, and / or passive element 272. Similarly, metal layer 156 can shield integrated device 104, bulk device 107, passive element 270, and / or passive element 272 from passive element 150, passive element 152, passive element 250, and passive element 252.

[0049] Metal layer 176 laterally surrounds encapsulation layer 174, passive element 170, and integrated device 172. Metal layer 176 can shield passive element 170 and integrated device 172 from integrated device 104, bulk device 105, passive element 270, and / or passive element 272. Similarly, metal layer 176 can shield integrated device 104, bulk device 105, passive element 270, and / or passive element 272 from passive element 170 and / or integrated device 172.

[0050] This configuration of package 100 has several advantages. First, using a block device with EMI shielding helps improve package performance by reducing and / or eliminating interference between components within package 100 and / or interference from components outside package 100. Second, using a block device with EMI shielding helps provide a more compact package because components within package 100 can be placed closer together without necessarily adversely affecting package 100 performance. Third, using a block device with predefined EMI shielding simplifies the manufacturing process during package assembly and fabrication.

[0051] EMI shielding elements (e.g., metal layers 156, 176, 109) can be configured as Faraday cages to provide electrical isolation between different circuit functions within the package. Using pre-applied compartmentalized shielding elements on these block-shaped devices provides excellent shielding without significantly altering the existing layout of the package. EMI shielding elements can be shielding members (e.g., EMI shielding members).

[0052] Note that package 100 may include a different number of block devices, such as one or more block devices. Furthermore, each block device may have a different number of electrical components (e.g., electrical devices, passive components, integrated devices) that are shielded from other components and / or devices within the package. Therefore, the configuration of package 100 shown in this application is merely exemplary.

[0053] Figures 3–6 illustrate various views of the bulk device 105. Figure 3 illustrates a side view of the bulk device 105 including passive element 150, passive element 152, encapsulation layer 154, and metal layer 156. A plurality of solder interconnects 151 are coupled to passive element 150. A plurality of solder interconnects 153 are coupled to passive element 152. In some implementations, the bottom of passive element 150 and / or the bottom of passive element 152 may be aligned with the bottom of encapsulation layer 154. For example, the bottom surface of passive element 150 and / or the bottom surface of passive element 152 may be aligned with the bottom surface of encapsulation layer 154. In some implementations, passive element 150 and / or passive element 152 may protrude from the bottom surface of encapsulation layer 154 such that a portion of the side of passive element 150 and / or a portion of the side of passive element 152 is not covered by encapsulation layer 154. Figure 4 illustrates another side view of the block device 105, which includes passive element 150, passive element 250, encapsulation layer 154, and metal layer 156.

[0054] Figure 5 illustrates a bottom plan view of a block assembly 105 including passive components 150, 152, 250, 252, an encapsulation layer 154, and a metal layer 156. A plurality of solder interconnects are coupled to terminals of passive components 150, 152, 250, and / or 252. Figure 6 illustrates a top plan view of the block assembly 105 including the metal layer 156. The metal layer 156 is located above the surface of the encapsulation layer 154.

[0055] Figures 7–10 illustrate various views of the bulk device 107. Figure 7 illustrates a side view of the bulk device 107 including a passive component 170, an integrated device 172, a bulk substrate 175, an encapsulation layer 174, and a metal layer 176. A plurality of solder interconnects 178 are coupled to the bulk substrate 175. The encapsulation layer 174 is located above the bulk substrate 175, the passive component 170, and the integrated device 172. The metal layer 176 is located above the surface of the encapsulation layer 174. The bulk substrate 175 includes at least one dielectric layer 177 and a plurality of interconnects 179. The plurality of solder interconnects 178 are coupled to some of the interconnects 179. Figure 8 illustrates another side view of the bulk device 107 including the passive component 170, the integrated device 172, the bulk substrate 175, the encapsulation layer 174, and the metal layer 176.

[0056] Figure 9 illustrates a bottom plan view of a bulk device 107 including a passive component 170, an integrated device 172, a bulk substrate 175 (which includes at least one dielectric layer 177 and a plurality of interconnects 179), an encapsulation layer 174, and a metal layer 176. The plurality of solder interconnects are coupled to some of the interconnects in the plurality of interconnects 179. Figure 10 illustrates a top plan view of the bulk device 107 including the metal layer 176. The metal layer 176 is located above the surface of the encapsulation layer 174.

[0057] In some implementations, the bulk device 107 may be implemented without the bulk substrate 175. In some implementations, the bulk device 105 may be implemented with the bulk substrate 175, as described for the bulk device 107.

[0058] Figures 11–14 illustrate various views of the bulk device 1107. The bulk device 1107 can be implemented in any package (e.g., 100). The bulk device 1107 can be similar to bulk device 107. However, the bulk device 1107 does not include a bulk substrate 175. Figure 11 illustrates a side view of the bulk device 1107 including a passive element 170, an integrated device 172, an encapsulation layer 174, and a metal layer 176. A plurality of solder interconnects 171 are coupled to the passive element 170. A plurality of solder interconnects 173 are coupled to the integrated device 172. In some implementations, the passive element 170 and / or the integrated device 172 may protrude from the bottom surface of the encapsulation layer 174 such that a portion of the side of the passive element 170 and / or a portion of the side of the integrated device 172 is not covered by the encapsulation layer 174. In some implementations, the bottom of the passive element 170 and / or the bottom of the integrated devices 172, 152 may be aligned with the bottom of the encapsulation layer 174. For example, the bottom surface of the passive element 170 and / or the bottom surface of the integrated device 172 may be aligned with the bottom surface of the encapsulation layer 174. Figure 12 illustrates another side view of the block device 1107 including the passive element 170, the integrated device 172, the encapsulation layer 174, and the metal layer 176.

[0059] Figure 13 illustrates a bottom plan view of a block device 1107 including a passive component 170, an integrated device 172, an encapsulation layer 174, and a metal layer 176. A plurality of solder interconnects 171 are coupled to terminals of the passive component 170. A plurality of solder interconnects 173 are coupled to the integrated device 172. Figure 14 illustrates a top plan view of the block device 1107 including the metal layer 176. The metal layer 176 is located above the surface of the encapsulation layer 174.

[0060] The integrated device (e.g., 104, 172) may include a die (e.g., a semiconductor bare die). The integrated device may include a power management integrated circuit (PMIC). The integrated device may include an application processor. The integrated device may include a modem. The integrated device may include radio frequency (RF) devices, passive devices, filters, capacitors, inductors, antennas, transmitters, receivers, gallium arsenide (GaAs)-based integrated devices, surface acoustic wave (SAW) filters, bulk acoustic wave (BAW) filters, light-emitting diode (LED) integrated devices, silicon (Si)-based integrated devices, silicon carbide (SiC)-based integrated devices, memory, power management processors, and / or combinations thereof. The integrated device (e.g., 104, 172) may include at least one electronic circuit (e.g., a first electronic circuit, a second electronic circuit, etc.). The integrated device may be an example of an electrical component and / or electrical device.

[0061] Various packages have been described; now, several methods for manufacturing packages will be described below. Exemplary process for manufacturing an encapsulation comprising a block-shaped device and a shield.

[0062] In some implementations, manufacturing a package includes several processes. Figures 15A–15B illustrate exemplary processes for providing or manufacturing a package. In some implementations, the processes of Figures 15A–15B can be used to provide or manufacture the package 100 of Figure 1. However, the processes of Figures 15A–15B can be used to manufacture any package described in this case.

[0063] It should be noted that the processes in Figures 15A–15B can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the package. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this invention.

[0064] As shown in Figure 15A, stage 1 illustrates the state after substrate 102 is provided. Substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder mask layer 126. Different implementations may use different substrates with different numbers of metal layers. The substrate may include a coreless substrate, a cored substrate, or an embedded trace substrate (ETS). Figures 20A–20B illustrate and describe examples of substrate fabrication.

[0065] Phase 2 describes the state after a plurality of solder interconnects 1500 are coupled to substrate 102 (e.g., provided on substrate 102). The plurality of solder interconnects 1500 may be coupled to at least some of the interconnects in a plurality of interconnects 122. The plurality of solder interconnects 1500 may represent a plurality of solder interconnects 140, 151, 153 and / or 178.

[0066] Phase 3 describes the state after integrated device 104, block device 105, and block device 107 are coupled to substrate 102 via a plurality of solder interconnects 1500. Block device 105 can be coupled to substrate 102 via a plurality of solder interconnects 151 and / or 153. Integrated device 104 can be coupled to substrate 102 via a plurality of solder interconnects 140. Block device 107 can be coupled to substrate 102 via a plurality of solder interconnects 178. Different implementations can couple different components and / or devices to substrate 102. Other components and / or devices can be coupled to substrate 102. A solder reflow process can be used to couple integrated device 104, block device 105, and block device 107 to substrate 102.

[0067] Phase 4 describes the state after an encapsulation layer 108 is provided (e.g., formed) on substrate 102. Encapsulation layer 108 may encapsulate block device 105, integrated device 104, and block device 107. Encapsulation layer 108 may encapsulate other devices and / or components coupled to substrate 102. Encapsulation layer 108 may include molding materials, resins, and / or epoxy resins. Compression molding, transfer molding, or liquid molding processes may be used to form encapsulation layer 108. Encapsulation layer 108 may be photoetchable. Encapsulation layer 108 may be an encapsulation member. As shown in Phase 4, encapsulation layer 108 exposes (e.g., is not covered by encapsulation layer 108) the tops of block device 105 and block device 107. In some implementations, the encapsulation layer 108 may be formed such that the encapsulation layer 108 is formed and located on top of and / or around the block device 105 and / or the block device 107.

[0068] As shown in Figure 15B, stage 5 illustrates the state after portions of block device 105 and block device 107 have been removed. A grinding and / or polishing process can remove portions of block device 105 and / or block device 107. In some implementations, the top of metal layer 156 of block device 105 and the top of metal layer 176 of block device 107 can be removed, thereby exposing encapsulation layers 154 and 174. Portions of encapsulation layer 154 and / or encapsulation layer 174 can also be removed. In some implementations, portions of encapsulation layer 108 can also be removed (e.g., when encapsulation layer 108 is present over block device 105 and / or block device 107).

[0069] Phase 6 describes the state after the metal layer 109 is formed on the outer surface of the encapsulation layer 108. The metal layer 109 can be formed and coupled to the encapsulation layer 108 using sputtering and / or electroplating processes. The metal layer 109 can be formed on the top surface of the encapsulation layer 108, the surface of the encapsulation layer 154, the surface of the encapsulation layer 174, the side surfaces of the encapsulation layer 108, and the side surfaces of the substrate 102. The metal layer 109 can be coupled to the metal layer 156 of the bulk device 105. The metal layer 109 can be coupled to the metal layer 176 of the bulk device 107. The metal layer 109 can be configured to be coupled to ground.

[0070] Phase 7 describes the state after the plurality of solder interconnects 130 are coupled to the substrate 102. The plurality of solder interconnects 130 can be coupled to the substrate 102 using a solder reflow process.

[0071] The placement of block devices can be achieved using surface mount technology (SMT) to position the block devices in the appropriate location. An exemplary flowchart of a method for manufacturing an encapsulation comprising a block device and a shield.

[0072] In some implementations, the manufacturing of a package comprising a block device and a mask involves several processes. Figure 16 illustrates an exemplary flowchart of a method 1600 for providing or manufacturing a package. In some implementations, method 1600 of Figure 16 can be used to provide or manufacture the package 100 of Figure 1 described herein. However, method 1600 can be used to provide or manufacture any package (e.g., 100) described herein.

[0073] It should be noted that the method in Figure 16 can combine one or more processes to simplify and / or clarify the method used to provide or manufacture the package. In some implementations, the order of the processes can be changed or modified.

[0074] This method (at 1605) provides a substrate (e.g., 102). Substrate 102 may be supplied by a vendor or manufactured. Substrate 102 can be manufactured using a process similar to that shown in Figures 20A–20B. However, different implementations may use different processes to manufacture substrate 102. Examples of processes that can be used to manufacture substrate 102 include semi-additive manufacturing (SAP) and modified semi-additive manufacturing (mSAP). Substrate 102 includes at least one dielectric layer 120, a plurality of interconnects 122, and a solder mask layer 126. Substrate 102 may include an embedded trace substrate (ETS). In some implementations, at least one dielectric layer 120 may include a prepreg layer. Stage 1 of Figure 15A illustrates and describes an example of providing a substrate.

[0075] This method (at 1610) provides a plurality of solder interconnects (e.g., 1500) on substrate 102. The plurality of solder interconnects 150 may be coupled to at least some of the interconnects in the plurality of interconnects 122. Phase 2 of Figure 15A illustrates and describes an example of providing solder interconnects.

[0076] This method (at 1615) couples components and / or devices to a first surface of substrate 102. For example, integrated device 104 is coupled to the first surface (e.g., the top surface) of substrate 102. Integrated device 104 may be coupled to substrate 102 via a plurality of solder interconnects 140. Block device 105 may be coupled to the first surface of substrate 102 via a plurality of solder interconnects 151 and / or 153. Block device 107 may be coupled to the first surface of substrate 102 via a plurality of solder interconnects 178. A solder reflow process may be used to couple integrated device 104, block device 105, and block device 107 to substrate 102 via a plurality of solder interconnects. Phase 3 of Figure 15A illustrates and describes an example of coupling at least components and / or devices to a substrate.

[0077] This method (at 1620) forms an encapsulation layer (e.g., 168) on a substrate (e.g., 102). The encapsulation layer 108 may be provided and formed on and / or around the substrate 102, integrated device 104, bulk device 105, and bulk device 107. In some implementations, the tops of integrated device 104, bulk device 105, and / or bulk device 107 may be exposed. The encapsulation layer 108 may encapsulate(s) integrated devices,(s) devices, and / or(s) components. The encapsulation layer 108 may include molding materials, resins, and / or epoxy resins. Compression molding, transfer molding, or liquid molding processes may be used to form the encapsulation layer 108. The encapsulation layer 108 may be photoetchable. The encapsulation layer 108 may be an encapsulation member. Phase 4 of Figure 15A illustrates and describes an example of forming an encapsulation layer.

[0078] This method (at 1625) removes portions of bulk device 105 and bulk device 107. A grinding and / or polishing process can remove portions of bulk device 105 and / or bulk device 107. In some implementations, the top of metal layer 156 of bulk device 105 and the top of metal layer 176 of bulk device 107 can be removed, thereby exposing encapsulation layers 154 and 174. Portions of encapsulation layer 154 and / or encapsulation layer 174 can also be removed. In some implementations, portions of encapsulation layer 108 can also be removed (e.g., when encapsulation layer 108 is present over bulk device 105 and / or bulk device 107). Stage 5 of Figure 15B illustrates and describes an example of removing portions of components and / or encapsulation layers via grinding.

[0079] The method (at 1630) forms a metal layer (e.g., 109) on the outer surface of the encapsulation layer 108. The metal layer 109 can be formed and coupled to the encapsulation layer 108 using sputtering and / or electroplating processes. The metal layer 109 can be formed on the top surface of the encapsulation layer 108, the surface of the encapsulation layer 154, the surface of the encapsulation layer 174, the side surfaces of the encapsulation layer 108, and the side surfaces of the substrate 102. The metal layer 109 can be coupled to the metal layer 156 of the bulk device 105. The metal layer 109 can be coupled to the metal layer 176 of the bulk device 107. The metal layer 109 can be configured to be coupled to ground.

[0080] This method (at 1635) couples a plurality of solder interconnects (e.g., 130) to substrate 102. A solder reflow process can be used to couple the plurality of solder interconnects 130 to substrate 102. Stage 7 of Figure 15B illustrates and describes an example of coupling solder interconnects to the substrate.

[0081] The package described in this case (e.g., 100) can be manufactured one at a time, or it can be manufactured together (as part of one or more wafers) and then cut into individual packages.

[0082] Depending on design and component requirements, several block assembly configurations can be used, such as tape-assisted molding, which can be used in conjunction with a carrier. Block devices can be coupled using SMT assembly rules and can be designed to be compatible with tape, physical components, and assembly procedures. The height of the block device may need to be adjusted to account for the target package thickness to allow for electrical connection to external EMI shielding components. Exemplary process for manufacturing a block-shaped device with a masking element

[0083] In some implementations, manufacturing the block device includes several processes. Figures 17A–17B illustrate exemplary processes for providing or manufacturing the block device. In some implementations, the processes of Figures 17A–17B can be used to provide or manufacture the block device 105. However, the processes of Figures 17A–17B can be used to manufacture any block device described in this case.

[0084] It should be noted that the processes in Figures 17A–17B may be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the block-shaped device. In some implementations, the order of the processes may be changed or modified. In some implementations, one or more processes may be substituted or replaced without departing from the scope of this invention.

[0085] As shown in Figure 17A, stage 1 illustrates the state after the tape 1700 is provided. The tape 1700 may include an adhesive. Note that another carrier may be used instead of the tape.

[0086] Phase 2 describes the state after the plurality of passive elements 1710 are mounted and coupled to band 1700. The plurality of passive elements 1710 may represent any passive element described in this application, such as passive elements 150, 152, 250, and / or 252. Note that other elements and / or devices may also be coupled to band 1700. For example, an integrated device (e.g., 104) may be mounted and coupled to band 1700.

[0087] Phase 3 describes the state after the encapsulation layer 154 is formed on the belt 1700. The encapsulation layer 154 can encapsulate the passive component 1710. The encapsulation layer 154 may include molding materials, resin and / or epoxy resin. The encapsulation layer 154 can be formed using compression molding, transfer molding, or liquid molding processes.

[0088] Phase 4 describes the state following cutting and / or slicing the encapsulation layer 154 (which creates a cutting line 1720 (e.g., a cavity)) within the encapsulation layer 154. The cutting line 1720 can be created using a saw and / or a laser. This produces several individual block-shaped devices with an encapsulation layer and several passive elements.

[0089] As shown in Figure 17B, stage 5 illustrates the state after the individual block devices, having an encapsulation layer and several passive elements, are decoupled (e.g., removed) from the belt 1700 and transferred to the carrier 1750. The individual block devices may be placed and coupled to the carrier 1750. Note that the transfer to the carrier may be optional.

[0090] Phase 6 describes the state after a metal layer 156 is formed on the encapsulation layer 154 of the individual bulk device (e.g., on the surface of the encapsulation layer 154). The metal layer 156 can be formed using sputtering and / or electroplating processes.

[0091] Phase 7 describes the state after the decoupling carrier 1750 leaves a plurality of block devices 105, each of which has a plurality of passive elements, an encapsulation layer 154, and a metal layer 156. The metal layer 156 can be configured as an EMI shield. Exemplary process for manufacturing a block-shaped device with a masking element

[0092] In some implementations, manufacturing the block device includes several processes. Figures 18A–18C illustrate exemplary processes for providing or manufacturing the block device. In some implementations, the processes of Figures 18A–18C can be used to provide or manufacture the block device 107. However, the processes of Figures 18A–18C can be used to manufacture any block device described in this case.

[0093] It should be noted that the processes in Figures 18A–18C can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the block-shaped device. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this invention.

[0094] As shown in Figure 18A, stage 1 illustrates the state after the bulk substrate 175 is provided. The bulk substrate 175 may include at least one dielectric layer 177 and a plurality of interconnects 179. Different implementations may use different materials for the at least one dielectric layer 177. For example, the at least one dielectric layer 177 may include a prepreg, glass, and / or quartz. Figures 20A–20B illustrate examples of substrate fabrication that can be used to manufacture the bulk substrate 175.

[0095] Phase 2 describes the state after a plurality of passive components 170 and a plurality of integrated devices 172 have been mounted and coupled to the bulk substrate 175. Note that other components and / or devices may also be coupled to the bulk substrate 175. The plurality of passive components 170 and the plurality of integrated devices 172 may be coupled to the bulk substrate 175 via a plurality of solder interconnects (e.g., 171, 173). A solder reflow process may be used to couple the plurality of passive components 170 and the plurality of integrated devices 172 to the bulk substrate 175.

[0096] Phase 3 describes the state after the encapsulation layer 174 is formed on the bulk substrate 175, the passive component 170, and the integrated device 172. The encapsulation layer 174 encapsulates the passive component 170 and the integrated device 172. The encapsulation layer 174 may include molding materials, resins, and / or epoxy resins. The encapsulation layer 174 can be formed using compression molding, transfer molding, or liquid molding processes.

[0097] Phase 4 explains the state after the bulk substrate 175, a plurality of passive components 170, a plurality of integrated devices 172, and encapsulation layer 174 are coupled to the carrier 1800.

[0098] As shown in Figure 18B, stage 5 describes the state after cutting and / or slicing the encapsulation layer 174 (which creates a cut line 1820 (e.g., a cavity)) in the encapsulation layer 174. The cut line 1820 can be created using a saw and / or a laser. This produces several individual block-shaped devices with an encapsulation layer and several passive elements and / or integrated devices.

[0099] Phase 6 describes the state after the individual block devices, having an encapsulation layer and several passive elements and / or integrated devices, are decoupled (e.g., removed) from carrier 1800 and transferred to carrier 1810. The individual block devices may be placed and coupled to carrier 1810. Note that in some implementations, transfer to another carrier may be optional.

[0100] Phase 7 describes the state after a metal layer 176 is formed on the encapsulation layer 174 of the individual bulk device (e.g., on the surface of the encapsulation layer 174). The metal layer 176 can be formed using sputtering and / or electroplating processes.

[0101] Phase 8 describes the state after the decoupling carrier 1810, leaving a plurality of block devices 107, each block device 107 having a block substrate 175, at least one passive element, at least one integrated device, an encapsulation layer 174, and a metal layer 176. The metal layer 176 may be configured as an EMI shield. At least a portion of the block substrate 175 may be configured as an EMI shield. Exemplary flowchart of a method for manufacturing an encapsulation including a block-shaped device with a shielding element

[0102] In some implementations, manufacturing a block device with a masking element includes several processes. Figure 19 illustrates an exemplary flowchart of a method 1900 for providing or manufacturing a block device. In some implementations, method 1900 of Figure 19 can be used to provide or manufacture the block device 107 of Figure 1 described in this document. Method 1900 will be described with reference to manufacturing block device 107. However, method 1900 can be used to provide or manufacture any block device described in this document (e.g., 105, 107).

[0103] It should be noted that the method of Figure 19 can combine one or more processes to simplify and / or clarify the method for providing or manufacturing the block device. In some implementations, the order of the processes can be changed or modified.

[0104] The method may (at 1905) optionally provide a bulk substrate (e.g., 175). The bulk substrate 175 may be supplied or manufactured by a supplier. The bulk substrate 175 may include at least one dielectric layer 177 and a plurality of interconnects 179. Phase 1 of Figure 18A illustrates and describes an example of providing a bulk substrate.

[0105] The method (in 1910) provides and couples at least one passive element (e.g., 170) and / or at least one integrated device (e.g., 172). The at least one passive element and / or the at least one integrated device may be coupled to a bulk substrate 175, or may be coupled to a strip or carrier. The at least one passive element and / or the at least one integrated device may be an example of an electrical element and / or an electrical device. Phase 2 of Figure 18A illustrates and describes an example of providing and / or coupling at least one passive element and / or at least one integrated device.

[0106] This method (in 1915) forms an encapsulation layer (e.g., 174) over a bulk substrate (e.g., 175), carrier, or strip. The encapsulation layer 174 may be provided and formed over and around the bulk substrate 175 and integrated devices (e.g., 172) and / or passive components (e.g., 170). The encapsulation layer 174 may encapsulate(s) the integrated devices and / or components. The encapsulation layer 174 may include molding materials, resins, and / or epoxy resins. Compression molding, transfer molding, or liquid molding processes may be used to form the encapsulation layer 174. The encapsulation layer 174 may be photoetchable. The encapsulation layer 174 may be an encapsulation member. Phase 4 of Figure 18A illustrates and describes an example of forming an encapsulation layer.

[0107] The method (at 1920) cuts the encapsulation layer (e.g., 174), which creates a cut line 1820 (e.g., a cavity) in the encapsulation layer 174. The cut line 1820 can be created using a saw and / or a laser. This produces several individual block devices having an encapsulation layer, passive elements, and / or integrated devices. Stage 5 of Figure 18B illustrates and describes an example of cutting the encapsulation layer. Once cutting is complete, the method allows the individual block devices to be placed (e.g., transferred) onto a carrier. Stage 6 of Figure 18B illustrates and describes an example of placing the individual block devices onto a carrier.

[0108] This method (in 1925) forms a metal layer (e.g., 176) over the encapsulation layer 174 of an individual bulk device. The metal layer can be formed and coupled to the outer surface of the encapsulation layer 174. The metal layer 176 can be formed using sputtering and / or electroplating processes. The metal layer 176 can be configured as an EMI shield. Stage 7 of Figure 18C illustrates and describes an example of forming the metal layer. Note that during the process of manufacturing the bulk device, various components can be decoupled, transferred, and / or coupled to various tapes and / or carriers. This method can then decouple the individual bulk device from the carrier. Stage 8 of Figure 18C illustrates and describes an example of decoupling the bulk device from the carrier.

[0109] Note that using appropriate design rules and cutting tolerances can minimize the risk of voids during the encapsulation of individual block devices and during the encapsulation process.

[0110] Note that removing the solder mask on the package and applying appropriate molding flow can further reduce the risk of molded voids. Block devices may include exposed pads, which may be thinner to increase spacing during package assembly, further reducing the risk of molded voids. Exemplary process for manufacturing a substrate

[0111] In some implementations, manufacturing the substrate includes several processes. Figures 20A–20B illustrate exemplary processes for providing or manufacturing the substrate. In some implementations, the processes of Figures 20A–20B can be used to provide or manufacture the substrate 102 of Figure 1. However, the processes of Figures 20A–20B can be used to manufacture any substrate described in this case.

[0112] It should be noted that the processes in Figures 20A–20B can be combined into one or more stages to simplify and / or clarify the processes used to provide or manufacture the substrate. In some implementations, the order of the processes can be changed or modified. In some implementations, one or more processes can be substituted or replaced without departing from the scope of this invention.

[0113] As shown in Figure 20A, stage 1 illustrates the state after a carrier 2000 is provided and a metal layer is formed on the carrier 2000. The metal layer can be patterned to form interconnects 2002. Plating and etching processes can be used to form the metal layer and the interconnects. In some implementations, the carrier 2000 may be provided with a metal layer that is patterned to form the interconnects 2002. In some implementations, a seed layer may be present on the carrier 2000. The seed layer may be located between the carrier 2000 and the metal layer forming the interconnects 2002.

[0114] Phase 2 describes the state after the dielectric layer 2020 is formed on the carrier 2000 and interconnect 2002. The dielectric layer 2020 can be formed using deposition and / or lamination processes. The dielectric layer 2020 may include polyimide. However, different implementations may use different materials for the dielectric layer.

[0115] Phase 3 describes the state after the plurality of cavities 2010 are formed in the dielectric layer 2020. The plurality of cavities 2010 can be formed using an etching process (e.g., a photolithography process) or a laser process.

[0116] Phase 4 describes the state after interconnects 2012 are formed in and above the dielectric layer 2020 (including in and above the plurality of cavities 2010). For example, vias, pads, and / or traces can be formed. These interconnects can be formed using plating processes.

[0117] Phase 5 describes the state after another dielectric layer 2022 is formed on top of dielectric layer 2020. Dielectric layer 2022 can be formed using deposition and / or lamination processes. Dielectric layer 2022 can be made of the same material as dielectric layer 2020. However, different implementations may use different materials for the dielectric layer.

[0118] As shown in Figure 20B, stage 6 illustrates the state after the formation of a plurality of cavities 2030 in the dielectric layer 2022. The cavities 2030 can be formed using an etching process or a laser process.

[0119] Phase 7 describes the state after interconnects 2014 are formed in and above the dielectric layer 2022 (including in and above the plurality of cavities 2030). For example, vias, pads, and / or traces may be formed. These interconnects may be formed using plating processes.

[0120] Note that stages 5 to 7 can be repeatedly performed to form additional metal and dielectric layers. Some or all of interconnects 2002, 2012, and / or 2014 can define a plurality of interconnects 122 of substrate 102. Dielectric layers 2020 and 2022 can be represented by at least one dielectric layer 120.

[0121] Phase 8 describes the state after the carrier 2000 is decoupled from at least one dielectric layer 120 (e.g., removed, ground away) to leave the substrate 102 comprising at least one dielectric layer 120 and a plurality of interconnects 122.

[0122] Stage 9 describes the state after the solder mask 124 and solder mask 126 are formed on the substrate 102. The solder mask 124 and solder mask 126 can be formed using a deposition process. In some implementations, a solder mask layer may not be formed or may be formed on at least one dielectric layer 120.

[0123] Different implementations may use different processes to form the metal layers. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form the metal layers. For example, sputtering, spraying, and / or electroplating processes may be used to form the metal layers. Exemplary flowchart of a method for manufacturing a substrate

[0124] In some implementations, manufacturing the substrate includes several processes. Figure 21 illustrates an exemplary flowchart of a method 2100 for providing or manufacturing a substrate. In some implementations, the method 2100 of Figure 21 can be used to provide or manufacture the substrates(s) of Figure 1. For example, the method of Figure 21 can be used to manufacture substrate 102.

[0125] It should be noted that method 2100 of Figure 21 can combine one or more processes to simplify and / or clarify the method for providing or manufacturing a substrate. In some implementations, the order of the processes can be changed or modified.

[0126] This method (at 2105) provides a carrier 2000. Different implementations may use different materials for the carrier. The carrier may include a seed layer. The carrier may include a substrate, glass, quartz, and / or carrier strips. Figure 20A illustrates and describes an example of the carrier provided in stage 1.

[0127] This method (in 2110) forms a metal layer on a carrier 2000. The metal layer can be patterned to form interconnects. A plating process can be used to form the metal layer and interconnects. In some implementations, the carrier may include a metal layer. The metal layer on the carrier can be patterned to form interconnects (e.g., 2002). Phase 1 of Figure 20A illustrates and describes an example of forming a metal layer and interconnects on a carrier.

[0128] The method (at 2115) forms a dielectric layer 2020 over a carrier 2000 and an interconnect 2002. The dielectric layer can be formed using deposition and / or lamination processes. The dielectric layer 2020 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 2010) within the dielectric layer 2020. These cavities can be formed using etching processes (e.g., photolithography) or laser processes. Stages 2–3 of Figure 20A illustrate and describe examples of forming a dielectric layer and forming cavities within it.

[0129] This method (at 2120) forms interconnects in and over the dielectric layer. For example, interconnect 2012 may be formed in and over the dielectric layer 2020. These interconnects may be formed using a plating process. Forming interconnects may include providing a patterned metal layer on and / or in the dielectric layer. Forming interconnects may also include forming interconnects in cavities of the dielectric layer. Phase 4 of Figure 20A illustrates and describes an example of forming interconnects in and over the dielectric layer.

[0130] The method (at 2125) forms a dielectric layer 2022 over the dielectric layer 2020 and these interconnects. The dielectric layer can be formed using deposition and / or lamination processes. The dielectric layer 2022 may include polyimide. Forming the dielectric layer may also include forming a plurality of cavities (e.g., 2030) within the dielectric layer 2022. These cavities can be formed using etching or laser processes. Steps 5–6 of Figures 20A–20B illustrate and describe examples of forming a dielectric layer and forming cavities within it.

[0131] This method (at 2130) forms interconnects in and / or on the dielectric layer. For example, interconnect 2014 can be formed. A plating process can be used to form the interconnects. Forming interconnects may include providing a patterned metal layer on and in the dielectric layer. Forming interconnects may also include forming interconnects in cavities of the dielectric layer. Stage 15 of Figure 20B illustrates and describes an example of forming interconnects in and on the dielectric layer.

[0132] This method can form additional dielectric layers and additional interconnects, as described at 2125 and 2130.

[0133] Once all dielectric layers and additional interconnects are formed, the method can decouple (e.g., remove, grind away) the carrier (e.g., 2000) from dielectric layer 2020, leaving the substrate. In some implementations, the method can form a solder mask layer (e.g., 124, 126) on the substrate.

[0134] Different implementations may use different processes to form the metal layers. In some implementations, chemical vapor deposition (CVD) and / or physical vapor deposition (PVD) processes are used to form the metal layers. For example, sputtering, spraying, and / or electroplating processes may be used to form the metal layers. Exemplary electronic devices

[0135] Figure 22 illustrates various electronic devices that can integrate any of the aforementioned devices, integrated devices, integrated circuit (IC) packages, integrated circuit (IC) devices, semiconductor devices, integrated circuits, chips, intermediaries, packages, stacked package (PoP), system-in-package (SiP), or system-on-a-chip (SoC). For example, mobile phone device 2202, laptop device 2204, fixed-location terminal device 2206, wearable device 2208, or motor vehicle 2210 may include the device 2200 as described herein. Device 2200 may be any of the devices and / or integrated circuit (IC) packages described herein, for example. Devices 2202, 2204, 2206, and 2208, and vehicle 2210 illustrated in Figure 22 are merely exemplary. Other electronic devices may also be characterized by device 2200, including but not limited to a group of devices (e.g., electronic devices) comprising: mobile devices, handheld personal communication system (PCS) units, portable data units (such as personal digital assistants), GPS-enabled devices, navigation devices, set-top boxes, music players, video players, entertainment units, fixed location data units (such as meter reading devices), communication devices, smartphones, tablets, computers, wearable devices (e.g., watches, glasses), Internet of Things (IoT) devices, servers, routers, electronic devices implemented in motor vehicles (e.g., autonomous vehicles), or any other device that stores or retrieves data or computer instructions, or any combination thereof.

[0136] One or more of the elements, procedures, features, and / or functions illustrated in Figures 1–14, 15A–15B, 16, 17A–17B, 18A–18C, and / or 19–22 may be rearranged and / or combined into a single element, procedure, feature, or function, or may be implemented in several elements, procedures, or functions. Additional elements, procedures, and / or functions may also be added without departing from this invention. It should also be noted that Figures 1–14, 15A–15B, 16, 17A–17B, 18A–18C, and / or 19–22 and their corresponding descriptions in this invention are not limited to chips and / or ICs. In some implementations, Figures 1–14, 15A–15B, 16, 17A–17B, 18A–18C, and / or 19–22 and their corresponding descriptions may be used to manufacture, establish, provide, and / or produce apparatus and / or integrate apparatus. In some implementations, the device may include a die, an integrated device, an integrated passive device (IPD), a die package, an integrated circuit (IC) device, a device package, an integrated circuit (IC) package, a wafer, a semiconductor device, a stacked package (PoP) device, a heat dissipation device, and / or an intermediary.

[0137] Note that the accompanying drawings in this application may represent actual and / or conceptual representations of various components, elements, objects, devices, packages, integrated devices, integrated circuits, and / or transistors. In some cases, the drawings may not be to scale. In some cases, not all elements and / or components are shown for clarity. In some instances, the positioning, location, size, and / or shape of the various components and / or elements in the drawings may be exemplary. In some implementations, the various elements and / or components in the drawings may be optional.

[0138] The term "exemplary" is used herein to mean "serving as an example, instance, or illustration." Any implementation or manner described herein as "exemplary" is not necessarily to be construed as superior to or better than other manners in this case. Similarly, the term "manner" does not require that all manners in this case include the features, advantages, or modes of operation discussed. The term "coupled" is used herein to refer to direct or indirect coupling between two objects (e.g., mechanical coupling). For example, if object A physically contacts object B, and object B contacts object C, then objects A and C can still be considered coupled to each other—even if they are not in direct physical contact. Object A coupled to object B may be coupled to at least a portion of object B. The term "electrically coupled" may mean that two objects are directly or indirectly coupled together such that current (e.g., signal, power, ground) can be transmitted between the two objects. Electrically coupled objects may or may not have current transmitted between them. The use of the terms "first," "second," "third," and "fourth" (and / or anything higher than fourth) is arbitrary. Any element described can be a first element, a second element, a third element, or a fourth element. For example, an element referred to as a second element can be a first element, a second element, a third element, or a fourth element. The terms "encapsulate," "encapsulate," and / or any derivative meaning that an object can partially or completely encapsulate another object. The terms "top" and "bottom" are arbitrary. An element located at the top can be situated on top of an element located at the bottom. A top element can be considered a bottom element, and vice versa. As described in this case, a first element situated "above" a second element can mean that the first element is located above or below the second element, depending on how bottom or top is arbitrarily defined. In another example, a first element can be situated above (e.g., above) a first surface of a second element, while a third element can be situated above (e.g., below) a second surface of a second element, where the second surface is opposite the first surface. Further note that the term "above," as used in this case in the context of an element being above another element, can be used to indicate that an element is on and / or in another element (e.g., on the surface of an element or embedded in an element). Thus, for example, "first element on second element" can mean: (1) the first element is on the second element but does not directly contact the second element; (2) the first element is on the second element (e.g., on the surface of the second element); and / or (3) the first element is in the second element (e.g., embedded in the second element). A first element located "in" the second element can be partially or completely located in the second element. As used in this case, the terms "about 'value X'" or "approximately value X" mean within ten percent of 'value X'. For example, a value of about 1 or approximately 1 would mean a value in the range of 0.9-1.1.

[0139] In some implementations, an interconnect is a component or element in a device or package that allows or facilitates an electrical connection between two points, elements, and / or components. In some implementations, an interconnect may include traces, vias, pads, pillars, metallization layers, redistribution layers, and / or under-bump metallization (UBM) layers / interconnects. In some implementations, an interconnect may include conductive material that can be configured to provide an electrical path for signals (e.g., data signals), ground, and / or power. An interconnect may include more than one component or element. An interconnect may be defined by one or more interconnects. An interconnect may include one or more metal layers. An interconnect may be part of a circuit. Different implementations may use different processes and / or steps to form interconnects. In some implementations, chemical vapor deposition (CVD), physical vapor deposition (PVD), sputtering, spraying, and / or electroplating processes may be used to form interconnects.

[0140] It should also be noted that the various disclosures contained herein can be described as programs illustrated as flowcharts, flow diagrams, block diagrams, or block diagrams. Although flowcharts can describe operations as a sequential procedure, many operations can be executed in parallel or concurrently. Furthermore, the order of operations can be rearranged. The program terminates when its operations are completed.

[0141] Further examples are described below to facilitate understanding of this case.

[0142] Specimen 1: A package comprising: a substrate; a first integrated device coupled to the substrate; a first bulk device coupled to the substrate, the first bulk device comprising: a first electrical component; a second electrical component; a first encapsulation layer encapsulating the first electrical component and the second electrical component; a first metal layer coupled to the first encapsulation layer; and a second encapsulation layer encapsulating at least partially the first integrated device and the first bulk device.

[0143] Version 2: The package as in Version 1, further comprising a second metal layer coupled to the second encapsulation layer, wherein the second metal layer is located on the outer surface of the second encapsulation layer.

[0144] State 3: The same as the package of State 2, wherein the second metal layer is coupled to the first metal layer of the first block device.

[0145] Type 4: Package as in Types 2 to 3, wherein the first metal layer and / or the second metal layer is configured as an electromagnetic interference (EMI) shield.

[0146] State 5: Package as in States 2 to 4, wherein the first metal layer and / or the second metal layer is configured to be coupled to ground.

[0147] State 6: Packages as in states 1 to 5, wherein the first block device further includes a block substrate, and wherein the first electrical component and the second electrical component are coupled to the block substrate.

[0148] State 7: Packages as in States 1 to 6, wherein the first electrical component includes a passive component or integrated device, and wherein the second electrical component includes another passive component or another integrated device.

[0149] State 8: Package as in states 1 to 7, wherein the first block device includes more than two electrical components.

[0150] State 9: The package as described in States 1 to 8 further includes a second block device coupled to the substrate, wherein the second block device includes: a third electrical component; a fourth electrical component; a third encapsulation layer encapsulating the third electrical component and the fourth electrical component; and a third metal layer coupled to the third encapsulation layer, wherein the third metal layer is configured as a mask for the second block device.

[0151] Type 10: Packages as in Types 1 to 9, wherein the first block device is coupled to the substrate via a plurality of solder interconnects.

[0152] Specimen 11: An apparatus comprising: a substrate; a first integrated device coupled to the substrate; a first block device coupled to the substrate, the first block device comprising: a first electrical component; a second electrical component; a first encapsulation member configured to encapsulate the first electrical component and the second electrical component; a first metal layer coupled to the first encapsulation member; and a second encapsulation member configured to at least partially encapsulate the first integrated device and the first block device.

[0153] Version 12: The equipment as in Version 11 further includes a second metal layer coupled to the second encapsulation member, wherein the second metal layer is located on the outer surface of the second encapsulation member.

[0154] State 13: As in State 12, wherein the second metal layer is coupled to the first metal layer of the first block device.

[0155] Version 14: The equipment as in versions 12 to 13, wherein the first metal layer and / or the second metal layer is configured as an electromagnetic interference (EMI) shield.

[0156] State 15: The equipment as in states 12 to 14, wherein the first metal layer and / or the second metal layer is configured to be coupled to ground.

[0157] Version 16: The equipment as in versions 11 to 15, wherein the first block device further includes a block substrate, and wherein the first electrical component and the second electrical component are coupled to the block substrate.

[0158] Version 17: The equipment as in versions 11 to 16, wherein the first electrical component includes a passive component or an integrated device, and wherein the second electrical component includes another passive component or another integrated device.

[0159] Version 18: The equipment as described in versions 11 to 17, wherein the first block device includes more than two electrical components.

[0160] Version 19: The equipment of versions 11 to 18 further includes a second block device coupled to the substrate, wherein the second block device includes: a third electrical element; a fourth electrical element; a third encapsulation member configured to encapsulate the third electrical element and the fourth electrical element; and a third metal layer coupled to the third encapsulation member, wherein the third metal layer is configured as a shielding member of the second block device.

[0161] Type 20: Equipment as described in Types 11 to 19, wherein the equipment includes devices selected from the group comprising: music players, video players, entertainment units, navigation devices, communication devices, mobile devices, mobile phones, smartphones, personal digital assistants, fixed-location terminals, tablet computers, computers, wearable devices, laptops, servers, Internet of Things (IoT) devices, and devices in motor vehicles.

[0162] Sample 21: A method for manufacturing a package, comprising: providing a substrate; coupling a first integrated device to the substrate; coupling a first bulk device to the substrate, the first bulk device including: a first electrical component; a second electrical component; a first encapsulation layer encapsulating the first electrical component and the second electrical component; and a first metal layer coupled to the first encapsulation layer; and forming a second encapsulation layer that at least partially encapsulates the first integrated device and the first bulk device.

[0163] Version 22: The method of version 21 further includes: forming a second metal layer on the outer surface of the second encapsulation layer.

[0164] State 23: The method of State 22, wherein the second metal layer is coupled to the first metal layer of the first block device.

[0165] Version 24: The method of Versions 22 to 23, wherein the first metal layer and / or the second metal layer is configured as an electromagnetic interference (EMI) shield.

[0166] Version 25: The method of versions 21 to 24, wherein the first block device further includes a block substrate, and wherein the first electrical element and the second electrical element are coupled to the block substrate.

[0167] The various features of this case described herein can be implemented in different systems without departing from this case. It should be noted that the above examples are merely illustrative and should not be construed as limiting the scope of this case. The descriptions of the various aspects of this case are intended to be illustrative and not to limit the scope of the appended claims. Therefore, the teachings of this case can be readily applied to other types of devices, and many substitutions, modifications, and variations will be apparent to those skilled in the art.

[0168] 100: Package 102:Substrate 104: Integrated Device 105: Block-shaped device 107: Block-shaped device 108: Encapsulation layer 109: Metal layer 120: Dielectric layer 122: Interconnection 124: Solder mask layer 126: Solder mask layer 130: Solder interconnect 140: Solder interconnect 150: Passive components 151: Solder interconnect 152: Passive Components 153: Passive Components 154: Encapsulation layer 156: Metal layer 170: Passive Components 171: Solder interconnect 172: Integrated Device 173: Solder interconnect 174: Encapsulation layer 175: Block substrate 176: Metal layer 177: Dielectric layer 178: Solder interconnect 179: Interconnection 250: Passive Components 252: Passive Components 270: Passive Components 272: Passive Components 1107: Block-shaped device 1500: Solder Interconnect 1600: Method 1605: Steps 1610: Steps 1615: Steps 1620: Steps 1625: Steps 1630: Steps 1635: Steps 1700: with 1710: Passive Components 1720: Cutting line 1750: Carrier 1800: Carrier 1810: Carrier 1820: Cutting line 1900: Method 1905: Steps 1910: Steps 1915: Steps 1920: Steps 1925: Steps 2000: Carrier 2002: Interconnection 2010: Cavity 2012: Interconnection 2014: Interconnection 2020: Dielectric Layer 2022: Dielectric Layer 2030: Cavity 2100: Method 2105: Steps 2110: Steps 2115: Steps 2120: Steps 2125: Steps 2130: Steps 2200: Device 2202: Equipment 2204: Equipment 2206: Equipment 2208: Equipment 2210: Transportation X: Coordinates Y: Coordinates Z: Coordinates

[0169] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A packaging integration device, comprising: One substrate; A first integrated device coupled to the substrate; A first block device coupled to the substrate, the first block device comprising: a first electrical component; a second electrical component; a first encapsulation layer encapsulating the first electrical component and the second electrical component; a first metal layer coupled to the first encapsulation layer; a second encapsulation layer at least partially encapsulating the first integrated device and the first block device; and a second metal layer located at least on the first block device, directly coupled to and contacting (i) a first surface of the first encapsulation layer of the first block device, (ii) a second surface of the second encapsulation layer, and (iii) the first metal layer.

2. The encapsulation integration apparatus of claim 1, wherein the second metal layer is located on the second encapsulation layer.

3. The encapsulation integration device as claimed in claim 1, wherein an entire portion of the first metal layer of the first block device is coupled to and contacts the first encapsulation layer and the second encapsulation layer along a vertical plane.

4. The packaged integration device as claimed in claim 1, wherein the first metal layer and / or the second metal layer is configured as an electromagnetic interference (EMI) shield.

5. The packaged integration device as claimed in claim 1, wherein the first metal layer and / or the second metal layer is configured to be coupled to ground.

6. The packaged integration apparatus of claim 1, wherein the first block device further includes a block substrate, and wherein the first electrical component and the second electrical component are coupled to the block substrate.

7. The packaged integrated device as claimed in claim 1, wherein the first electrical component includes a passive component or an integrated device, and wherein the second electrical component includes another passive component or another integrated device.

8. The packaged integrated device as claimed in claim 1, wherein the first block device includes more than two electrical components.

9. The packaging integration apparatus of claim 1, further comprising a second block-shaped device coupled to the substrate, wherein the second block-shaped device includes: A third electrical component; A fourth electrical component; A third encapsulation layer encapsulating the third electrical component and the fourth electrical component; and a third metal layer coupled to the third encapsulation layer, wherein the third metal layer is configured as a shielding element of the second block device.

10. The packaged integration apparatus of claim 1, wherein the first block device is coupled to the substrate via a plurality of solder interconnects.

11. An apparatus having a packaged integrated device, comprising: One substrate; A first integrated device coupled to the substrate; A first block device coupled to the substrate, the first block device comprising: a first electrical component; a second electrical component; a first encapsulation member configured to encapsulate the first electrical component and the second electrical component; a first metal layer coupled to the first encapsulation member; a second encapsulation member configured to at least partially encapsulate the first integrated device and the first block device; and a second metal layer located at least above the first block device, directly coupled to and contacting (i) a first surface of the first encapsulation member of the first block device, (ii) a second surface of the second encapsulation member, and (iii) the first metal layer.

12. The equipment as claimed in claim 11, wherein the second metal layer is located on the second encapsulation member.

13. The equipment as claimed in claim 11, wherein an entire portion of the first metal layer of the first block device is coupled to and contacts the first encapsulating member and the second encapsulating member along a vertical plane.

14. The equipment as claimed in claim 11, wherein the first metal layer and / or the second metal layer is configured as an electromagnetic interference (EMI) shield.

15. The equipment as claimed in claim 11, wherein the first metal layer and / or the second metal layer is configured to be coupled to ground.

16. The apparatus of claim 11, wherein the first block device further includes a block substrate, and wherein the first electrical element and the second electrical element are coupled to the block substrate.

17. The equipment of claim 11, wherein the first electrical component includes a passive element or an integrated device, and wherein the second electrical component includes another passive element or another integrated device.

18. The equipment as claimed in claim 11, wherein the first block device comprises more than two electrical components.

19. The apparatus of claim 11 further includes a second block-shaped device coupled to the substrate, wherein the second block-shaped device includes: A third electrical component; A fourth electrical component; A third encapsulation member configured to encapsulate the third electrical element and the fourth electrical element; and a third metal layer coupled to the third encapsulation member, wherein the third metal layer is configured as a shielding member of the second block device.

20. The equipment as claimed in claim 11, wherein the equipment includes a device selected from the group consisting of: a music player, a video player, an entertainment unit, a navigation device, a communication device, a mobile device, a mobile phone, a smartphone, a digital assistant, a fixed-location terminal, a tablet computer, a computer, a wearable device, a laptop computer, a server, an Internet of Things (IoT) device, and a device in a motor vehicle.

21. A method for manufacturing a package, comprising: Provide a substrate; A first integrated device is coupled to the substrate; A first bulk device is coupled to the substrate, the first bulk device comprising: a first electrical component; a second electrical component; a first encapsulation layer encapsulating the first electrical component and the second electrical component; a first metal layer coupled to the first encapsulation layer; a second encapsulation layer formed to at least partially encapsulate the first integrated device and the first bulk device; and a second metal layer formed at least on the first bulk device, the second metal layer being directly coupled to and contacting (i) a first surface of the first encapsulation layer of the first bulk device, (ii) a second surface of the second encapsulation layer, and (iii) the first metal layer.

22. The method of claim 21, wherein the second metal layer is located on an outer surface of the second encapsulation layer.

23. The method of claim 21, wherein an entire portion of the first metal layer of the first block device is coupled to and contacts the first encapsulation layer and the second encapsulation layer along a vertical plane.

24. The method of claim 21, wherein the first metal layer and / or the second metal layer is configured as an electromagnetic interference (EMI) shield.

25. The method of claim 21, wherein the first block device further includes a block substrate, and wherein the first electrical element and the second electrical element are coupled to the block substrate.

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