Methods of forming memory device with reduced resistivity

Abstract

Memory devices and methods for forming memory devices are described. These memory devices include a silicon nitride hard mask layer on a ruthenium layer. Forming the silicon nitride hard mask layer on ruthenium includes pretreating the ruthenium layer with plasma to form an interface layer on the ruthenium layer; and forming the silicon nitride layer on the interface layer by plasma-enhanced chemical vapor deposition (PECVD). In some embodiments, pretreating the ruthenium layer results in a reduced roughness of the interface layer and a reduced resistivity of the memory device compared to a memory device without an interface layer.

Description

Technical Field

[0001] The embodiments disclosed herein relate to the field of memory devices and the manufacture of memory devices. More particularly, the embodiments disclosed herein provide memory devices with reduced resistance and methods for forming the same, the memory devices including an interface layer with reduced roughness. Prior Technology

[0002] Due to the high resistivity of tungsten (W) layers, there is a growing interest in replacing tungsten (W) with ruthenium (Ru) as the metal layer in both dynamic random access memory (DRAM) and logic devices. However, the resistivity (i.e., thin-film resistance) and surface roughness of the ruthenium (Ru) layer may increase during the deposition of silicon nitride (SiN) layers and subsequent high-temperature steps.

[0003] Current methods utilize two steps to deposit silicon nitride (SiN) layers on ruthenium (Ru) layers, comprising: (1) depositing the SiN layer by atomic layer deposition (ALD); and (2) depositing the SiN layer by plasma-enhanced chemical vapor deposition (PECVD) or by furnace deposition. These current methods involve depositing the SiN layer in two separate substrate processing chambers, reducing throughput and introducing additional interfaces, which accelerates the oxidation of the ruthenium (Ru) layer during high-temperature annealing. Oxidation of the ruthenium layer is believed to increase its resistivity. Due to the high deposition temperatures during silicon nitride layer formation, surface reactions between the metal layer and the silicon nitride layer may occur. It is also desirable to form and protect high-quality silicon nitride layers, excluding the electrical properties, resistivity (i.e., sheet resistance), and surface roughness of other layers in the memory device.

[0004] Therefore, there is a need in the art for memory devices with reduced resistance, and methods for forming such memory devices. Summary of the Invention

[0005] One or more embodiments disclosed herein relate to a method for forming a silicon nitride hard mask layer on a ruthenium layer, the method comprising pretreating the ruthenium layer with plasma to form an interface layer on the ruthenium layer; and forming the silicon nitride layer on the interface layer using a plasma-enhanced chemical vapor deposition (PECVD) process.

[0006] Additional embodiments disclosed herein relate to methods for forming a memory device including a silicon nitride hard mask layer on a ruthenium layer. These methods include pretreating the ruthenium layer in the presence of plasma to form an interface layer on the ruthenium layer, and forming a silicon nitride layer on the interface layer by a plasma-enhanced chemical vapor deposition (PECVD) process. Compared to memory devices without an interface layer, pretreating the ruthenium layer results in a reduced roughness of the interface layer and a reduced resistivity in the memory device.

[0007] Further embodiments disclosed herein relate to memory devices including a first layer on a substrate; a ruthenium layer on the first layer; an interface layer on the ruthenium layer; and a silicon nitride layer on the interface layer. Simple Explanation of the Diagram

[0008] To gain a more detailed understanding of the features described above, reference can be made to the embodiments for a more specific description of the disclosure, some of which are illustrated in the accompanying drawings. However, it should be noted that the drawings illustrate only typical embodiments of the disclosure and should not be considered as limiting its scope, as the disclosure allows for other equally effective embodiments. The embodiments described herein are illustrated in the drawings by way of example rather than limitation, and the same reference numerals denote similar elements in the drawings.

[0009] Figure 1 illustrates a schematic diagram of a memory device according to one or more embodiments; and

[0010] Figure 2 illustrates a flowchart method for forming a silicon nitride hard mask layer on a ruthenium layer according to one or more embodiments. Implementation

[0011] Before describing several exemplary embodiments of this disclosure, it should be understood that this disclosure is not limited to the details of the construction or processing steps set forth in the following description. This disclosure can have other embodiments and can be practiced or performed in various ways.

[0012] As used herein, "substrate" refers to any substrate or material surface formed on a substrate during the manufacturing process on which a film treatment is performed. For example, depending on the application, substrate surfaces on which treatments can be performed include materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other materials such as metals, metal nitrides, metal alloys, and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. Substrates can be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to performing film treatments directly on the surface of the substrate itself, any of the film treatment steps disclosed in this disclosure can also be performed on an underlayer formed on the substrate, as disclosed in more detail below, and the term "substrate surface" is intended to include such an underlayer as the context suggests. Thus, for example, when a film / layer or a portion of a film / layer has already been deposited onto the substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0013] As used in this specification and the appended claims, the term "substrate" refers to the surface or part of the surface on which the process is performed. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, reference to substrate may also refer to only a portion of the substrate. Furthermore, reference to deposition on a substrate may refer to both a bare substrate and a substrate on which one or more films or features are deposited or formed.

[0014] The term "on" indicates that there is direct contact between elements. The term "directly on" indicates that there is direct contact between elements without any intermediary elements.

[0015] As used herein, the terms "Dynamic Random Access Memory" or "DRAM" refer to a memory cell that stores data bits by storing charge packets (i.e., binary 1s) or no charge packets (i.e., binary 0s) on a capacitor. The charge is gated onto the capacitor via an access transistor and is sensed by turning on the same transistor and observing the voltage fluctuations generated by transferring the charge packets to the interconnects at the transistor output. Therefore, a single DRAM cell is made of one transistor and one capacitor. As used herein, the terms "resistivity" and "sheet resistance" are used interchangeably.

[0016] In one or more embodiments, an interface layer and a method for forming an interface layer with reduced roughness compared to a film without an interface layer are provided. Embodiments provide memory devices, and also provide methods for forming memory devices with reduced resistivity compared to memory devices without an interface layer. In some embodiments, the interface layer between a ruthenium layer and a silicon nitride layer reduces the resistivity of the ruthenium layer and the memory device as a whole. It has been found that the formation of ruthenium silicon silicide (RuSi) leads to an increase in the resistivity of the device. More specifically, the use of conventional PECVD processes that do not utilize ruthenium layer pretreatment before depositing the silicon nitride layer facilitates RuSi formation, increases the surface roughness of the ruthenium layer, and increases the resistivity of the device. The presence or absence of RuSi is detected using transmission electron microscopy (TEM) and energy-dispersive x-ray spectroscopy (EDX). According to one or more embodiments, the device and the method for manufacturing the device are substantially free of RuSi, and have a lower resistivity than a device without an interface layer.

[0017] In one or more exemplary embodiments, the memory device formed according to the embodiments of the present disclosure may be a DRAM-type integrated circuit. Figure 1 illustrates a portion of a memory device 100 according to one or more embodiments of the present disclosure. In one or more embodiments, the memory device 100 includes a first layer 120 on a substrate 110. A ruthenium layer 130, an interface layer 140 on the ruthenium layer 130, and a silicon nitride layer 150 are present on the interface layer 140. Figure 2 is a flowchart illustrating a method 200 for forming a silicon nitride hard mask layer on a ruthenium layer, according to one or more embodiments, particularly a method 200 for forming the memory device 100 shown in Figure 1.

[0018] Referring to Figure 2, an exemplary embodiment of method 200 includes pretreating a ruthenium layer with plasma at operation 210 to form an interface layer on the ruthenium layer at operation 220. At operation 240, the method includes forming a silicon nitride layer on the interface layer. In one or more embodiments, the pretreating of the ruthenium layer and the formation of the silicon nitride layer are performed in a single processing chamber configured to process the substrate without repositioning the substrate to a second chamber.

[0019] The memory device 100 includes a substrate 110 having a first layer 120. The substrate 110 comprises one or more of the materials described above. The first layer 120 can be any suitable conductive material. In some embodiments, the first layer 120 comprises one or more of titanium (Ti), tantalum (Ta), titanium silicon (TiSi), or tantalum silicon (TaSi). In one or more embodiments, the first layer 120 comprises titanium nitride (or is substantially composed of titanium nitride). As used in this manner, the term "substantially composed of" means that, atomically, the first layer contains greater than or equal to about 95%, 98%, 99%, or 99.9% of the said element or composition. For example, a first layer 120 substantially composed of titanium nitride means that, atomically, the sum of titanium atoms and nitrogen atoms in the film accounts for greater than or equal to about 95%, 98%, 99%, or 99.5% of the deposited first layer 120.

[0020] The thickness of the first layer 120 can vary. In one or more embodiments, the first layer 120 has a thickness in the range of about 3 nm to about 5 nm. In one or more embodiments, the thickness of the first layer 120 is in the range of about 3.1 nm to about 4.9 nm, about 3.2 nm to about 4.8 nm, about 3.3 nm to about 4.8 nm, about 3.4 nm to about 4.7 nm, about 3.5 nm to about 4.6 nm, about 3.6 nm to about 4.5 nm, about 3.7 nm to about 4.4 nm, about 3.8 nm to about 4.3 nm, about 3.9 nm to about 4.2 nm, or about 4.0 nm to about 4.1 nm. In one or more embodiments, the thickness of the substrate 110 is in the range of about 100 μm to about 900 μm.

[0021] In some embodiments, the memory device 100 includes a ruthenium layer 130 on a first layer 120. The thickness of the ruthenium layer 130 may vary. In one or more embodiments, the thickness of the ruthenium layer 130 is in the range of about 10 nm to about 15 nm. In one or more embodiments, the thickness of the ruthenium layer 130 is in the range of about 11 nm to about 14 nm, or in the range of about 12 nm to about 13 nm.

[0022] Referring to Figures 1 and 2, method 200 includes plasma pretreatment of a ruthenium layer 130 at operation 210. In some embodiments, plasma pretreatment of the ruthenium layer 130 includes flowing a gas selected from the group consisting of NH3, N2O, N2, Ar, and combinations thereof. In one or more embodiments, method 200 further includes controlling the flow of the gas. In one or more embodiments, at operation 210, plasma pretreatment of the ruthenium layer 130 includes turning on the gas flow to a desired flow rate and stabilizing the desired flow rate before performing operation 220. In one or more embodiments, plasma pretreatment of the ruthenium layer 130 includes flowing NH3 at a rate of about 50 sccm to about 500 sccm. In one or more embodiments, plasma pretreatment of the ruthenium layer 130 includes flowing N2O at a rate of about 1000 sccm to about 5000 sccm. In one or more embodiments, plasma pretreatment of the ruthenium layer 130 includes flowing N₂ at a rate of about 1000 sccm to about 9000 sccm. In one or more embodiments, plasma pretreatment of the ruthenium layer 130 includes flowing Ar at a rate of about 1000 sccm to about 5000 sccm. In one or more embodiments, plasma pretreatment of the ruthenium layer 130 is performed at a pressure in the range of about 3 Torr to about 5 Torr.

[0023] In one or more embodiments, the plasma power during the pretreatment of the ruthenium layer 130 is in the range of about 200 watts to about 600 watts. In one or more embodiments, the plasma power is in the range of about 250 watts to about 550 watts, about 300 watts to about 500 watts, about 350 watts to about 450 watts, or about 375 watts to about 420 watts.

[0024] In one or more embodiments, during pretreatment, the ruthenium layer 130 is subjected to a temperature in the range of about 300°C to about 600°C. In one or more embodiments, the temperature is in the range of about 350°C to about 550°C, in the range of about 400°C to about 500°C, or in the range of about 425°C to about 475°C.

[0025] In one or more embodiments, the method includes pretreating a ruthenium layer 130 at operation 210 to prevent the formation of silicides. In one or more embodiments, the pretreating ruthenium layer 130 prevents the formation of ruthenium silicide (RuSi). In one or more embodiments, preventing the formation of ruthenium silicide (RuSi) results in a decrease in resistivity compared to memory devices having ruthenium silicide (RuSi) in the layer.

[0026] In one or more embodiments, method 200 includes forming an interface layer 140 on a ruthenium layer 130 at operation 220. The interface layer 140 is formed by pretreating the ruthenium layer with plasma. In one or more embodiments, the interface layer 140 comprises ruthenium, ruthenium nitride, ruthenium oxide, ruthenium carbide, or a combination thereof.

[0027] In one or more embodiments, the interface layer 140 is substantially oxygen-free. As used in this manner, the term "substantially oxygen-free" means that, on an atomic basis, the oxygen content in the interface layer is less than or equal to 5%, 4%, 3%, 2%, 1%, or 0.5%. In one or more embodiments, at operation 210, during plasma pretreatment of the ruthenium layer 130, a gas selected from the group consisting of NH3, N2O, N2, Ar, and combinations thereof is flowed to form the substantially oxygen-free interface layer 140.

[0028] In one or more embodiments, the interface layer contains oxygen. In one or more embodiments, an oxygen-containing gas is flowed during plasma pretreatment of the ruthenium layer to form an oxygen-containing interface layer. In one or more embodiments, plasma pretreatment of the ruthenium layer 130 includes flowing about 1000 sccm to about 5000 sccm of N₂O. In one or more embodiments, the resistivity of the oxygen-containing interface layer is greater than that of a substantially oxygen-free interface layer.

[0029] The thickness of the interface layer 140 can vary. In some embodiments, the thickness of the interface layer 140 is less than about 10 nm or less than about 5 nm. In some embodiments, the thickness of the interface layer 140 is less than about 2 nm. In some embodiments, the thickness of the interface layer 140 is in the range of about 0.1 nm to about 1 nm. In one or more embodiments, the thickness of the interface layer 140 is less than about 0.1 nm.

[0030] In one or more embodiments, method 200 may include, at operation 230, purifying a processing chamber between the pretreated ruthenium layer and the formed silicon nitride layer. The purifying processing chamber removes unreacted precursors, reaction products, and byproducts. As used in this manner, the term "processing chamber" also includes a portion of the processing chamber adjacent to the substrate surface, but does not encompass the entire internal volume of the processing chamber. For example, in a spatially separated sector of a processing chamber, precursors in a portion of the processing chamber adjacent to the substrate surface are purified by any suitable technique, including but not limited to moving the substrate through an air curtain to a precursor-free or substantially precursor-free portion or sector of the processing chamber. In one or more embodiments, purifying the processing chamber includes applying a vacuum. In some embodiments, purifying the processing chamber includes flowing a purifying gas over the substrate. In some embodiments, this portion of the processing chamber refers to a micro-volume or small-volume processing station within the processing chamber. The term "adjacent" with respect to the substrate surface means a physical space adjacent to the surface of the substrate that can provide sufficient space for surface reactions (e.g., precursor adsorption) to occur. In one or more embodiments, the purge gas is selected from one or more of nitrogen (N₂), helium (He), and argon (Ar). The purge process chamber, portions of the process chamber, and areas adjacent to the substrate surface remove unreacted reactants, reaction products, and byproducts from areas adjacent to the substrate surface. In one or more embodiments, production capacity can be increased by eliminating the purge step.

[0031] In one or more embodiments, the pretreatment of the ruthenium layer and the formation of the silicon nitride layer are performed in a single processing chamber configured to process the substrate without transferring it to a different or separate processing chamber. In one or more embodiments, during the cleanup at operation 230, the memory device 100 remains in the substrate processing chamber.

[0032] At operation 240, a silicon nitride layer 150 is formed on the interface layer 140. The thickness of the silicon nitride layer 150 can vary. In one or more embodiments, the thickness of the silicon nitride layer 150 is less than about 5 nm. In one or more embodiments, the thickness of the silicon nitride layer 150 is in the range of about 1 nm to about 5 nm.

[0033] In one or more embodiments, the silicon nitride layer 150 is formed by plasma-enhanced chemical vapor deposition (PECVD). PECVD is used for thin film deposition due to its cost-effectiveness and versatility in film properties. For example, in a PECVD process, a hydrocarbon source, such as vapor of gaseous or liquid hydrocarbons already entrained in a carrier gas, is introduced into a PECVD chamber. A plasma-initiating gas, typically helium, is also introduced into the chamber. The plasma is then initiated in the chamber to generate excited CH- radicals. The excited CH- radicals chemically bond to the surface of the substrate located in the chamber, thereby forming the desired film on that surface. PECVD processes can be performed using any suitable thin film deposition system. Any device descriptions herein are illustrative and should not be construed as limiting the scope of the embodiments described herein.

[0034] In one or more embodiments, method 200 includes, at operation 240, flowing a silicon-containing precursor. In one or more embodiments, flowing a silicon-containing precursor includes flowing one or more of the following: silane (SiH4), ethoxysilane (Si2H6), propane (Si3H8), tetrasilane (Si4H10), isotetrasilane, neopentylsilane (Si5H12), cyclopentylsilane (Si5H10), hexasilane (C6H14), cyclohexylsilane (Si6H12), silicon-containing precursors having the general formula SixHy where x is 2 or greater.

[0035] In one or more embodiments, method 200 further includes heating the silicon nitride layer 150 at operation 250. The deposition temperature of the silicon nitride layer 150 can be controlled to, for example, maintain the thermal budget of the device being formed. In one or more embodiments, heating the silicon nitride layer includes heating the silicon nitride layer to a temperature in the range of about 775°C to about 1075°C. In one or more embodiments, the silicon nitride layer is heated to a temperature in the range of about 750°C to about 1100°C, about 800°C to about 1050°C, about 825°C to about 1025°C, about 850°C to about 1000°C, about 875°C to about 975°C, or about 900°C to about 950°C.

[0036] In some embodiments, the migration of elements from the silicon nitride layer 150 to the ruthenium layer 130 is substantially prevented. For example, if the silicon nitride layer 150 contains silicon and nitrogen atoms, the migration of either silicon or nitrogen atoms to the ruthenium layer 130 is substantially prevented. As used in this manner, the term "substantially prevented" means that less than or equal to about 10% or 5% of the silicon nitride layer 150 elements migrate to the ruthenium layer 130 via the interface layer 140.

[0037] Additional embodiments of the present invention relate to methods for forming memory devices including silicon nitride hard mask layers on ruthenium layers, the methods including pretreating the ruthenium layer in the presence of plasma to form an interface layer on the ruthenium layer. The silicon nitride layer is formed on the interface layer by a plasma-enhanced chemical vapor deposition (PECVD) process.

[0038] In one or more embodiments, pre-treating the ruthenium layer results in a reduced roughness of the interface layer and a reduced resistivity of the memory device compared to a memory device without an interface layer.

[0039] In one or more embodiments, after pretreating the ruthenium layer in the presence of plasma to form an interface layer on the ruthenium layer, resistivity (i.e., thin-film resistance) and surface roughness are measured. In one or more embodiments, after heating the silicon nitride layer, resistivity (i.e., thin-film resistance) and surface roughness are measured again.

[0040] In one or more embodiments, the surface roughness of each of the first layer 120, ruthenium layer 130, interface layer 140, and silicon nitride layer 150 is measured. In one or more embodiments, the surface roughness at the interface between each of the first layer 120, ruthenium layer 130, interface layer 140, and silicon nitride layer 150 is measured.

[0041] In one or more embodiments, the resistivity (i.e., sheet resistance) of the ruthenium layer 130 is measured. In one or more embodiments, the resistivity (i.e., sheet resistance) of the memory device 100 is measured. In one or more embodiments, the resistivity (i.e., sheet resistance) of the memory device varies. In one or more embodiments, the sheet resistance is measured using a four-point probe. In one or more embodiments, the four-point probe comprises four electrical probes arranged in a row, wherein the spacing between each of the four probes is equal.

[0042] In one or more embodiments, after pretreating the ruthenium layer and forming the silicon nitride layer, the sheet resistance of the memory device 100 is in the range of about 9 ohms / square (Ω-cm) to about 11 ohms / square (Ω-cm). In one or more embodiments, after pretreating the ruthenium layer to form an interface layer and forming the silicon nitride layer, the resistivity (i.e., sheet resistance) of the memory device is lower than the resistivity (i.e., sheet resistance) of a memory device without an interface layer.

[0043] In one or more embodiments, surface roughness is measured using an atomic force microscope (AFM). In one or more embodiments, the surface roughness varies within the ruthenium layer. In one or more embodiments, the ruthenium layer 130 is pretreated to form an interface layer 140, followed by the formation of a silicon nitride layer 150, which has a lower surface roughness compared to a film where the silicon nitride layer is directly on the ruthenium layer without an interface layer in between. In one or more embodiments, after pretreatment of the ruthenium layer 130 and formation of the silicon nitride layer 150, the roughness of the interface layer 140 is in the range of about 0.6 nm to about 0.9 nm. It has been determined that when the silicon nitride layer is formed directly on the ruthenium layer without an interface layer in between, the roughness of the ruthenium is about 0.3 nm to 0.5 nm higher than when an interface layer is present. For example, when the interface layer is absent, the roughness of the ruthenium layer is in the range of about 1.0 nm to about 1.5 nm. In one or more embodiments, heating the silicon nitride layer 150 at operation 250 does not change the roughness of the interface layer 140. In one or more embodiments, after heating the silicon nitride layer 150 (operation 250), the roughness of the interface layer 140 is in the range of about 0.6 nm to about 0.9 nm.

[0044] In one or more embodiments, spectroscopic and microscopic techniques are used to analyze the composition of the interface layer 140 between the silicon nitride layer 150 and the ruthenium layer 130. In one or more embodiments, transmission electron microscopy (TEM) is used to analyze the composition of the interface layer 140.

[0045] In one or more embodiments, energy-dispersive x-ray spectroscopy (EDX) is used to analyze the composition of the interface layer 140. In one or more embodiments, the EDX system is attached to a TEM. EDX is based on the emission of characteristic x-rays from the sample.

[0046] In one or more embodiments, spectroscopic and microscopic techniques are used to analyze the diffusion of ruthenium atoms in the ruthenium layer 130. In one or more embodiments, a secondary ion mass spectrometer (SIMS) is used to measure the diffusion of ruthenium atoms in the ruthenium layer 130. In one or more embodiments, SIMS analysis of a memory device having an interface layer 140 between the ruthenium layer 130 and the silicon nitride layer 150 shows no diffusion of ruthenium atoms in the silicon nitride layer 150. In one or more embodiments, SIMS analysis of a memory device without an interface layer between the ruthenium layer and the silicon nitride layer shows diffusion of ruthenium atoms in the silicon nitride layer. It is believed that the diffusion of ruthenium atoms into the silicon nitride layer negatively affects device performance.

[0047] In the context of describing the materials and methods discussed herein (particularly in the context of the following claims), the terms "a" and "an" and "the," and similar designations, shall be construed as encompassing both the singular and plural, unless otherwise stated herein or clearly contradicted by the context. Unless otherwise stated herein, descriptions of numerical ranges are intended only as a shorthand for individually referring to each individual value falling within that range, and each individual value is incorporated into the specification as if it were described separately herein. Unless otherwise stated herein or clearly contradicted by the context, all methods described herein may be performed in any suitable order. The use of any and all illustrative or exemplary language (e.g., "such as") provided herein is intended only to better elucidate the materials and methods, and, unless otherwise stated, does not constitute a limitation on the scope. No language in the specification should be construed as indicating that any unclaimed element is essential to the materials and methods disclosed in practice.

[0048] Throughout this specification, references to "one embodiment," "some embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in connection with that embodiment is included in at least one embodiment of this disclosure. Therefore, the appearance of phrases such as "in one or more embodiments," "in some embodiments," "in one embodiment," or "in one embodiment" throughout this specification does not necessarily refer to the same embodiment of this disclosure. Furthermore, in one or more embodiments, a particular feature, structure, material, or characteristic may be combined in any suitable manner.

[0049] Although this disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of this disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus disclosed herein without departing from the spirit and scope of this disclosure. Therefore, this disclosure is intended to include modifications and variations within the scope of the appended claims and their equivalents.

[0050] 100: Memory Device 110:Substrate 120: First Floor 130: Ruthenium layer 140: Interface Layer 150: Silicon nitride layer 200: Method 210: Operation 220: Operation 230: Operation 240: Operation 250: Operation

[0051] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for forming a silicon nitride hard mask layer on a ruthenium metal layer, the method comprising the steps of: forming a first layer on a substrate, the first layer being selected from the group consisting of titanium (Ti), tantalum (Ta), titanium silicon silicide (TiSi), or tantalum silicon silicide (TaSi); forming the ruthenium metal layer on the first layer; pretreating the ruthenium metal layer with a plasma to form an interface layer on the ruthenium metal layer by means of a gas selected from the group consisting of NH3, N2O, N2, Ar, and combinations thereof, the interface layer comprising one or more of an oxide, a nitride, and a carbide of ruthenium; and forming the silicon nitride hard mask layer directly on the interface layer using a plasma-enhanced chemical vapor deposition (PECVD) process.

2. The method as described in claim 1 further includes the step of controlling the flow rate of the gas.

3. The method as described in claim 1, wherein the pretreatment of the ruthenium metal layer and the formation of the silicon nitride hard mask layer are performed in a processing chamber configured as a processing substrate.

4. The method as described in claim 1, wherein during the pretreatment of the ruthenium metal layer, a plasma power is in the range of about 200 watts to about 600 watts.

5. The method as described in claim 4, wherein during the pretreatment, the ruthenium metal layer is at a temperature in the range of about 300°C to about 600°C.

6. The method as claimed in claim 4, wherein during the formation of a silicon nitride hard mask layer on the interface layer using a plasma-enhanced chemical vapor deposition, a plasma power is in the range of 500 watts to 1200 watts.

7. The method as described in claim 1, wherein the interface layer is substantially oxygen-free.

8. The method as described in claim 1, wherein the thickness of the interface layer is less than about 1 nm.

9. The method as described in claim 1, wherein the step of forming the silicon nitride hard mask layer includes the step of: flowing a silicon-containing precursor.

10. The method as claimed in claim 9, wherein the step of flowing the silicon-containing precursor comprises the following steps: flowing one or more of the following silicon-containing precursors and combinations thereof: silane (SiH4), ethoxysilane (Si2H6), propane (Si3H8), tetrasilane (Si4H10), isotetrasilane, neopentylsilane (Si5H12), cyclopentylsilane (Si5H10), hexasilane (C6H14), cyclohexylsilane (Si6H12), having the general formula SixHy in which x is 2 or greater.

11. The method as described in claim 1, further comprising the step of heating the silicon nitride hard mask layer to a temperature in the range of about 750°C to about 1100°C.

12. The method of claim 3 further includes the step of: purifying the processing chamber between the pre-treatment of the ruthenium metal layer and the formation of the silicon nitride hard mask layer, the purging step including the steps of: applying a vacuum or causing a purging gas to flow over the ruthenium metal layer, the purging gas comprising one or more of nitrogen (N2), helium (He) and argon (Ar).

13. The method of claim 1, wherein a memory device comprising the silicon nitride hard mask layer formed by the method has a sheet resistance in the range of about 9 ohms / square (Ω-cm) to about 11 ohms / square (Ω-cm) after pretreatment of the ruthenium metal layer and formation of the silicon nitride hard mask layer.

14. A method of forming a memory device, the memory device including a silicon nitride hard mask layer on a ruthenium metal layer, the method comprising the steps of: forming a first layer on a substrate, the first layer being selected from the group consisting of titanium (Ti), tantalum (Ta), titanium silicon silicide (TiSi), or tantalum silicon silicide (TaSi); forming the ruthenium metal layer on the first layer; pretreating the ruthenium metal layer with a plasma to form an interface layer on the ruthenium metal layer; and forming the silicon nitride hard mask layer directly on the interface layer using a plasma-enhanced chemical vapor deposition (PECVD) process, wherein the pretreating of the ruthenium metal layer results in the interface layer having a roughness in the range of about 0.6 nm to about 0.9 nm.

15. The method as described in claim 14, wherein after pretreating the ruthenium metal layer and forming the silicon nitride hard mask layer, the thin-film resistance of the memory device is in the range of about 9 ohms / square (Ω-cm) to about 11 ohms / square (Ω-cm).

16. A memory device, comprising: The first layer is on a substrate; A ruthenium layer on the first layer; an interface layer on the ruthenium layer; And a silicon nitride layer on the interface layer, wherein the ruthenium layer, the interface layer and the silicon nitride layer are formed according to the method described in claim 1.

17. The memory device as claimed in claim 16, wherein the first layer comprises titanium nitride.

18. The memory device as described in claim 16, wherein the interface layer is substantially oxygen-free.

19. The memory device as claimed in claim 16, wherein the roughness of the interface layer is in the range of about 0.6 nm to about 0.9 nm, and the resistance of a thin layer of the memory device is in the range of about 9 ohms / square (Ω-cm) to about 11 ohms / square (Ω-cm).

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