Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes a semiconductor stack, a protective layer on the semiconductor stack, an electrode on the semiconductor stack and electrically connected to the semiconductor stack, and a conductive bump on the electrode. The distance from the top of the conductive bump to the uppermost surface of the protective layer is defined as the thickness of the conductive bump, and the ratio of the thickness of the conductive bump to the maximum width of the conductive bump is between 0.1 and 0.4.

Description

Technical Field

[0001] This invention relates to light-emitting elements, and in particular to the structure of a light-emitting element with conductive bumps and its manufacturing method. Prior Technology

[0002] Light-emitting diodes (LEDs) have the characteristics of low power consumption, long lifespan, small size, fast response speed and stable optical output, and have been widely used in the fields of lighting and display.

[0003] As LED technology continues to evolve, the brightness of LED chips is constantly improving, and the size of LED chips is gradually shrinking, for example, to less than 100μm, 50μm, or 30μm. The applications of LED chips are no longer limited to general lighting or as backlights for LCD screens. Using LED chips directly as pixels in LED displays has the potential to become a trend in next-generation displays.

[0004] An LED display requires millions or even tens of millions of LED chips. Handling such a large number of LED chips requires rapid and precise alignment as well as highly reliable die bonding technology. Summary of the Invention

[0005] A semiconductor device includes a semiconductor stack, a protective layer on the semiconductor stack, an electrode on the semiconductor stack and electrically connected to the semiconductor stack, and a conductive bump on the electrode. The distance from the top of the conductive bump to the uppermost surface of the protective layer is defined as the thickness of the conductive bump, and the ratio of the thickness of the conductive bump to the maximum width of the conductive bump is between 0.1 and 0.4.

[0006] A method for manufacturing a semiconductor device includes providing a substrate, forming a semiconductor stack on the substrate, forming an electrode on the semiconductor stack, forming a bonding pad on the electrode, forming an adhesive on the bonding pad, providing laser energy to irradiate the bonding pad and the adhesive, melting the bonding pad to form a conductive bump on the electrode, the adhesive covering the conductive bump, and cleaning the adhesive. Simple Explanation of the Diagram

[0007] Figure 1A is a top view schematic diagram of a semiconductor element array according to an embodiment of the present invention. Figure 1B is a cross-sectional view of line segment AA' in Figure 1A. Figure 1C is a top view schematic diagram of a semiconductor element array according to another embodiment of the present invention. Figure 1D is a cross-sectional view of line segment AA' in Figure 1C. Figure 1E is a schematic cross-sectional view of a semiconductor element array according to another embodiment of the present invention. Figure 2A is a perspective view of a semiconductor element according to an embodiment of the present invention. Figure 2B is a cross-sectional view of the semiconductor element along line BB' in Figure 2A. Figure 2C is a schematic cross-sectional view of a semiconductor element according to another embodiment of the present invention. Figure 2D is a perspective view of a semiconductor element according to another embodiment of the present invention. Figure 2E is a cross-sectional view of the semiconductor element along line segment BB' in Figure 2D. Figure 3A is a top view schematic diagram of a semiconductor element according to an embodiment of the present invention. Figure 3B is a schematic cross-sectional view of the semiconductor device along the CC' line segment in Figure 3A. Figure 3C is a schematic cross-sectional view of the semiconductor device along the DD' line segment in Figure 3A. Figure 4A is a cross-sectional schematic diagram of a semiconductor element array 2000 according to an embodiment of the present invention. Figure 4B is a cross-sectional view of the semiconductor element array in Figure 4A after one semiconductor element has been removed. Figure 4C is a top view of the semiconductor element array in Figure 4A after one semiconductor element has been removed. Figure 4D is a cross-sectional schematic diagram of a semiconductor element array 3000 according to another embodiment of the present invention. Figure 4E is a cross-sectional schematic diagram of a semiconductor element array 3001 according to another embodiment of the present invention. Figures 5A to 5D are flowcharts of transferring semiconductor elements according to one embodiment of the present invention. Figures 6A to 6C are flowcharts of a transfer semiconductor element according to another embodiment of the present invention. Figures 7A-7D are flowcharts illustrating the fabrication of a semiconductor device according to an embodiment of the present invention. Figures 8A to 8D are flowcharts of the fabrication of a semiconductor device according to another embodiment of the present invention. Figure 9A is a perspective view of a semiconductor element according to another embodiment of the present invention. Figure 9B is a cross-sectional view of the semiconductor element along line segment BB' in Figure 9A. Figure 10A is a schematic diagram of a semiconductor element fixed to a target substrate according to an embodiment of the present invention. Figure 10B is a schematic diagram of a semiconductor element fixed to a target substrate according to another embodiment of the present invention. Implementation

[0008] The following embodiments will be illustrated with drawings to explain the concept of the invention. In the drawings or description, similar or identical parts are referred to by the same reference numerals, and the shape, thickness, or height of elements may be enlarged or reduced within reasonable limits in the drawings. The embodiments listed in this invention are for illustrative purposes only and are not intended to limit the scope of the invention. Any obvious modifications or changes made to this invention do not depart from the spirit and scope of the invention.

[0009] Figure 1A is a top view schematic diagram of a semiconductor element array 1000 according to an embodiment of the present invention. The semiconductor element array 1000 includes a plurality of semiconductor elements 1 arranged in an array on a substrate. The semiconductor elements 1 can be light-emitting diodes (LEDs), laser diodes (LDs), or transistors, etc. The semiconductor element array 1000 can be composed of a single type or different types of semiconductor elements 1. The substrate 10 can be a growth substrate for the semiconductor elements 1, or a carrier for the semiconductor elements 1 after the growth substrate has been removed. The substrate 10 is made of materials including, but not limited to, germanium (Ge), gallium arsenide (GaAs), indium phosphide (InP), sapphire, silicon carbide (SiC), silicon (Si), lithium aluminate (LiAlO2), zinc oxide (ZnO), gallium nitride (GaN), aluminum nitride (AlN), metals, glass, thermal release tape, UV release tape, chemical release tape, heat-resistant tape, blue tape, or tape with a dynamic release layer (DRL). Each semiconductor element 1 has a pair of conductive bumps 2a and 2b on the side away from the substrate 10 for electrical and physical connection with external circuits (e.g., circuit boards, backplanes, etc.). In the top view, the projected shape of the conductive bumps is approximately rectangular, as shown in Figures 1A and 3A.

[0010] Figure 1B is a cross-sectional view of line segment AA' in Figure 1A. The semiconductor element 1 has a pair of electrodes 3a and 3b on the side away from the substrate 10. Conductive bumps 2a and 2b are directly disposed on electrodes 3a and 3b, respectively. The upper surfaces of the conductive bumps 2a and 2b are arc-shaped and not parallel to the upper surfaces of electrodes 3a and 3b.

[0011] It is preferable that the conductive bumps 2a and 2b and the electrodes 3a and 3b are made of different materials. The electrode materials include metals, such as gold (Au), silver (Ag), copper (Cu), chromium (Cr), aluminum (Al), platinum (Pt), nickel (Ni), titanium (Ti), or alloys thereof, or stacked combinations thereof. The conductive bumps 2a and 2b may be made of low-melting-point metals or low-liquidity-melting-point alloys with a melting point or liquefaction temperature below 210°C, such as bismuth (Bi), tin (Sn), indium (In), or alloys thereof. In one embodiment, the low-melting-point metal or the low-liquidity-melting-point alloy has a melting point or liquefaction temperature below 170°C. The low-liquidity-melting-point alloy may be a tin-indium alloy or a tin-bismuth alloy.

[0012] Figure 1C is a top view schematic diagram of a semiconductor element array 1001 according to another embodiment of the present invention. The semiconductor element array 1001 includes a plurality of semiconductor elements 1 arranged in a predetermined pattern on a substrate 10. The substrate 10 has a generally circular shape. The material of the substrate can be referred to the foregoing related paragraphs. Figure 1D is a cross-sectional schematic diagram of line segment AA' in Figure 1C. An adhesive structure 4 is provided between the semiconductor element 1 and the substrate 10. The semiconductor element 1 is temporarily fixed to the substrate 10 through the adhesive structure 4. A pair of electrodes 3a and 3b are provided on the side of the semiconductor element 1 away from the substrate 10. Conductive bumps 2a and 2b are respectively directly disposed on the electrodes 3a and 3b. The upper surfaces of the conductive bumps 2a and 2b are arc-shaped and not completely parallel to the upper surfaces of the electrodes 3a and 3b. The adhesive structure 4 may contain a polymer, such as polyimide or benzocyclobutane (BCB). The materials of the conductive bumps 2a and 2b and the electrodes 3a and 3b can be referred to the relevant paragraphs above. As shown in Figure 1D, the outer edge 42 of the adhesive structure 4 is generally flush with the outermost edge 19 of the semiconductor element 1. The adhesive portion 4 has a thickness H4, approximately 2-3 μm or 1-10 μm. In another embodiment, the outer edge 42 is not flush with the outermost edge 19 of the semiconductor element 1, and the adhesive structure 4 may be recessed or protruding relative to the outermost edge 19 of the semiconductor element 1. The adhesive structure 4 has a maximum width W5, and the semiconductor element 1 has a maximum width W6. W5 is generally equal to W6. In another embodiment, W5 may be less than or greater than W6.

[0013] Figure 1E is a cross-sectional schematic diagram of a semiconductor element array 1001' according to another embodiment of the present invention. The semiconductor element array 1001' includes a plurality of semiconductor elements 1 arranged in a predetermined pattern on a substrate 10. The material of the substrate can be referred to in the foregoing relevant paragraphs. An adhesive structure 4 is provided between the semiconductor element 1 and the substrate 10. The semiconductor element 1 is temporarily fixed to the substrate 10 through the adhesive structure 4. A pair of electrodes 3a and 3b are provided on the side of the semiconductor element 1 away from the substrate 10. Conductive bumps 2a and 2b are respectively directly disposed on the electrodes 3a and 3b. The material of the adhesive structure 4, the structure and material of the conductive bumps 2a and 2b and the electrodes 3a and 3b can be referred to in the foregoing relevant paragraphs. As shown in Figure 1E, the adhesive structure 4 has a raised portion 43 and a continuous portion 44. The continuous portion 44 is a continuous structure and is continuously distributed on the substrate 10 to pass under all semiconductor elements 1 and in the area between two adjacent semiconductor elements 1. Each raised portion 43 is located between the semiconductor element 1 and the continuous portion 44, protruding upward from the continuous portion 44 and corresponding to a single semiconductor element 1. The outer edge 42 of the raised portion 43 is flush with or close to the outermost edge 19 of the semiconductor element 1. The adhesive portion 4 has a thickness H4, approximately 2-3 μm. The continuous portion 44 has a thickness H5, greater than 0 μm and less than 1 μm. In another embodiment, the outer edge 42 is not flush with the outermost edge 19 of the semiconductor element 1, and the raised portion 43 may be recessed or protruding relative to the outermost edge 19 of the semiconductor element 1. The raised portion 43 has a maximum width W5, and the semiconductor element 1 has a maximum width W6. W5 is substantially equal to W6. In another embodiment, W5 may be less than or greater than W6.

[0014] Figure 2A is a perspective view of a semiconductor element 1 according to an embodiment of the present invention. The maximum side length of the semiconductor element 1 is no greater than 100 μm or 50 μm. For example, the maximum side length of the semiconductor element is approximately 40 μm and the width is approximately 20 μm. The conductive bumps 2a and 2b have opposite polarities (positive and negative), and the minimum horizontal distance D between them is less than 40 μm. For example, the maximum side length of the semiconductor element is approximately 40 μm, and D is approximately 15 μm. The conductive bumps 2a and 2b completely cover the electrodes (such as electrodes 3a / 3b in Figure 1B) and have an outwardly convex arc shape and a top 21a and 21b. Referring to Figure 1A, the tops 21a and 21b are approximately located at the geometric center of the conductive bumps 2a and 2b and / or the electrodes.

[0015] Figure 2B is a cross-sectional view of the semiconductor element along line BB' in Figure 2A. The semiconductor element 1 is placed on substrate 10 and has a semiconductor stack 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, and a second conductive bump 2b. The outermost edge 19 of the semiconductor stack 14 is an inclined surface, inclined to substrate 10. The semiconductor stack 14 includes a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13. The first semiconductor layer 11 and the second semiconductor layer 13 can respectively provide electrons and holes, allowing electrons and holes to recombine in the active layer 12 to emit light. The first semiconductor layer 11, the active layer 13, and the second semiconductor layer 13 can contain III-V group semiconductor materials, such as AlxInyGa(1-xy)N or AlxInyGa(1-xy)P, where 0≦x, y≦1; (x+y)≦1. Depending on the material of the active layer, the LED chip can emit red light with a peak value between 610 nm and 650 nm, green light with a peak value between 530 nm and 570 nm, cyan light with a peak value between 500 nm and 485 nm, blue light with a peak value between 450 nm and 490 nm, violet light with a peak value between 400 nm and 450 nm, or ultraviolet light with a peak value between 280 nm and 400 nm. The maximum thickness of the semiconductor stack 14 is approximately equal to or less than 10 μm. In one embodiment, the lower surface 17 of the first semiconductor layer 11 is in contact with the substrate 10 and is a rough surface. In another embodiment, the lower surface 17 of the first semiconductor layer 11 is a generally flat surface (not shown). In another embodiment, substrate 10 is a growth substrate for epitaxially growing semiconductor stack 14. The entire upper surface of substrate 10 facing semiconductor stack 14 is a rough surface (not shown), for example, a patterned sapphire substrate (PSS). In one embodiment, semiconductor element 1 includes a carrier (not shown) located below semiconductor stack 14 and used to support semiconductor stack 14. The carrier can be an epitaxial growth substrate or a non-epitaxy growth substrate of semiconductor stack 14. The material of the carrier can be referred to the relevant paragraphs above regarding substrate 10, and the selection of materials should conform to theoretical and practical feasibility.

[0016] The semiconductor stack 14 has a platform 16 for exposing the first semiconductor layer 11 outside the active layer 12 and the second semiconductor layer 13. A protective layer 15 covers the upper surface of the second semiconductor layer 13, the sidewalls of the first semiconductor layer 11, the sidewalls of the active layer 12, the sidewalls of the second semiconductor layer 13, and the upper surface of the first semiconductor layer 11 located in the platform 16. The protective layer 15 can be in direct contact with the substrate 10. In another embodiment, the protective layer 15 does not contact the substrate 10. The protective layer 15 has a first opening 5a in the platform 16 to expose a portion of the first semiconductor stack 11. The protective layer 15 has a second opening 5b on the second semiconductor layer 13 to expose a portion of the second semiconductor layer 13. A first electrode 3a is located in the platform 16, having a portion formed on the protective layer 15, covering the protective layer 15 located in the platform 16 and a portion of the protective layer 15 located outside the platform 16. The first electrode 3a has a first recess 6a formed in the first opening 5a and is electrically connected to the first semiconductor layer 11. The first electrode 3a has a stepped shape at the position of platform 16. The second electrode 3b has a portion on the protective layer 15 outside the second opening 5b, and a second recess 6b is formed in the second opening 5b and electrically connected to the second semiconductor layer 13.

[0017] The protective layer 15 can be a single-layer or multi-layer structure and has electrically insulating properties. The single-layer structure can contain oxides, nitrides, or polymers. Oxides can contain aluminum oxide (Al₂O₃), silicon oxide (SiO₂), titanium dioxide (TiO₂), tantalum pentoxide (Ta₂O₅), or aluminum oxide (AlO₂x). Nitrides can contain aluminum nitride (AlN) or silicon nitride (SiN₂x). Polymers can contain polyimide or benzocyclobutane (BCB). The multi-layer structure can contain aluminum oxide (Al₂O₃), silicon oxide (SiO₂), titanium dioxide (TiO₂), niobium pentoxide (Nb₂O₅), silicon nitride (SiN₂x), or combinations thereof. The multi-layer structure can also form a distributed Bragg reflector (DBR).

[0018] Referring to Figure 2B, the first conductive bump 2a is formed directly above the first electrode 3a. The first conductive bump 2a can completely or partially fill the first recess 6a of the first electrode 3a, and its outermost surface 22a has a macroscopically smooth and convex arc shape. The first conductive bump 2a has a top 21a, which is the region where the first conductive bump 2a is furthest from the substrate 10. As shown, the outermost surface 22a of the first conductive bump 2a is not parallel to the lowermost surface of the first conductive bump 2a, nor is it parallel to the upper surface of the first electrode 3a. The lower surface 17 of the first semiconductor layer 11 is a rough surface, and the roughness of the outermost surface 22a of the first conductive bump 2a is smaller than the roughness of the lower surface 17 of the first semiconductor layer 11, and also smaller than the roughness of the upper surface of the first electrode 3a.

[0019] Referring to Figure 2B, the second conductive bump 2b directly covers the second electrode 3b. The second conductive bump 2b can completely or partially fill the second recess 6b of the second electrode 3b, and its outermost surface 22b has a macroscopically smooth and convex arc shape. The second conductive bump 2b has a top 21b, which is the area where the second conductive bump 2b is furthest from the substrate 10. As shown, the outermost surface 22b of the second conductive bump 2b is not parallel to the lowermost surface of the second conductive bump 2b, nor is it parallel to the upper surface of the second electrode 3b. The roughness of the outermost surface 22b of the second conductive bump 2b is smaller than the roughness of the lower surface 17 of the first semiconductor layer 11, and also smaller than the roughness of the upper surface of the second electrode 3b. Preferably, the top 21a of the first conductive bump 2a and the top 21b of the second conductive bump 2b are approximately at the same horizontal height, which is beneficial for the subsequent stable fixing of the semiconductor element 1 to the substrate. However, in practice, a certain degree of height difference is permissible within the limits of the manufacturing process. The lowest surfaces of the first conductive bump 2a and the second conductive bump 2b are typically conformally formed on the first electrode 3a and the second electrode 3b, respectively, and their lowest points are often not at the same horizontal level. Referring to Figure 2B, the vertical distance from the top 21a of the first conductive bump 2a to the uppermost surface 151 of the protective layer 15 can be measured as a first thickness H1. The first conductive bump 2a has a first (maximum) width W1, and H1 / W1 is between 0.1 and 0.4, preferably between 0.1 and 0.25. The vertical distance from the top 21b of the second conductive bump 2b to the uppermost surface 151 of the protective layer 15 can be measured as a second thickness H2. The second conductive bump 2b has a second (maximum) width W2, and H2 / W2 is between 0.1 and 0.4, preferably between 0.1 and 0.25. H1 / W1 and H2 / W2 can be the same or different. The second thickness H2 of the second conductive bump 2b is 4~6 μm.

[0020] If the first conductive bump 2a is filled more densely into the first recess 6a of the first electrode 3a, and the second conductive bump 2b is filled more densely into the second recess 6b of the second electrode 3b, the reliability of the physical and electrical connection between the semiconductor element 1 and the circuit board (without display) can be improved, and the probability of failure can be reduced. Specifically, if the structure of the semiconductor element 1 is as shown in Figure 2B but without conductive bumps 2a / 2b, when the semiconductor element 1 is fixed to the circuit board with solder, the solder between the first electrode 3a and the circuit board (without display) will occasionally generate holes near the first recess 6a; the solder between the second electrode 3b and the circuit board (without display) will occasionally generate holes near the second recess 6b. These holes will reduce the bonding strength between the semiconductor element 1 and the circuit board.

[0021] If a heat treatment step is involved in the formation of the conductive bumps, under specific material selection combinations for the conductive bumps and electrodes, discretely distributed metal particles may form inside the conductive bumps after the heat treatment step, as shown in Figure 2C. Figure 2C is a schematic cross-sectional view of a semiconductor element 1 according to another embodiment of the present invention. The structure of Figure 2C can be referred to the description in Figure 2B and related paragraphs. Discretely distributed, irregularly sized, and irregularly shaped particles 7 are scattered within the first conductive bump 2a and the second conductive bump 2b. The material of the particles 7 is different from that of the conductive bumps 2a and 2b, but is the same as part of the material of the electrodes 3a and 3b, such as gold, platinum, or alloys of the aforementioned materials. The shape of the particles 7 can be elongated, polygonal, leaf-shaped, or teardrop-shaped.

[0022] Figures 2D-2E are schematic diagrams of a semiconductor element 1' according to another embodiment of the present invention. Its structure can be referred to the description in Figures 2A-2B and related paragraphs. As shown in Figure 2D, conductive bumps 2a and 2b have an outwardly convex arc shape and tops 21a and 21b. Tops 21a and 21b are not at the same horizontal height. Top 21a is slightly lower than top 21b. Figure 2E is a schematic cross-sectional view of the semiconductor element 1' along line segment BB' in Figure 2D. Conductive bump 2a is located above platform 16. When the volumes of conductive bump 2a and conductive bump 2b are approximately the same, because part of conductive bump 2a needs to fill platform 16, the top 21a of conductive bump 2a is slightly lower than the top 21b of conductive bump 2b. In one embodiment, the first thickness H1 of the first conductive bump 2a is 0.4-1 μm smaller than the first thickness H1 of the first conductive bump 2a.

[0023] Figure 3A is a top view of a semiconductor element 1 according to an embodiment of the present invention. Figure 3B is a cross-sectional view of the semiconductor element 1 along line segment CC' in Figure 3A. Figure 3C is a cross-sectional view of the semiconductor element 1 along line segment DD' in Figure 3A. The semiconductor element 1 includes a semiconductor stack 14, and electrodes 3 and conductive bumps 2 located on the semiconductor stack 14. In Figure 3A, the conductive bumps 2 and electrodes 3 are generally rectangular in shape. In the cross-sectional view, the outermost surface 22 of the conductive bumps 2 has a macroscopically smooth and convex arc shape. As shown in Figure 3B, the outermost surface 22 is in contact with the upper surface of the electrode 3, and the tangent of the conductive bumps 2 at the contact point forms an angle θ1 with the upper surface of the electrode 3. The angle θ1 is approximately 90 degrees, preferably 70 degrees < θ1 < 90 degrees. As shown in Figure 3C, the outermost surface 22 is in contact with the upper surface of the electrode 3, and the tangent of the conductive bump 2 at the contact point forms an angle θ2 with the upper surface of the electrode 3. The angle θ2 < the angle θ1, preferably 30 degrees < θ2 < 70 degrees. In other words, as shown in Figure 3A, the cross-sectional shape of the conductive bump 2 in the direction parallel to the side length of the electrode 3 is different from the cross-sectional shape of the electrode 3 in the diagonal direction.

[0024] Figure 4A illustrates a semiconductor element array 2000 according to an embodiment of the present invention. The semiconductor element array 2000 includes a plurality of semiconductor elements 1 (for simplicity, only three semiconductor elements 1 in one dimension are shown in the figure; however, the semiconductor element array 2000 may include m*n semiconductor elements 1, where m and n are positive integers greater than or equal to 0, and m and n are not simultaneously 0) and a carrier 30. The semiconductor elements 1 are disposed on the carrier 30 with conductive bumps 2 facing the carrier 30 (or, as in flip-chip), respectively. The carrier 30 supports and fixes the semiconductor elements 1. The carrier 30 includes a carrier plate 31 and an adhesive layer 32. The carrier plate 31 may be made of glass, sapphire, or a polymer material, or a light-transmitting material that can be penetrated by light of a specific wavelength emitted by a light-emitting diode or laser diode. The adhesive layer 32 may include thermally removable adhesive, photodissociative adhesive, chemically removable adhesive, heat-resistant adhesive, blue film, or tape with a power release layer. In another embodiment, the adhesive layer may also comprise a polymer, such as polyimide or benzocyclobutane (BCB). When the aforementioned semiconductor element 1 is arranged on the carrier 30 in a flip-chip orientation, the smooth, convex outermost surface 22 of its conductive bump 2 directly contacts the adhesive layer 32. As shown in the figure, the conductive bump 2 is partially embedded in the adhesive layer 32, with the embedded portion having a maximum width W3 parallel to the surface of the adhesive layer 32, while the conductive bump 2 itself has a maximum width W4, where W4 > W3. Furthermore, the outermost surface 22 of the conductive bump 2 is smooth and arc-shaped. In a selected projection direction, the projected area of ​​the portion of the conductive bump 2 embedded in the adhesive layer (such as the area of ​​the indentation 34 in Figure 4C) is smaller than the area of ​​the electrode, and the adhesion is lower, which is beneficial for the subsequent transfer process of moving the semiconductor element 1 from the carrier 30 to another location. The transfer process of the semiconductor element 1 will be described in later paragraphs.

[0025] Figures 4B and 4C show the side and top views of the semiconductor element array 2000 in Figure 4A after removing a single semiconductor element 1. Referring to Figure 4C, from the top view, a removal region 33 (as shown by the dashed line) can be defined on the upper surface of the carrier 30, representing the area exposed on the carrier 30 after the semiconductor element 1 is removed, i.e., the projected area of ​​the semiconductor element 1 in the top view. The removal region 33 contains an indentation 34. The indentation 34 is the area where the adhesive layer 32 is pressed into by the conductive bump 2, and the indentation 34 has a projected area in the top view. According to experimental results, when the ratio of the projected area of ​​the conductive bump indentation 34 to the projected area of ​​the semiconductor element 1 is less than 0.2, the semiconductor element 1 is more easily picked up from the carrier 30 and moved to other positions.

[0026] Figures 4D-4E illustrate a semiconductor element array according to another embodiment of the present invention. Figure 4D shows a semiconductor element array 3000, which can be referred to in the description of Figure 4A and related paragraphs. The semiconductor element array 3000 includes a plurality of semiconductor elements 1 and a carrier 30. The carrier 30 includes a carrier plate 31 and an adhesive layer 32. The semiconductor elements 1 are disposed on the carrier 30 with conductive bumps 2 facing the carrier 30. The conductive bumps 2 and electrodes 3 are completely embedded in and completely covered by the adhesive layer 32. The adhesive layer 32 also covers the lower surface of the semiconductor elements 1 not covered by the electrodes 3. By being temporarily fixed to the adhesive layer 32, the relative positions between the plurality of semiconductor elements 1 are maintained and are less likely to change due to subsequent processes. Figure 4E shows a semiconductor element array 3001, which can be referred to in the description of Figure 4D and related paragraphs. The semiconductor element array 3001 includes a plurality of semiconductor elements 1 and a carrier 30. The carrier 30 includes a carrier plate 31 and a plurality of separate adhesive layers 32, each adhesive layer 32 corresponding to a semiconductor element 1 in horizontal position and width. A channel 33 with a value greater than 0 is provided between two adjacent adhesive layers 32. The plurality of semiconductor elements 1 are arranged on the carrier 30 with conductive bumps 2 facing the carrier 30. The conductive bumps 2 and electrodes 3 are completely embedded in and fully covered by the adhesive layers 32. The adhesive layers 32 also cover the lower surface of the semiconductor element 1 not covered by the electrodes 3.

[0027] Figures 5A-5D are schematic diagrams illustrating the steps of transferring semiconductor element 1 according to an embodiment of the present invention. Figure 5A shows that a plurality of semiconductor elements 1 are arranged in an array on a carrier 30. Each semiconductor element 1 is in contact with the adhesive layer 32 of the carrier 30 via a portion of the surface of a conductive bump 2 and is temporarily fixed to the carrier 30. A gripping tool 40 is provided to move the semiconductor element 1 from the carrier 30 to another location. The gripping tool 40 has a plurality of gripping portions 41, each gripping portion 41 corresponding to the position of the semiconductor element 1 to be gripped. As shown in Figure 5B, the gripping tool 40 moves closer to the plurality of semiconductor elements 1, and after the gripping portion 41 contacts the semiconductor element 1, it moves upward to remove the semiconductor element 1 gripped by the gripping portion 41 from the carrier 30. It is worth noting that the adhesion between the gripping portion 41 and the semiconductor element 1 must be greater than the adhesion between the semiconductor element 1 and the carrier 30 at the time of the gripping step. Semiconductor elements 1 that are not contacted by the gripping portion 41 remain on the carrier 30. As shown in Figure 5C, the gripping tool 40, together with the semiconductor element 1 temporarily fixed on the gripping part 41, moves to a preset position above the target substrate 50. At this preset position, the semiconductor element 1 can directly or indirectly contact the target substrate 50 and is ultimately placed or fixed directly on the target substrate 50. As shown in Figure 5D, the semiconductor element 1 leaves the gripping tool 40 and remains on the target substrate 50, while the gripping tool 40 can move to the same or different carriers 30 to grip other semiconductor elements 1. The transferred semiconductor element 1 is positioned on the target substrate 50 with the conductive bumps 2 facing the target substrate 50. The target substrate 50 can be a circuit board used in a display, a TFT substrate, a substrate with a redistribution layer (RDL), or a sub-mount of a package. In another embodiment, the target substrate 50 can be a temporary carrier similar to the aforementioned carrier 30. In Figures 5A to 5D, the contact mode between the semiconductor element 1 and the carrier 30 is not limited to the state shown in Figure 4A, but can also be the state shown in Figures 4D and 4E.

[0028] Figures 6A-6C are schematic diagrams illustrating the steps of transferring a semiconductor element 1 according to another embodiment of the present invention. Figure 6A shows a plurality of semiconductor elements 1 placed in an array on a carrier 30. Each semiconductor element 1 is in contact with the adhesive layer 32 of the carrier 30 via a portion of the surface of a conductive bump 2 and is temporarily fixed to the carrier 30. Next, the structure of Figure 6A is flipped or the target substrate 50 is moved so that the semiconductor element 1 is positioned between the carrier 30 and the target substrate 50, but the semiconductor element 1 is not in direct contact with the target substrate 50; for example, as shown in Figure 6B, the semiconductor element 1 is suspended above the target substrate 50. A laser energy L1 is provided to irradiate a specific location of the adhesive layer 32 from the side of the carrier plate 31, this specific location corresponding to a semiconductor element 1 to be transferred. The laser energy L1 can be a single-shot laser or a multi-shot laser. In one embodiment, a single location of a semiconductor element 1 or an adhesive layer 32 can be irradiated by one or more lasers in one irradiation process. In another embodiment, multiple locations of a semiconductor element 1 or an adhesive layer 32 can be irradiated with one or more lasers during an irradiation process. As shown in Figure 6C, the adhesive layer 32 irradiated by laser energy L1 causes a decrease in adhesion between the semiconductor element 1 and the adhesive layer 32, or the downward force on the semiconductor element 1 exceeds the adhesion of the adhesive layer 32 to the semiconductor element 1, causing the semiconductor element 1 to fall from the carrier 30 onto the target substrate 50. The transferred semiconductor element 1 is positioned on the target substrate 50 with conductive bumps 2 away from the target substrate 50. In another embodiment, in the step of Figure 6B, the semiconductor element 1 can first directly contact the target substrate 50 before being irradiated with laser energy L1, thus allowing for more precise alignment of the semiconductor element 1 with the target substrate 50. After the step of Figure 6C, a removal step can be selectively applied to the semiconductor element 1 to remove residual adhesive layer 32 on the semiconductor element 1. The removal step can include dry etching or wet etching; dry etching can be an oxygen plasma etching process. In Figures 6A to 6C, the contact mode between the semiconductor element 1 and the carrier 30 is not limited to the state shown in Figure 4A, but can also be the state shown in Figures 4D and 4E.

[0029] Figures 7A-7D are schematic diagrams illustrating the steps of fabricating a semiconductor element 1 according to an embodiment of the present invention. As shown in Figure 7A, a plurality of semiconductor units 100 are disposed on a substrate 10. Each semiconductor unit 100 includes a semiconductor stack 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The semiconductor unit 100 is disposed on the substrate 10 with the first electrode 3a and the second electrode 3b away from the substrate 10. Each of the first electrode 3a and the second electrode 3b has a recess, and the relevant structural description can be found in the foregoing paragraphs. Next, two separate clumps of adhesive 80 are formed on the first electrode 3a and the second electrode 3b, respectively. The adhesive 80 includes a resin 81 and a plurality of conductive particles 82 dispersed in the resin 81. In one embodiment, the adhesive 80 can be formed by printing, coating, spraying, or dispensing. The printing method can include aerosol jet printing or inkjet printing. The resin 81 comprises a thermosetting plastic and a flux. The thermosetting plastic may be epoxy, silicone, polymethyl methacrylate, or episulfide. The conductive particles 82 have a melting point lower than the curing temperature of the resin 81. In one embodiment, the conductive particles 82 may be made of gold, silver, or copper. In another embodiment, the conductive particles 82 may be made of a low-melting-point metal or an alloy with a low liquefaction point. In one embodiment, the low-melting-point metal or alloy with a low liquefaction point has a melting point or liquefaction temperature below 210°C. In another embodiment, the low-melting-point metal or alloy with a low liquefaction point has a melting point or liquefaction temperature below 170°C. The low-liquefaction-point alloy may be a tin alloy, such as a tin-indium alloy or a tin-bismuth alloy.

[0030] As shown in Figure 7B, a laser energy L2 is used to irradiate the adhesive 80 or its adjacent area to heat the adhesive 80. The laser energy L2 may include an ultraviolet (UV) laser beam, a visible laser beam, or an infrared (IR) laser beam. In one embodiment, the laser energy L2 is a pulsed infrared laser beam with a wavelength in the range of 750 nm to 2,000 nm, a spot size of 0.004 to 0.002 cm², a beam diameter of 100 to 500 μm, a pulse width of less than 20 ms, a repetition frequency of 500 to 4000 Hz, a duty cycle of 1% to 10%, a laser power of 100 W, and a laser energy of 595 to 850 J / cm². As shown in Figure 7C, during the heating process, conductive particles 82 accumulate on the first electrode 3a and the second electrode 3b, forming a first conductive bump 2a and a second conductive bump 2b with convex outer surfaces. Resin 81 then moves to the area 18 between the first conductive bump 2a, the second conductive bump 2b, and the first electrode 3a and the second electrode 3b. After heating, the first conductive bump 2a and the second conductive bump 2b solidify, while the resin 81 covering them also heats up but is not fully solidified, remaining in a liquid or semi-liquid state. Next, as shown in Figure 7D, a cleaning step is performed to remove the uncured resin 81, exposing the first conductive bump 2a and the second conductive bump 2b to the external environment for subsequent transfer and contact with the carrier plate. The cleaning step can be carried out using solvents, which may include N-methylpyrrolidinone (NMP), methyl ethyl ketone (MEK), acetone (ACE), or isopropyl alcohol (ACE).

[0031] Figures 8A-8D are schematic diagrams illustrating the steps of fabricating a semiconductor element 1 according to another embodiment of the present invention. As shown in Figure 8A, a plurality of semiconductor units 100 are disposed on a substrate 10. Each semiconductor unit 100 includes a semiconductor stack 14, a protective layer 15, a first electrode 3a, and a second electrode 3b. The semiconductor unit 100 is disposed on the substrate 10 with the first electrode 3a and the second electrode 3b away from the substrate 10. Each of the first electrode 3a and the second electrode 3b has a recess, and the relevant structural description can be found in the foregoing paragraphs. A first bonding pad 23a and a second bonding pad 23b are formed on the first electrode 3a and the second electrode 3b respectively by electroplating, chemical plating, or vapor deposition. The upper surface 24a of the first bonding pad 23a and the upper surface 24b of the second bonding pad 23b are substantially conformal to the upper surfaces of the first electrode 3a and the second electrode 3b, that is, their outlines are similar, and they have recesses and / or rough textures. A single clump of adhesive 83 is formed on the semiconductor cell 100, the first bonding pad 23a, and the second bonding pad 23b. In this example, adhesive 83 contains only resin. In another embodiment, adhesive 83 contains resin and a lower concentration of conductive particles (compared to the conductive particles in Figure 7A). In one embodiment, adhesive 80 can be formed by printing, coating, spraying, or dispensing. Printing methods can include aerosol printing or inkjet printing. The materials of the first bonding pad 23a and the second bonding pad 23b can be referred to the relevant paragraphs concerning the conductive bumps 2a and 2b. The material of the resin can be referred to the relevant paragraphs.

[0032] As shown in Figure 8B, a laser energy L3 is used to irradiate the positions of the first bonding pad 23a and the second bonding pad 23b to heat the adhesive 83, the first bonding pad 23a, and the second bonding pad 23b. The laser energy L3 can include an ultraviolet (UV) laser beam, a visible laser beam, or an infrared (IR) laser beam. In one embodiment, the laser energy L3 is an infrared laser beam with a wavelength in the range of 750 nm to 2,000 nm. As shown in Figure 8C, during the heating process, the first bonding pad 23a and the second bonding pad 23b are heated and melted into the adhesive 83, and accumulate on the first electrode 3a and the second electrode 3b (if the resin contains conductive particles, the conductive particles will also partially or completely move towards the first electrode 3a and the second electrode 3b after heating), forming a first conductive bump 2a and a second conductive bump 2b with an outwardly convex arc-shaped outer surface. The adhesive 83 then moves to the region 18 between the first conductive bump 2a, the second conductive bump 2b, and the first electrode 3a and the second electrode 3b. Upon heating, the first conductive bump 2a and the second conductive bump 2b solidify, while the adhesive 83 (or resin) covering them also heats up but is not yet fully solidified, remaining in a liquid or semi-liquid state. Next, as shown in Figure 8D, a cleaning step is performed to remove the uncured adhesive 83 (or resin), exposing the first conductive bump 2a and the second conductive bump 2b to the external environment for subsequent transfer and contact with the carrier plate. The cleaning step can be referred to the relevant paragraphs in Figure 7D above.

[0033] In another embodiment, during the cleaning steps of Figures 7D and 8D, if the adhesive between the conductive bumps 2a and 2b is not completely removed and remains on the semiconductor element 100, the maximum horizontal height of the residual adhesive is preferably not higher than the conductive bumps 2a and 2b to avoid affecting subsequent transfer and die bonding processes. Figure 9A is a perspective view of a semiconductor element 20 according to another embodiment of the present invention. Figure 9B is a cross-sectional view of the semiconductor element 20 in Figure 9A along line segment BB'. Referring to Figure 9A, the upper side of the semiconductor element 20 has two separate first conductive bumps 2a and second conductive bumps 2b. Between the first conductive bumps 2a and the second conductive bumps 2b, at least one clump of residual adhesive 84 covers the semiconductor element 20. In the top view, the residual adhesive 84 has an irregular shape and a variable area. Referring to Figure 9B, the semiconductor element 20 has a semiconductor stack 14, a protective layer 15, a first electrode 3a, a second electrode 3b, a first conductive bump 2a, and a second conductive bump 2b. The outermost edge 19 of the semiconductor stack 14 is an inclined surface, inclined to the substrate 10. The semiconductor stack 14 includes a first semiconductor layer 11, an active layer 12, and a second semiconductor layer 13. Residual adhesive 84 is located on the protective layer 15 between the first conductive bump 2a and the second conductive bump 2b. The uppermost surface of the residual adhesive 84 is not higher than the highest horizontal height of the first conductive bump 2a and the second conductive bump 2b, and has a rough outer surface. Because the height of the residual adhesive 84 does not exceed the conductive bumps 2a and 2b, it will not affect subsequent transfer and die bonding processes.

[0034] Figure 10A is a schematic diagram of a semiconductor element 1 being die-bonded to a target substrate 51 according to an embodiment of the present invention. The target substrate 51 can be a circuit board with conductive lines used in a display, a TFT substrate, a substrate with a redistribution layer (RDL), or a sub-substrate of a package. The target substrate 51 has a plurality of conductive connection pads 52. The semiconductor element 1 can be any of the aforementioned structures. The conductive bumps are heated, melted, and solidified to form a bonding layer 53 to connect the semiconductor element 1 and the conductive connection pads 52. The semiconductor element 1 can receive power and / or drive signals through the conductive connection pads 52 and the bonding layer 53. The bonding layer 53 can selectively cover the side surface 521 of the conductive connection pads 52. During the process of heating the conductive bumps to form the bonding layer 53, due to the adjustment of process parameters such as heating temperature and heating time, dispersed metal particles may appear in the bonding layer 53. Figure 10B is a schematic diagram of a semiconductor element 1 being die-bonded to a target substrate 51 according to another embodiment of the present invention. After the bonding layer 53 is solidified, irregular particles 8 appear in the bonding layer 53. In other words, the bonding layer 53 contains discretely distributed, irregularly shaped particles 8. The material of these particles 8 differs from that of the bonding layer 53, but is the same as a portion of the material of the electrodes 3a, 3b, and / or the conductive pads 52 of the semiconductor element 1, such as gold, platinum, or alloys of the aforementioned materials. In one embodiment, the heat curing method can apply a laser energy, which can include an ultraviolet (UV) laser beam, a visible laser beam, or an infrared (IR) laser beam. In one embodiment, the infrared laser beam has a wavelength in the range of 750 nm to 2,000 nm.

[0035] The embodiments described above are merely for illustrating the technical ideas and features of the present invention. Their purpose is to enable those skilled in the art to understand the content of the present invention and implement it accordingly. They should not be used to limit the patent scope of the present invention. That is, all equivalent changes or modifications made in accordance with the spirit disclosed in the present invention should still be covered within the patent scope of the present invention.

[0036] 1, 20: Semiconductor components 2, 2a, 2b: Conductive bumps 3, 3a, 3b: Electrodes 4: Adhesive structure 5a: First opening 5b: Second opening 6a: First recess 6b: Second recess 7, 8: Particles 10:Substrate 11: First semiconductor layer 12: Active layer 13: Second semiconductor layer 14: Semiconductor stack 15: Protective layer 16: Platform 17: Lower surface 18: Area 19: Outermost edge 21, 21a, 21b: Top 22, 22a, 22b: Outermost surface 23a: First joint pad 23b: Second joint pad 24a, 24b: Upper surface 30: Carrier 31: Support plate 32: Adhesive layer 33: Area 34: Indentation 40: Scraping tools 41: Grabbing Department 50, 51: Target substrate 52: Conductive connection pad 53: Bonding layer 80, 84: Rubber compound 81, 83: Resin 82: Conductive particles 151:Top surface 521: Side surface 1000, 1001, 1001', 2000: Semiconductor element arrays θ1, θ2: included angle D: Distance H1, H2, H3, H4, H5: Thickness L1, L2, L3: Laser Energy W1, W2, W3, W4: Width

Claims

1. A method of fabricating a semiconductor device, comprising: providing a substrate; forming a semiconductor stack on the substrate; forming an electrode on the semiconductor stack; forming a resin on the electrode; forming a conductive bump on the electrode, wherein the conductive bump is covered by the resin; and cleaning the resin.

2. The method for manufacturing a semiconductor device as described in claim 1, wherein the cleaning step comprises cleaning the resin with a solvent.

3. The method of manufacturing a semiconductor element as claimed in claim 1, wherein a plurality of conductive particles are distributed in the resin, and further includes a heating process to aggregate the conductive particles to form the conductive bump.

4. The method of manufacturing a semiconductor element as claimed in claim 3, wherein the heating process includes irradiating the conductive particles in the resin with a laser energy.

5. The method of manufacturing a semiconductor device as claimed in claim 4, wherein the laser energy comprises an ultraviolet laser beam, a visible laser beam, or an infrared laser beam.

6. The method of fabricating a semiconductor element as claimed in claim 1 further includes forming a bonding pad on the electrode and a heating process to form the conductive bump on the bonding pad.

7. A method for manufacturing a semiconductor element as described in claim 3 or 6, wherein the resin system is solid or semi-solid during the heating process.

8. The method of manufacturing a semiconductor device as claimed in claim 1 further includes providing a target substrate and fixing the conductive bump to the target substrate.

9. A method for providing a semiconductor device, comprising: providing a substrate; forming a semiconductor stack on the substrate; forming an electrode on the semiconductor stack; forming a conductive bump on the electrode by means of a first laser energy; providing a target substrate; and fixing the conductive bump to the target substrate by means of a second laser energy.

10. The method of manufacturing a semiconductor device as claimed in claim 9, wherein either the first laser energy or the second laser energy comprises an ultraviolet laser beam, a visible laser beam, or an infrared laser beam.

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