Multilayer ceramic capacitor, circuit board, and integrated circuit package

Abstract

This invention relates to a multilayer capacitor and a circuit board containing the multilayer capacitor. The capacitor includes a body comprising a set of interleaved dielectric layers and internal electrode layers, wherein the set includes a first internal electrode layer and a second internal electrode layer, and each internal electrode layer includes a top edge defining a body of the internal electrode layer, a bottom edge opposite to the top edge, and two side edges extending between the top edge and the bottom edge. Each internal electrode layer includes at least one lead terminal extending from the top edge of the body of the internal electrode layer and at least one lead terminal extending from the bottom edge of the body of the internal electrode layer, wherein the at least one lead terminal extending from the top edge of the body of the internal electrode layer and the at least one lead terminal extending from the bottom edge of the body of the internal electrode layer include a lateral edge aligned with a side edge of the body of the internal electrode layer. External terminals are electrically connected to the internal electrode layers, wherein the external terminals are formed on a top surface of the capacitor, a bottom surface of the capacitor opposite to the top surface of the capacitor, and extend along an end surface between the top surface and the bottom surface.

Description

Prior Technology

[0001] Multilayer capacitors are typically constructed having a plurality of dielectric layers and internal electrode layers arranged in a stack. During manufacturing, the stacked dielectric layers and internal electrode layers are pressed and sintered to achieve a substantially monolithic capacitor body. Various configurations and designs have been employed for these dielectric layers and internal electrode layers in attempts to improve the performance of such capacitors.

[0002] However, with the rapid changes in the electronics industry requiring new performance criteria, such configurations are often manipulated. Specifically, various application design considerations have created a need to redefine capacitor parameters and their performance in high-speed environments, especially given the faster and denser integrated circuits. For example, higher current, denser circuit boards, and spiraling costs all contribute to the focus on the need for better and more efficient capacitors. In addition, the design of various electronic components has been driven by the overall industry trend toward miniaturization and increased functionality.

[0003] In this regard, there is a need to provide a capacitor with improved operating characteristics. Summary of the Invention

[0004] According to one embodiment of the present invention, a multilayer capacitor is disclosed. The capacitor includes a body comprising a set of interleaved dielectric layers and internal electrode layers, wherein the set includes a first internal electrode layer and a second internal electrode layer, and each internal electrode layer includes a top edge defining a body of the internal electrode layer, a bottom edge opposite to the top edge, and two side edges extending between the top edge and the bottom edge. Each internal electrode layer includes at least one lead terminal extending from the top edge of the body of the internal electrode layer and at least one lead terminal extending from the bottom edge of the body of the internal electrode layer, wherein the at least one lead terminal extending from the top edge of the body of the internal electrode layer and the at least one lead terminal extending from the bottom edge of the body of the internal electrode layer include a lateral edge aligned with a side edge of the body of the internal electrode layer. External terminals are electrically connected to the internal electrode layers, wherein the external terminals are formed on a top surface of the capacitor and a bottom surface of the capacitor opposite to the top surface of the capacitor, and extend along an end surface between the top surface and the bottom surface.

[0005] Other features and aspects of the invention are described in more detail below. Simple Explanation of the Diagram

[0006] A complete and practicable disclosure of the invention (including the best mode for those skilled in the art) is set forth in more particular in the remainder of the specification (including reference to the accompanying drawings), in which:

[0007] Figure 1A illustrates generally top and side external perspective views of one embodiment of a capacitor comprising two external terminals according to the present invention;

[0008] Figure 1B shows a top external perspective view of one of the internal electrode layers of the capacitor in Figure 1A;

[0009] Figure 2A illustrates generally top and side perspective views of one embodiment of a capacitor comprising four external terminals according to the present invention; and

[0010] Figure 2B shows a top external perspective view of one of the internal electrode layers of the capacitor in Figure 2A. Implementation

[0011] [Cross-reference to related applications] []

[0012] This application claims the benefit of U.S. Provisional Patent Application No. 63 / 219,559, filed on July 8, 2021, the entire contents of which are incorporated herein by reference.

[0013] Those skilled in the art will understand that this description is merely one example of an embodiment and is not intended to limit the scope of the invention.

[0014] Generally, this invention relates to a multilayer capacitor. The multilayer capacitor includes at least one capacitor element within a body. Specifically, the at least one capacitor element is housed in a single, monolithic package. In this regard, the multilayer capacitor includes a set of interleaved dielectric layers and internal electrode layers. Generally, a set of interleaved dielectric layers and internal electrode layers defines a capacitor element.

[0015] The specific configuration of the capacitor element can provide several advantages. For example, the capacitor of the present invention can be mounted as a surface mount capacitor on a circuit board and can provide a smaller coverage area on the circuit board. This, in turn, allows for a reduction in the size of a circuit board.

[0016] Furthermore, in certain applications, it is desirable to maintain the lowest possible inductance (i.e., parasitic inductance). The capacitor employing the present invention allows for a significant reduction in inductance. Specifically, minimizing the distance or path of a ground connection can help reduce inductance. Generally, compared to employing multiple individual multilayer ceramic capacitors, the capacitor employing the present invention allows for at least one order of magnitude reduction in inductance. For example, compared to prior art capacitors exhibiting much larger inductance values, the capacitor employing the present invention can produce an inductance on the order of picohenry or even nanopicohenry. Generally, this inductance can be less than 1 nanohenry. Specifically, this inductance can be 900 picohenry or less, such as 750 picohenry or less, such as 500 picohenry or less, such as 400 picohenry or less, such as 250 picohenry or less, such as 100 picohenry or less, such as 50 picohenry or less, such as 25 picohenry or less, such as 15 picohenry or less, such as 10 picohenry or less. The inductance can be 1 nanopicohenry or greater, such as 25 nanopicohenry or greater, such as 50 nanopicohenry or greater, such as 100 nanopicohenry or greater, such as 250 nanopicohenry or greater, such as 500 nanopicohenry or greater, such as 750 nanopicohenry or greater. Minimizing this inductance contributes to good performance, especially good decoupling performance, particularly under high-speed transient conditions.

[0017] Additionally, the capacitor can provide the desired capacitance. Specifically, the capacitance can be 1,000 µF or less, such as 750 µF or less, such as 500 µF or less, such as 250 µF or less, such as 100 µF or less, such as 50 µF or less, such as 25 µF or less, such as 20 µF or less, such as 15 µF or less, such as 10 µF or less, such as 5 µF or less, such as 2.5 µF or less, such as 1 µF or less, such as 0.75 µF or less, such as 0.5 µF or less. The capacitance can be 1 pF or greater, such as 10 pF or greater, such as 25 pF or greater, such as 50 pF or greater, such as 100 pF or greater, such as 250 pF or greater, such as 500 pF or greater, such as 750 pF or greater, such as 900 pF or greater, such as 1 µF or greater, such as 2 µF or greater, such as 3 µF or greater, such as 5 µF or greater, such as 8 µF or greater, such as 10 µF or greater. The capacitance can be measured using common techniques known in this art.

[0018] In addition, the capacitor can provide a desired resistance. Specifically, the resistance can be 100 mOhm or less, such as 75 mOhm or less, such as 50 mOhm or less, such as 40 mOhm or less, such as 30 mOhm or less, such as 25 mOhm or less, such as 20 mOhm or less, such as 15 mOhm or less, such as 10 mOhm or less, such as 5 mOhm or less. The resistance can be 0.01 mOhm or greater, such as 0.1 mOhm or greater, such as 0.25 mOhm or greater, such as 0.5 mOhm or greater, such as 1 mOhm or greater, such as 1.5 mOhm or greater, such as 2 mOhm or greater, such as 5 mOhm or greater, such as 10 mOhm or greater. The resistance can be measured using common techniques known in this art.

[0019] As indicated above, the present invention includes a multilayer capacitor comprising a plurality of capacitive elements within a single, monolithic package. The capacitor includes a top surface and a bottom surface opposite the top surface. The capacitor also includes at least one side surface, particularly at least two side surfaces, extending between the top and bottom surfaces. The capacitor may include at least one end surface, particularly at least two end surfaces, extending between the top and bottom surfaces. Generally, the side surfaces extend along a length (L) direction and have a generally longer dimension than the end surfaces, which extend along a width (W) direction and have a generally shorter dimension. In one embodiment, the capacitor includes at least six total surfaces (e.g., a top surface, a bottom surface, two side surfaces, and two end surfaces). For example, the capacitor may have a parallelepiped shape, such as a cuboid shape.

[0020] Additionally, the capacitor may have a desired height. For example, the height may be 10 micrometers or greater, such as 25 micrometers or greater, such as 50 micrometers or greater, such as 100 micrometers or greater, such as 200 micrometers or greater, such as 250 micrometers or greater, such as 300 micrometers or greater, such as 350 micrometers or greater, such as 400 micrometers or greater, such as 450 micrometers or greater, such as 500 micrometers or greater, such as 1,000 micrometers or greater, such as 2,000 micrometers or greater. The height may also be 5,000 micrometers or less, such as 4,000 micrometers or less, such as 2,500 micrometers or less, such as 2,000 micrometers or less, such as 1,000 micrometers or less, such as 750 micrometers or less, such as 600 micrometers or less, such as 500 micrometers or less, such as 450 micrometers or less. When surrounded by a ball grid array, the height of the capacitor can be within 10% of the height (or diameter) of the balls in the ball grid array, such as within 7%, within 5%, within 3%, within 2%, or within 1%. For example, this height can be the original height before any reflow.

[0021] The capacitor may have a desired length. For example, the length may be 10 micrometers or greater, such as 25 micrometers or greater, such as 50 micrometers or greater, such as 100 micrometers or greater, such as 200 micrometers or greater, such as 250 micrometers or greater, such as 300 micrometers or greater, such as 350 micrometers or greater, such as 400 micrometers or greater, such as 450 micrometers or greater, such as 500 micrometers or greater, such as 1,000 micrometers or greater, such as 1,500 micrometers or greater, such as 2,000 micrometers or greater, such as 2,500 micrometers or greater, such as 3,000 micrometers or greater, such as 3,500 micrometers or greater, such as 4,000 micrometers or greater. The length can be 10,000 micrometers or less, such as 8,000 micrometers or less, such as 6,000 micrometers or less, such as 5,000 micrometers or less, such as 4,000 micrometers or less, such as 3,000 micrometers or less, such as 2,500 micrometers or less, such as 2,000 micrometers or less, such as 1,000 micrometers or less, such as 750 micrometers or less, such as 600 micrometers or less, such as 500 micrometers or less, such as 450 micrometers or less.

[0022] The capacitor may also have a desired width. For example, the width may be 10 micrometers or greater, such as 25 micrometers or greater, such as 50 micrometers or greater, such as 100 micrometers or greater, such as 200 micrometers or greater, such as 250 micrometers or greater, such as 300 micrometers or greater, such as 350 micrometers or greater, such as 400 micrometers or greater, such as 450 micrometers or greater, such as 500 micrometers or greater, such as 750 micrometers or greater, such as 1,000 micrometers or greater, such as 1,500 micrometers or greater, such as 2,000 micrometers or greater, such as 2,500 micrometers or greater, such as 3,000 micrometers or greater. The width can be 5,000 micrometers or less, such as 4,000 micrometers or less, such as 3,000 micrometers or less, such as 2,500 micrometers or less, such as 2,000 micrometers or less, such as 1,500 micrometers or less, such as 1,000 micrometers or less, such as 750 micrometers or less, such as 600 micrometers or less, such as 500 micrometers or less, such as 450 micrometers or less.

[0023] Generally, a multilayer capacitor contains a set of interleaved dielectric layers and internal electrode layers. The capacitor also includes external terminals electrically connected to the internal electrode layers, wherein the external terminals are formed on a top surface of the capacitor and a bottom surface of the capacitor opposite to the top surface of the capacitor and at least two opposite end surfaces.

[0024] Generally, the capacitor comprises at least one set of interleaved dielectric layers and internal electrode layers. The capacitor may also contain a second set of interleaved dielectric layers and internal electrode layers. In this regard, the capacitor may comprise at least two sets, such as at least three sets, such as at least four sets of interleaved dielectric layers and internal electrode layers. However, it should be understood that the invention may comprise any number of sets of interleaved dielectric layers and internal electrode layers and is not limited thereto. Furthermore, each set of interleaved dielectric layers and internal electrode layers may be separated from an adjacent set by a certain distance. For example, that distance may be greater than the thickness of one of the individual dielectric layers in that set. Specifically, this distance may be at least twice, such as at least three times, such as at least five times, such as at least ten times, the thickness of one of the dielectric layers in that set.

[0025] The alternating dielectric layers and internal electrode layers can form at least a portion of the body of the capacitor. By configuring the dielectric layers and internal electrode layers in a stacked or multilayered configuration, the capacitor can be referred to as a multilayer capacitor, and in particular, for example, when the dielectric layer includes a ceramic layer, it is referred to as a multilayer ceramic capacitor.

[0026] The set of interleaved dielectric layers and internal electrode layers includes dielectric layers disposed interleaved with the internal electrode layers. Specifically, the internal electrode layers include first internal electrode layers and second internal electrode layers, which are interleaved with a dielectric layer located between the internal electrode layers in a relative and spaced-apart relationship.

[0027] Generally, the thickness of the dielectric layer and the internal electrode layer is not limited and can be any thickness depending on the desired performance characteristics. For example, the thickness of the internal electrode layer can be (but is not limited to) about 500 nm or more, such as about 1 μm or more, such as about 2 μm or more to about 10 μm or less, such as about 5 μm or less, such as about 4 μm or less, such as about 3 μm or less, such as about 2 μm or less. For example, the internal electrode layer can have a thickness from about 1 μm to about 2 μm.

[0028] Furthermore, the present invention is not limited to the number of interleaved dielectric layers and internal electrode layers in each group or the number of internal electrode layers in the entire capacitor. For example, each group may contain 10 or more, such as 25 or more, such as 50 or more, such as 100 or more, such as 200 or more, such as 300 or more, such as 500 or more, such as 600 or more, such as 750 or more, such as 1,000 or more internal electrode layers. Each group may have 5,000 or fewer, such as 4,000 or fewer, such as 3,000 or fewer, such as 2,000 or fewer, such as 1,500 or fewer, such as 1,000 or fewer, such as 750 or fewer, such as 500 or fewer, such as 400 or fewer, such as 300 or fewer, such as 250 or fewer, such as 200 or fewer, such as 175 or fewer, such as 150 or fewer internal electrode layers. Furthermore, the entire capacitor may contain the aforementioned number of electrode layers.

[0029] The internal electrode layer has a top edge and a bottom edge opposite to the top edge. The internal electrode layer also has two side edges extending between the top and bottom edges. In one embodiment, the side edges, top edge, and bottom edge define a body of the internal electrode layer. Generally, this body may have a rectangular configuration or shape.

[0030] Generally, the top and bottom edges may have the same dimension (e.g., length-L direction). The side edges may have the same dimension (e.g., height-T direction). Generally, the side edges may have a dimension shorter than one of the dimensions of the top and / or bottom edges (e.g., length-L direction) (e.g., height-T direction). In this respect, the height of one side edge of the inner electrode layer extending between the top and bottom surfaces of the capacitor may be less than the length of the top and / or bottom edges of the inner electrode layer extending between the end surfaces of the capacitor. In other words, the inner electrode layer may have a top and / or bottom edge with a dimension greater than the smaller side edge dimension. In this respect, the "short" side of these layers may be aligned with the height direction of the capacitor.

[0031] The internal electrode layer has lead tabs extending from one of the main bodies of the layer. The lead tabs extend from a top edge and a bottom edge. In other words, the internal electrode layer may have lead tabs extending from the "long" side or edge of the layer. The lead tabs may extend to an edge of a dielectric layer and / or a surface of the capacitor. For example, in a stacked configuration, a front edge of the lead tabs may extend to an edge of a dielectric layer. This front edge can be used to form external terminals. Additionally, this edge may have at least one lead tab extending from it, such as at least two lead tabs, such as at least three lead tabs, such as at least four lead tabs.

[0032] Each top and bottom edge of the internal electrode layer may have an equal number of lead terminals extending therefrom. For example, each edge may have at least one lead terminal extending therefrom. In another embodiment, each edge may have at least two lead terminals extending therefrom. However, it should be understood that the invention may include any number of lead terminals extending from the internal electrode layer and is not necessarily limited thereto.

[0033] In one embodiment, at least one lead patch extends from a top edge and a bottom edge of the body of the inner electrode layer, wherein the edge of the lead patch is aligned with a side edge of the body of the inner electrode layer. For example, at least one lateral edge of the lead patch (i.e., an edge aligned along a height direction) may be substantially aligned with a side edge of the body of the inner electrode layer. In this respect, at least one lead patch may not be offset from a side edge of the inner electrode layer.

[0034] Furthermore, when more than one lead patch may exist along an edge, the lead patch may extend from the inner portion of one of the top edges and one of the bottom edges of the body of the inner electrode layer. In this respect, the lead patch may not extend directly from one side edge of the inner electrode layer. In other words, the lead patch may be offset from one side edge of the inner electrode layer. This offset may cause it to be offset and positioned between the side edges of the inner electrode layer, particularly at a location at least 50% of the length of the inner electrode layer (e.g., beyond the center of the inner electrode layer).

[0035] Lead tabs extending from the top edge of one of the respective internal electrode layers and the bottom edge of the same internal electrode layer may be offset by the same distance from one side edge. In this respect, at least one lateral edge of the lead tab (i.e., the edge aligned along a height direction) may be substantially aligned. In one embodiment, the two lateral edges of the respective lead tabs may be substantially aligned.

[0036] Similarly, the length of one lead piece extending from the top edge (i.e., extending longitudinally from one end surface to the other end surface) may be the same as the length of a corresponding lead piece extending from the bottom edge.

[0037] The length of the lead-in terminal block can be 0.3 mm or greater, such as 0.4 mm or greater, such as 0.5 mm or greater, such as 0.6 mm or greater, such as 0.7 mm or greater. The length of the lead-in terminal block can be 1.1 mm or less, such as 0.9 mm or less, such as 0.8 mm or less, such as 0.7 mm or less, such as 0.6 mm or less, such as 0.5 mm or less. When there is more than one lead-in terminal block along an edge, all lead-in terminal blocks can have the same length.

[0038] In another embodiment, each lead patch may have a different length. For example, a lead patch substantially aligned with the side edge of the inner electrode layer may have a length greater than that of a lead patch offset from the side edge of the inner electrode layer. In this regard, the ratio of the length of the lead patch aligned with the side edge of the inner electrode layer to the length of the lead patch offset from the side edge of the inner electrode layer may be 0.3 or greater, such as 0.5 or greater, such as 0.7 or greater, such as 0.9 or greater, such as 1 or greater, such as 1.1 or greater, such as 1.2 or greater, such as 1.3 or greater, such as 1.4 or greater, such as 1.5 or greater. This ratio may be 5 or less, such as 4 or less, such as 3 or less, such as 2 or less, such as 1.8 or less, such as 1.7 or less, such as 1.6 or less, such as 1.5 or less, such as 1.4 or less.

[0039] Essentially, alignment means that the offset of one side edge of a lateral edge of a first lead patch and / or a second lead patch on a top edge is within + / -10% of the offset of one side edge of a corresponding lateral edge of a first lead patch and / or a second lead patch on a bottom edge, such as within + / -5%, within + / -4%, within + / -3%, within + / -2%, within + / -1%, or within + / -0.5%.

[0040] The distance between adjacent exposed lead tabs of an internal electrode layer in a given row can be specifically designed to ensure guided terminal formation. This distance between exposed lead tabs of an internal electrode layer in a given row can be about 10 micrometers or less, such as about 8 micrometers or less, such as about 5 micrometers or less, such as about 4 micrometers or less, such as about 2 micrometers or less, such as about 1.5 micrometers or less, such as about 1 micrometer or less. The distance can also be about 0.25 micrometers or greater, such as about 0.5 micrometers or greater, such as about 1 micrometer or greater, such as about 1.5 micrometers or greater, such as about 2 micrometers or greater, such as about 3 micrometers or greater. However, it should be understood that this distance is not necessarily limited.

[0041] Additionally, the distance between adjacent columnar stacks of electrode terminals may (but is not limited to) be at least twice as large as the distance between adjacent lead terminals in a given row to ensure that dissimilar terminals do not connect together. In some embodiments, the distance between adjacent columnar stacks of exposed metallization is approximately four times the distance between adjacent exposed electrode terminals in a particular stack. However, this distance may vary depending on the desired capacitance performance and circuit board configuration.

[0042] The distance can be 0.1 mm or greater, such as 0.2 mm or greater, such as 0.3 mm or greater, such as 0.4 mm or greater, such as 0.5 mm or greater, such as 0.6 mm or greater. The distance can be 1.5 mm or less, such as 1.3 mm or less, such as 1 mm or less, such as 0.9 mm or less, such as 0.7 mm or less, such as 0.6 mm or less, such as 0.5 mm or less, such as 0.4 mm or less. In one embodiment, this distance can be determined based on the center point of each lead patch. In another embodiment, this distance can be based on the distance between adjacent lateral edges of the lead patches. Additionally, this distance can correspond to the separation distance of balls on a ball grid array.

[0043] A set of interleaved dielectric layers and internal electrode layers includes lead terminals of a first internal electrode layer and a lead terminal of a second internal electrode layer, offset from each other along a longitudinal direction. That is, the lead terminals of each internal electrode layer can be symmetrically offset a certain distance from a centerline (e.g., a longitudinal centerline or around a vertical line) of one of the internal electrode layers and / or the dielectric layer. Specifically, the lead terminals of each internal electrode layer can be symmetrically offset around a vertical line of one of the internal electrode layers and / or the dielectric layer. In any case, a gap region is formed between the lead terminals of each internal electrode layer.

[0044] Furthermore, the internal electrode layer, regardless of the number of lead terminals extending from it, can be symmetrical along a given direction. For example, the lead terminals can be symmetrical about a horizontal line passing through the center of the body of the internal electrode layer (i.e., a line extending from the center of one side edge of the internal electrode layer to the center of the other side edge).

[0045] Furthermore, as indicated herein, each internal electrode layer comprises at least two side edges. When stacked to form the body of the capacitor, these side edges of the staggered internal electrode layers may not be substantially aligned with each other. For example, the side edges may be offset from each other.

[0046] As indicated herein, the capacitor comprises a set of alternating dielectric layers and internal electrode layers. If the capacitor comprises a second set of alternating dielectric layers and internal electrode layers, in one embodiment, the distance between a first internal electrode layer of one set and the last internal electrode layer of another set may be greater than the distance between adjacent internal electrode layers within a given set. For example, the distance between a first internal electrode layer of a first set and the last internal electrode layer of a second set may be greater than the distance between a first internal electrode layer and a second internal electrode layer of the first set.

[0047] The capacitor of the present invention also includes external terminals on a top surface and a bottom surface. The capacitor also includes external terminals on opposite end surfaces. In a particular embodiment, the external terminals may not be present on one side surface of the capacitor.

[0048] The external terminals include at least one first polarity terminal and at least one second and opposite polarity terminal. The capacitor may include at least one, such as at least two, at least four, at least six, or at least eight, first polarity terminals and / or second and opposite polarity terminals on one of its top surfaces. Additionally, the capacitor may include the aforementioned number of terminals on one of its bottom surfaces.

[0049] A capacitor may have an equal number of first polarity terminals and / or second polarity terminals on its top surface and bottom surface. On the top surface of a capacitor, the number of first polarity terminals may be equal to the number of second polarity terminals of opposite polarity. On the bottom surface of a capacitor, the number of first polarity terminals may be equal to the number of second polarity terminals of opposite polarity. The total number of terminals on the top surface of the capacitor may be equal to the total number of terminals on the bottom surface of the capacitor. The total number of first polarity terminals on both the top and bottom surfaces of the capacitor may be equal to the total number of second polarity terminals on both the top and bottom surfaces of the capacitor.

[0050] Generally, the terminals of the same polarity on the bottom surface of the capacitor, corresponding to a specific set of interleaved dielectric layers and internal electrode layers, are electrically connected to the terminals of the same polarity on the top surface of the capacitor. The terminals of the same polarity located on one top surface and one bottom surface of a capacitor may not be interdigitated. In this respect, corresponding terminals of the same polarity on one top surface and one bottom surface may not be offset to a terminal position, but may instead be located directly above or below another terminal of the same polarity on the opposite top or bottom surface. In other words, the corresponding terminals of the same polarity corresponding to a specific set of interleaved dielectric layers and internal electrode layers, and particularly the corresponding lead terminals of this set, can be substantially aligned. In essence, alignment means that the offset of one side edge of a polarity terminal on a top surface is within + / -10% of the offset of one side edge of a corresponding polarity terminal on a bottom surface, such as within + / -5%, such as within + / -4%, such as within + / -3%, such as within + / -2%, such as within + / -1%, such as within + / -0.5%.

[0051] Generally, the pitch of external terminals (i.e., the nominal distance between centers, also known as center-to-center spacing) can be determined by a specific circuit board configuration. The pitch between external terminals in one direction (i.e., the x or y direction) can be the same as the pitch between adjacent external terminals in another direction (i.e., the y or x direction respectively). That is, the pitch between any two adjacent external terminals can be substantially the same as the pitch between any other two adjacent external terminals.

[0052] The pitch can be about 0.1 mm or greater, such as about 0.2 mm or greater, such as about 0.3 mm or greater, such as 0.4 mm or greater, such as about 0.5 mm or greater, such as about 0.6 mm or greater, such as about 0.7 mm or greater, such as about 0.8 mm or greater, such as about 0.9 mm or greater, such as about 1.0 mm or greater. The pitch can also be about 2.0 mm or less, such as about 1.5 mm or less, such as about 1.4 mm or less, such as about 1.3 mm or less, such as about 1.2 mm or less, such as about 1.1 mm or less, such as about 1.0 mm or less. For example, the pitch can be about 0.2 mm, about 0.4 mm, about 0.6 mm, about 0.8 mm, about 1.0 mm, about 1.2 mm, etc. Specifically, the pitch can be 0.6 mm, 0.8 mm, or 1.0 mm. In one embodiment, the pitch may be about 0.6 mm, such as 0.6 mm + / - 10%, such as + / - 5%, such as + / - 2%, such as + / - 1%. In another embodiment, the pitch may be about 0.8 mm, such as 0.8 mm + / - 10%, such as + / - 5%, such as + / - 2%, such as + / - 1%. In a further embodiment, the pitch may be about 1 mm, such as 1 mm + / - 10%, such as + / - 5%, such as + / - 2%, such as + / - 1%.

[0053] As indicated above, the extension of the leading edge of a lead patch can assist in forming an external terminal. In this regard, the pitch between a lead patch on a first internal electrode layer and a lead patch on a second internal electrode layer can be the same as the pitch mentioned above. That is, the pitch between a lead patch on a first internal electrode layer and a lead patch on a second internal electrode layer can be substantially the same as the pitch between the corresponding external terminals of the lead patches during formation.

[0054] Furthermore, the external terminals can be positioned similarly to a ball grid array configuration. For example, the external terminals can be configured to make contacts as typically used by a ball grid array, particularly a peripheral ball grid array. In this regard, the pitch of the external terminals can be the same as the pitch of a peripheral ball grid array. That is, the pitch can be within 10% of the pitch of a peripheral ball grid array, such as within 5%, such as within 2%, such as within 1%, such as within 0.5%, such as within 0.1%.

[0055] Furthermore, like a ball grid array, external terminals can be arranged in columns and rows. That is, external terminals can be arranged such that they exist in at least two columns and at least two rows. For example, external terminals can exist in at least two columns, such as at least three columns, such as at least four columns. The number of columns can be determined by the number of different sets of interleaved dielectric layers and internal electrode layers. Additionally, external terminals can exist in at least two rows, such as at least three rows, such as at least four rows. The number of rows can be determined by the number of different columnar terminals of the internal electrodes.

[0056] Furthermore, the length of one of the external terminals extending along the top surface (i.e., extending longitudinally from one end surface to the other end surface) can be the same as the length of a corresponding external terminal extending along the bottom surface.

[0057] The length of the external terminals can be 0.3 mm or greater, such as 0.4 mm or greater, such as 0.5 mm or greater, such as 0.6 mm or greater, such as 0.7 mm or greater. The length of the external terminals can be 1.1 mm or less, such as 0.9 mm or less, such as 0.8 mm or less, such as 0.7 mm or less, such as 0.6 mm or less, such as 0.5 mm or less. When there is more than one external terminal along a surface, all external terminals can have the same length. Furthermore, the length of the external terminals can be less than the length of the capacitor, such as 50% or less, such as 40% or less, such as 30% or less, such as 25% or less, such as 20% or less, such as 15% or less.

[0058] In another embodiment, each external terminal may have a different length. For example, an external terminal adjacent to one end surface may have a length greater than that of an external terminal offset from that end surface. In this regard, the ratio of the length of the external terminal adjacent to one end surface to the length of the external terminal offset from that end surface may be 0.3 or greater, such as 0.5 or greater, such as 0.7 or greater, such as 0.9 or greater, such as 1 or greater, such as 1.1 or greater, such as 1.2 or greater, such as 1.3 or greater, such as 1.4 or greater, such as 1.5 or greater. The ratio may be 5 or less, such as 4 or less, such as 3 or less, such as 2 or less, such as 1.8 or less, such as 1.7 or less, such as 1.6 or less, such as 1.5 or less, such as 1.4 or less.

[0059] Furthermore, the width of one of the external terminals extending from one side surface to an opposite side surface may be the same on both the top and bottom surfaces. For example, this width may be 0.3 mm or greater, such as 0.4 mm or greater, such as 0.5 mm or greater, such as 0.6 mm or greater, such as 0.7 mm or greater. The width of the external terminal may be 1.1 mm or less, such as 0.9 mm or less, such as 0.8 mm or less, such as 0.7 mm or less, such as 0.6 mm or less, such as 0.5 mm or less. When there is more than one external terminal along a surface, each external terminal may have the same width. Furthermore, the width of the external terminal may be smaller than the width of the capacitor.

[0060] The capacitor of the present invention can be further described with reference to the embodiments illustrated in Figures 1A to 1B and Figures 2A to 2B.

[0061] Figure 1A illustrates a capacitor 10 in a 1×2 configuration. That is, the capacitor includes two terminals along one dimension of a top surface and a bottom surface. Additionally, the capacitor includes terminals along one end surface, such that they wrap around the adjacent end surfaces from the top surface to the bottom surface. In this regard, the capacitor 10 includes a total of two external terminals 12, 14 on a top surface and two corresponding external terminals (not shown) on a bottom surface, wherein the external terminals on the top surface are electrically connected to the corresponding external terminals on the bottom surface.

[0062] The capacitor 10 in Figure 1A includes external terminals 12, 14 and a set of interleaved dielectric layers and internal electrode layers 110, as shown in Figure 1D. As shown in Figure 1B, the set of interleaved dielectric layers and internal electrode layers 110 includes internal electrode layers 105, 115 and dielectric layers (not shown) arranged in an interleaved configuration.

[0063] Generally, the internal electrode layers 105, 115 include at least one lead patch 120, 130, 140, 150 extending from a top edge and a bottom edge of one of the bodies of the internal electrode layers. Generally, the lead patches 120, 130, 140, 150 of the internal electrode layers 105, 115 extend to the top and bottom surfaces of the capacitor and assist in forming external terminals. In this respect, the lead patches 120, 130, 140, 150 may be exposed on the top and bottom surfaces of the capacitor and allow connection between the body of the internal electrode layer and the external terminals. For example, the lead patches 120, 130, 140, 150 may include front edges 123, 133, 143, 153 extending to an edge of a dielectric layer and allowing the formation of external terminals.

[0064] As shown in Figure 1B, a first internal electrode layer 105 includes a lead patch 120, 130 extending from the body 135 along a top edge 105c and a bottom edge 105d. A second internal electrode layer 115 includes a lead patch 140, 150 extending from the body 145 along a top edge and a bottom edge.

[0065] The lead terminals 120 and 130 on the top and bottom edges of the first internal electrode layer 105 can be aligned vertically. That is, the lateral edges 121 and 122 of a first lead terminal 120 along a top edge 105c can be aligned with the lateral edges 131 and 132 of a first lead terminal 130 along a bottom edge 105d opposite to the top edge 105c. In addition, these lateral edges 121 and 131 can be aligned with the side edges 105a of the internal electrode layer 105.

[0066] However, it should be understood that the two lateral edges 121, 122 of the first lead patch 120 along a top edge 105c can be aligned with the lateral edges 131, 132 of the first lead patch 130 along a bottom edge 105d opposite to the top edge 105c. In other words, the two lateral edges 122, 132 can be aligned and offset by the same distance along a bottom edge 105d and a top edge 105c from the side edges 105a to 105b.

[0067] Similarly, the lead tabs 140 and 150 on the top and bottom edges of the second internal electrode layer 115 can be aligned vertically. That is, the lateral edges 141 and 142 of a first lead tab 140 along a top edge can be aligned with the lateral edges 151 and 152 of a first lead tab 150 along a bottom edge opposite to the top edge. In one embodiment, the two lateral edges 141 and 142 of a first lead tab 140 along a top edge can be aligned with the lateral edges 151 and 152 of a first lead tab 150 along a bottom edge opposite to the top edge. The relationship between the lateral edges of a first lead tab on a top edge and a first lead tab on a bottom edge, as mentioned with respect to internal electrode layer 105, can also be applied to internal electrode layer 115.

[0068] Using this configuration, a gap can be formed between the lead patch 120 of the first internal electrode layer 105 and the lead patch 140 of the second internal electrode layer 115. Similarly, a gap can be formed between the lead patch 130 of the first internal electrode 105 and the lead patch 150 of the second internal electrode layer 115. The size of each gap can be substantially the same.

[0069] Lead terminals 120 and 140 can be arranged parallel to lead terminals 130 and 150, respectively, extending from the inner electrode layers 105 and 115, so that the lead terminals extending from the staggered electrode layers 105 and 115 can be aligned in their respective rows. For example, lead terminals 120 and 130 of the inner electrode layer 105 can be configured in a stacked configuration, while lead terminals 140 and 150 of the inner electrode layer 115 can be configured in a stacked configuration.

[0070] It will be understood that lead connector 120 is connected to external terminal 12, and lead connector 140 is connected to external terminal 14. Accordingly, each lead connector 120 will be interdigitated with its respective lead connector 140 in a manner similar to that of external terminals 12 and 14. The interdigitated lead connectors can provide multiple, adjacent current injection points to the associated main electrode portion.

[0071] Additionally, the capacitor 10 of FIG1A includes at least one first polarity terminal and at least one second and opposite polarity terminal on a top surface. Although not shown, the bottom surface includes at least one first polarity terminal and one second and opposite terminal. Also not shown, the first polarity terminal 12 extends along the end surface to the bottom surface.

[0072] As illustrated in Figures 1A and 1B, the capacitor includes two external terminals on each surface and each internal electrode layer includes at least one lead terminal extending from a top edge and a bottom edge. However, as indicated above, the invention is not limited to the number of external terminals and / or the number of lead terminals extending from a top edge and / or a bottom edge.

[0073] For example, Figure 2A illustrates a capacitor 20, which includes four external terminals on each surface and two lead terminals extending from the top and bottom surfaces of each internal electrode layer.

[0074] As shown in Figure 2A, capacitor 20 has a 1×4 configuration. That is, the capacitor includes four terminals along one dimension of the top and bottom surfaces. In this regard, the capacitor includes a total of four external terminals 22a to 22b, 24a to 24b on a top surface and four corresponding external terminals (not shown) on a bottom surface, wherein the external terminals on the top surface are electrically connected to the corresponding external terminals 22a to 22b, 24a to 24b on the bottom surface. In addition, the external terminals 22a and 24a extend from the top surface to the bottom surface along adjacent end surfaces.

[0075] The capacitor 20 of Figure 2A includes external terminals 22a to 22b, 24a to 24b and a set of interleaved dielectric layers and internal electrode layers 210, as shown in Figure 2B. As shown in Figure 2B, the set of interleaved dielectric layers and internal electrode layers 210 includes internal electrode layers 205, 215 and dielectric layers (not shown) arranged in an interleaved configuration.

[0076] Generally, the internal electrode layers 205 and 215 include at least one lead terminal piece 220a to 220b, 230a to 230b, 240a to 240b, and 250a to 250b extending from a top edge and a bottom edge of one of the bodies of the internal electrode layers. Generally, the lead terminal pieces 220a to 220b, 230a to 230b, 240a to 240b, and 250a to 250b of the internal electrode layers 205 and 215 extend to the top and bottom surfaces of the capacitor and assist in forming external terminals. In this respect, the lead terminal pieces 220a to 220b, 230a to 230b, 240a to 240b, and 250a to 250b are exposed on the top and bottom surfaces of the capacitor and allow connection between the body of the internal electrode layer and the external terminals. For example, lead terminals 220a to 220b, 230a to 230b, 240a to 240b, 250a to 250b may include front edges 223a to 223b, 233a to 233b, 243a to 243b, 253a to 253b extending to one edge of a dielectric layer and allowing the formation of external terminals.

[0077] As shown in Figure 2B, the internal electrode layers 205 and 215 include at least two lead terminals 220a-220b, 230a-230b, 240a-240b, and 250a-250b along a top edge and a bottom edge. As shown in Figure 2B, a first internal electrode layer 205 includes two lead terminals 220a-220b and 230a-230b extending from the body 235 along each top edge 205c and bottom edge 205d. A second internal electrode layer 215 includes two lead terminals 240a-240b and 250a-250b extending from the body 245 along each top edge and bottom edge.

[0078] The lead terminals 220a to 220b and 230a to 230b on the top edge 205c and bottom edge 205d of the first internal electrode layer 205 can be aligned vertically. That is, the lateral edges 221a and 222a of a first lead terminal 220 along a top edge 205c can be aligned with the lateral edges 231a and 232a of a first lead terminal 230 along a bottom edge 205d opposite to the top edge 205c. In addition, these side edges 221a and 231a can be aligned with the side edges 205a of the internal electrode layer 205.

[0079] However, it should be understood that the two lateral edges 221a and 222a of the first lead patch 220a along a top edge 205c can be aligned with the lateral edges 231a and 232a of the first lead patch 230a along a bottom edge 205d opposite to the top edge 205c. In other words, the two lateral edges 222a and 232a can be offset by the same distance from the side edges 205a to 205b along a bottom edge 205d and a top edge 205c.

[0080] When a top edge 205c and a bottom edge 205d contain at least two lead terminals 220a to 220b and 230a to 230b, at least one lateral edge of each lead terminal on the top edge 205c may be aligned with a corresponding lateral edge of one lead terminal on the bottom edge 205d. Furthermore, two lateral edges of each lead terminal on the top edge 205c may be aligned with corresponding lateral edges of the lead terminals on the bottom edge 205d.

[0081] Similarly, the lead terminals 240a to 240b and 250a to 250b on the top and bottom edges of the second internal electrode layer 215 can be aligned vertically. That is, the lateral edges 241a and 242a of a first lead terminal 240 along a top edge can be aligned with the lateral edges 251a and 252a of a first lead terminal 250 along a bottom edge opposite to the top edge. The two lateral edges 241a and 242a of a first lead terminal 240 along a top edge can be aligned with the lateral edges 251a and 252a of a first lead terminal 250 along a bottom edge opposite to the top edge. The relationship between the lateral edges of a first lead terminal on a top edge and a first lead terminal on a bottom edge, as mentioned with respect to internal electrode layer 205, can also be applied to internal electrode layer 215.

[0082] Using this configuration, a gap can be formed between any lead pads along the top edge 205c of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, a gap can be formed between any lead pads 220a to 220b, 240a to 240b extending from the top edge of their respective internal electrode layers. Additionally, a gap can be formed between any lead pads along the bottom edge 205d of the first internal electrode layer 205, the second internal electrode layer 215, or both. For example, a gap can be formed between any lead pads 230a to 230b, 250a to 250b extending from the top edge of their respective internal electrode layers. Furthermore, regardless of whether they originate from the same internal electrode layer or adjacent internal electrode layers, the size of a gap between two respective leads extending from a top edge can be substantially the same as the size of a gap between corresponding two leads extending from a bottom edge. For example, the gap between lead terminals 220a and 220b can be substantially the same as the gap between lead terminals 230a and 230b. Similarly, the gap between lead terminals 220a and 240a can be substantially the same as the gap between lead terminals 230a and 250a.

[0083] Any or all of the lead terminals 220a to 220b, 240a to 240b can be arranged parallel to the lead terminals 230a to 230b, 250a to 250b extending from layers 205 and 215, respectively, so that the lead terminals extending from the interleaved electrode layers 205 and 215 can be aligned in their respective rows. For example, the lead terminals 220a to 220b and 230a to 230b of the inner electrode layer 205 can be configured in a stacked configuration, while the lead terminals 240a to 240b and 250a to 250b of the inner electrode layer 215 can be configured in a stacked configuration.

[0084] It will be understood that lead terminals 220a to 220b are respectively connected to external terminals 22a to 22b, and lead terminals 240a to 240b are respectively connected to external terminals 24a to 24b. Accordingly, each lead terminal 220a to 220b will be connected to its respective lead terminal 240a to 240b in an interdigitated manner similar to that of external terminals 22a to 22b and 24a to 24b. The interdigitated lead terminals can provide multiple, adjacent current injection points to the associated main electrode portion.

[0085] Additionally, the capacitor 20 of FIG2A includes at least one first polarity terminal and at least one second and opposite polarity terminal on a top surface. Although not shown, the bottom surface includes at least one first polarity terminal and one second and opposite polarity terminal. Specifically, FIG2A includes two positive terminals 22a to 22b and two negative terminals 24a to 24b on a top surface.

[0086] As illustrated in Figures 2A and 2B, the capacitor contains four external terminals on each surface and two sets of interleaved dielectric layers and internal electrode layers. However, as indicated above, the present invention is not limited by the number of external terminals and / or the number of sets of interleaved dielectric layers and internal electrode layers.

[0087] Furthermore, the embodiment shown in the accompanying drawings employs only two internal electrode layers per group of staggered dielectric layers and internal electrode layers. However, it should be understood that the present invention may include any number of internal electrode layers per group (as indicated herein) and is not necessarily limited thereto.

[0088] Generally speaking, the present invention provides a capacitor with a unique configuration that offers a variety of benefits and advantages. In this regard, it should be understood that the materials used in constructing the capacitor are not limited and can be any of those commonly used in the art and formed using any method commonly used in the art.

[0089] Generally, dielectric layers are typically formed of a material having a relatively high dielectric constant (K), such as from about 10 to about 40,000, from about 50 to about 30,000 in some embodiments, and from about 100 to about 20,000 in some embodiments.

[0090] In this regard, the dielectric material can be a ceramic. The ceramic can be provided in various forms, such as a wafer (e.g., pre-fired) or a dielectric material co-fired within the device itself.

[0091] Specific examples of high-dielectric materials include, for example, NPO (COG) (up to about 100), X7R (from about 3,000 to about 7,000), X7S, Z5U, and / or Y5V materials. It should be understood that the aforementioned materials are described by their industry-accepted definitions, some of which are standard classifications established by the Electronic Industries Alliance (EIA) and should therefore be recognized by those skilled in the art. For example, such materials may comprise a ceramic. These materials may comprise perovskites, such as barium titanate and related solid solutions (e.g., barium strontium titanate, barium calcium titanate, barium zirconate titanate, barium strontium zirconate titanate, barium calcium zirconate titanate, etc.), lead titanate and related solid solutions (e.g., lead zirconate titanate, lanthanum lead zirconate titanate), sodium bismuth titanate, etc. In one particular embodiment, barium strontium titanate (“BSTO”) of the chemical formula BaxSr1-xTiO3 may be used, wherein x is from 0 to 1, from about 0.15 to about 0.65 in some embodiments, and from about 0.25 to about 0.6 in some embodiments. Other suitable perovskites may include, for example, BaxCa1-xTiO3 (where x ranges from about 0.2 to about 0.8, and in some embodiments from about 0.4 to about 0.6), PbxZr1-xTiO3 (“PZT”) (where x ranges from about 0.05 to about 0.4), lead zirconate titanate lanthanum (“PLZT”), lead titanate (PbTiO3), barium calcium zirconate titanate (BaCaZrTiO3), sodium nitrate (NaNO3), KNbO3, LiNbO3, LiTaO3, PbNb2O6, PbTa2O6, KSr(NbO3)5KHb2PO4. The additional composite perovskite may also contain A[B1 1 / 3B2 2 / 3]O3 material, wherein the A-series BaxSr 1-x (x can be a value from 0 to 1); the B1-series MgyZn 1-y (y can be a value from 0 to 1); and the B2-series TazNb 1-z (z can be a value from 0 to 1). In a particular embodiment, the dielectric layer may include a titanate.

[0092] The internal electrode layer can be formed from any of a variety of different metals known in the art. The internal electrode layer can be made of a metal, such as a conductive metal. These materials can include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. Sputtered titanium / tungsten (Ti / W) alloys and individual sputtered layers of chromium, nickel, and gold may also be suitable. In a particular embodiment, the internal electrode layer may include nickel or an alloy thereof.

[0093] External terminals can be formed from any of a variety of different metals known in the art. External terminals can be made of a metal, such as a conductive metal. These materials can include noble metals (e.g., silver, gold, palladium, platinum, etc.), base metals (e.g., copper, tin, nickel, chromium, titanium, tungsten, etc.), and various combinations thereof. In a particular embodiment, the external terminal may include copper or an alloy thereof.

[0094] External terminals can be formed using any method known in this technology. External terminals can be formed using techniques such as sputtering, coating, printing, electroless plating or fine copper termination (FCT), electroplating, plasma deposition, propellant jetting / air brushing, etc.

[0095] The external terminal can be formed such that it is a thin film electroplated layer of a metal. This thin film electroplated layer can be formed by depositing a conductive material, such as a conductive metal, on an exposed portion of an internal electrode layer. For example, a leading edge of an internal electrode layer can be exposed to allow the formation of an electroplated terminal.

[0096] The external terminals may have an average thickness of about 50 μm or less, such as about 40 μm or less, such as about 30 μm or less, such as about 25 μm or less, such as about 20 μm or less to about 5 μm or greater, such as about 10 μm or greater, such as about 15 μm or greater. For example, the external terminals may have an average thickness of about 5 μm to about 50 μm, such as about 10 μm to about 40 μm, such as about 15 μm to about 30 μm, such as about 15 μm to about 25 μm.

[0097] Generally, an external terminal may include an electroplated terminal. For example, an external terminal may include an electroplated terminal, an electroless electroplated terminal, or a combination thereof. For example, an electroplated terminal may be formed by electrolytic plating. An electroless electroplated terminal may be formed by electroless plating.

[0098] When multiple layers constitute an external terminal, the external terminal may include an electroplated terminal and an electroless electroplated terminal. For example, an initial material layer may be deposited first using electroless electroplating. Then, the electroplating technology can be switched to an electrochemical electroplating system, which allows one of the materials to be deposited more quickly.

[0099] When electroplating terminals are formed using any electroplating method, the leading edge of one of the lead terminals of the internal electrode layer exposed from the capacitor body is subjected to an electroplating solution. By being subjected to this solution, in one embodiment, the capacitor can be immersed in the electroplating solution.

[0100] The electroplating solution contains a conductive material, such as a conductive metal, for forming the electroplating terminals. This conductive material can be any of the aforementioned materials or any of those well known in the art. For example, the electroplating solution can be a nickel sulfamate bath or other nickel solution, such that the plating layer and external terminals comprise nickel. Alternatively, the electroplating solution can be a copper acid bath or other suitable copper solution, such that the plating layer and external terminals comprise copper.

[0101] Furthermore, it should be understood that the electroplating solution may include other additives as well known in the art. For example, such additives may include other organic additives and media that can assist the electroplating process. Additionally, additives may be used to allow for the use of an electroplating solution with a desired pH. In one embodiment, a resistance-reducing additive may be used in such solutions to assist in achieving electroplating coverage and bonding of the electroplated material to the exposed front edges of the lead terminals of the capacitor and internal electrode layers.

[0102] The capacitor may be exposed, submerged, or immersed in an electroplating solution for a predetermined period of time. This exposure time is not limited, but it may be sufficient to allow adequate plating material to deposit to form the plated terminals. In this regard, the time should be sufficient to allow a continuous connection to be formed between the adjacent leading edges of the leads of a given polarity within a set of interleaved dielectric layers and internal electrode layers, through which they are to be exposed.

[0103] Generally, the difference between electroplating and electroless plating lies in the fact that electroplating employs an electrical bias, such as by using an external power supply. Electroplating solutions are typically designed to withstand a high current density range, for example, 10 to 15 amp / ft² (rated at 9.4 volts). A connection can be formed using a negative connection to the capacitor to which the plating terminals are to be formed and a positive connection to a solid material in the same plating solution (e.g., Cu in a Cu plating solution). That is, the capacitor is biased to a polarity opposite to that of the plating solution. Using this method, the conductive material of the plating solution is attracted to the exposed front edge of the metal of the lead terminals of the internal electrode layer.

[0104] Various pretreatment steps can be performed before immersing or subjecting the capacitor to an electroplating solution. These steps can be performed for a variety of purposes, including catalyzing, accelerating, and / or improving the adhesion of the electroplating material to the leading edge of the lead.

[0105] Additionally, an initial cleaning step may be performed prior to electroplating or any other pretreatment step. This step can be used to remove any oxide deposits formed on the exposed lead tabs of the internal electrode layer. This cleaning step can be particularly helpful in removing any nickel oxide deposits when the internal electrodes or other conductive components are formed of nickel. Component cleaning can be achieved by complete immersion in a pre-cleaning bath, such as a pre-cleaning bath containing an acidic cleaning agent. In one embodiment, exposure may be for a predetermined time, such as on the order of about 10 minutes. Cleaning can also be achieved alternatively by chemical polishing or harmorizing steps.

[0106] Additionally, a step can be performed to activate the exposed metal leading edge of the lead-connected terminals of the internal electrode layer to promote the deposition of conductive material. Activation can be achieved by immersion in palladium salts, photo-patterning of palladium organometallic precursors (via masking or laser), screen printing or inkjet deposition of palladium compounds, or electrophoretic palladium deposition. It should be understood that palladium-based activation is currently revealed only as one example of an activation solution, which is generally well-suited for the activation of exposed terminal portions formed of nickel or its alloys. However, it should be understood that other activation solutions can also be used and are therefore not limited thereto.

[0107] Furthermore, instead of the aforementioned activation steps, or in addition to other activation steps, the activating dopant can be introduced into the conductive material during the formation of the internal electrode layer of the capacitor. For example, when the internal electrode layer comprises nickel and the activating dopant comprises palladium, the palladium dopant can be introduced into the nickel ink or composition forming the internal electrode layer. This eliminates the need for a palladium activation step. It should also be understood that some of the aforementioned activation methods, such as organometallic precursors, are also suitable for co-deposition of glass-forming agents to increase adhesion to the generally ceramic body of the capacitor. When the activation steps are taken as described above, trace amounts of the activating agent material may typically remain on the exposed conductive portions before and after termination plating.

[0108] Furthermore, post-treatment steps following electroplating can be employed as desired or required. These steps can be performed for various purposes, including enhancing and / or improving the adhesion of the material. For example, a heating (or annealing) step can be performed after the electroplating step. This heating can be performed through baking, laser treatment, UV exposure, microwave exposure, arc welding, etc.

[0109] As indicated herein, an external terminal includes at least one electroplated layer. In one embodiment, an external terminal may include only one electroplated layer. However, it should be understood that an external terminal may include a plurality of electroplated layers. For example, an external terminal may include a first electroplated layer and a second electroplated layer. Additionally, an external terminal may also include a third electroplated layer. Furthermore, the materials of these electroplated layers may be any of those described above and well known in the art.

[0110] For example, an electroplated layer, such as a first electroplated layer, may include copper or an alloy thereof. Another electroplated layer, such as a second electroplated layer, may include nickel or an alloy thereof. Alternatively, another electroplated layer, such as a second electroplated layer, may include copper or an alloy thereof. Another electroplated layer, such as a third electroplated layer, may include tin, lead, gold, or a combination thereof, such as an alloy. Alternatively, an initial electroplated layer may include nickel, followed by an electroplated layer of tin or gold. In another embodiment, an initial electroplated layer of copper may be formed, followed by the formation of a nickel layer.

[0111] In one embodiment, the initial or first plating layer may be a conductive metal (e.g., copper). This area is then covered with a second layer containing one of a resistive polymer materials for sealing. The area may then be polished to selectively remove the resistive polymer material, and subsequently electroplated again with a third layer containing one of a conductive, metallic materials (e.g., copper).

[0112] The second layer above the initial electroplated layer may correspond to a solder resist layer, such as a nickel solder resist layer. In some embodiments, the aforementioned layer may be formed by electroplating an additional metal layer (e.g., nickel or copper) on top of an initial electroless or electrolytic electroplated layer (e.g., electroplated copper). Other exemplary materials for forming the aforementioned solder resist layer include nickel-phosphorus, gold, and silver. In some embodiments, a third layer above the aforementioned solder resist layer may correspond to a conductive layer, such as electroplated Ni, Ni / Cr, Ag, Pd, Sn, Pb / Sn, or other suitable electroplated solder.

[0113] Alternatively, a metal plating layer can be formed, followed by an electroplating step to provide a resistive alloy or a metal alloy coating with higher resistance, such as an electroless Ni-P alloy over this metal plating layer. However, it should be understood that any metal coating may be included, as will be understood by those skilled in the art from the full disclosure herein.

[0114] It should be understood that either of the foregoing steps may occur as a bulk process such as roller electroplating, fluidized bed electroplating and / or flow-based electroplating termination processes, all of which are well known in this technology. Such ontology processes implement processing of multiple components at once, thereby providing an efficient and rapid termination process. This is a specific advantage relative to the learned termination methods, such as the printing of thick film terminations that require individual component processing.

[0115] As described herein, the formation of the external terminal is usually guided by the position of the lead lug of the internal electrode layer through the exposed front edge. This phenomenon may be termed “self-determination”, this is because the formation of the external electroplating terminals is judged by the configuration of the internal electrode layer at selected peripheral locations on the capacitor through the exposed conductive metal.

[0116] Additional states of the above techniques for forming thin-film electroplating terminations are described in U.S. Patent No. 7,177,137 granted to Ritter et al., and U.S. Patent No. 7,463,474 granted to Ritter et al., which are incorporated herein by reference for all purposes. It should be understood that additional techniques for forming capacitor terminals may also be within the scope of the present technique. Instantiated alternatives comprise (but are not limited to) the formation of terminations by resorting to electroplating, magnetism, masking, electrophoresis / static electricity, splattering, vacuum deposition, printing, or other techniques used to form both a thick film conductive layer or a thin film conductive layer.

[0117] In addition, the capacitor can then be subjected to a solder mask. For example, this may allow coating capacitors. Not intended to be constrained, this mask can assist in preventing the oxidation of electroplating layers, such as copper electroplating layers, particularly when this layer is the final electroplating layer for external terminals. This solder mask material may not be subject to the limitations of the present invention. For example, this material may contain any of the materials mentioned above with respect to resistive welding layers. Additionally or alternatively, this material may comprise an epoxy resin, such as a subsequently cured liquid epoxy resin.

[0118] When this material is provided on a capacitor, it may be necessary to access the electroplating layer and external terminals to form a one-electric connection. In this regard, a laser can be utilized to form a hole through the mask layer. This hole can then be filled with a conductive material, such as copper. This can then be utilized to form an electrical connection with the capacitor.

[0119] As disclosed herein, capacitors can be mounted using various means. For example, a capacitor can be mounted to a circuit board containing a substrate (e.g., an insulating layer) having an upper surface and a lower surface. The circuit board has a plurality of current paths defined therein. The external terminals of the capacitor are electrically connected to each predetermined current path of the circuit board. Alternatively, the external terminals of the capacitor can be physically connected to the circuit board using any method well known in this art, such as common soldering techniques.

[0120] Additionally, an integrated circuit package may also be disposed on the circuit board. The integrated circuit package may be connected to the circuit board using a ball grid array. The circuit board may further include a processor. The processor may also be connected to the integrated circuit package using a ball grid array.

[0121] Generally, the ball grid array can be configured to have a pitch of 1.5 mm or less, such as 1.25 mm or less, such as 1 mm or less, such as 0.8 mm or less, such as 0.6 mm or less, and 0.4 mm or more, such as 0.5 mm or more, such as 0.6 mm or more.

[0122] Alternatively, an integrated circuit package can also be connected to a circuit board using a capacitor as defined herein. In this regard, the internal electrode layers of the capacitor can be positioned such that they are orthogonal to a horizontal plane of the circuit board and the integrated circuit package. In other words, the internal electrode layers of the capacitor can be positioned such that they are substantially non-parallel to the circuit board. For example, the capacitor can be positioned between the integrated circuit package and the circuit board, such that the capacitor is "sandwiched" between the two components. In this regard, the capacitor is directly connected to the integrated circuit package and the circuit board. For example, the capacitor can be connected to the circuit board and / or circuit package using any method well known in this art, such as common soldering techniques (e.g., physical and / or electrical).

[0123] By employing capacitors in the aforementioned configuration, it is possible to remove some of the original ball grid array. However, the capacitors may still be surrounded by a ball grid array.

[0124] In addition to the above, although not illustrated herein, in one embodiment, the integrated circuit package itself may include multiple layers of capacitors. In this respect, the capacitors can be directly embedded in the package. This incorporation of capacitors allows for a size reduction, which may be beneficial for various electronic applications.

[0125] While the foregoing provides one example of a means for mounting capacitors as disclosed herein, it should be understood that other methods may also be used. For example, capacitors may be mounted via a platform grid array configuration. Capacitors may also be embedded in another substrate or component.

[0126] Without departing from the spirit and scope of this invention, those skilled in the art can practice these and other modifications and variations of the invention. Furthermore, it should be understood that the various embodiments can be interchanged in whole or in part. Moreover, those skilled in the art will understand that the foregoing description is merely illustrative and is not intended to limit the invention as further described in the appended claims.

[0127] 10: Capacitor 12: External terminal / First polarity terminal 14:External terminal 20: Capacitor 22a: External terminal / positive terminal 22b: External terminal / positive terminal 24a: External terminal / negative terminal 24b: External terminal / negative terminal 105: Internal electrode layer / First internal electrode layer 105a: Side edge 105b: Side edge 105c: Top edge 105d: Bottom edge 110: Dielectric layer and internal electrode layer 115: Inner electrode layer / Second inner electrode layer 120: Lead wire connector / First lead wire connector 121: Horizontal edge 122: Horizontal edge 123: Front edge 130: Lead wire connector / First lead wire connector 131: Horizontal edge 132: Horizontal edge 133: Front edge 135: Main Body 140: Lead wire connector / First lead wire connector 141: Horizontal edge 142: Horizontal edge 143: Leading edge 150: Lead wire connector / First lead wire connector 151: Horizontal edge 152: Horizontal edge 153: Leading edge 205: Internal electrode layer / First internal electrode layer 205a: Side edge 205b: Side edge 205c: Top edge 205d: Bottom edge 210: Dielectric layer and internal electrode layer 215: Inner electrode layer / Second inner electrode layer 220a: Lead connector / First lead connector 220b: Lead wire connector 221a: Lateral edge 222a: Horizontal edge 223a: Leading edge 223b: Leading edge 230a: Lead connector / First lead connector 230b: Lead wire connector 231a: Lateral edge 232a: Lateral edge 233a: Leading edge 233b: Leading edge 235: Main Body 240: First lead connector 240b: Lead wire connector 241a: Lateral edge 243a: Leading edge 243b: Leading edge 250a: Lead wire connector 250b: Lead wire connector 251a: Lateral edge 252a: Lateral edge 253a: Leading edge 253b: Leading edge

Claims

1. A multilayer capacitor, comprising: A body comprising an alternating set of dielectric layers and internal electrode layers, the set including a first internal electrode layer and a second internal electrode layer, the first internal electrode layer comprising: a body having a top edge, a bottom edge opposite the top edge, a first side edge, and a second side edge opposite the first side edge along a length direction, the first side edge and the second side edge extending between the top edge and the bottom edge, and a first lead tab and a second lead tab extending from the top edge of the body, and a first lead tab and a second lead tab extending from the bottom edge of the body, wherein each of the first lead tab extending from the top edge of the body and the first lead tab extending from the bottom edge of the body includes a first lateral edge aligned with the first side edge of the body; and the second internal electrode layer comprising: A main body having a top edge, a bottom edge opposite to the top edge, a first side edge, and a second side edge opposite to the first side edge along the length direction, the first side edge and the second side edge extending between the top edge and the bottom edge. A first lead terminal and a second lead terminal extending from the top edge of the body, and a first lead terminal and a second lead terminal extending from the bottom edge of the body, wherein each of the first lead terminal extending from the top edge of the body and the first lead terminal extending from the bottom edge of the body includes a first lateral edge aligned with the first side edge of the body, wherein the first side edge of the first internal electrode layer is opposite to the first side edge of the second internal electrode layer along the length direction; and external terminals electrically connected to the internal electrode layers, the external terminals being formed on a top surface of the capacitor, a bottom surface of the capacitor opposite to the top surface of the capacitor, and on a pair of opposing end surfaces of the capacitor extending along a width direction between the top surface and the bottom surface. The external terminals include a first external terminal electrically connected to a first internal electrode layer along a first end surface of the top surface, the bottom surface, and one of the pairs of opposite end surfaces, and the external terminals include a second external terminal electrically connected to a second internal electrode layer along a second end surface of the top surface, the bottom surface, and one of the pairs of opposite end surfaces.

2. The capacitor of claim 1, wherein the first internal electrode layer and the second internal electrode layer are interleaved in a relative relationship and a dielectric layer is positioned between the first internal electrode layer and the second internal electrode layer.

3. The capacitor of claim 2, wherein the dielectric layer comprises a ceramic.

4. The capacitor of claim 1, wherein the internal electrode layers comprise a conductive metal.

5. The capacitor of claim 1, wherein the external terminals comprise an electroplated layer.

6. The capacitor of claim 1, wherein the external terminals include an electroless plating layer.

7. The capacitor of claim 1, wherein the external terminals comprise an electroless plating layer and an electroplated layer.

8. The capacitor of claim 1, wherein the external terminals comprise a first electroless plating layer, a second plating layer and a third plating layer.

9. The capacitor of claim 8, wherein the first electroless plating layer comprises copper, the second plating layer comprises nickel, and the third plating layer comprises tin.

10. The capacitor of claim 1, wherein the capacitor comprises at least three sets of interleaved dielectric layers and internal electrode layers.

11. The capacitor of claim 1, wherein each of the second lead terminals extending from the top edge of the body of the first internal electrode layer and each of the second lead terminals extending from the bottom edge of the body of the first internal electrode layer are offset from and positioned between the first side edge and the second side edge of the first internal electrode layer, and wherein each of the second lead terminals extending from the top edge of the body of the second internal electrode layer and each of the second lead terminals extending from the bottom edge of the body of the second internal electrode layer are offset from and positioned between the first side edge and the second side edge of the second internal electrode layer.

12. The capacitor as claimed in claim 1, wherein, Along the length direction, the first lead terminal and the second lead terminal extending from the top edge of the body of the first inner electrode layer are offset from each other, and are also offset from each of the first lead terminal and the second lead terminal extending from the top edge of the body of the second inner electrode layer.

13. The capacitor of claim 1, wherein the capacitor includes a pair of opposing side surfaces extending along a height direction between the top surface and the bottom surface and along a length direction between the pair of opposing end surfaces, the pair of opposing side surfaces including a first side surface and a second side surface, wherein a first external terminal is offset from both the first side surface and the second side surface along the width direction, and wherein a second external terminal is offset from both the first side surface and the second side surface along the width direction.

14. The capacitor of claim 1, wherein the external terminals include a third external terminal electrically connected to one of the first internal electrode layers along the top surface of the capacitor, and a fourth external terminal electrically connected to one of the first internal electrode layers along the bottom surface of the capacitor.

15. The capacitor of claim 14, wherein the first external terminal is electrically connected to the first internal electrode layer along a first lead tab extending from the top edge of the body of the first internal electrode layer, the first side edge of the body of the first internal electrode layer, and a first lead tab extending from the bottom edge of the body of the first internal electrode layer; wherein the third external terminal is electrically connected to the first internal electrode layer along a second lead tab extending from the top edge of the body of the first internal electrode layer; and wherein the fourth external terminal is electrically connected to the first internal electrode layer along a second lead tab extending from the bottom edge of the body of the first internal electrode layer.

16. The capacitor of claim 14, wherein the external terminals include a fifth external terminal electrically connected to one of the second internal electrode layers along the top surface of the capacitor, and a sixth external terminal electrically connected to one of the second internal electrode layers along the bottom surface of the capacitor, wherein the first, third and fourth external terminals have a first polarity, and the second, fifth and sixth external terminals have a second polarity opposite to the first polarity.

17. A circuit board comprising a capacitor as claimed in claim 1 positioned on the circuit board.

18. The circuit board of claim 17, wherein the circuit board further includes an integrated circuit package, and wherein the capacitor is positioned in a vertical direction between the circuit board and the integrated circuit package, such that the circuit board, the capacitor and the integrated circuit package are present in a stacked configuration.

19. The circuit board of claim 18, wherein the capacitor is directly connected to the circuit board and the integrated circuit package.

20. An integrated circuit package comprising a capacitor as claimed in claim 1.

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