Semiconductor device and method for manufacturing the same

Abstract

A semiconductor device includes: a substrate having a first region and a second region thereon; a first active region located in the first region; an active pattern protruding from the first active region; a second active region located in the second region; a first gate electrode located on the active pattern; a second gate electrode located on the second active region; a first gate insulating layer including a first first insulating layer located between the active pattern and the first gate electrode; and a second gate insulating layer including a second first insulating layer and a second second insulating layer below the second first insulating layer located between the second active region and the second gate electrode, wherein the thickness of the first gate electrode overlapping the active pattern in a vertical direction is equal to the thickness of the second gate electrode overlapping the second active region in a vertical direction, and the upper surface of the first gate electrode is formed at the same level as the upper surface of the second gate electrode.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device and a method of manufacturing the same. Cross-reference to related applications

[0002] This application is based on and claims the priority of Korean Patent Application No. 10-2021-0123719, filed on September 16, 2021, with the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety.

Background Art

[0003] Although the voltage decreases as semiconductor elements are miniaturized, there are cases where a booster circuit is provided inside, or the power supply voltage itself is about 12 volts, an example of which is vehicle applications. To solve such applications, it is common to form a high-voltage transistor and a low-voltage transistor inside the same semiconductor element. In the process of forming a low-voltage transistor and a high-voltage transistor inside the same semiconductor element, there is a problem that the heights of the gate electrodes are formed non-uniformly.

Summary of the Invention

[0004] Various embodiments of this disclosure provide a semiconductor device and a method of manufacturing a semiconductor, which can enable a low-voltage transistor, an intermediate-voltage transistor, and a high-voltage transistor formed on the same substrate to have respective gate electrodes of the same thickness and respective gate insulating layers of different thicknesses, thereby being formed at the same level on the substrate.

[0005] According to an embodiment, a semiconductor device is provided, which may include: a substrate having a first region and a second region thereon; a first active region located in the first region; an active pattern protruding from the first active region; a second active region located in the second region; a first gate electrode located on the active pattern; a second gate electrode located on the second active region; a first gate insulating layer including a first first insulating layer located between the active pattern and the first gate electrode; and a second gate insulating layer including a second first insulating layer and a second second insulating layer under the second first insulating layer, located between the second active region and the second gate electrode, wherein the thickness in the vertical direction of the first gate electrode overlapping the active pattern in the vertical direction is equal to the thickness in the vertical direction of the second gate electrode overlapping the second active region in the vertical direction, and the upper surface of the first gate electrode is formed at the same level as the upper surface of the second gate electrode.

[0006] According to an exemplary embodiment, a semiconductor device may include: a substrate having a first region to a third region thereon; a first active region located in the first region; an active pattern protruding from the first active region; a second active region located in the second region; a third active region located in the third region; a first gate electrode located on the active pattern; a second gate electrode located on the second active region; a third gate electrode located on the third active region; a first gate insulating layer including a first first insulating layer located between the active pattern and the first gate electrode; and a second gate insulating layer including a second first insulating layer and a second second insulating layer under the second first insulating layer, located between the second active region and the second gate electrode; and a third gate insulating layer including a third first insulating layer, a third second insulating layer under the third first insulating layer, and a third third insulating layer under the third second insulating layer, located between the third active region and the third gate electrode, wherein a thickness in a vertical direction of the first gate electrode overlapping the active pattern in the vertical direction, a thickness in a vertical direction of the second gate electrode overlapping the second active region in the vertical direction, and a thickness in a vertical direction of the third gate electrode overlapping the third active region in the vertical direction are equal to each other, and wherein upper surfaces of the first gate electrode, the second gate electrode, and the third gate electrode are formed at the same level on the substrate.

[0007] According to an exemplary embodiment, a method of manufacturing a semiconductor device is provided. The method may include: providing a substrate having a first region to a third region thereon; etching an upper surface of the substrate at the second region to form a first groove, and etching the upper surface of the substrate at the third region to form a second groove; forming a first insulating material layer inside each of the first groove and the second groove; etching the substrate at the first region to form an active pattern; etching the substrate at each of the first region to the third region to form a first active region to a third active region; etching at least a portion of the first insulating material layer formed on the third active region; forming a second insulating material layer on the third active region; etching the first insulating material layer formed on the second active region; forming a third insulating material layer on each of the second active region and the second insulating material layer of the third active region; forming an insulating layer on each of the active pattern, the third insulating material layer formed on the second active region, and the third insulating material layer formed on the third active region; and forming a first gate electrode on the insulating layer on the active pattern, a second gate electrode on the insulating layer on the second active region, and a third gate electrode on the insulating layer on the third active region, wherein a thickness in a vertical direction of the first gate electrode overlapping the active pattern in the vertical direction, a thickness in a vertical direction of the second gate electrode overlapping the second active region in the vertical direction, and a thickness in a vertical direction of the third gate electrode overlapping the third active region in the vertical direction are equal to each other, and wherein upper surfaces of the first gate electrode, the second gate electrode, and the third gate electrode are formed at the same level.

[0008] However, aspects are not limited to the aspects set forth herein. By referring to the detailed description given below, the above and other aspects will become more apparent to those of ordinary skill in the art to which this disclosure pertains.

Embodiments

[0010] The embodiments described herein are example embodiments, and thus, the inventive concept is not limited thereto and may be implemented in various other forms.

[0011] It should be understood that when an element or layer is referred to as "above", "on top of", "on", "below", "beneath", "under", "connected to" or "coupled to" another element or layer, the element or layer can be directly above, on top of, on, below, beneath, under, connected to or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly above", "directly on top of", "directly on", "directly below", "directly beneath", "directly under", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0012] It should be understood that although terms such as first, second, third, fourth, first first, first second, etc. may be used herein to describe various elements, components, regions, layers and / or sections, these elements, components, regions, layers and / or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another region, layer or section. Thus, without departing from the teachings of the concepts of the present invention, the first element, component, region, layer or section discussed below may be referred to as the second element, component, region, layer or section.

[0013] As used herein, a phrase such as "at least one of..." when preceding a list of elements modifies the entire list of elements and not individual elements of the list. For example, the phrase "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c.

[0014] Although the diagrams of semiconductor devices according to some embodiments show fin field-effect transistors (FinFETs) having a channel region in the shape of, for example, a fin pattern, the present disclosure is not limited thereto. In some other embodiments, the corresponding semiconductor device may include a MBCFETTM (multi-bridge-channel field-effect transistor) having a nanosheet as its channel region.

[0015] Hereinafter, a semiconductor device according to an embodiment will be described with reference to FIGS. 1 and 2.

[0016] FIG. 1 is a schematic layout diagram for explaining a semiconductor device according to some embodiments. FIG. 2 is a cross-sectional view taken along each of lines A-A', B-B', C-C', and D-D' of FIG. 1.

[0017] Referring to FIGS. 1 and 2, a semiconductor device according to an embodiment includes: a substrate 100; a field insulating layer 105; a first gate electrode G1, a second gate electrode G2, and a third gate electrode G3; a first gate insulating layer to a third gate insulating layer; a first gate spacer 121, a second gate spacer 122, and a third gate spacer 123; a first capping pattern 131, a second capping pattern 132, and a third capping pattern 133; a first source / drain region SD1, a second source / drain region SD2, and a third source / drain region SD3; a first interlayer insulating layer 140; an etch stop layer 150; and a second interlayer insulating layer 160.

[0018] The substrate 100 may be a silicon substrate or silicon-on-insulator (SOI). In contrast, the substrate 100 may include but is not limited to silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. However, the present disclosure is not limited thereto.

[0019] A first region I, a second region II, and a third region III may be defined on the substrate 100. According to an embodiment, a low-voltage transistor may be disposed on the substrate 100 at the first region I, a medium-voltage transistor may be disposed on the substrate 100 at the second region II, and a high-voltage transistor may be disposed on the substrate 100 at the third region III.

[0020] Each of a first active region AR1, a second active region AR2, and a third active region AR3 may extend on the substrate 100 in a first horizontal direction DR1. Each of the first active region AR1, the second active region AR2, and the third active region AR3 may protrude from the substrate 100 in a vertical direction DR3. Each of the first active region AR1, the second active region AR2, and the third active region AR3 may be a part of the substrate 100, or may be or may include an epitaxial layer grown from the substrate 100.

[0021] The first active region AR1 can be disposed in the first region I, the second active region AR2 can be disposed on the second region II, and the third active region AR3 can be disposed in the third region III. The first active region AR1 can be defined by a first deep trench DT1 formed in the first region I. The second active region AR2 can be defined by a second deep trench DT2 formed in the second region II. The third active region AR3 can be defined by a third deep trench DT3 formed in the third region III.

[0022] The first active pattern F1 and the second active pattern F2 can be formed to extend in a first horizontal direction DR1 on the first active region AR1. Each of the first active pattern F1 and the second active pattern F2 can protrude from the first active region AR1 in a vertical direction DR3. The second active pattern F2 can be spaced apart from the first active pattern F1 in a second horizontal direction DR2, the second horizontal direction DR2 being different from the first horizontal direction DR1. Each of the first active pattern F1 and the second active pattern F2 can serve as a channel structure of a corresponding transistor formed in the first region I.

[0023] According to an embodiment, the upper surface of the second active region AR2 can be formed at a level lower than the upper surface of the first active pattern F1. The upper surface of the second active region AR2 can be formed at a level between the upper surface of the first active region AR1 and the upper surface of the first active pattern F1. The upper surface of the third active region AR3 can be formed at a level lower than the upper surface of the second active region AR2. The upper portions of the first active region AR2 and the second active region AR3 can serve as channel structures of corresponding transistors formed in the second region II and the third region III, respectively.

[0024] The field insulating layer 105 can be disposed on the substrate 100. The field insulating layer 105 can surround the sidewalls of each of the first active region AR1, the second active region AR2, and the third active region AR3. The field insulating layer 105 can surround the sidewalls of each of the first active pattern F1 and the second active pattern F2. Each of the first active pattern F1 and the second active pattern F2 can protrude above the level of the upper surface of the field insulating layer 105 in the vertical direction DR3. The field insulating layer 105 can include, for example, an oxide film, a nitride film, a nitroxide film, or a combined film thereof.

[0025] The first gate electrode G1 can extend in the second horizontal direction DR2 on the first active region AR1. The first gate electrode G1 can be disposed on the first active pattern F1 and the second active pattern F2. The second gate electrode G2 can extend in the second horizontal direction DR2 on the second active region AR2. The third gate electrode G3 can extend in the second horizontal direction DR2 on the third active region AR3.

[0026] The thicknesses of the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 in the vertical direction DR3 may be equal to each other. For example, a first thickness t1 in the vertical direction DR3 of the first gate electrode G1 that overlaps with the first active pattern F1 in the vertical direction DR3, a second thickness t2 in the vertical direction DR3 of the second gate electrode G2 that overlaps with the second active region AR2 in the vertical direction DR3, and a third thickness t3 in the vertical direction DR3 of the third gate electrode G3 that overlaps with the third active region AR3 in the vertical direction DR3 may be equal to each other.

[0027] The upper surfaces of the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 may be formed at the same level on the substrate 100. For example, an upper surface G1u of the first gate electrode G1 that contacts the bottom surface of the first capping pattern 131, an upper surface G2u of the second gate electrode G2 that contacts the bottom surface of the second capping pattern 132, and an upper surface G3u of the third gate electrode G3 that contacts the bottom surface of the third capping pattern 133 may be formed at the same level on the substrate 100.

[0028] Each of the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 may include, for example, at least one of the following: titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof. Each of the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 may include a conductive metal oxide, a conductive metal oxynitride, and the like, and may include an oxidized form of the substances mentioned above.

[0029] The first source / drain region SD1 can be disposed on at least one side of the first gate electrode G1. The first source / drain region SD1 can be disposed on each of the first active pattern F1 and the second active pattern F2. The second source / drain region SD2 can be disposed on at least one side of the second gate electrode G2. The second source / drain region SD2 can be disposed on the second active region AR2. The third source / drain region SD3 can be disposed on at least one side of the third gate electrode G3. The third source / drain region SD3 can be disposed on the third active region AR3.

[0030] According to an embodiment, the upper surface of the second source / drain region SD2 can be formed at a level lower than the upper surface of the first source / drain region SD1. The upper surface of the third source / drain region SD3 can be formed at a level lower than the upper surface of the second source / drain region SD2. According to an embodiment, the thickness of the third source / drain region SD3 in the vertical direction DR3 can be greater than the thickness of the second source / drain region SD2 in the vertical direction DR3.

[0031] The first gate spacer 121 can extend along two sidewalls of the first gate electrode G1 in the second horizontal direction DR2. The second gate spacer 122 can extend along two sidewalls of the second gate electrode G2 in the second horizontal direction DR2. The third gate spacer 123 can extend along two sidewalls of the third gate electrode G3 in the second horizontal direction DR2.

[0032] Each of the first gate spacer 121, the second gate spacer 122, and the third gate spacer 123 can include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon dioxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0033] In the first region I, the first gate insulating layer 111 can include the first insulating layer 111. The first gate insulating layer 111 can be formed of a single film including the first insulating layer 111. The first gate insulating layer 111 can be disposed between the first gate spacers 121.

[0034] In the first region I, the first insulating layer 111 can be disposed along the sidewall and the bottom surface of the first gate electrode G1. According to an embodiment, the first insulating layer 111 can be disposed between the first active pattern F1 and the first gate electrode G1. The first insulating layer 111 can be disposed between the field insulating layer 105 and the first gate electrode G1. The first insulating layer 111 can be disposed between the first gate spacer 121 and the first gate electrode G1.

[0035] In the second region II, the second gate insulating layer 111 and the second gate insulating layer 112 may include a second insulating layer 112 and a first insulating layer 111 disposed on the second insulating layer 112. The first insulating layer 111 may be disposed along the sidewalls and the bottom surface of the second gate electrode G2. The second gate insulating layer 111 and the second gate insulating layer 112 may be disposed between the second gate spacers 122.

[0036] According to an embodiment, in the second region II, the first insulating layer 111 may be disposed between the second active region AR2 and the second gate electrode G2. The first insulating layer 111 may be disposed between the second gate spacer 122 and the second gate electrode G2. According to an embodiment, the second insulating layer 112 may be disposed between the second active region AR2 and the first insulating layer 111.

[0037] According to an embodiment, in the second region II, the width of the second insulating layer 112 in the first horizontal direction DR1 may be equal to the width of the first insulating layer 111 in the first horizontal direction DR1. According to an embodiment, the thickness of the second insulating layer 112 in the vertical direction DR3 may be greater than the thickness of the first insulating layer 111 in the vertical direction DR3.

[0038] In the third region III, the third gate insulating layer 111, the third gate insulating layer 112, and the third gate insulating layer 113 may include a first insulating layer 111, a second insulating layer 112, and a third insulating layer 113. The first insulating layer 111 may be disposed along the sidewalls and the bottom surface of the third gate electrode G3. The third gate insulating layer 111, the third gate insulating layer 112, and the third gate insulating layer 113 may be disposed between the third gate spacers 123.

[0039] According to an embodiment, in the third region III, the first insulating layer 111 may be disposed between the third active region AR3 and the third gate electrode G3. The first insulating layer 111 may be disposed between the third gate spacer 123 and the third gate electrode G3. According to an embodiment, the second insulating layer 112 may be disposed between the third active region AR3 and the first insulating layer 111. According to an embodiment, the third insulating layer 113 may be disposed between the third active region AR3 and the second insulating layer 112.

[0040] According to an embodiment, the width of the third insulating layer 113 in the first horizontal direction DR1 may be equal to each of the width of the second insulating layer 112 in the first horizontal direction DR1 and the width of the first insulating layer 111 in the first horizontal direction DR1. According to an embodiment, the thickness of the third insulating layer 113 in the vertical direction DR3 may be greater than the thickness of the second insulating layer 112 in the vertical direction DR3.

[0041] The first insulating layer 111 may include, for example, at least one of the following: silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), and a high-k material having a dielectric constant greater than that of silicon oxide (SiO2). The high-k material may include, for example, one or more of the following: hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanate, barium titanate, strontium titanate, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0042] Each of the second insulating layer 112 and the third insulating layer 113 may include, for example, silicon oxide (SiO2). In some other embodiments, each of the second insulating layer 112 and the third insulating layer 113 may include silicon oxynitride (SiON), silicon nitride (SiN), or a high-k material having a dielectric constant higher than that of silicon oxide (SiO2).

[0043] The first capping pattern 131 may be disposed on the first gate electrode G1, the first insulating layer 111, and the first gate spacer 121. The first capping pattern 131 may extend in the second horizontal direction DR2. The second capping pattern 132 may be disposed on the second gate electrode G2, the first insulating layer 111, and the second gate spacer 122. The second capping pattern 132 may extend in the second horizontal direction DR2. The third capping pattern 133 may be disposed on the third gate electrode G3, the first insulating layer 111, and the third gate spacer 123. The third capping pattern 133 may extend in the second horizontal direction DR2.

[0044] Each of the first capping pattern 131, the second capping pattern 132, and the third capping pattern 133 may include, for example, at least one of the following: silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxynitride carbon (SiOCN), and combinations thereof.

[0045] The first interlayer insulating layer 140 may be disposed on the field insulating layer 105. The first interlayer insulating layer 140 may be disposed on each of the first source / drain region SD1, the second source / drain region SD2, and the third source / drain region SD3, and the first gate spacer 121, the second gate spacer 122, and the third gate spacer 123. According to one embodiment, the upper surface of the first interlayer insulating layer 140 may be formed on the substrate 100 at the same level as the upper surfaces of the first capping pattern 131, the second capping pattern 132, and the third capping pattern 133.

[0046] The first interlayer insulating layer 140 may include, for example, at least one of the following: silicon oxide, silicon nitride, silicon oxycarbide, silicon oxynitride, silicon carbon oxynitride, and low-k materials. The low-k materials may include, for example, Fluorinated TetraEthylOrthoSilicate (FTEOS), Hydrogen SilsesQuioxane (HSQ), Bis-benzoCycloButene (BCB), TetraMethylOrthoSilicate (TMOS), OctaMethyleyCloTetraSiloxane (OMCTS), HexaMethylDiSiloxane (HMDS), TriMethylSilyl Borate (TMSB), DiAcetoxyDitertiaryButoSiloxane (DADBS), TriMethylSilil Phosphate (TMSP), PolyTetraFluoroEthylene (PTFE), Tonen SilaZen (TOSZ), Fluoride Silicate Glass (FSG), polyimide nanofoam such as polypropylene oxide, Carbon Doped silicon Oxide (CDO), Organo Silicate Glass (OSG), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof. However, the present disclosure is not limited thereto.

[0047] The etching stop layer 150 may be disposed on each of the first interlayer insulating layer 140 and the first capping pattern 131, the second capping pattern 132, and the third capping pattern 133. Although FIG. 2 shows the etching stop layer 150 formed as a single film, the present disclosure is not limited thereto. In some other embodiments, the etching stop layer 150 may be formed as multiple films. The etching stop layer 150 may include, for example, at least one of the following: silicon oxide, silicon nitride, silicon oxynitride, and low-k materials.

[0048] The second interlayer insulating layer 160 may be disposed on the etching stop layer 150. The second interlayer insulating layer 160 may include, for example, at least one of the following: silicon oxide, silicon nitride, silicon oxynitride, and low-k materials.

[0049] Hereinafter, a method of manufacturing a semiconductor device according to some embodiments will be described with reference to FIGS. 2 to 20.

[0050] FIGS. 3 to 20 are intermediate stage diagrams for explaining a method of manufacturing the semiconductor device illustrated in FIGS. 1 and 2 according to an embodiment.

[0051] Referring to FIG. 3, a substrate 100 may be provided, in which a first region I, a second region II, and a third region III are defined. Subsequently, a first mask pattern M1 may be formed on the upper surface of the substrate 100. Subsequently, the upper surface of the substrate 100 may be etched at the second region II by using the first mask pattern M1 as a mask to form a first trench TR1. In addition, the upper surface of the substrate 100 may be etched at the third region III by using the first mask pattern M1 as a mask to form a second trench TR2. According to an embodiment, the first trench TR1 and the second trench TR2 may be formed to have equal depths. That is, the lower surface of the first trench TR1 and the lower surface of the second trench TR2 may be formed at the same level on the substrate 100.

[0052] Referring to FIG. 4, a first insulating material layer 10 may be formed inside each of the first trench TR1 and the second trench TR2. The first insulating material layer 10 may include, for example, silicon oxide (SiO2). Thereafter, the first mask pattern M1 may be removed through a planarization process. Thus, the upper surface of the substrate 100 and the upper surface of the first insulating material layer 10 may be coplanar.

[0053] Referring to FIG. 5, a second mask pattern M2 may be formed on the upper surfaces of the substrate 100 and the first insulating material layer 10. Subsequently, by using the second mask pattern M2 as a mask to etch a part of the substrate 100 at the first region I, a first active pattern F1 and a second active pattern F2 extending in a first horizontal direction DR1 may be formed.

[0054] Referring to FIG. 6, a field insulating layer 105 may be formed to surround sidewalls of each of the first active pattern F1 and the second active pattern F2 and sidewalls of the second mask pattern M2. According to an embodiment, the upper surface of the field insulating layer 105 may be formed in the same plane as the upper surface of the second mask pattern M2.

[0055] Referring to FIG. 7, the third mask pattern M3 can be formed on the field insulating layer 105 and the second mask pattern M2. Subsequently, the third mask pattern M3 can be used as a mask to etch a part of the second mask pattern M2, a part of the first insulating material layer 10, a part of the field insulating layer 105, and a part of the substrate 100. Through this etching process, the first deep trench DT1 can be formed on the substrate 100 at the first region I, the second deep trench DT2 can be formed on the substrate 100 at the second region II, and the third deep trench DT3 can be formed on the substrate 100 at the third region III.

[0056] Therefore, the first active region AR1 defined by the first deep trench DT1 can be formed on the substrate 100 at the first region I, the second active region AR2 defined by the second deep trench DT2 can be formed on the substrate 100 at the second region II, and the third active region AR3 defined by the third deep trench DT3 can be formed on the substrate 100 at the third region III. Each of the first active region AR1, the second active region AR2, and the third active region AR3 can extend in the first horizontal direction DR1.

[0057] Referring to FIG. 8, the field insulating layer 105 can be further formed inside each of the first deep trench DT1, the second deep trench DR2, and the third deep trench DR3. Subsequently, the third mask pattern M3 and the second mask pattern M2 can be removed through a planarization process. Therefore, the upper surfaces of each of the first active pattern F1 and the second active pattern F2, the upper surface of the field insulating layer 105, and the upper surface of the first insulating material layer 10 can be formed at the same level on the substrate 100.

[0058] Referring to FIG. 9, the fourth mask pattern M4 can be formed in the first region I and the second region II. Subsequently, the fourth mask pattern M4 can be used as a mask to etch a part of the field insulating layer 105 and the first insulating material layer 10 formed in the third region III. For example, the first insulating material layer 10 formed in the third region III can be completely etched.

[0059] Referring to FIG. 10, the second insulating material layer 20 can be formed on the third active region AR3. According to an embodiment, a part of the upper portion of the third active region AR3 can be oxidized to form the second insulating material layer 20. The second insulating material layer 20 can include, for example, silicon oxide (SiO2).

[0060] Referring to FIG. 11, the first protective layer 30 can be formed in the first region I and the third region III. The first protective layer 30 can expose a part of the second insulating material layer 20 formed in the third region III.

[0061] Subsequently, the first protective layer 30 can be used as a mask to etch the fourth mask pattern M4 formed in the second region II, a part of the field insulating layer 105, and the first insulating material layer 10. For example, the first insulating material layer 10 formed in the second region II can be completely etched. In addition, an implantation groove IT can be formed by etching a part of the second insulating material layer 20 exposed in the third region III using the first protective layer 30 as a mask. The upper surface of the third active region AR3 can be exposed via the implantation groove IT.

[0062] Referring to FIG. 12, the second source / drain region SD2 can be formed in the second active region AR2. In addition, the third source / drain region SD3 can be formed in the third active region AR3 via the implantation groove IT. Subsequently, the first protective layer 30 can be removed. According to an embodiment, the thickness of the third source / drain region SD3 in the vertical direction DR3 can be formed to be greater than the thickness of the second source / drain region SD2 in the vertical direction DR3.

[0063] Referring to FIG. 13, the third insulating material layer 40 can be formed in the first region I, the second region II, and the third region III. For example, the third insulating material layer 40 can be conformally formed. For example, the upper surface of the third insulating material layer 40 formed in the second region II and the third region III can be formed at the same level as the upper surface of the first active pattern F1. The third insulating material layer 40 can include, for example, silicon oxide (SiO2).

[0064] Referring to FIG. 14, the third insulating material layer 40 formed in the first region I can be removed. Subsequently, the fifth mask pattern M5 can be formed on the fourth mask pattern M4 in the first region I and the third insulating material layer 40 in the second region II and the third region III.

[0065] Referring to FIG. 15, the second protective layer 50 can be formed on the fifth mask pattern M5 in the second region II and the third region III. Subsequently, the second protective layer 50 can be used as a mask to etch the fifth mask pattern M5 and the fourth mask pattern M4 in the first region I. In addition, a part of the field insulating layer 105 can be etched to expose the upper parts of each of the first active pattern F1 and the second active pattern F2.

[0066] Referring to FIG. 16, the second protective layer 50 and the fifth mask pattern M5 in the second region II and the third region III can be removed. Subsequently, the dummy gate material layer DGM can be formed on the first active pattern F1 and the second active pattern F2 in the first region I, the field insulating layer 105 in the first region I, and the third insulating material layer 40 in the second region II and the third region III.

[0067] Referring to FIG. 17, the sixth mask pattern M6 can be formed on the dummy gate material layer DGM. Next, the dummy gate material layer DGM can be etched using the sixth mask pattern M6 as a mask. Through this etching process, a plurality of dummy gates DG extending in the second horizontal direction DR2 can be formed in each of the first region I, the second region II, and the third region III.

[0068] The third insulating material layer 40 in the second region II can be etched while forming the plurality of dummy gates DG. The remaining unetched third insulating material layer 40 can be defined as the second insulating layer 112. In addition, the third insulating material layer 40 and the second insulating material layer 20 in the third region III can be etched while forming the plurality of dummy gates DG. The unetched third insulating material layer 40 in the third region III can also be defined as the second insulating layer 112, and the unetched second insulating material layer 20 in the third region III can be defined as the third insulating layer 113.

[0069] Referring to FIG. 18, gate spacers can be formed on two sidewalls of the plurality of dummy gates DG in the first horizontal direction DR1. For example, the first gate spacer 121 can be formed on two sidewalls of the dummy gate DG in the first region I, the second gate spacer 122 can be formed on two sidewalls of the dummy gate DG in the second region II, and the third gate spacer 123 can be formed on two sidewalls of the dummy gate DG in the third region III.

[0070] The first gate spacer 121 can also be formed on the sidewall of the sixth mask pattern M6 in the first region I. The second gate spacer 122 can also be formed on each of the sidewall of the sixth mask pattern M6 in the second region II and the sidewall of the second insulating layer 112 in the second region II. The third gate spacer 123 can also be formed on the sidewall of the sixth mask pattern M6 in the third region III, the sidewall of the second insulating layer 112 in the third region III, and the sidewall of the third insulating layer 113 in the third region III.

[0071] Subsequently, the third protective layer 60 can be formed in the first region I and the third region III. Subsequently, a part of the first active pattern F1 can be etched using the dummy gate DG and the first gate spacer 121 in the first region I as a mask. Subsequently, the first source / drain region SD1 can be formed in the etched part of a part of the first active pattern F1.

[0072] Referring to FIG. 19, the third protective layer 60 can be removed. Subsequently, the first interlayer insulating layer 140 can be formed on the first gate spacer 121, the second gate spacer 122, and the third gate spacer 123, the first source / drain region SD1, the second source / drain region SD2, and the third source / drain region SD3, and the sixth mask pattern M6. Subsequently, a portion of the first interlayer insulating layer 140 and the sixth mask pattern M6 can be etched via a planarization process to expose the plurality of dummy gates DG.

[0073] Thereafter, the plurality of dummy gates DG can be removed to form the first gate trench GT1, the second gate trench GT2, and the third gate trench GT3. According to an embodiment, the first gate trench GT1 can be defined by the first gate spacer 121 on the first active pattern F1 in the first region I. The second gate trench GT2 can be defined by the second gate spacer 122 on the second insulating layer 112 in the second region II. The third gate trench GT3 can be defined by the third gate spacer 123 on the second insulating layer 112 in the third region III.

[0074] Referring to FIG. 20, the first insulating layer 111 can be formed on each of the first active pattern F1, the second insulating layer 112 on the second active region AR2, and the second insulating layer 112 on the third active region AR3.

[0075] For example, the first insulating layer 111 can be formed along the sidewalls and bottom surface of the first gate trench (GT1 in FIG. 19) in the first region I. The first insulating layer 111 can be formed along the sidewalls and bottom surface of the second gate trench (GT2 in FIG. 19) in the second region II. The first insulating layer 111 can be formed along the sidewalls and bottom surface of the third gate trench (GT3 in FIG. 19) in the third region III.

[0076] Subsequently, the gate electrodes can be formed on the first insulating layer 111. For example, the first gate electrode G1 can be formed on the first insulating layer 111 in the first region I. The second gate electrode G2 can be formed on the first insulating layer 111 in the second region II. The third gate electrode G3 can be formed on the first insulating layer 111 in the third region III. Each of the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 can extend in the second horizontal direction DR2.

[0077] Subsequently, a first capping pattern 131 may be formed on the first gate electrode G1, the first insulating layer 111, and the first gate spacer 121. A second capping pattern 132 may be formed on the second gate electrode G2, the first insulating layer 111, and the second gate spacer 122. A third capping pattern 133 may be formed on the third gate electrode G3, the first insulating layer 111, and the third gate spacer 123.

[0078] Each of the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 may be formed to have the same thickness in a vertical direction DR3. For example, a first thickness (t1 in FIG. 2) of the first gate electrode G1 in the vertical direction DR3 that overlaps with the first active pattern F1 in the vertical direction DR3, a second thickness (t2 in FIG. 2) of the second gate electrode G2 in the vertical direction DR3 that overlaps with the second active region AR2 in the vertical direction DR3, and a third thickness (t3 in FIG. 2) of the third gate electrode G3 in the vertical direction DR3 that overlaps with the third active region AR3 in the vertical direction DR3 may be formed to be equal to each other.

[0079] The upper surface of each of the first gate electrode G1, the second gate electrode G2, and the third gate electrode G3 may be formed at the same level on the substrate 100. For example, an upper surface G1u of the first gate electrode G1 that contacts the lowermost surface of the first capping pattern 131, an upper surface G2u of the second gate electrode G2 that contacts the lowermost surface of the second capping pattern 132, and an upper surface G3u of the third gate electrode G3 that contacts the lowermost surface of the third capping pattern 133 may be formed at the same level on the substrate 100.

[0080] Subsequently, an etch stop layer 150 and a second interlayer insulating layer 160 may be sequentially formed on the first interlayer insulating layer 140 and each of the first capping pattern 131, the second capping pattern 132, and the third capping pattern 133, as illustrated in FIG. 2.

[0081] The semiconductor device and the method of manufacturing the semiconductor device according to the above embodiments may enable the low-voltage transistors, the intermediate-voltage transistors, and the high-voltage transistors formed on the same substrate to have respective gate electrodes with the same thickness and respective gate insulating layers with different thicknesses, thereby being formed at the same level on the substrate.

[0082] Hereinafter, a method of manufacturing a semiconductor device according to other embodiments will be described with reference to FIGS. 21 to 27. Differences in the method of manufacturing the semiconductor device illustrated in FIGS. 3 to 20 will be described below, and repeated descriptions will be omitted.

[0083] FIGS. 21 to 27 are intermediate stage diagrams for explaining a method of manufacturing a semiconductor device according to other embodiments.

[0084] Referring to FIG. 21, a substrate 100 is provided, in which a first region I, a second region II, and a third region III are defined. Subsequently, a first mask pattern M1 may be formed on the upper surface of the substrate 100. Subsequently, the upper surface of the substrate 100 at the second region II may be etched using the first mask pattern M1 as a mask to form a first trench TR1. In addition, the upper surface of the substrate 100 at the third region III may be etched using the first mask pattern M1 as a mask to form a third trench TR3. The third trench TR3 may be formed deeper than the first trench TR1. That is, the lower surface of the third trench TR3 may be formed at a level lower than the lower surface of the first trench TR1.

[0085] Referring to FIG. 22, a first insulating material layer 10 may be formed inside each of the first trench TR1 and the third trench TR3. Thereafter, the first mask pattern M1 may be removed via a planarization process.

[0086] Referring to FIG. 23, a second mask pattern M2 may be formed on the upper surfaces of the substrate 100 and the first insulating material layer 10. Subsequently, a part of the substrate 100 at the first region I may be etched using the second mask pattern M2 as a mask to form a first active pattern F1 and a second active pattern F2 extending in a first horizontal direction DR1.

[0087] Referring to FIG. 24, a field insulating layer 105 may be formed to surround sidewalls of each of the first active pattern F1 and the second active pattern F2 and sidewalls of the second mask pattern M2. For example, the upper surface of the field insulating layer 105 may be formed in the same plane as the upper surface of the second mask pattern M2.

[0088] Referring to FIG. 25, a third mask pattern M3 may be formed on the field insulating layer 105 and the second mask pattern M2. Subsequently, a part of the second mask pattern M2, a part of the first insulating material layer 10, a part of the field insulating layer 105, and a part of the substrate 100 may be etched using the third mask pattern M3 as a mask. Through this etching process, a first deep trench DT1 may be formed on the substrate 100 at the first region I, a second deep trench DT2 may be formed on the substrate 100 at the second region II, and a third deep trench DT3 may be formed on the substrate 100 at the third region III.

[0089] Referring to FIG. 26, the field insulating layer 105 may also be formed inside each of the first deep trench DT1, the second deep trench DR2, and the third deep trench DR3. Subsequently, the third mask pattern M3 and the second mask pattern M2 may be removed via a planarization process.

[0090] Referring to FIG. 27, a fourth mask pattern M4 may be formed in the first region I and the second region II. Subsequently, the fourth mask pattern M4 may be used as a mask to etch a part of the field insulating layer 105 formed in the third region III and a part of the first insulating material layer 10. The remaining unetched first insulating material layer 10 in the third region III may be defined as the second insulating material layer 20. For example, the upper surface of the second insulating material layer 20 in the third region III may be formed at the same level as the upper surface of the second active region AR2 in the second region II.

[0091] Subsequently, after performing the manufacturing processes illustrated in FIGS. 11 to 20, an etch stop layer 150 and a second interlayer insulating layer 160 may be sequentially formed on the first interlayer insulating layer 140 and each of the first capping pattern 131, the second capping pattern 132, and the third capping pattern 133. The semiconductor device illustrated in FIG. 2 may be manufactured by the foregoing method.

[0092] Hereinafter, a semiconductor device according to other embodiments will be described with reference to FIG. 28. The differences between the semiconductor devices illustrated in FIGS. 1 and 2 will be described below, and repeated descriptions will be omitted.

[0093] FIG. 28 is a cross-sectional view for explaining a semiconductor device according to other embodiments.

[0094] Referring to FIG. 28, in a semiconductor device according to other embodiments, a first insulating layer 211 may be formed on the bottom surface of each of the first gate electrode G21, the second gate electrode G22, and the third gate electrode G23. According to an embodiment, the sidewall of the first gate electrode G21 may be in contact with the first gate spacer 221. The sidewall of the second gate electrode G22 may be in contact with the second gate spacer 222. The sidewall of the third gate electrode G23 may be in contact with the third gate spacer 223.

[0095] A first capping pattern 231 may be disposed on the first gate electrode G21, a second capping pattern 232 may be disposed on the second gate electrode G22, and a third capping pattern 233 may be disposed on the third gate electrode G23. The first capping pattern 231 is disposed between the first gate spacers 221, the second capping pattern 232 is disposed between the second gate spacers 222, and the third capping pattern 233 may be disposed between the third gate spacers 223.

[0096] The thicknesses of the first gate electrode G21, the second gate electrode G22, and the third gate electrode G23 in the vertical direction DR3 may be equal to each other. For example, a fourth thickness t4 in the vertical direction DR3 of the first gate electrode G21 overlapping with the first active pattern F1 in the vertical direction DR3, a fifth thickness t5 in the vertical direction DR3 of the second gate electrode G22 overlapping with the second active region AR2 in the vertical direction DR3, and a sixth thickness t6 in the vertical direction DR3 of the third gate electrode G23 overlapping with the third active region AR3 in the vertical direction DR3 may be equal to each other.

[0097] The upper surfaces of the first gate electrode G21, the second gate electrode G22, and the third gate electrode G23 may be formed at the same level on the substrate 100. For example, an upper surface G21u of the first gate electrode G21 in contact with the lowermost surface of the first capping pattern 231, an upper surface G22u of the second gate electrode G22 in contact with the lowermost surface of the second capping pattern 232, and an upper surface G23u of the third gate electrode G23 in contact with the lowermost surface of the third capping pattern 233 may be formed at the same level on the substrate 100.

[0098] Hereinafter, a method of manufacturing a semiconductor device according to other embodiments will be described with reference to FIGS. 28 to 32. The differences from the method of manufacturing the semiconductor device illustrated in FIGS. 3 to 20 will be described, and repeated descriptions will be omitted.

[0099] FIGS. 29 to 32 are intermediate stage diagrams for explaining a method of manufacturing a semiconductor device according to other embodiments.

[0100] Referring to FIG. 29, after performing the manufacturing processes illustrated in FIGS. 3 to 15, the second protective layer (50 in FIG. 15) and the fifth mask pattern (M5 in FIG. 15) in the second region II and the third region III may be removed. Subsequently, a fourth insulating material layer 80 may be formed on the first active pattern F1 and the second active pattern F2 in the first region I, the field insulating layer 105 in the first region I, and the third insulating material layer 40 in the second region II and the third region III. For example, the fourth insulating material layer 80 may be conformally formed.

[0101] Subsequently, a gate material layer GM may be formed on the fourth insulating material layer 80 in the first region I, the second region II, and the third region III. The upper surface of the gate material layer GM may be formed flat via a planarization process. Next, a capping material layer 130M may be formed on the gate material layer GM in the first region I, the second region II, and the third region III. For example, the capping material layer 130M may be conformally formed.

[0102] Referring to FIG. 30, via a patterning process, the fourth insulating material layer 80 is etched to form the first insulating layer 211, and the gate material layer GM can be etched to form the first gate electrode G21, the second gate electrode G22, and the third gate electrode G23.

[0103] Specifically, the sixth mask pattern M6 can be formed on the cover material layer 130M. Next, the sixth mask pattern M6 can be used as a mask to etch the cover material layer 130M, the gate material layer GM, the fourth insulating material layer 80, the third insulating material layer 40, and the second insulating material layer 20.

[0104] For example, in the first region I, by using the sixth mask pattern M6 as a mask, the cover material layer 130M can be etched to form the first cover pattern 231, the gate material layer GM can be etched to form the first gate electrode G21, and the fourth insulating material layer 80 can be etched to form the first insulating layer 211.

[0105] In addition, in the second region II, by using the sixth mask pattern M6 as a mask, the cover material layer 130M can be etched to form the second cover pattern 232, the gate material layer GM can be etched to form the second gate electrode G22, the fourth insulating material layer 80 can be etched to form the first insulating layer 211, and the third insulating material layer 40 can be etched to form the second insulating layer 112.

[0106] In addition, in the third region III, by using the sixth mask pattern M6 as a mask, the cover material layer 130M can be etched to form the third cover pattern 233, the gate material layer GM can be etched to form the third gate electrode G23, the fourth insulating material layer 80 can be etched to form the first insulating layer 211, the third insulating material layer 40 can be etched to form the second insulating layer 112, and the second insulating material layer 20 can be etched to form the third insulating layer 113.

[0107] Referring to FIG. 31, the sixth mask pattern M6 can be removed. Subsequently, in the first region I, the first gate spacer 221 can be formed on both sidewalls of each of the first cover pattern 231, the first gate electrode G21, and the first insulating layer 211 in the first horizontal direction DR1.

[0108] In addition, in the second region II, the second gate spacer 222 may be formed on two sidewalls of each of the second capping pattern 232, the second gate electrode G22, the first insulating layer 211, and the second insulating layer 112 in the first horizontal direction DR1. In addition, in the third region III, the third gate spacer 223 may be formed on two sidewalls of each of the third capping pattern 233, the third gate electrode G23, the first insulating layer 211, the second insulating layer 112, and the third insulating layer 113 in the first horizontal direction DR1.

[0109] Referring to FIG. 32, the third protection layer 60 may be formed in the first region I and the third region III. Subsequently, the first capping pattern 231 and the first gate spacer 221 in the first region I may be used as masks to etch a part of the first active pattern F1. Subsequently, the first source / drain region SD1 may be formed at a position where a part of the first active pattern F1 has been etched.

[0110] Referring to FIG. 28, the third protection layer 60 may be removed. Subsequently, the first gate spacer 221, the second gate spacer 222, the third gate spacer 223, the first source / drain region SD1, the second source / drain region SD2, and the third source / drain region SD3, and the first interlayer insulating layer 140 may be formed. Subsequently, a part of the first interlayer insulating layer 140 may be etched via a planarization process to expose the first capping pattern 231, the second capping pattern 232, and the third capping pattern 233.

[0111] Subsequently, the etch stop layer 150 and the second interlayer insulating layer 160 may be sequentially formed on the first interlayer insulating layer 140 and each of the first capping pattern 231, the second capping pattern 232, and the third capping pattern 233. The semiconductor device illustrated in FIG. 28 may be manufactured by the foregoing method.

[0112] Hereinafter, a semiconductor device according to other embodiments will be described with reference to FIG. 33. The differences between the semiconductor devices illustrated in FIGS. 1 and 2 will be described, and repeated descriptions will be omitted.

[0113] FIG. 33 is a cross-sectional view for explaining a semiconductor device according to some other embodiments.

[0114] Referring to FIG. 33, in a semiconductor device according to other embodiments, the first insulating layer 111 may be disposed along the sidewalls and the bottom surface of the first gate electrode G1 in the first region I. In addition, the first insulating layer 211 may be formed on the bottom surface of the second gate electrode G22 in the second region II. In addition, the first insulating layer 211 may be formed on the bottom surface of the third gate electrode G23 in the third region III. According to an embodiment, the sidewalls of the second gate electrode G22 may be in contact with the second gate spacer 222, and the sidewalls of the third gate electrode G23 may be in contact with the third gate spacer 223.

[0115] The second capping pattern 232 may be disposed on the second gate electrode G22, and the third capping pattern 233 may be disposed on the third gate electrode G23. The second capping pattern 232 may be disposed between the second gate spacers 222, and the third capping pattern 233 may be disposed between the third gate spacers 223.

[0116] The thicknesses of the first gate electrode G1, the second gate electrode G22, and the third gate electrode G23 in the vertical direction DR3 may be equal to each other. For example, a first thickness t1 of the first gate electrode G1 in the vertical direction DR3 that overlaps with the first active pattern F1 in the vertical direction DR3, a fifth thickness t5 of the second gate electrode G22 in the vertical direction DR3 that overlaps with the second active region AR2 in the vertical direction DR3, and a sixth thickness t6 of the third gate electrode G23 in the vertical direction DR3 that overlaps with the third active region AR3 in the vertical direction DR3 may be equal to each other.

[0117] The upper surfaces of the first gate electrode G1, the second gate electrode G22, and the third gate electrode G23 may be formed at the same level on the substrate 100. For example, an upper surface G1u of the first gate electrode G1 that is in contact with the bottom surface of the first capping pattern 131, an upper surface G22u of the second gate electrode G22 that is in contact with the bottom surface of the second capping pattern 232, and an upper surface G23u of the third gate electrode G23 that is in contact with the bottom surface of the third capping pattern 233 may be formed at the same level on the substrate 100.

[0118] In summarizing the detailed description, those of ordinary skill in the art will understand that many variations and modifications can be made to the above embodiments without substantially departing from the principles. Therefore, the embodiments of the present disclosure are for general and descriptive purposes only and are not for restrictive purposes.

Brief Description of the Drawings

[0009] The foregoing and other aspects and features of the disclosure will become more apparent by referring to the accompanying drawings which detail exemplary embodiments thereof, wherein: FIG. 1 is a schematic layout diagram for explaining a semiconductor device according to an embodiment. FIG. 2 is a cross-sectional view taken along each of lines A-A', B-B', C-C', and D-D' of FIG. 1. FIGS. 3 to 20 are intermediate stage diagrams for explaining a method of manufacturing a semiconductor device according to an embodiment. FIGS. 21 to 27 are intermediate stage diagrams for explaining a method of manufacturing a semiconductor device according to an embodiment. FIG. 28 is a cross-sectional view for explaining a semiconductor device according to an embodiment. FIGS. 29 to 32 are intermediate stage diagrams for explaining a method of manufacturing a semiconductor device according to an embodiment. FIG. 33 is a cross-sectional view for explaining a semiconductor device according to an embodiment.

Claims

1. A semiconductor device, comprising: The base, which includes the first, second and third zones; The first active region, within the first region; An active pattern is present on the first active region; The second active area, within the second area; A third active region is located in the third region; a first gate electrode is located on the active pattern; The second gate electrode is located on the second active region; A third gate electrode is located in the third active region; a first gate insulating layer includes a first first insulating layer between the active pattern and the first gate electrode; a second gate insulating layer includes a second first insulating layer and a second second insulating layer below the second first insulating layer between the second active region and the second gate electrode. And a third gate insulating layer, including a third first insulating layer, a third second insulating layer below the third first insulating layer, and a third third insulating layer below the third second insulating layer, between the third active region and the third gate electrode, wherein the thickness of the first gate electrode overlapping the active pattern in the vertical direction is equal to the thickness of the second gate electrode overlapping the second active region in the vertical direction, and wherein the upper surface of the first gate electrode is formed at the same level as the upper surface of the second gate electrode.

2. The semiconductor device of claim 1, wherein the upper surface of the second active region is located at a level between the upper surface of the first active region and the upper surface of the active pattern.

3. The semiconductor device of claim 1, wherein the first insulating layer is on the sidewall and bottom surface of the first gate electrode.

4. The semiconductor device as claimed in claim 3, wherein the second first insulating layer is on the sidewall and bottom surface of the second gate electrode.

5. The semiconductor device as claimed in claim 1, further comprising: The first gate spacer is located on the sidewall of the first gate electrode; and a second gate spacer on the sidewall of the second gate electrode, wherein the first gate insulating layer is between the first gate spacers and the second gate insulating layer is between the second gate spacers.

6. The semiconductor device of claim 5, wherein the sidewall of the first gate electrode contacts the first gate spacer, and wherein the sidewall of the second gate electrode contacts the second gate spacer.

7. The semiconductor device of claim 1, wherein the thickness of the third gate electrode overlapping the third active region in the vertical direction is equal to the thickness of the first gate electrode overlapping the active pattern in the vertical direction.

8. The semiconductor device of claim 1, wherein the upper surface of the third gate electrode is formed at the same level as the upper surface of the first gate electrode.

9. A semiconductor device, comprising: The base, which includes regions one through three; The first active region, within the first region; An active pattern is present on the first active region; The second active area, within the second area; A third active region is located in the third region; a first gate electrode is located on the active pattern; The second gate electrode is located on the second active region; A third gate electrode is located on the third active region; a first gate insulating layer, including a first first insulating layer, is located between the active pattern and the first gate electrode. The second gate insulating layer includes a second first insulating layer and a second second insulating layer below the second first insulating layer, between the second active region and the second gate electrode; and a third gate insulating layer includes a third first insulating layer, a third second insulating layer below the third first insulating layer and a third third insulating layer below the third second insulating layer, between the third active region and the third gate electrode, wherein the thickness of the first gate electrode overlapping the active pattern in the vertical direction, the thickness of the second gate electrode overlapping the second active region in the vertical direction, and the thickness of the third gate electrode overlapping the third active region in the vertical direction are all equal to each other, and wherein the upper surfaces of the first gate electrode, the second gate electrode, and the third gate electrode are formed at the same level on the substrate.

10. The semiconductor device of claim 9, wherein the thickness of the third insulating layer in the vertical direction is greater than the thickness of the third second insulating layer in the vertical direction, and wherein the thickness of the third second insulating layer in the vertical direction is greater than the thickness of the third first insulating layer in the vertical direction.

11. The semiconductor device of claim 9, wherein the upper surface of the second active region is formed at a level below the upper surface of the active pattern, and wherein the upper surface of the third active region is formed at a level below the upper surface of the second active region.

12. The semiconductor device as claimed in claim 9, further comprising: The first source / drain region is disposed on at least one side of the first gate electrode; The second source / drain region is disposed on at least one side of the second gate electrode; And a third source / drain region disposed on at least one side of the third gate electrode, wherein the upper surface of the second source / drain region is formed at a level lower than the upper surface of the first source / drain region, and wherein the upper surface of the third source / drain region is formed at a level lower than the upper surface of the second source / drain region.

13. The semiconductor device of claim 12, wherein the thickness of the third source / drain region in the vertical direction is greater than the thickness of the second source / drain region in the vertical direction.

14. A method of manufacturing a semiconductor device, the method comprising: A substrate is provided, wherein the substrate includes a first region to a third region; The upper surface of the substrate is etched at the second region to form a first trench, and the upper surface of the substrate is etched at the third region to form a second trench; a first insulating material layer is formed inside each of the first trench and the second trench; the substrate is etched at the first region to form an active pattern; the substrate is etched at each of the first to third regions to form a first active region to a third active region; at least a portion of the first insulating material layer formed on the third active region is etched; A second insulating material layer is formed on the third active region; the first insulating material layer formed on the second active region is etched. A third insulating material layer is formed on each of the second insulating material layers in the second active region and the third active region; an insulating layer is formed on each of the active pattern, the third insulating material layer formed on the second active region, and the third insulating material layer formed on the third active region; and a first gate electrode is formed on the insulating layer on the active pattern, a second gate electrode is formed on the insulating layer on the second active region, and a third gate electrode is formed on the insulating layer on the third active region, wherein the thickness of the first gate electrode overlapping the active pattern in the vertical direction, the thickness of the second gate electrode overlapping the second active region in the vertical direction, and the thickness of the third gate electrode overlapping the third active region in the vertical direction are equal to each other, and wherein the upper surfaces of the first gate electrode, the second gate electrode, and the third gate electrode are formed at the same horizontal level.

15. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the formation of the second insulating material layer on the third active region comprises: The first insulating material layer formed on the third active region is completely etched; And oxidize a portion of the upper part of the third active region to form the second insulating material layer.

16. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the formation of the second insulating material layer on the third active region comprises etching a portion of the first insulating material layer formed on the third active region to form the second insulating material layer on the third active region.

17. The method of manufacturing a semiconductor device as claimed in claim 16, wherein the lower surface of the second trench is formed at a level below the lower surface of the first trench.

18. A method of manufacturing a semiconductor device as claimed in claim 14, wherein the formation of the insulating layer comprises: A virtual gate is formed on each of the active pattern, the third insulating material layer formed on the second active region, and the third insulating material layer formed on the third active region; A gate spacer is formed on the sidewall of the virtual gate; Remove the virtual gate to form a gate trench; and form the insulating layer on the sidewalls and bottom surface of the gate trench.

19. The method of manufacturing a semiconductor device as claimed in claim 14, wherein the formation of the insulating layer and the first gate electrode to the third gate electrode comprises: A fourth insulating material layer is formed on each of the active pattern, the third insulating material layer formed on the second active region, and the third insulating material layer formed on the third active region; A gate material layer is formed on the fourth insulating material layer; And patterning the fourth insulating material layer and the gate material layer to form the insulating layer and the first gate electrode to the third gate electrode.

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