Manufacturing methods for metal wiring, manufacturing methods for transistors, metal wiring, transistors and electronic components

Abstract

A method for manufacturing a metal wiring, which is a method for manufacturing a metal wiring on a substrate, includes the steps of: forming a first layer comprising a first material on at least a portion of the substrate; forming cracks in the first layer to form a cracked first layer; and forming a second layer comprising a second material on the cracked first layer.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing metal wiring, a method for manufacturing transistors, and metal wiring. This application claims priority based on Japanese Patent Application No. 2021-125285, filed on July 30, 2021, the contents of which are incorporated herein by reference. [Previous Technology]

[0002] Previously, as a method for manufacturing components such as transistors, the application of inexpensive solution processing, which is suitable for large-scale production, was studied. If a solution processing method is used, transistors and the like can be manufactured at lower temperatures than before. Furthermore, flexible organic transistors can also be manufactured by forming an organic semiconductor layer using an organic semiconductor material on a flexible substrate using a resin material.

[0003] In the transistor manufacturing method described above, chemical plating (electrolytic plating) can be used, which is a reduction plating method that utilizes the contact action of the material surface. Since no electrical energy is used in electroless plating, it can also be applied to insulators such as resin materials or glass.

[0004] For example, Patent Document 1 describes a method for manufacturing a thin-film transistor that selectively forms source and drain electrodes by performing an electroless plating process. On the other hand, when using a flexible substrate, it is preferable to maintain the conductivity of wiring, etc., even when the substrate is bent. [Prior Art Documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Application Publication No. 2014-123670 [Summary of the Invention]

[0006] The first aspect of the present invention is a method for manufacturing a metal wiring, which is a method for manufacturing a metal wiring on a substrate, comprising: a first layer forming step of forming a first layer comprising a first material on at least a portion of the substrate; a step of forming cracks on the first layer to form a first layer having cracks; and a step of forming a second layer comprising a second material on the first layer having cracks.

[0007] The second aspect of the present invention is a metal wiring, which is a metal wiring disposed on a substrate. The metal wiring includes a gold layer or a copper layer on a nickel-phosphorus layer. The resistance increase rate of the metal wiring before and after the buckling test using a Tension-Free U-shape Folding Tester with a bending radius of 5 mm and 100 bending times is 7.0% or less.

[0008] The third aspect of the present invention is a metal wiring, which is a metal wiring disposed on a substrate. The metal wiring includes a first layer, a second layer and a third layer. In a direction perpendicular to a predetermined plane including the substrate, the first layer is a layer containing a first material, the second layer includes a first region containing the first material and a second region containing a second material, and the third layer contains the second material.

Implementation Method

[0010] Hereinafter, a preferred embodiment of the method for manufacturing the metal wiring of the present invention will be described. However, the present invention is not limited to these embodiments.

[0011] <Method for Manufacturing Metal Wiring> This embodiment is a method for manufacturing metal wiring on a flexible substrate. This embodiment includes the steps of: forming a first layer comprising nickel-phosphorus (a first material) on at least a portion of the substrate by electroless plating; forming cracks in the first layer to form a cracked first layer; and contacting a displacement gold plating bath or a displacement copper plating bath on the cracked first layer to form a second layer comprising gold or copper (a second material).

[0012] In the step of forming cracks, cracks are intentionally formed on the first layer in a direction substantially orthogonal to the substrate. The shape of the cracks is not particularly limited, but it is preferable to form uniform cracks, such as mesh-like cracks.

[0013] In this embodiment, the crack may be shallowly formed near the surface of the first layer, or it may be formed by breaking the first layer through the crack. In this embodiment, a nickel-phosphorus layer and an interstitial portion are alternately formed by forming cracks on the first layer.

[0014] The term "crack" in this specification refers to a fine crack, crazing, fine peeling, or other damage that occurs on the first layer, or a broken line in the first layer. There is no particular limitation on the depth of the crack. For example, when the thickness of the first layer is 50 to 100 nm, the depth of the crack is preferably 50 to 100 nm.

[0015] If a replacement gold plating bath or a replacement copper plating bath is brought into contact with the first layer having cracks, a replacement gold plating layer or a replacement copper plating layer is formed by filling the gaps in the formed cracks.

[0016] For example, a flexible substrate with metal wiring formed using nickel-phosphorus as the forming material is conceived for use by bending. If cracks are generated by bending the nickel-phosphorus wiring, the conductivity is impaired, resulting in problems such as increased resistance or wire breakage.

[0017] In this embodiment, cracks are intentionally formed on the first layer, and then a gold-plating bath or a copper-plating bath is contacted to form a second layer containing gold or copper. In this way, even if the manufactured substrate is bent, it is difficult to generate new cracks and the conductivity is maintained.

[0018] Hereinafter, preferred embodiments of the present invention will be described.

[0019] First Embodiment Referring to FIG1, the first embodiment will be described. The first embodiment includes, in sequence, the steps of forming a first layer, forming a crack, removing the resist layer, and forming a second layer.

[0020] [First layer formation step] First, in the step of forming the first layer, as shown in FIG1(a), a nickel-phosphorus layer 32 is formed on the substrate 31 by electroless plating.

[0021] Next, as shown in Figure 1(b), a corrosion-resistant layer 33 is formed on the nickel-phosphorus layer 32.

[0022] Next, the resist layer 33 is developed by irradiating it with pattern light. After development, the resist layer 33 and the nickel-phosphorus layer 32 are etched. Thereby, as shown in FIG1(c), the nickel-phosphorus layer 32a and the resist layer 33a with a predetermined pattern shape are formed on the substrate 31.

[0023] [Crack Formation Step] A crack 34 is formed on the nickel-phosphorus layer 32a using a crack formation method. The crack formation method is described later. Thereby, as shown in FIG1(d), a nickel-phosphorus layer 32b with cracks is formed on the substrate 31.

[0024] [Resist Removal Step] After the crack 34 is formed, the resist layer 33a is removed. Thereby, as shown in FIG1(e), a cracked nickel-phosphorus layer 32b is formed on the substrate 31.

[0025] [Second Layer Formation Step] Then, a second layer 35a containing gold or copper is formed by contacting a displacement gold plating bath or a displacement copper plating bath on the cracked first layer 32b (the cracked nickel-phosphorus layer 32b). Thus, as shown in FIG1(f), the second layer 35a containing gold or copper is formed by filling the gaps of the formed cracks.

[0026] Second Embodiment Referring to FIG2, the second embodiment will be described. The second embodiment includes, in sequence, the steps of forming the first layer, forming cracks, forming a resist layer, and forming the second layer.

[0027] [First layer formation step] First, as shown in FIG2(a), in the step of forming the first layer, a nickel-phosphorus layer 32 is formed on the substrate 31 by electroless plating.

[0028] [Steps for forming cracks] Next, cracks 34 are formed on the nickel-phosphorus layer 32 using a crack forming method. The crack forming method is described later. Thus, as shown in FIG2(b), a nickel-phosphorus layer 32c with cracks 34 is formed on the substrate 31.

[0029] [Steps for forming the resist layer] Next, as shown in FIG2(c), a resist layer 33 is formed on the nickel-phosphorus layer 32c on which the crack 34 is formed.

[0030] Next, the resist layer 33 is developed by irradiating pattern light. After development, the resist layer 33 and the nickel-phosphorus layer 32c are etched. Thereby, as shown in FIG2(d), the nickel-phosphorus layer 32b and the resist layer 33a with a predetermined pattern shape of cracks are formed on the substrate 31.

[0031] [Resist Removal Step] Then, the resist layer 33a is removed. Thereby, as shown in FIG2(e), a cracked nickel-phosphorus layer 32b is formed on the substrate 31.

[0032] [Second Layer Formation Step] Then, a second layer 35a containing gold or copper is formed by contacting a gold-plating bath or a copper-plating bath with the first layer 32b having cracks. In this way, as shown in FIG2(f), the second layer 35a containing gold or copper is formed by filling the gaps of the formed cracks.

[0033] Third Embodiment Referring to FIG3, the third embodiment will be described. The third embodiment includes, in sequence, the steps of forming a first layer, forming a crack, forming a second layer, and forming a resist layer.

[0034] [First layer formation step] First, as shown in FIG3(a), in the step of forming the first layer, a nickel-phosphorus layer 32 is formed on the substrate 31 by electroless plating.

[0035] [Steps for forming cracks] Next, cracks 34 are formed on the nickel-phosphorus layer 32 using a crack forming method. The crack forming method is described later. Thus, as shown in FIG3(b), a nickel-phosphorus layer 32c with cracks 34 is formed on the substrate 31.

[0036] [Second Layer Formation Step] Then, a second layer 35 containing gold or copper is formed by contacting a gold-plating bath or a copper-plating bath on the first layer 32c with cracks. In this way, as shown in FIG3(c), the second layer 35 containing gold or copper is formed by filling the gaps of the formed cracks.

[0037] [Steps for forming the resist layer] Next, as shown in FIG3(d), a resist layer 33 is formed on the second layer 35 containing gold or copper.

[0038] Next, the resist layer 33 is developed by irradiating pattern light. After development, the resist layer 33, the second layer 35 containing gold or copper, and the nickel-phosphorus layer 32c are etched. Thereby, as shown in FIG3(e), the nickel-phosphorus layer 32b with a predetermined pattern of cracks, the second layer 35a containing gold or copper, and the resist layer 33a are formed on the substrate 31.

[0039] [Resist Removal Step] Then, the resist layer 33a is removed. Thereby, as shown in FIG3(f), a nickel-phosphorus layer 32b having a predetermined pattern of cracks and a second layer 35a containing gold or copper are formed on the substrate 31.

[0040] 《Fourth Embodiment》 Referring to FIG4, the fourth embodiment will be described. The fourth embodiment includes, in sequence, the steps of forming a resist layer on a substrate, developing the resist layer by irradiating pattern light, forming a first layer on the substrate exposed after development, forming a crack, forming a second layer, and removing the resist layer.

[0041] [Resist Layer Formation Step] In this embodiment, firstly, as shown in FIG4(a), a resist layer 33 is formed on the substrate 31. Secondly, the resist layer 33 is developed by irradiating pattern light. Thereby, as shown in FIG4(b), the substrate exposed portion P exposed after development and the resist layer 33a are formed on the substrate 31.

[0042] [Step of forming the first layer] A nickel-phosphorus layer 32a is formed on the exposed portion P of the substrate by electroless plating. Thus, as shown in FIG4(c), a resist layer 33a and a nickel-phosphorus layer 32a are formed on the substrate 31.

[0043] [Steps for forming cracks] Next, cracks 34 are formed on the nickel-phosphorus layer 32a using a crack forming method. The crack forming method is described later. Thus, as shown in FIG4(d), a nickel-phosphorus layer 32b with cracks 34 is formed on the substrate 31.

[0044] [Steps for forming the second layer] Then, by contacting a gold-plating bath or a copper-plating bath on the cracked first layer 32b, a second layer 35a containing gold or copper is formed. In this way, as shown in FIG4(e), the second layer 35a containing gold or copper is formed by filling the gaps of the formed cracks.

[0045] [Resist Removal Step] Then, the resist layer 33a is removed. Thereby, as shown in FIG4(f), a nickel-phosphorus layer 32b having a predetermined pattern of cracks and a second layer 35a containing gold or copper are formed on the substrate 31.

[0046] 《Fifth Embodiment》 Referring to FIG5, the fifth embodiment will be described. The fifth embodiment includes the following steps in sequence: forming a resist layer on a substrate, developing the resist layer by irradiating pattern light, forming a first layer on the substrate exposed after development, removing the resist layer, forming cracks, and forming a second layer.

[0047] [Resist Layer Formation Step] In this embodiment, firstly, as shown in FIG5(a), a resist layer 33 is formed on the substrate 31. Secondly, the resist layer 33 is developed by irradiating pattern light. Thereby, as shown in FIG5(b), the substrate exposed portion P exposed after development and the resist layer 33a are formed on the substrate 31.

[0048] [Step of forming the first layer] A nickel-phosphorus layer 32a is formed on the exposed portion P of the substrate by electroless plating. Thus, as shown in FIG5(c), a resist layer 33a and a nickel-phosphorus layer 32a are alternately formed on the substrate 31.

[0049] [Resist Removal Step] Then, the resist layer 33a is removed. Thereby, as shown in FIG5(d), a nickel-phosphorus layer 32a with a predetermined pattern shape is formed on the substrate 31.

[0050] [Steps for forming cracks] Next, cracks 34 are formed on the nickel-phosphorus layer 32a using a crack forming method. The crack forming method is described later. Thereby, as shown in FIG5(e), a nickel-phosphorus layer 32b with a predetermined pattern of cracks 34 is formed on the substrate 31.

[0051] [Steps for forming the second layer] Then, a second layer 35a containing gold or copper is formed by contacting a replacement gold plating bath or a replacement copper plating bath on the first layer 32b, which has a predetermined pattern shape with cracks. In this way, as shown in FIG5(f), the second layer 35a containing gold or copper is formed by filling the gaps of the formed cracks.

[0052] Sixth Embodiment Referring to FIG6, the sixth embodiment will be described. The sixth embodiment includes the following steps in sequence: forming a resist layer on a substrate, developing the resist layer by irradiating pattern light, forming a first layer on the substrate exposed after development, forming a crack, removing the resist layer, and forming a second layer.

[0053] [Resist Layer Formation Step] In this embodiment, firstly, as shown in FIG6(a), a resist layer 33 is formed on the substrate 31. Secondly, the resist layer 33 is developed by irradiating pattern light. Thereby, as shown in FIG6(b), the substrate exposed portion P exposed after development and the resist layer 33a are formed on the substrate 31.

[0054] [Step of forming the first layer] A nickel-phosphorus layer 32a is formed on the exposed portion P of the substrate by electroless plating. Thus, as shown in FIG6(c), a resist layer 33a and a nickel-phosphorus layer 32a are alternately formed on the substrate 31.

[0055] [Steps for forming cracks] Next, cracks 34 are formed on the nickel-phosphorus layer 32a using a crack forming method. The crack forming method is described later. Thus, as shown in FIG6(d), a resist layer 33a and a nickel-phosphorus layer 32b with cracks are alternately formed on the substrate 31.

[0056] [Resist Removal Step] Then, the resist layer 33a is removed. Thereby, as shown in FIG6(e), a nickel-phosphorus layer 32b with a predetermined pattern shape and forming cracks is formed on the substrate 31.

[0057] [Steps for forming the second layer] Then, a second layer 35a containing gold or copper is formed by contacting a gold-plating bath or a copper-plating bath with the first layer 32b having cracks. In this way, as shown in FIG6(f), the second layer 35a containing gold or copper is formed by filling the gaps of the formed cracks.

[0058] The metal wiring of embodiments 1 to 6 will be described using FIG10. FIG10 is a side view of the metal wiring. The metal wiring can be considered as having a 3-layer structure divided by dashed lines in FIG10. More specifically, it consists of the following 3 layers: layer A (layer 1) 32a, which includes a first material, namely a nickel-phosphorus layer; layer B (layer 2) 36, which includes a first region containing nickel-phosphorus and a second region containing a second material, namely gold or copper; and layer C (layer 3) 35a, which contains gold or copper. Layer B is formed by gold or copper, which becomes the second material, entering into the crack gaps of the nickel-phosphorus layer, thus becoming a layer including the first region and the second region.

[0059] In the above embodiments 1 to 6, the first material of the first layer is described as nickel-phosphorus, and the second material of the second layer is described as gold or copper, but it is not limited to this. Materials used for metal wiring can also be appropriately selected as the first material and the second material.

[0060] Substrate Processing Apparatus Figure 7 shows a schematic diagram of the overall structure of the substrate processing apparatus used in the metal wiring manufacturing method of this embodiment. The substrate processing apparatus 100 shown in Figure 7 includes: a processing tank BT1 for contacting an electroless plating solution on a long strip sheet substrate S, a processing tank BT2 for etching, a crack forming means CR, and a processing tank BT3 for replacement gold plating or copper plating.

[0061] These devices are appropriately arranged along the conveying path of the sheet substrate S, enabling production in a so-called roll-to-roll manner.

[0062] In the manufacturing method of the metal wiring of this embodiment, as shown in FIG7, an XYZ coordinate system is set, and the XYZ coordinate system will be used appropriately for the following description. The XYZ coordinate system sets the X-axis and Y-axis along the horizontal plane, and sets the Z-axis upward along the vertical direction. Furthermore, the substrate processing apparatus 100 as a whole transports the sheet substrate S along the X-axis from its negative side (-side) to its positive side (+side). At this time, the width direction (short strip direction) of the sheet substrate S is set as the Y-axis direction.

[0063] The sheet substrate S, which is to be processed in the substrate processing apparatus 100, may use a resin film, for example. For example, the resin film may use materials such as: polyolefin resin, polysilicon resin, polyethylene resin, polypropylene resin, polyester resin, ethylene-vinyl alcohol copolymer resin, polyvinyl chloride resin, cellulose resin, polyamide resin, polyimide resin, polycarbonate resin, polystyrene resin, vinyl acetate resin, etc.

[0064] The width direction (short strip direction) dimension of the sheet substrate S is, for example, formed to be about 1 m to 2 m, and the length direction (long strip direction) dimension is, for example, formed to be 10 m or more. Of course, this dimension is only one example and is not limited thereto. For example, the Y direction dimension of the sheet substrate S can be 50 cm or less, or it can be 2 m or more. Furthermore, the X direction dimension of the sheet substrate S can be 10 m or less.

[0065] The sheet substrate S is preferably formed in a flexible form. Here, flexibility refers to the property that the substrate will not break or fracture even when subjected to a force equal to its own weight, and that the substrate can be bent. Furthermore, the property of bending under its own weight is also included in flexibility.

[0066] Furthermore, the aforementioned flexibility varies depending on the material, size, thickness, or environmental factors such as temperature of the substrate. The following describes each step in the case of forming metal wiring using a roll-to-roll method.

[0067] [Step of forming an electroless plating layer] In this step, firstly, it is preferable to apply an electroless plating catalyst to the surface of the sheet substrate S to form a catalyst layer. The electroless plating catalyst is a catalyst that reduces metal ions contained in the plating solution used for electroless plating, such as silver or palladium.

[0068] Then, the sheet substrate S is immersed in an electroless plating bath, i.e., a treatment tank BT1, to reduce metal ions on the catalyst surface, so that the plating layer is deposited on the sheet substrate S. At this time, if the reduction is insufficient, it can also be immersed in a reducing agent solution such as sodium hypophosphite or sodium borohydride to actively reduce the metal ions on the amine.

[0069] In this embodiment, the plating material is nickel-phosphorus (NiP). In this embodiment, the phosphorus content constituting the plating layer is preferably less than the nickel content. Specifically, the phosphorus content can be set to 1% by mass or more and 13% by mass or less, with a lower limit of 5% by mass, more preferably 7% by mass, and an upper limit of 12% by mass, more preferably 10% by mass. If the phosphorus content is within the above range, cracks are easily formed on the wiring during the crack formation step described later.

[0070] [Steps for forming the resist film] A resist film is formed on the manufactured plating layer. First, a resist material R is coated on the plating layer and pre-baked to form an unpatterned resist layer. The resist material R can be a positive photoresist or a negative photoresist.

[0071] Then, the resist layer is exposed to ultraviolet L by a mask having an opening at a position corresponding to the area where wiring is formed and a light-shielding part in the area where wiring is not formed.

[0072] Next, a patterned resist film with the above-mentioned openings is formed by developing the resist layer with a developer D that dissolves the resist layer irradiated by ultraviolet light.

[0073] The obtained anti-corrosion film is preferably washed using washing method C.

[0074] [Steps for forming metal wiring] A sheet substrate S, on which a plating layer and a patterned resist film are sequentially deposited, is immersed in a processing tank BT2 for etching. Thereby, the resist film is used as a mask, the plating layer is etched, and the desired metal wiring is formed on the sheet substrate S.

[0075] [Steps for stripping the resist film] Then, the resist film is removed using a known developer A.

[0076] [Steps for forming cracks] Then, the sheet substrate S with the desired metal wiring formed is transferred to the crack forming means CR. Using the crack forming means CR, cracks are intentionally formed on the surface of the metal wiring. Preferably, the crack forming means CR forms cracks in a direction perpendicular to the sheet substrate S by applying a physical impact.

[0077] In this embodiment, it is preferable to form cracks by using the sheet substrate conveying step of the tension roller mechanism DR as shown in FIG8. By using the crack forming means CR combined with the conveying step, cracks can be formed on the metal wiring at the same time as conveying.

[0078] The support rollers 20a, 20b, and 20c of the tension roller mechanism DR are configured to move freely up, down, left, and right, and can apply the required tension to the sheet substrate S during transport. By applying tension using the tension roller mechanism DR, cracks can be formed on the surface of the metal wiring.

[0079] The number of supporting rollers is not limited to the schematic diagram shown in Figure 8, and can be increased or decreased as appropriate.

[0080] In this embodiment, it is preferable to form cracks by using the sheet substrate conveying step of the calendering roller mechanism including roller 10 and roller 11 as shown in FIG9.

[0081] The surface of the crack is prone to oxidation, so the step of forming the crack is preferably carried out before the step of immersion in the replacement gold plating bath or replacement copper plating bath.

[0082] [Step of immersion in a displacement gold plating bath or displacement copper plating bath] A sheet substrate S having metal wiring with cracks is immersed in a processing bath BT3 for displacement gold plating or copper plating. By immersing in the processing bath BT3, gold or copper is deposited by displacement to cover the surface of the metal wiring pattern with cracks. In this way, a two-layer metal wiring can be manufactured in which the cracked parts are filled with gold or copper, and a gold plating layer or a copper plating layer is formed on the metal wiring using nickel-phosphorus as the forming material.

[0083] <Metallic Wiring> Using the manufacturing method of this embodiment described above, metallic wiring disposed on a substrate can be manufactured. The metallic wiring includes a nickel-phosphorus layer, and a gold layer or a copper layer is included on the nickel-phosphorus layer. The resistance increase rate of the metallic wiring before and after a buckling test using a Tension-Free U-shape Folding Tester with a bending radius of 5 mm and 100 bending cycles is 7.0% or less.

[0084] Specifically, firstly, the resistance value of the metal wiring disposed on the substrate is measured. This measured value is set as the resistance value before the buckling test. Then, a buckling test is performed using a planar unloaded U-shaped stretching tester with a bending radius of 5 mm and 100 bending cycles. The resistance value of the metal wiring is measured after the buckling test. This measured value is set as the resistance value after the buckling test. Based on the resistance values ​​of the metal wiring before and after the buckling test, the resistance increase rate is calculated using the following formula: Resistance increase rate (%) = (Resistance value after buckling test - Resistance value before buckling test) / Resistance value before buckling test × 100.

[0085] For example, the DMLHB-FS-C of Yuasa Systems Co., Ltd. can be used as a planar body unloaded U-shaped expansion tester.

[0086] In this embodiment, the resistance increase rate of the metal wiring measured by the above method is preferably 0% or more and 7.0% or less, and more preferably 0% or more and 3.0% or less.

[0087] <Method for manufacturing a transistor> Further, a method for manufacturing a transistor that uses the metal wiring obtained by the above-described method for manufacturing metal wiring as a gate electrode will be described.

[0088] First, an insulating layer is formed on the electroless plating pattern formed using the above-described metal wiring manufacturing method. The insulating layer can be formed, for example, by applying a coating solution containing one or more UV-curable acrylic resins, epoxy resins, ethoxylate resins, silicone resins, etc., dissolved in an organic solvent. By irradiating the coating film with ultraviolet light through a mask with openings corresponding to the area where the insulating layer is formed, the insulating layer can be formed into the desired pattern.

[0089] A source electrode and a drain electrode are formed on an insulating layer using known methods.

[0090] For example, a hydrophilic region is formed in the portion forming the source electrode and the drain electrode, and an electroless plating catalyst is carried on the hydrophilic region. After the catalyst layer is formed, electroless plating is performed, thereby forming a plating layer (source electrode) and another plating layer (drain electrode).

[0091] A semiconductor layer is formed between a plating layer (source electrode) and another plating layer (drain electrode). The semiconductor layer may use commonly known inorganic or organic semiconductor materials. Inorganic semiconductor materials may include, for example, IGZO (indium gallium zinc oxide). Organic semiconductor materials may include, for example, p-type semiconductors such as copper phthalocyanine (CuPc), condensed pentaphenyl, red fluorene, condensed tetraphenyl, and poly(3-hexylthiophene-2,5-diyl), or fullerenes such as C60, or n-type semiconductors such as perylene derivatives such as PTCDI-C8H (N,N'-dioctyl-3,4,9,10-perylene tetracarboxylic diimide).

[0092] Among them, soluble pentacene such as TIPS (6,13-Bis(triisopropyl silylethynyl)pentacene, or organic semiconductor polymers such as P3HT are soluble in organic solvents such as toluene, which is preferred.

[0093] Alternatively, a solution obtained by dissolving the organic semiconductor material soluble in an organic solvent as described above in the organic solvent can be coated between a plating layer (source electrode) and another plating layer (drain electrode) and then dried to form the solution.

[0094] Furthermore, the semiconductor layer can also be formed by adding one or more insulating polymers such as PS (polystyrene) or PMMA (polymethyl methacrylate) to the above solution, and then coating and drying the solution containing the insulating polymer. If the semiconductor layer is formed in the above manner, the insulating polymer is concentrated below the semiconductor layer.

[0095] When polar groups such as amine groups are present at the interface between the organic semiconductor and the insulating layer, there is a tendency for the transistor properties to decrease. However, by configuring the organic semiconductor through the aforementioned insulating polymer, the decrease in transistor properties can be suppressed. As described above, a transistor can be manufactured.

[0096] Furthermore, there are no particular limitations on the structure of the transistor, and it can be appropriately selected according to the purpose. For example, transistors of the top contact / bottom gate type, top contact / top gate type, and bottom contact / top gate type can be manufactured. [Example]

[0097] Hereinafter, specific descriptions will be given by way of examples, but the present invention is not limited to the following examples.

[0098] <Preparation of the test substrate> Electroless plating was performed on a polyethylene naphthalate (PEN) substrate with dimensions of 5 cm × 1 cm and a film thickness of 100 μm to form a nickel-phosphorus layer. SE-680 manufactured by Kanigen Corporation of Japan was used for the electroless plating. At this time point, no cracks were observed in the nickel-phosphorus layer.

[0099] Then, a resist material is coated on the nickel-phosphorus layer, exposed through a mask with a predetermined pattern, and developed to form a resist pattern. Using the resist pattern as a mask, the nickel-phosphorus layer is etched to fabricate a 1 mm wide and 40 mm long metal wiring on a PEN substrate using nickel-phosphorus as the forming material. The resist film is removed using a developer.

[0100] During these steps, the PEN substrate containing the nickel-phosphorus layer is bent to apply stress, thereby forming cracks in the nickel-phosphorus layer. Then, an optical microscope is used to confirm the formation of cracks in the nickel-phosphorus layer.

[0101] Then, the surface of the nickel-phosphorus wiring with cracks is subjected to replacement gold plating to form a metal wiring consisting of two layers with a gold plating layer on the nickel-phosphorus wiring.

[0102] Example 1: The resistance value of a two-layer metal wiring formed on a PEN substrate was measured. This measured value is designated as the "resistance value before the buckling test". Then, the two-layer metal wiring formed on the PEN substrate was subjected to a buckling test with 100 bends using a planar unloaded U-shaped stretching tester, and the resistance value was measured. This measured value is designated as the "resistance value after the buckling test". Based on the resistance values ​​of the metal wiring before and after the buckling test, the resistance increase rate was calculated using the following formula: Resistance increase rate (%) = (Resistance value after buckling test - Resistance value before buckling test) / Resistance value before buckling test × 100.

[0103] The results are recorded in Table 1. In Table 1, the "resistance value before the buckling test" is recorded as "before the test", and the "resistance value after the buckling test" is recorded as "after the test".

[0104] (Surface Body No-Load U-Shaped Expansion Testing Machine) The surface body no-load U-shaped expansion testing machine uses the following device. Device used: DMLHB-FS-C (manufactured by Yuasa Systems Co., Ltd.) Bending radius: 5 mm

[0105] 《Examples 2-5》 Except that the number of bends is changed to the number shown in Table 1, the resistance value of the metal wiring is determined using the same method as in Example 1.

[0106] Comparative Example 1: The resistance value of a nickel-phosphorus wiring with cracks that had not undergone replacement gold plating was measured as Comparative Example 1.

[0107] [Table 1] Number of bends Resistance value (Ω) Resistance increase rate (%) Before the experiment After the test Example 1 100 34 35 2.94 Example 2 1000 33 35 6.06 Example 3 3000 35 35 0 Example 4 10000 34 35 2.94 Example 5 20000 38 39 2.63 Comparative Example 1 0 Unable to determine Unable to determine -

[0108] As shown in Table 1 above, the resistance increase rate of Examples 1 to 5 from before the bending test to after the bending test was less than 6.06%, indicating good conductivity. In Comparative Example 1, which did not undergo replacement gold plating, the resistance value was outside the detection range even with 0 bending cycles, making it impossible to measure the resistance value. [Simplified Explanation of the Diagram]

[0009] [Figure 1] is a schematic diagram illustrating one example of the manufacturing method of the metal wiring according to this embodiment. [Figure 2] is a schematic diagram illustrating one example of the manufacturing method of the metal wiring according to this embodiment. [Figure 3] is a schematic diagram illustrating one example of the manufacturing method of the metal wiring according to this embodiment. [Figure 4] is a schematic diagram illustrating one example of the manufacturing method of the metal wiring according to this embodiment. [Figure 5] is a schematic diagram illustrating one example of the manufacturing method of the metal wiring according to this embodiment. [Figure 6] is a schematic diagram illustrating one example of the manufacturing method of the metal wiring according to this embodiment. [Figure 7] is a schematic diagram showing the overall structure of the substrate processing apparatus. [Figure 8] is a schematic diagram showing the structure of a part of the substrate processing apparatus. [Figure 9] is a schematic diagram showing the structure of a part of the substrate processing apparatus. [Figure 10] is a schematic diagram of the side view of the metal wiring.

Claims

1. A metal wiring disposed on a substrate, the metal wiring comprising a first layer containing a first material, and a second layer containing a second material above the first layer, the second layer being formed by filling the gaps of cracks in the first layer and being in contact with the side and top surfaces of the first layer, wherein the resistance increase rate of the metal wiring before and after a buckling test performed using a planar unloaded U-shaped stretching tester is 7.0% or less, and the test conditions for the buckling test are a length of 40 mm, a bending radius of 5 mm, and 100 bending cycles.

2. As in request item 1, the metal wiring, wherein, The first material mentioned above is an alloy.

3. As in request item 2, the metallic wiring, wherein, The alloy contains nickel and phosphorus.

4. As in request item 1, the metallic wiring, wherein, The second material mentioned above contains gold or copper.

5. As in request item 1, the metallic wiring, wherein, The aforementioned substrate is flexible.

6. As in request item 1, the metallic wiring, wherein, The substrate is made of resin material.

7. A transistor wherein at least one of its gate electrode, source electrode, and drain electrode is formed of a metal wiring as claimed in claim 1.

8. An electronic component comprising the transistor as claimed in claim 7.

9. A method for manufacturing metal wiring, comprising a method for manufacturing metal wiring on a substrate, comprising: The step of forming a first layer having a wiring shape and containing a first material on the aforementioned substrate; The steps include forming a crack in the first layer of the wiring shape to form a first layer with cracks; and forming a second layer containing a second material on the first layer with cracks by plating; wherein the first material contains nickel and phosphorus.

10. A method for manufacturing a metal wiring, comprising a method for manufacturing a metal wiring on a substrate, comprising: The step of forming a first layer having a wiring shape and containing a first material on the aforementioned substrate; The steps include forming a crack in the first layer of the wiring shape to form a first layer with cracks; and forming a second layer containing a second material on the first layer with cracks by plating; the substrate is flexible.

11. A method for manufacturing metal wiring as claimed in claim 10, wherein, The first material mentioned above contains nickel and phosphorus.

12. A method for manufacturing metal wiring as claimed in claim 9 or 10, wherein, The first layer is formed on the substrate by electroless plating.

13. A method for manufacturing metal wiring as claimed in claim 9 or 10, wherein, The second material mentioned above contains gold or copper.

14. A method for manufacturing metal wiring as claimed in claim 9 or 10, wherein, In the step of forming the second layer, the first layer with cracks in the wiring shape is brought into contact with a gold plating bath or a copper plating bath to form the second layer.

15. A method for manufacturing metal wiring as claimed in claim 9 or 10, wherein, The substrate is made of resin material.

16. A method for manufacturing metal wiring as claimed in claim 9 or 10, wherein, In the step of forming the above-mentioned cracks, the above-mentioned cracks are formed by using a tension roller mechanism or a calendering roller mechanism to transport the substrate.

17. A method for manufacturing metal wiring as claimed in claim 9 or 10, wherein, The aforementioned metal wiring corresponds to the circuit patterns used in electronic components.

18. A method for manufacturing a transistor, comprising the steps of: forming at least one of a gate electrode, a source electrode, and a drain electrode using a method for manufacturing metal wiring as claimed in claim 9 or 10.

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