Semiconductor memory device

Abstract

A semiconductor memory device includes a memory cell array, a column hammer management circuit, and control logic circuitry. The memory cell array includes multiple columns of memory cells. The column hammer management circuitry, for example, counts the number of access instances for each of the memory cell columns in response to a received active command, storing the count value in a counting cell of each of the memory cell columns as counting data. In response to a first command, it initiates an internal read-update-write operation to read the count data, update the read count data, and write the updated count data into the counting cell. The control logic circuitry can perform an internal write operation during a second write time interval less than a first write time interval associated with a normal write operation to write the updated count data into the counting cell.