Low resistance mtj antifuse circuitry designs and methods of operation

Abstract

This disclosure specifically relates to an antifuse circuit. The antifuse circuit includes a plurality of antifuse bit units and a reference resistor. Each antifuse bit unit includes two or more memory bits and a reference resistor. The two or more memory bits are configured to be in a programmed state and at least one unprogrammed state.

Description

Low-resistance MTJ antifuse circuit design and operation method This disclosure relates to magnetoresistive tunnel junction ("MTJ") devices and related methods, including the design and device of MTJ antifuse circuits and related operating methods. In magnetoresistive tunnel junction ("MTJ") antifuse circuit design, a reference resistor is used to sense the state of the MTJ. Possible states of the MTJ include programmed (e.g., resistance less than or equal to approximately 500 ohms due to MTJ breakdown), unprogrammed low (e.g., the MTJ resistance range in the low state), and unprogrammed high (e.g., the MTJ resistance range in the high state). Here, programming refers to breaking down the MTJ in any way, such as when the programmed low-resistance state is permanent, meaning the MTJ resistance does not change after programming. The reference resistor value can be set between the programmed state and the unprogrammed low state (MTJ resistance in the low state) to obtain the maximum read signal. If a large-diameter MTJ or a low-resistance area ("RA") multiplied by the MTJ is used, the window between the programmed state and the unprogrammed low state may be too small to place the reference resistor for high-volume sensing operation. Numerous inventions, and various forms and embodiments thereof, are described and illustrated herein. When using large-diameter MTJs or low-resistance area ("RA") product MTJs, the window between the programmed state and the unprogrammed low state may be too small to accommodate a reference resistor (i.e., reference resistor 18) for high-volume sensing operation. Therefore, a design method is needed to increase the sensing window for low-resistance MTJ antifuse readout. This method may be desirable for large technology nodes using large MTJ diameters. Furthermore, the forms of this disclosure may be combined, configured, or otherwise integrated with forms of any prior Everspin disclosure (e.g., U.S. Patent Nos. 7,224,630 and 7,532,533, which are incorporated herein by reference in their entirety). The various states discussed herein may include an antifuse circuit. This antifuse circuit may include a plurality of antifuse bit units and a reference resistor. Each antifuse bit unit may include two or more memory bits and a reference resistor. These two or more memory bits may be configured to be in a programmed state and at least one unprogrammed state. The antifuse circuit may include one or more of the following states: Each of the two or more memory bits may be a magnetoresistive tunnel junction (MTJ). The two or more MTJs may be connected via a multiplexer circuit. The antifuse circuit may further include a pull-up programming circuit, a pull-down programming circuit, and two or more word lines. The two or more word lines may be configured to selectively couple the pull-up programming circuit or the pull-down programming circuit to one or more of the plurality of antifuse bit cells or the reference resistor. The antifuse circuit may further include a PMOS or an NMOS. The antifuse circuit may further include a transmission gate. The at least one unprogrammed state may include a low unprogrammed state and a high unprogrammed state. Each antifuse bit may include a resistor of approximately 500 ohms in a programmed state, a resistor between approximately 1,800 ohms and approximately 5,000 ohms in a low unprogrammed state, and a resistor between approximately 3,500 ohms and approximately 10,000 ohms in a high unprogrammed state. A reference resistor may include a resistor between approximately 1,000 ohms and approximately 3,500 ohms. In another embodiment, a method of operating an antifuse circuit may include performing a read operation on one or more of a plurality of antifuse bit cells, the antifuse circuit including the plurality of antifuse bit cells. Each antifuse bit cell may include at least one memory bit and a reference resistor. The at least one memory bit may be configured to be in a programmed state, a low unprogrammed state, and a high unprogrammed state. The method of operating the antifuse circuit may include one or more of the following states: Each of the at least one memory bit may be a magnetoresistive tunnel junction. Each antifuse bit cell may include two magnetoresistive tunnel junctions. Each antifuse bit cell includes a PMOS or an NMOS. The antifuse circuit may include pull-up programming circuitry, pull-down programming circuitry, and two or more word lines. The two or more word lines may be configured to selectively couple the pull-up programming circuitry or the pull-down programming circuitry to one or more of the plurality of antifuse bit cells or the reference resistor. The method may further include writing one or more of the plurality of antifuse bit cells to a high state just before performing a read operation. The high state may include a resistance range between approximately 3,500 ohms and approximately 10,000 ohms. The programmed state may include a resistance of approximately 500 ohms, and the reference resistor may include a resistance between approximately 500 ohms and approximately 3,500 ohms. In another embodiment, an antifuse circuit may include a plurality of antifuse bit units and a reference resistor. Each antifuse bit unit may include two or more memory bits and a reference resistor. The two or more memory bits may be configured to be in a programmed state and at least one unprogrammed state. The at least one unprogrammed state may include a low unprogrammed state and a high unprogrammed state. The antifuse circuit may include one or more of the following states: Each antifuse bit cell may include a resistor of approximately 500 ohms in a programmed state, a resistor between approximately 1,800 ohms and approximately 5,000 ohms in a low unprogrammed state, and a resistor between approximately 3,500 ohms and approximately 10,000 ohms in a high unprogrammed state. A reference resistor may include a resistor between approximately 1,000 ohms and approximately 3,500 ohms. The two or more memory bits may be magnetoresistive tunnel junctions. The antifuse circuit may include pull-up programming circuitry, pull-down programming circuitry, and two or more word lines. The two or more word lines may be configured to selectively couple the pull-up programming circuitry or the pull-down programming circuitry to one or more of the plurality of antifuse bit cells or the reference resistor. The antifuse circuit may further include a PMOS or an NMOS. Cross-reference to related applications This application claims the benefit of U.S. Provisional Patent Application No. 63 / 313,419, filed February 24, 2022, the entire contents of which are incorporated herein by reference. This disclosure generally relates to magnetoresistive devices having a magnetoresistive stack or structure (e.g., a part of a magnetoresistive memory device, a magnetoresistive sensor / transducer device, etc.) and methods of operating said magnetoresistive devices. For example, the present embodiment describes a low-resistance MTJ antifuse circuit design and a method of operating an MTJ antifuse device. Please note that all values ​​disclosed herein (including all disclosed thickness values, limits, and ranges) may vary by ±10% relative to the disclosed values ​​(unless a different variation is specified). For example, a resistance disclosed as "r" resistance units may vary from (r-0.1r) units to (r+0.1r) units. Furthermore, all related terms such as "about," "substantially," and "approximately" are used to indicate a possible variation of ±10% (unless otherwise stated or specified). Additionally, in the claims, values, limits, and / or ranges of the thickness and atomic composition of the described layer / region, for example, indicate that value, limit, and / or range ±10%. Please note that the exemplary resistance values ​​discussed in this disclosure are expected values ​​of resistance (i.e., not measured values). As will be recognized by those skilled in the art, such resistance values ​​may change after further processing (e.g., exposure to high temperatures) or the passage of time. Please note that the descriptions set forth herein are illustrative in nature only and are not intended to limit the embodiments of the subject matter, or the application and use of such embodiments. Any embodiment described herein as exemplary should not be construed as superior or advantageous to other embodiments. Rather, the term "exemplary" is used in the meaning of example or "illustrative" rather than "ideal." The terms "comprising," "including," "having," "with," and any variations thereof are used synonymously to indicate or describe a non-exclusive inclusion. Thus, an apparatus or method using such terms may include not only those elements or steps but also other elements and steps not expressly listed or inherent to such apparatus or method. Furthermore, the terms "first," "second," etc., used herein do not indicate any order, quantity, or importance, but are used to distinguish one element from another. Similarly, relative orientation terms such as "top," "bottom," "adjacent," "next to," etc., are used with reference to the orientation of the structures shown in the described figures. Moreover, the terms "a" and "an" used herein do not indicate a limitation of quantity, but indicate the presence of at least one of the referenced items. For the sake of brevity, prior art related to semiconductor processing may not be described in detail herein. Exemplary embodiments may be fabricated using any suitable currently known or future-developed process, such as known lithography processes. The fabrication of integrated circuits, microelectronic devices, microelectromechanical devices, microfluidic devices, and photonic devices involves the formation of several layers or regions of material (e.g., including one or more layers) that interact in a certain way. One or more of these regions may be patterned such that the respective regions of the layers have different electrical or other properties, which may be interconnected within the region or interconnected to other regions to form electrical components and circuits. These regions may be formed by selectively introducing or removing various materials. The pattern defining a specific area of ​​the device according to this disclosure is typically formed by a photolithography process. For example, a layer of photoresist can be applied to a layer covering a wafer substrate. A photomask (containing transparent and opaque areas) can be used to selectively expose the photoresist by some form of radiation (such as ultraviolet light, electrons, or X-rays). The photoresist exposed to or not exposed to radiation can be removed by applying a developer. Etching can then be used / applied to pattern the layer (or material) not protected by the remaining photoresist. Alternatively, an addition process can be used, in which a photoresist is used as a template to build the structure. The magnetoresistive device disclosed herein may include magnetic tunnel junction bits (MTJ bits). MTJ bits may be formed from a magnetoresistive stack / structure, which may include one or more conductive electrodes, vias, or conductors on any side of the magnetoresistive stack / structure, or be operatively coupled to one or more conductive electrodes, vias, or conductors. The magnetoresistive stack / structure forming the MTJ bits may include a number of different material regions and / or layers, some of which include magnetic materials, while others do not. In at least one embodiment, a method of manufacturing the disclosed device may include sequentially depositing, growing, sputtering, evaporating, and / or providing (collectively referred to herein as "depositing" or other verb tenses (e.g., "deposited" or "deposited")) layers and regions, which, after further processing (e.g., etching), form MTJ bits (or a plurality of MTJ bits stacked on top of each other or configured in an array). As is known in the art, the resistance of the described MTJ bits can be varied based on whether the magnetization direction (e.g., direction of the magnetic moment) of the free region adjacent to the nonmagnetic layer (e.g., a dielectric layer used as a tunnel barrier) is parallel or antiparallel to the magnetization direction (e.g., direction of the magnetic moment) of the fixed region adjacent to the nonmagnetic layer. Typically, if the two regions have the same magnetization alignment, the resulting relatively lower resistance is considered to be the digit "0", while if the alignment is antiparallel, the resulting relatively higher resistance is considered to be the digit "1". Memory devices (e.g., MRAM) may include a plurality of such MTJ bits configured in an array of rows and columns, which may be referred to as memory cells or elements. By measuring the current through each cell, the resistance of each cell can be read, thereby reading the data stored in the memory array. Figure 1 illustrates exemplary resistance ranges for a programmed MTJ, an unprogrammed MTJ in a low state, and an unprogrammed MTJ in a high state. The resistance of a programmed MTJ is typically less than or equal to a first resistance A, for example, approximately 500 ohms or less for a series of MTJ diameters or RA products. The high-state resistance of an MTJ can be between a first high-state resistance B (e.g., approximately 3,500 ohms) and a second high-state resistance C (e.g., approximately 10,000 ohms), depending on various MTJ parameters. However, the low-state resistance of an MTJ can be significantly reduced due to larger diameter MTJs and / or lower RA products, falling between a first low-state resistance D (e.g., approximately 1,800 ohms) and a second low-state resistance E (e.g., approximately 5,000 ohms). The first low-state resistance D may be lower than the first high-state resistance B. The second low-state resistance E may be lower than the second high-state resistance C, for example, between the first high-state resistance B and the second high-state resistance C. A reference resistor may also be included. The reference resistor may include a reference resistor R, for example, a reference resistor R of approximately 1,000 ohms. Figure 1 also shows a sensing window W for antifuse readings between the resistance of the programmed MTJ (e.g., the first resistance A) and the low-side resistance of the unprogrammed MTJ in a low state (e.g., the first low-state resistance D). Figure 2 illustrates an MTJ antifuse circuit 10, such as an MTJ antifuse circuit array. As shown in Figure 2, the MTJ antifuse bit cell 12 typically has one or more P-channel metal-oxide-semiconductor ("PMOS") transistors 14 and one MTJ 16. The PMOS region may cover multiple MTJs 16; however, only one MTJ 16 is connected to a PMOS select device. Alternatively or additionally, the MTJ antifuse bit cell 12 may include one or more n-channel metal-oxide-semiconductor ("NMOS") transistor select devices. The MTJ 16 may be configured on one pin of the array, and the reference resistor 18 may be configured on the other pin of the array. The MTJ antifuse bit cell array typically has a plurality of word lines (not shown), such as 32 word lines. Half of the word lines may be on even-numbered bit lines (i.e., bit lines <0>), while the other half may be on odd-numbered bit lines (i.e., bit lines <1>). Each reference resistor 18 may include its own word line selection devices 22A, 22B, for example, present on two bit lines. One method of operation may include selecting either bit line <0> 22A or bit line <1> 22B for the reference resistor 18, and selecting either bit line <0> 20A or bit line <1> 20B for the MTJ. Thus, a single MTJ 16 can be compared to the reference resistor 18 (e.g., a 1,000-ohm resistor). Additionally, the MTJ antifuse circuit 10 may include one or more connections 30 to the sense amplifier and programming circuitry. The various states disclosed herein include using at least two MTJs in series for each antifuse bit, instead of using a single MTJ for each antifuse bit and comparing a single MTJ to a reference resistor. As shown in Figure 3, using two MTJs in series can help increase the sensing window for antifuse readout. In this example, the resistance of the MTJ in each configuration may be doubled. Figure 3 shows an exemplary resistance range for two MTJs. As discussed above, the programmed MTJ resistance is typically less than or equal to the first resistance F, for example, approximately 1,000 ohms or less for a series of MTJ diameters or RA products. In this isomorphic example, the programmed MTJ resistance may be twice the first resistance A, for example, when both MTJs are programmed. The MTJ high-state resistance of the two MTJs may be between the first high-state resistance G (e.g., approximately 7,000 ohms) and the second high-state resistance H (e.g., approximately 20,000 ohms), depending on various MTJ parameters. However, the MTJ low-state resistance of the two MTJs may be reduced due to the larger diameter MTJ and / or the lower RA product, between the first low-state resistance I (e.g., approximately 3,600 ohms) and the second low-state resistance J (e.g., approximately 10,000 ohms). The first low-state resistance I may be lower than the first high-state resistance G. The second low-state resistance J may be lower than the second high-state resistance H, for example, between the first high-state resistance G and the second high-state resistance H. One or more reference resistors R may also be included. The reference resistors may include reference resistors R, for example, a reference resistor R of approximately 1,000 ohms. Additionally, Figure 3 shows a sensing window X for antifuse readings between the resistance of the programmed MTJ (e.g., the first resistance F) and the low-side resistance of the unprogrammed MTJ in a low state (e.g., the first low-state resistance I). In this example, the second sensing window X can extend between the resistance of the two programmed MTJs (e.g., approximately 1,000 ohms or less) and the low-side resistance of the two MTJs in a low state (e.g., approximately 3,600 ohms or higher). In this configuration, the sensing window X can extend between approximately 1,000 ohms and approximately 3,600 ohms, for example, for a sensing window range of 2,600 ohms (twice as large or wide as the approximately 1,300 ohm sensing window range of a single MTJ configuration). In this configuration, the reference resistor R can be located in the middle of the sensing window range, which may help provide more reliable sensor measurements (allowing for easier readings, adaptation to MTJ variations or tolerances, sensor readings, etc.). The various configurations of the embodiments discussed herein can be used for older and / or larger MTJs while still allowing for small or low resistance. Figure 4 below illustrates an exemplary MTJ antifuse circuit 110 with two MTJs 116 for each MTJ antifuse bit cell 112. The antifuse circuit 110 may include two source lines 132A, 132B and may be connected to a sense amplifier and programmable circuitry 130. Although not shown, one or more of the states discussed herein may include more than two MTJs 116 per bit cell 112. Two MTJs 116 may be configured on one pin of the array, and a reference resistor 118 may be configured on the other pin of the array. As shown, the MTJ antifuse bit cell 112 may include a PMOS 114 (or an NMOS) and two MTJs 116 configured in series. Furthermore, horizontal word lines 120A and 120B can be added to the sensor array, allowing for individual programming of the two MTJs 116, for example, via selective coupling to pull-up programming circuitry 134 and / or pull-down programming circuitry 136 (i.e., via switch 138). The configuration of the MTJ antifuse circuitry 110 shown in Figure 4 enables an increased sensing window (i.e., as discussed above with respect to Figure 3) without increasing the size of the MTJ antifuse bit cell array. For example, the PMOS (or NMOS) region can remain the same as a bit cell with a single MTJ (e.g., Figure 1). Additionally, there may be no current creeping path in the array during one or more programming and readouts. Although not shown in Figure 4, another embodiment of the antifuse device with two MTJ 116s per bit cell 112 may not include the programming word lines 120A, 120B. Instead, the MTJ 116 can be programmed using a high voltage on the source lines (i.e., source lines 132A, 132B). For example, when two MTJ 116s are configured in series, a supply voltage of approximately 3 volts ("VDD") can be applied to the source lines. In this case, a sufficiently high voltage on the source lines can program the series-connected MTJ 116s. Figure 5 illustrates the MTJ antifuse circuit 110 in read mode. As shown, the connections to the pull-up programming circuit 134 and the pull-down programming circuit 136 (e.g., via switch 138 and horizontal word lines 120A and 120B) may be in a floating (high Z or high impedance) state. Additionally, the bit array may include sixteen (16) bit cells 112 for even number lines 120A and may also include sixteen (16) bit cells 112 for odd number lines 120B. Each bit cell 112 may be connected to a voltage source (e.g., VDD 140) to perform a read operation on the antifuse circuit 110 with a reference resistor 118. Furthermore, as discussed above, each bit cell 112 may be connected to a sense amplifier and programming circuit 130. Figure 6 shows a portion of the antifuse circuit 110 in a programmed state for the first MTJ 116A, including at least one antifuse bit cell 112. As shown, with the pull-down programming circuit 136 enabled (and therefore the pull-up programming circuit 134 disabled), current 150 can flow from a voltage source (e.g., VDD 140), through the first MTJ 116A (but not through the second MTJ 116B), and to the pull-down programming circuit 136 to program the first MTJ 116A. The connection 130 to the sense amplifier and programming circuit can be in a floating (e.g., high Z or high impedance) state. Figure 7 below shows a portion of the antifuse circuit 110 in a programmed state for the second MTJ 116B, including at least one antifuse bit cell 112. As shown, with the pull-up programming circuit 134 enabled (and therefore the pull-down programming circuit 136 disabled), current 150 may flow from the pull-up programming circuit 134, through the second MTJ 116B (and not through the first MTJ 116A), and to the pull-down programming circuit 136 (e.g., via connection 130 to the sense amplifier and programming circuit) to program the second MTJ 116B. Connections to voltage sources (e.g., VDD 140) on one or more source lines may be in a floating (e.g., high Z or high impedance) or VDD state. Although not shown, other embodiments of the MTJ antifuse circuit design may include two MTJs 116 in series configuration for each antifuse bit cell 112. Each bit cell 112 may include one or more transmission gates, instead of the PMOS 114 or NMOS devices discussed above. Furthermore, although not shown, the series connection of the two MTJs 116 may be formed outside the array, for example via a multiplexer ("MUX") circuit, allowing the two MTJs 116 to be spaced apart from each other. Such embodiments may also facilitate the measurement of low-resistance MTJ antifuses. Alternatively, other embodiments of the MTJ antifuse circuit design may include a single MTJ 116 for each antifuse bit cell 112, as discussed below with reference to FIG8. As discussed above, MTJ 116 may include a high state having a resistance range between a first high-state resistance B and a second high-state resistance C. Additionally, MTJ 116 may also include a low state having a resistance range between a first low-state resistance D and a second low-state resistance E. In this configuration, bit cell 112 may be written to a high state just before a fuse readout operation (e.g., before nanoseconds, microseconds, milliseconds, centiseconds, minutes, seconds, or minutes). Then, just after the write operation, a fuse readout operation may be performed on antifuse bit cell 112. In this configuration, it can be generally ensured that MTJ 116 is in a high state rather than a low state. Therefore, the sensing window Y may be self-programmed to extend the MTJ resistance A (e.g., approximately 500 ohms) to the low end of the first high-state resistance B (e.g., approximately 3,500 ohms of the high state). In some examples, the sensing window Y can extend between approximately 500 ohms and approximately 3,500 ohms, for example, a sensing window range of approximately 3,000 ohms. As discussed above, a reference resistor with resistance R (i.e., resistors 18, 118) can be located in the middle of the sensing window range, which may help provide more reliable sensor measurements (allowing for easier readings, adaptation to variations or tolerances in the MTJ, sensor readings, etc.). The various embodiments discussed herein can be used for older technology nodes and / or larger MTJs, while still allowing for small or low resistances. The various forms of antifuse circuit design discussed in this paper for MTJ-based circuits may help improve the reliability of antifuse bit cells and / or provide other benefits. For example, compared to laser fuse designs, polysilicon fuse designs, metal fuse designs, etc., MTJ-based antifuse circuit designs may require less area and may involve a less complex design. Furthermore, the various embodiments discussed herein do not require very high voltages (e.g., 5 V or higher) for programming. Instead, commonly available input-output ("IO") voltage levels, such as approximately 1.2 V, approximately 1.5 V, and approximately 3 V, are sufficient for MTJ antifuse programming. In addition, the various features of the MTJ-based antifuse circuit designs discussed herein can be programmed at different stages of product development, such as at the wafer-level probe stage, at the package testing stage, and at the customer board level. At these various stages, the various features of the MTJ-based antifuse circuit designs discussed herein can be programmed using the power supply voltage of the product (e.g., sensor or bit cell array or product chip). Furthermore, such antifuse circuit designs based on MTJs can be used at large technology nodes (e.g., approximately 90 nm or above), and for example for large-diameter MTJs (e.g., approximately 90 nm) and for low resistance. While this document describes the principles of the present disclosure with reference to illustrative examples of specific applications, it should be understood that the present disclosure is not limited thereto. For example, instead of MTJ-based bit cells, alternative memory bit technologies, such as resistive RAM or ferroelectric RAM, can be used to design the antifuse circuit of the present disclosure. The alternative memory bit may have a programmed state and at least one unprogrammed state. This at least one unprogrammed state may further include multiple unprogrammed states, such as a low unprogrammed state, a high unprogrammed state, and one or more intermediate unprogrammed states. Those skilled in the art who will be able to access the teachings provided herein will recognize that additional modifications, applications, embodiments, and equivalent substitutions are within the scope of the features described herein. Therefore, the claimed features should not be considered as limited by the foregoing description. In one embodiment, an antifuse circuit may include a plurality of antifuse bit units and a reference resistor. Each antifuse bit unit may include two or more memory bits and a reference resistor. The two or more memory bits may be configured to be in a programmed state and at least one unprogrammed state. Various embodiments of the antifuse circuit may include: each of the two or more memory bits may be a magnetoresistive tunnel junction; the two or more magnetoresistive tunnel junctions may be connected via a multiplexer circuit; the antifuse circuit may further include: a pull-up programming circuit; a pull-down programming circuit; and two or more word lines; the two or more word lines may be configured to selectively couple the pull-up programming circuit or the pull-down programming circuit to one or more of the plurality of antifuse bit cells or the reference resistor; the antifuse circuit may further include a PMOS or NMOS; the antifuse circuit may further include a transmission gate; the at least one unprogrammed state may include a low unprogrammed state and a high unprogrammed state; each antifuse bit cell may include a resistor of approximately 500 ohms in the programmed state, a resistor between approximately 1,800 ohms and approximately 5,000 ohms in the low unprogrammed state, and a resistor between approximately 3,500 ohms and approximately 10,000 ohms in the high unprogrammed state; the reference resistor may include a resistor between approximately 1,000 ohms and approximately 3,500 ohms. In another embodiment, a method of operating an antifuse circuit may include performing a read operation on one or more of a plurality of antifuse bit cells, the antifuse circuit including the plurality of antifuse bit cells. Each antifuse bit cell may include at least one memory bit and a reference resistor. The at least one memory bit may be configured to be in a programmed state, a low unprogrammed state, and a high unprogrammed state. Various embodiments of the method of operating the antifuse circuit may include: each of the at least one memory bit may be a magnetoresistive tunnel junction; each antifuse bit cell may include two magnetoresistive tunnel junctions; each antifuse bit cell includes a PMOS or an NMOS; the antifuse circuit may include a pull-up programming circuit, a pull-down programming circuit, and two or more word lines; the two or more word lines may be configured to selectively couple the pull-up programming circuit or the pull-down programming circuit to one or more of the plurality of antifuse bit cells or the reference resistor; the method may further include writing one or more of the plurality of antifuse bit cells to a high state just before performing the read operation; the high state may include a resistance range between approximately 3,500 ohms and approximately 10,000 ohms; the programmed state may include a resistance of approximately 500 ohms, and the reference resistor may include a resistance between approximately 500 ohms and approximately 3,500 ohms. In another embodiment, an antifuse circuit may include a plurality of antifuse bit units and a reference resistor. Each antifuse bit unit may include two or more memory bits and a reference resistor. The two or more memory bits may be configured to be in a programmed state and at least one unprogrammed state. The at least one unprogrammed state may include a low unprogrammed state and a high unprogrammed state. Various embodiments of the antifuse circuit may include: each antifuse bit cell may include a resistor of approximately 500 ohms in the programmed state, a resistor between approximately 1,800 ohms and approximately 5,000 ohms in the low unprogrammed state, and a resistor between approximately 3,500 ohms and approximately 10,000 ohms in the high unprogrammed state; the reference resistor may include a resistor between approximately 1,000 ohms and approximately 3,500 ohms; the two or more memory bits may be magnetoresistive tunnel junctions; the antifuse circuit may include pull-up programming circuitry, pull-down programming circuitry, and two or more word lines; the two or more word lines may be configured to selectively couple the pull-up programming circuitry or the pull-down programming circuitry to one or more of the plurality of antifuse bit cells or the reference resistor; the antifuse circuit may further include PMOS or NMOS. The invention has been described for clarity and understanding. It is not intended to limit the invention to the precise forms disclosed. Various modifications are possible within the scope and equivalents of this application. 10: MTJ antifuse circuit; 12: MTJ antifuse bit cell; 14: P-channel metal-oxide-semiconductor; 16: MTJ; 18: Reference resistor; 22A: Bit line; 22B: Bit line; 30: Connection; 110: Antifuse circuit; 112: Bit cell; 114: PMOS; 116: MTJ; 120A: Horizontal word line; 120B: Horizontal word line; 130: Connection; 132A: Source line; 132B: Source line; 134: Pull-up programming circuit; 136: Pull-down programming circuit; 138: Switch; 140: Voltage source; 150: Current. Embodiments of this disclosure may be implemented in conjunction with the forms shown in the accompanying drawings. These drawings illustrate different forms of this disclosure, and where appropriate, similar symbols for structures, components, materials, and / or elements shown in different drawings may be similarly designated. It should be understood that various combinations of structures, components, and / or elements other than those specifically shown are conceivable and fall within the scope of this disclosure. For simplicity and clarity, the accompanying drawings illustrate the general structure and / or configuration of the various embodiments described herein. Descriptions and details of well-known features (e.g., interconnections) and technologies have been omitted to avoid obscuring other features. Elements in the drawings are not necessarily drawn to scale. The dimensions of some features may be exaggerated relative to other features to improve understanding of the exemplary embodiments. Furthermore, although certain regions / layers and features are shown with straight 90-degree edges, in practice, such regions / layers may be more "rounded" and / or gradually sloping. Please note that, unless specifically mentioned, a pattern described with reference to one embodiment may be applicable to and used in other embodiments. Furthermore, numerous embodiments are described and illustrated herein. This disclosure is not limited to any single pattern or embodiment thereof, nor to any combination and / or arrangement of such patterns and / or embodiments. Moreover, each pattern and / or embodiment of this disclosure may be used alone or in combination with one or more of other patterns and / or embodiments of this disclosure. For the sake of brevity, certain arrangements and combinations are not discussed and / or described separately herein. It is important to note that embodiments or implementations described herein as "exemplary" should not be construed as superior or advantageous to other embodiments or implementations, for example; rather, they are intended to reflect or indicate that the embodiments are "example" embodiments. Figure 1 shows a diagram of the resistance distribution of a group of MTJs. Figure 2 shows a circuit with an antifuse bit cell containing a single MTJ. Figure 3 shows a diagram of the resistance distribution of two MTJs in a series configuration according to one embodiment. Figure 4 shows an exemplary antifuse circuit design where each antifuse bit cell has two MTJs. Figure 5 shows an exemplary circuit in a read state. Figure 6 shows an exemplary circuit in a programmed state. Figure 7 shows an exemplary circuit in another programmed state. Figure 8 shows a diagram of the resistance distribution of a single MTJ according to another embodiment for antifuse read. Similarly, numerous embodiments are described and illustrated herein. This disclosure is not limited to any single variant or embodiment thereof, nor is it limited to any combination and / or arrangement of such variants and / or embodiments. Each variant and / or embodiment thereof may be used alone or in combination with one or more of the other variants and / or embodiments thereof. For the sake of brevity, many of these combinations and arrangements are not discussed individually herein. 110: Anti-fuse circuit 112: Bit unit 114:PMOS 116:MTJ 120A: Horizontal letter line 120B: Horizontal letter bar 130: Connection 132A: Source line 132B: Source line 134: Pull-up programmable circuit 136: Pull-down programmed circuit 138: Switch 140: Voltage source

Claims

1. An antifuse circuit, comprising: A plurality of magnetoresistive tunnel junction (MTJ) antifuse bit cells, comprising a first MTJ antifuse bit cell and a second MTJ antifuse bit cell, wherein each of the plurality of MTJ antifuse bit cells comprises: an MTJ having a first electrode and a second electrode and a magnetoresistive stack / structure disposed therebetween, wherein the MTJ is configured to be either (i) a programmed antifuse state or (ii) an unprogrammed antifuse state, wherein if the MTJ is configured to the unprogrammed antifuse state, the MTJ can be configured to an unprogrammed low state and an unprogrammed high state; and a first select transistor electrically coupled to the first electrode of the MTJ of the associated MTJ antifuse bit cell, wherein the first select transistor comprises a gate; and a first reference resistor; A second select transistor electrically coupled to the first reference resistor, wherein the second select transistor includes a gate; a plurality of electrical conductors including a first electrical conductor and a second electrical conductor, wherein the first MTJ antifuse bit cell is coupled to the first electrical conductor and the first reference resistor is coupled to the second electrical conductor; a sense amplifier having a first input electrically coupled to the first electrical conductor and a second input electrically coupled to the second electrical conductor; wherein in a first operation, (i) the first select transistor of the first MTJ antifuse bit cell is responsively enabled by a voltage applied to the gate of the first select transistor of the first MTJ antifuse bit cell to electrically connect the MTJ of the first MTJ antifuse bit cell to the sense amplifier via the first electrical conductor and (ii) the second select transistor is responsively enabled by a voltage applied to the gate of the second select transistor to electrically connect the reference resistor to the first reference resistor via the second electrical conductor. Electrically connected to the sensing amplifier, wherein the sensing amplifier is configured to sense whether the MTJ of the first MTJ antifuse bit unit is in the programmed antifuse state or the unprogrammed antifuse state; and wherein the MTJ of the first MTJ antifuse bit unit is connected between the first select transistor and the first conductor of the first MTJ antifuse bit unit, and the MTJ of the second MTJ antifuse bit unit is connected between the first select transistor and the second conductor of the second MTJ antifuse bit unit.

2. The antifuse circuit of claim 1 further comprises: a second reference resistor coupled to the first electrical conductor; and a third select transistor electrically coupled to the second reference resistor, wherein the third select transistor includes a gate.

3. As in request item 1, the antifuse circuit, wherein: One of the first reference resistors is connected to the second selective transistor; the second terminal of the first reference resistor is electrically connected to the second electrical conductor; the second conductor is electrically connected to the second input of the sense amplifier; the second selective transistor is electrically connected to a voltage source; and in the first operation, the second selective transistor is responsively enabled by the voltage applied to the gate of the second selective transistor to electrically connect the voltage source to the first terminal of the first reference resistor.

4. The antifuse circuit of claim 1, further comprising: a second reference resistor electrically coupled to the first electrical conductor; and a third select transistor electrically coupled to the second reference resistor, wherein the third select transistor includes a gate, wherein: The first reference resistor is connected between the second selective transistor and the second electrical conductor; and the second reference resistor is connected between the third selective transistor and the first electrical conductor.

5. As in request item 4, the antifuse circuit, wherein: Each of the second and third selective transistors is a PMOS transistor.

6. The antifuse circuit of claim 4, wherein in a second operation, (i) the first select transistor is responsively enabled by a voltage applied to the gate of the first select transistor of the second MTJ antifuse bit cell to electrically connect the MTJ of the second MTJ antifuse bit cell to the sense amplifier via the second conductor, and (ii) the third select transistor is responsively enabled by a voltage applied to the gate of the third select transistor to electrically connect the second reference resistor to the sense amplifier via the first conductor, and wherein the sense amplifier is configured to sense whether the MTJ of the second MTJ antifuse bit cell is in the programmed antifuse state or the unprogrammed antifuse state.

7. The antifuse circuit of claim 1, wherein the first selected transistor system of each of the first MTJ antifuse bit unit and the second MTJ antifuse bit unit is a PMOS transistor.

8. The antifuse circuit as described in request item 1, wherein: The first select transistor system of each of the first MTJ antifuse bit unit and the second MTJ antifuse bit unit is a PMOS transistor; the first electrode of the MTJ of the first MTJ antifuse bit unit is connected to the first select transistor of the first MTJ antifuse bit unit; the second electrode of the MTJ of the first MTJ antifuse bit unit is connected to the first electrical conductor; the first conductivity system is connected to the first input of the sense amplifier; the first select transistor system of the first MTJ antifuse bit unit is electrically connected to a voltage source; and wherein in the first operation, the first select transistor is responsively enabled by applying a voltage to the gate of the first select transistor, so that the voltage source is electrically connected to the first electrode of the MTJ of the first MTJ antifuse bit unit.

9. The antifuse circuit of claim 1, wherein the second selected transistor system is a PMOS transistor.

10. A method for determining the antifuse state of a first magnetoresistive tunnel junction (MTJ) antifuse bit cell in an antifuse circuit, wherein the first MTJ antifuse bit cell is one of a plurality of MTJ antifuse bit cells in the antifuse circuit, wherein each MTJ antifuse bit cell comprises: (a) an MTJ having a plurality of electrodes and a magnetoresistive stack / structure disposed between the plurality of electrodes, wherein the MTJ is configured to be only one of: (i) a programmed antifuse state corresponding to the MTJ having a resistance within a first resistance range or (ii) An unprogrammed antifuse state, wherein if the MTJ is configured to the unprogrammed antifuse state, the MTJ can be configured to an unprogrammed low state and an unprogrammed high state, the unprogrammed low state corresponding to the MTJ having a resistance in a second resistance range, wherein the resistance in the second resistance range is greater than the resistance in the first resistance range, and the unprogrammed high state corresponding to the MTJ having a resistance in a third resistance range, wherein a majority of the resistances in the third resistance range is greater than all the resistances in the first resistance range and the second resistance range, the method of reading the antifuse bit cell of the first MTJ of the antifuse circuit includes: Perform a write operation to write the unprogrammed high state to the MTJ of the first MTJ antifuse bit cell; And immediately after performing the write operation to write the unprogrammed high state to the MTJ of the first MTJ antifuse bit unit, a read operation of the first MTJ antifuse bit unit is performed, including sensing a resistance of the MTJ of the first MTJ antifuse bit unit, wherein: (i) if the resistance of the MTJ of the first MTJ antifuse bit unit is lower than a lower limit of a third resistance range, then the MTJ of the first MTJ antifuse bit unit is in the programmed antifuse state; and (ii) if the resistance of the MTJ of the first MTJ antifuse bit unit is greater than the lower limit of the third resistance range, then the MTJ of the first MTJ antifuse bit unit is in the unprogrammed antifuse state.

11. The method of claim 10, further comprising: before performing the write operation to write the unprogrammed high state to the MTJ of the first MTJ antifuse bit cell, wherein in response to the MTJ breaking down, the MTJ of the first MTJ antifuse bit cell is programmed to a programmed antifuse state.

12. The method of claim 11, wherein in response to performing a write operation to write the unprogrammed high state to the MTJ of the first MTJ antifuse bit cell, the resistance of the MTJ remains within the range of the first resistance.

13. The method of claim 11, wherein immediately after performing the write operation to write the unprogrammed high state to the MTJ of the first MTJ antifuse bit unit, a read operation of the first MTJ antifuse bit unit is performed, including sensing the low resistance of the MTJ of the first MTJ antifuse bit unit to determine that the first MTJ antifuse bit unit is in the programmed antifuse state.

14. An antifuse circuit, comprising: A plurality of magnetoresistive tunnel junction (MTJ) antifuse bit cells, comprising a first MTJ antifuse bit cell and a second MTJ antifuse bit cell, wherein each of the plurality of MTJ antifuse bit cells comprises: an MTJ having a first electrode and a second electrode and a magnetoresistive stack / structure disposed therebetween, wherein the MTJ is configured to be only one of the following: (i) a programmed antifuse state or (ii) an unprogrammed antifuse state, wherein the unprogrammed antifuse state comprises an unprogrammed low state and an unprogrammed high state; and a first PMOS transistor coupled to the first electrode of the MTJ of the associated MTJ antifuse bit cell, wherein the first PMOS transistor comprises a gate; a first reference resistor; a second reference resistor; and a plurality of electrical conductors comprising: A first electrical conductor coupled to the first MTJ antifuse bit cell and the second reference resistor; and a second electrical conductor coupled to the second MTJ antifuse bit cell and the first reference resistor; a sense amplifier having a first input coupled to the first electrical conductor and a second input coupled to the second electrical conductor; and wherein in a first operation, (i) the first PMOS transistor of the first MTJ antifuse bit cell is responsively enabled by a voltage applied to the gate of the first PMOS transistor of the first MTJ antifuse bit cell to electrically connect the MTJ of the first MTJ antifuse bit cell to the sense amplifier via the first electrical conductor, and wherein the sense amplifier is configured to sense whether the MTJ of the first MTJ antifuse bit cell is in the programmed antifuse state or the unprogrammed antifuse state based on a resistance of the MTJ of the first MTJ antifuse bit cell and a resistance of the first reference resistor.

15. The antifuse circuit as described in claim 14, wherein: The unprogrammed low state of the unprogrammed antifuse state corresponds to the MTJ having a resistance in one of a second resistance range, wherein when the MTJ is in a programmed antifuse state, the resistances in the second resistance range are greater than the resistance of the MTJ; the unprogrammed high state of the unprogrammed antifuse state corresponds to the MTJ having a resistance in one of a third resistance range, wherein most of the resistances in the third resistance range are greater than all of the resistances in the second resistance range; and each of the resistance of the first reference resistor and the resistance of the second reference resistor is (i) higher than a lower limit of the second resistance range and (ii) lower than a lower limit of the third resistance range.

16. The antifuse circuit of claim 15, further comprising: a second PMOS transistor electrically connected to the first reference resistor to responsively connect the first reference resistor to the second electrical conductor during the first operation.

17. The antifuse circuit of claim 15, further comprising: a second PMOS transistor electrically connected to the first reference resistor to responsively connect the first reference resistor to the second electrical conductor during the first operation; and a third PMOS transistor electrically connected to the second reference resistor to electrically disconnect the second reference resistor from the first electrical conductor during the first operation.

18. The antifuse circuit of claim 14, further comprising: a second PMOS transistor electrically connected to the first reference resistor to (i) connect the first reference resistor to the second electrical conductor during the first operation and (ii) disconnect the first reference resistor from the second electrical conductor during a second operation; A third PMOS transistor electrically connected to the second reference resistor to (i) disconnect the second reference resistor from the first electrical conductor during the first operation and (ii) connect the second reference resistor to the first electrical conductor during the second operation, wherein in the second operation, (i) the first PMOS transistor of the second MTJ antifuse bit cell is responsively enabled by applying a voltage to the gate of the first PMOS transistor of the second MTJ antifuse bit cell to electrically connect the MTJ of the second MTJ antifuse bit cell to the sense amplifier via the second electrical conductor and (ii) the third PMOS transistor is responsively enabled by applying a voltage to the gate of the third PMOS transistor to electrically connect the second reference resistor to the sense amplifier via the first electrical conductor, and wherein the sense amplifier is configured during operation to sense whether the MTJ of the second MTJ antifuse bit cell is in the programmed antifuse state or the unprogrammed antifuse state.

19. The antifuse circuit of request item 18, wherein: The unprogrammed low state of the unprogrammed antifuse state corresponds to the MTJ having a resistance in one of a second resistance range, wherein when the MTJ is in a programmed antifuse state, the resistances in the second resistance range are greater than the resistance of the MTJ; the unprogrammed high state of the unprogrammed antifuse state corresponds to the MTJ having a resistance in one of a third resistance range, wherein most of the resistances in the third resistance range are greater than all of the resistances in the second resistance range; and each of the resistance of the first reference resistor and the resistance of the second reference resistor (i) is higher than a lower limit of the second resistance range and (i) is lower than a lower limit of the third resistance range.

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