Semiconductor memory device

Abstract

A semiconductor memory element includes: a substrate; a plurality of memory cells disposed along a first direction and at least one strip cell located between the plurality of memory cells; a plurality of bit line contacts electrically connected to a plurality of drain doped regions of the plurality of memory cells; and at least one source line contact electrically connected to a diffusion region of the at least one strip cell, wherein the at least one source line contact and the plurality of bit line contacts are aligned in the first direction.

Description

Technical Field

[0001] This invention relates to the field of semiconductor technology, and in particular to a flash memory device. Prior Technology

[0002] Flash memory is a type of storage device that can be erased and reprogrammed in blocks. Flash memory consists of a memory array with a large number of memory cells. Each memory cell includes a floating-gate field-effect transistor (FET) capable of retaining charge. Memory cells are typically divided into blocks, and by charging the floating gate, the memory cells within a block can be electrically programmed randomly. The data in a memory cell depends on the presence or absence of charge in the floating gate, and the charge can be removed from the floating gate through a block erase operation.

[0003] Common types of flash memory cells include stacked flash cells and split flash cells (e.g., third-generation SUPERFLASH (ESF3) memory cells). Compared to stacked flash cells, split flash cells offer lower power consumption, higher injection efficiency, less susceptibility to short-channel effects, and better over-erasure resistance. However, a drawback of existing ESF3 memory cells is the need to create source line contacts on the strap cell between two adjacent control gate lines, which can lead to short circuits between the erase gate line and the source line. Summary of the Invention

[0004] The main objective of this invention is to provide an improved semiconductor memory device to overcome the shortcomings and disadvantages of the prior art.

[0005] The present invention provides a semiconductor memory element comprising: a substrate; a plurality of element lines, including a select gate line, a control gate line, an erase gate line, and a source line extending parallel to each other along a first direction, wherein the control gate line is disposed between the erase gate line and the select gate line, and the source line is located in the substrate below the erase gate line, wherein the plurality of element lines define a plurality of memory cells spaced apart along the length of the element lines and at least one strip cell located between the plurality of memory cells; a plurality of bit line contacts electrically connected to a plurality of drain doped regions of the plurality of memory cells, wherein the plurality of drain doped regions are adjacent to the select gate line; and at least one source line contact electrically connected to a diffusion region of the strip cell below the select gate line, wherein the at least one source line contact is aligned with the plurality of bit line contacts in the first direction.

[0006] According to an embodiment of the present invention, each of the plurality of memory cells includes a floating gate disposed below the control gate line.

[0007] According to an embodiment of the present invention, the diffusion region of the band cell is a heavily doped region.

[0008] According to an embodiment of the present invention, the diffusion region extends along the second direction to the area directly below the control gate line.

[0009] According to an embodiment of the present invention, the band cell comprises an asymmetric active region layout structure.

[0010] According to an embodiment of the present invention, the asymmetrical active region layout structure includes a longer active region extending along a second direction, a shorter active region extending along the second direction and parallel to the longer active region, and an intermediate active region connecting the longer active region and the shorter active region.

[0011] According to an embodiment of the present invention, the at least one source line contact is disposed on the end portion of the longer active region.

[0012] According to an embodiment of the present invention, no contact is provided directly above the intermediate active region, and no interruption is provided in the erasure gate line directly above the at least one band cell.

[0013] According to an embodiment of the present invention, each of the plurality of memory cells is contained in a first gate dielectric layer between the select gate line and the substrate, and the at least one strip cell is contained in a second gate dielectric layer between the select gate line and the substrate, wherein the second gate dielectric layer is thicker than the first gate dielectric layer.

[0014] According to an embodiment of the present invention, the at least one band cell includes a dummy floating gate below the control gate line and a permanently conductive floating gate channel directly below the dummy floating gate.

[0015] Another aspect of the present invention provides a semiconductor memory element comprising: a substrate; a plurality of memory cells disposed along a first direction and at least one strip cell located between the plurality of memory cells; a plurality of bit line contacts electrically connected to a plurality of drain doped regions of the plurality of memory cells; and at least one source line contact electrically connected to a diffusion region of the at least one strip cell, wherein the at least one source line contact and the plurality of bit line contacts are aligned in the first direction.

[0016] According to an embodiment of the present invention, the semiconductor memory element further includes a plurality of element lines, including a select gate line, a control gate line, an erase gate line, and a source line extending parallel to each other along a first direction, wherein the control gate line is disposed between the erase gate line and the select gate line, and the source line is located in the substrate below the erase gate line.

[0017] According to an embodiment of the present invention, the plurality of memory cells and the at least one band cell are arranged along the length of the element line.

[0018] According to an embodiment of the present invention, the plurality of drain doped regions and the select gate are adjacent to each other.

[0019] According to an embodiment of the present invention, each of the plurality of memory cells includes a floating gate disposed below the control gate line.

[0020] According to an embodiment of the present invention, each of the plurality of memory cells is contained in a first gate dielectric layer between the select gate line and the substrate, and the at least one strip cell is contained in a second gate dielectric layer between the select gate line and the substrate, wherein the second gate dielectric layer is thicker than the first gate dielectric layer.

[0021] According to an embodiment of the present invention, the diffusion region of the at least one band cell is a heavily doped region, wherein the diffusion region extends along the second direction to the region directly below the control gate line.

[0022] According to an embodiment of the present invention, the at least one band cell comprises an asymmetric active region layout structure.

[0023] According to an embodiment of the present invention, the asymmetric active region layout structure includes a longer active region extending along the second direction, a shorter active region extending along the second direction and parallel to the longer active region, and an intermediate active region connecting the longer active region and the shorter active region.

[0024] According to an embodiment of the present invention, the at least one source line contact is disposed on the end portion of the longer active region. Simple Explanation of the Diagram

[0025] Figure 1 is a partial layout schematic diagram of a semiconductor memory element according to an embodiment of the present invention. Figures 2 to 4 are schematic cross-sectional views along tangents I-I', II-II', and III-III' in Figure 1, respectively. Implementation

[0026] In the following description, details will be illustrated with reference to the accompanying drawings, which also form part of the detailed description of the specification, and are depicted in a manner that describes specific examples in which the embodiments can be implemented. The embodiments described below are described in sufficient detail to enable those skilled in the art to implement them.

[0027] Of course, other embodiments may also be adopted, or any structural, logical, and electrical changes may be made without departing from the embodiments described herein. Therefore, the detailed description below should not be regarded as limiting; rather, the embodiments included therein will be defined by the appended claims.

[0028] Please refer to Figures 1 to 4, where Figure 1 is a partial layout schematic diagram of a semiconductor memory element 1 according to an embodiment of the present invention, and Figures 2 to 4 are schematic cross-sectional views shown along tangents I-I', II-II', and III-III' in Figure 1, respectively. As shown in Figures 1 to 4, the semiconductor memory element 1 includes a substrate 100, for example, a P-type doped silicon substrate, but not limited thereto. A plurality of element lines DL are provided on the substrate 100, including a select gate line SGL, a control gate line CGL, an erase gate line EGL, and a source line SL extending parallel to a first direction D1, wherein the control gate line CGL is disposed between the erase gate line EGL and the select gate line SGL, and the source line SL is located in the substrate 100 directly below the erase gate line EGL.

[0029] As shown in Figure 1, in the substrate 100, the source line SL extending along the first direction D1 and a plurality of elongated active regions AA extending along the second direction D2 intersect. According to an embodiment of the present invention, the source line SL may be a heavily doped region formed in the substrate 100, for example, an N+ heavily doped region.

[0030] According to an embodiment of the present invention, as shown in FIG1, a plurality of element lines DL define a plurality of memory cells MC (formed on each elongated active region AA) spaced apart from each other along their length (or the first direction D1) and at least one strip cell SC located between the plurality of memory cells MC. For example, a select gate contact SGC can be formed on the strip cell SCS, and a control gate contact CGC can be formed on the strip cell SCC. The control gate contact CGC can be provided on the extension CGE that extends outward from the control gate line CGL along the second direction D2.

[0031] According to an embodiment of the present invention, a plurality of bit line contacts BLC are provided on the first direction D1, each electrically connected to the drain doped region DD of the memory cell MC, wherein the drain doped region DD is adjacent to the select gate line SGL. According to an embodiment of the present invention, the semiconductor memory element 1 further includes at least one source line contact SLC electrically connected to the diffusion region DR of the strip cell SC located below the select gate line SGL. According to an embodiment of the present invention, the diffusion region DR of the strip cell SC is a heavily doped region, for example, an N+ heavily doped region. According to an embodiment of the present invention, as shown in Figures 1 and 2, the diffusion region DR extends continuously along the second direction D2 to the region directly below the control gate line CGL.

[0032] According to an embodiment of the present invention, as shown in FIG1, the source line contact SLC is substantially aligned with the bit line contact BLC in a first direction D1. According to an embodiment of the present invention, as shown in FIG4, each memory cell MC includes a floating gate FG disposed below the control gate line CGL. According to an embodiment of the present invention, as shown in FIGS. 2 and 3, the strip cell SC includes a dummy floating gate DFG below the control gate line CGL, and a permanently conductive floating gate channel CHF directly below the dummy floating gate DFG.

[0033] According to an embodiment of the present invention, as shown in FIG. 4, each memory cell MC is contained in a first gate dielectric layer GDL1 between the select gate line SGL and the substrate 100. According to an embodiment of the present invention, as shown in FIG. 2, the strip cell SC is contained in a second gate dielectric layer GDL2 between the select gate line SGL and the substrate 100. According to an embodiment of the present invention, the second gate dielectric layer GDL2 is thicker than the first gate dielectric layer GDL1.

[0034] As shown in Figures 2 to 4, an etch stop layer 310 and an interlayer dielectric layer 320 may be deposited on the substrate 100. The etch stop layer 310 conformally covers the select gate line SGL, the control gate line SGL, and the erase gate line EGL, while the interlayer dielectric layer 320 covers the etch stop layer 310. According to an embodiment of the present invention, the source line contact SLC penetrates the interlayer dielectric layer 320 and the etch stop layer 310, and is electrically connected to the diffusion region DR located below the select gate line SGL.

[0035] According to an embodiment of the present invention, as shown in FIG1, the band cell SC includes an asymmetric active region layout structure 200. According to an embodiment of the present invention, the asymmetric active region layout structure 200 includes a longer active region 210 extending along a second direction D2, a shorter active region 220 extending along the second direction D2 and parallel to the longer active region 210, and an intermediate active region 230 connecting the longer active region 210 and the shorter active region 220. As shown in FIGS. 1 and 3, a shallow trench insulation structure ST is provided between the shorter active region 220 and the longer active region 210 in the same row as the adjacent region along the second direction D2 to avoid disturbance during programming operations.

[0036] According to an embodiment of the present invention, as shown in Figures 1 and 2, the source line contact SLC is disposed on the heavily doped region DDS at the end portion of the longer active region 210 in the second direction D2, and aligned with the bit line contact BLC in the first direction D1. According to an embodiment of the present invention, no contact is disposed directly above the intermediate active region 230, and no discontinuity is provided in the erase gate line EGL directly above the strip cell SC. In other words, the erase gate line EGL passes continuously through the strip cell SC. Since it is not necessary to provide a discontinuity or opening in the erase gate line EGL directly above the strip cell SC, the problem of short circuit between the erase gate line and the source line can be effectively avoided.

[0037] The semiconductor memory element 1 of the present invention includes: a substrate 100; a plurality of memory cells MC disposed along a first direction D1 and a strip cell SC located between the plurality of memory cells MC; a plurality of bit line contacts BLC electrically connected to a plurality of drain doped regions DD of the plurality of memory cells MC; and a source line contact SLC electrically connected to a diffusion region DR of the strip cell SC. According to an embodiment of the present invention, the source line contact SLC and the plurality of bit line contacts BLC are aligned in the first direction D1.

[0038] According to an embodiment of the present invention, the semiconductor memory element 1 further includes a plurality of element lines DL, including a select gate line SGL, a control gate line CGL, an erase gate line EGL, and a source line SL extending parallel to a first direction D1, wherein the control gate line CGL is disposed between the erase gate line EGL and the select gate line SGL, and the source line SL is located in the substrate 100 below the erase gate line EGL.

[0039] According to an embodiment of the present invention, a plurality of memory cells MC and band cells SC are arranged along the length of the element line DL.

[0040] According to an embodiment of the present invention, a plurality of drain doped regions DD and select gate lines SGL are adjacent to each other.

[0041] According to an embodiment of the present invention, each memory cell MC includes a floating gate FG disposed below the control gate line CGL.

[0042] According to an embodiment of the present invention, each memory cell MC is contained in a first gate dielectric layer GDL1 between the select gate line SGL and the substrate 100, and the strip cell SC is contained in a second gate dielectric layer GDL2 between the select gate line SGL and the substrate 100, wherein the second gate dielectric layer GDL2 is thicker than the first gate dielectric layer GDL1.

[0043] According to an embodiment of the present invention, the diffusion region DR of the band cell SC is a heavily doped region, wherein the diffusion region DR extends along the second direction D2 to the region directly below the control gate line CGL.

[0044] According to an embodiment of the present invention, the band cell SC includes an asymmetric active region layout structure 200.

[0045] According to an embodiment of the present invention, the asymmetric active region layout structure 200 includes a longer active region 210 extending along a second direction D2, a shorter active region 220 extending along the second direction D2 and parallel to the longer active region 210, and an intermediate active region 230 connecting the longer active region 210 and the shorter active region 220.

[0046] According to an embodiment of the present invention, the source line contact SLC is disposed on the end portion of the longer active region 210. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made in accordance with the claims of the present invention shall be covered by the present invention.

[0047] 1: Semiconductor memory devices 100: Base 200: Asymmetric active region layout structure 210: Longer active region 220: Shorter active region 230: Intermediate Active Region 310: Etching Stop Layer 320: Interlayer dielectric layer 3 AA: Active Region BLC: Bit Line Contact CGC: Control gate contact CGL: Control gate line CGE: Extension CHF: Floating Gate Channel DD: Drain-doped region DDS: Heavily Doped Region DFG: Fictitious floating gate DL: Component Line DR: Diffusion Region EGL: Wipe the gate line FG: Floating gate GDL1: First gate dielectric layer GDL2: Second gate dielectric layer MC: Memory Cell SC, SCS, SCC: Z-cells SGC: Selector Gate Contact SGL: Select gate line SL: Source Line SLC: Source Line Contact ST: Shallow trench insulation structure D1: First Direction D2: Second Direction

Claims

1. A semiconductor memory element, comprising: a substrate; and a plurality of element lines, including a select gate line, a control gate line, an erase gate line, and a source line extending parallel to each other along a first direction, wherein, The control gate line is disposed between the erase gate line and the select gate line, and the source line is located in the substrate below the erase gate line. The plurality of element lines define a plurality of memory cells spaced apart along the length of the element lines and at least one strip cell located between the plurality of memory cells. A plurality of bit line contacts are electrically connected to a plurality of drain doped regions of the plurality of memory cells, wherein the plurality of drain doped regions are adjacent to the select gate line. At least one source line contact is electrically connected to the diffusion region of the strip cell below the select gate line, wherein the at least one source line contact is aligned with the plurality of bit line contacts in the first direction. The at least one strip cell includes a dummy floating gate below the control gate line and a permanently conductive floating gate channel directly below the dummy floating gate.

2. The semiconductor memory element according to claim 1, wherein, Each of the plurality of memory cells includes a floating gate disposed below the control gate line.

3. The semiconductor memory element according to claim 1, wherein, The diffusion region of the band cell is a heavily doped region.

4. The semiconductor memory element according to claim 3, wherein, The diffusion region extends along the second direction to the area directly below the control gate line.

5. The semiconductor memory element according to claim 4, wherein, The band cells contain an asymmetric active region layout structure.

6. The semiconductor memory element according to claim 5, wherein, The asymmetric active region layout structure includes a longer active region extending along the second direction, a shorter active region extending along the second direction and parallel to the longer active region, and an intermediate active region connecting the longer active region and the shorter active region.

7. The semiconductor memory element according to claim 6, wherein, The at least one source wire contact is disposed on the end portion of the longer active region.

8. The semiconductor memory element according to claim 6, wherein, There is no contact directly above the intermediate active region, and there is no interruption in the erasure gate line directly above the at least one band cell.

9. The semiconductor memory element according to claim 1, wherein, Each of the plurality of memory cells is contained in a first gate dielectric layer between the select gate line and the substrate, and the at least one strip cell is contained in a second gate dielectric layer between the select gate line and the substrate, wherein the second gate dielectric layer is thicker than the first gate dielectric layer.

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