Light emitting element and display device including the same

Abstract

A light-emitting element includes: a light-emitting element core comprising a first semiconductor layer, a second semiconductor layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer; and a single-crystal insulating layer surrounding a side surface of the light-emitting element core.

Description

Technical Field

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2021 - 0116304, filed with the Korean Intellectual Property Office (KIPO) on September 1, 2021, the entire disclosure of which is incorporated herein by reference.

[0003] One or more embodiments of this disclosure relate to a light - emitting element and a display device including the same.

Prior Art

[0004] With the development of multimedia, the importance of display devices has also increased. Accordingly, various display devices such as Organic Light Emitting Displays (OLEDs) and Liquid Crystal Displays (LCDs) have been widely used.

[0005] A display device is a device for displaying images and includes a display panel such as an organic light - emitting display panel and / or a liquid - crystal display panel. The display panel may include a light - emitting element, which may be a Light Emitting Diode (LED). Examples of light - emitting diodes include Organic Light Emitting Diodes (OLEDs) that use organic materials as light - emitting materials, inorganic light - emitting diodes that use inorganic materials as light - emitting materials, and the like.

Summary of the Invention

[0006] One or more aspects of embodiments of this disclosure provide a light - emitting element having improved element efficiency and reliability by forming a first element insulating layer as a single - crystal insulating layer between a side surface of a light - emitting element core and a second element insulating layer, thereby improving surface defects of the light - emitting element core including a plurality of semiconductor layers and physically separating internal defects of the second element insulating layer from the light - emitting element core.

[0007] One or more aspects of embodiments of the present disclosure further provide a light-emitting element having improved element efficiency and reliability by forming a superlattice structure having alternately stacked first and second layers with different materials between a side surface of a light-emitting element core and a second element insulating layer, thereby improving surface defects of the light-emitting element core including a plurality of semiconductor layers and preventing or reducing diffusion of impurities from the second element insulating layer to the light-emitting element core.

[0008] One or more aspects of embodiments of the present disclosure further provide a display device having improved display quality by including a light-emitting element having a first element insulating layer as a single crystal insulating layer, or including a first element insulating layer having a superlattice structure.

[0009] However, aspects of embodiments of the present disclosure are not limited to the content described herein. Through reference to the detailed description of the present disclosure below, the above and other aspects of the present disclosure will become clearer to those of ordinary skill in the art to which the present disclosure pertains.

[0010] According to one or more embodiments of the present disclosure, a light-emitting element may include: a light-emitting element core including a first semiconductor layer, a second semiconductor layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer; and a single crystal insulating layer surrounding a side surface (e.g., located thereon) of the light-emitting element core.

[0011] The light-emitting element may further include an element insulating layer located on an outer surface of the single crystal insulating layer.

[0012] The element insulating layer may include a first element insulating film located on an outer surface of (e.g., surrounding) the single crystal insulating layer and a second element insulating film located on an outer surface of the first element insulating film.

[0013] The single crystal insulating layer may have a superlattice structure including alternately stacked first and second layers of different materials, and the first and second layers may be stacked in a direction substantially perpendicular to (e.g., perpendicular to) a side surface of the light-emitting element core.

[0014] Each of the first and second layers may be a single crystal insulating film.

[0015] Each of the first and second layers may have a thickness equal to or less than a critical thickness.

[0016] At least one of the plurality of first layers may include a first compound semiconductor, and at least one of the plurality of second layers may include a second compound semiconductor different from the first compound semiconductor.

[0017] Each of the first compound semiconductor and the second compound semiconductor may include a III-V group semiconductor compound.

[0018] The chemical formula of the first compound semiconductor may be AB (where A is a group III element and B is a group V element), and the chemical formula of the second compound semiconductor may be AxC1-xB (where 0 ≤ x < 1, A and C are group III elements, and B is a group V element).

[0019] Each of the first layer and the second layer may have a thickness greater than 0 and equal to or less than 5 nm.

[0020] The single-crystal insulating layer may be directly located on the side surface of the light-emitting element core, and the side surface of the light-emitting element core may include at least one of the side surface of the first semiconductor layer, the side surface of the second semiconductor layer, or the side surface of the light-emitting layer.

[0021] According to one or more embodiments of the present disclosure, a light-emitting element may include: a light-emitting element core including a first semiconductor layer, a second semiconductor layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer; and a first element insulating layer located on (e.g., surrounding) the side surface of the light-emitting element core, wherein the first element insulating layer has a superlattice structure in which a first layer including a first compound semiconductor and a second layer including a second compound semiconductor different from the first compound semiconductor are alternately stacked.

[0022] Each of the first compound semiconductor and the second compound semiconductor may include a III-V group semiconductor compound.

[0023] The chemical formula of the first compound semiconductor may be AB (where A is a group III element and B is a group V element), and the chemical formula of the second compound semiconductor may be AxC1-xB (where 0 ≤ x < 1, A and C are group III elements, and B is a group V element).

[0024] Each of the first layer and the second layer may be a single-crystal layer.

[0025] Each of the first layer and the second layer may have a thickness greater than 0 and equal to or less than 5 nm.

[0026] The light-emitting element may further include a second element insulating layer located on (e.g., surrounding) the first element insulating layer.

[0027] The second element insulating layer may include a first element insulating film on an outer surface of the first element insulating layer and a second element insulating film on an outer surface of (e.g., surrounding) the first element insulating film.

[0028] The light-emitting element may further include a first element insulating film on a side surface of (e.g., surrounding) the light-emitting element core; and a second element insulating film on an outer surface of (e.g., surrounding) the first element insulating layer, wherein the first element insulating layer may be between the first element insulating film and the second element insulating film.

[0029] According to one or more embodiments of the present disclosure, a display device may include: a first electrode and a second electrode separated from each other on a substrate; and a light-emitting element between the first electrode and the second electrode, wherein the light-emitting element includes: a light-emitting element core including a first semiconductor layer, a second semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer; and a single-crystal insulating layer on a side surface of (e.g., surrounding) the light-emitting element core.

[0030] The single-crystal insulating layer may have a superlattice structure in which a first layer and a second layer including different materials are alternately stacked, and the first layer and the second layer may be stacked in a direction substantially perpendicular to a side surface of the light-emitting element core.

[0031] The first layer may include a first compound semiconductor, and the second layer may include a second compound semiconductor different from the first compound semiconductor.

[0032] Each of the first layer and the second layer may be a single-crystal insulating film.

[0033] According to one or more embodiments of the present disclosure, a display device may include: a first electrode and a second electrode separated from each other on a substrate; and a light-emitting element between the first electrode and the second electrode, wherein the light-emitting element includes: a light-emitting element core including a first semiconductor layer, a second semiconductor layer, and a light-emitting layer between the first semiconductor layer and the second semiconductor layer; and a first element insulating layer on a side surface of the light-emitting element core, and the first element insulating layer has a superlattice structure in which a first layer including a first compound semiconductor and a second layer including a second compound semiconductor different from the first compound semiconductor are alternately stacked.

[0034] Each of the first compound semiconductor and the second compound semiconductor may include a III-V group semiconductor compound.

[0035] The chemical formula of the first compound semiconductor may be AB (where A is a Group III element and B is a Group V element), and the chemical formula of the second compound semiconductor may be AxC1-xB (where 0 ≤ x < 1, A and C are Group III elements, and B is a Group V element).

[0036] Each of the first layer and the second layer may be a single crystal layer.

[0037] Further details of other embodiments will be described in the detailed description and illustrated in the accompanying drawings.

[0038] A light-emitting element according to one or more embodiments may include: a light-emitting element core including a plurality of semiconductor layers, and a first element insulating layer located on (e.g., surrounding) a side surface (or outer peripheral layer) of the light-emitting element core. The first element insulating layer may be directly located on the side surface of the light-emitting element core and may be a single crystal insulating layer including an insulating material having a single crystal structure. When the first element insulating layer is a single crystal insulating layer, the single crystal insulating layer may be directly located on the surface (side surface) of the light-emitting element core body, so that the surface of the light-emitting element core may have a surface-treated effect, and thus surface defects of the light-emitting element core may be improved.

[0039] In addition, when the light-emitting element further includes a second element insulating layer on an outer surface of the first element insulating layer, the first element insulating layer may be disposed between the light-emitting element core and the second element insulating layer to physically separate internal defects of the light-emitting element core from the second element insulating layer, and prevent or reduce diffusion of impurities from the second element insulating layer to the plurality of semiconductor layers of the light-emitting element core, thereby improving element efficiency and reliability of the light-emitting element.

[0040] A light-emitting element according to one or more other embodiments may include a light-emitting element core including a plurality of semiconductor layers and a first element insulating layer located on (e.g., surrounding) a side surface (or outer peripheral surface) of the light-emitting element, and having a superlattice structure in which heterogeneous first and second layers are alternately stacked. Each of the first layer and the second layer may be a single crystal insulating film. In this case, each of the first layer and the second layer may be formed to have a thickness equal to or less than a critical thickness, thereby maintaining a single crystal structure, and the first element insulating layer may have a structure in which the single crystal insulating films are stacked into a plurality of layers, and thus may be formed to have a large (e.g., appropriate) thickness. Therefore, insulating characteristics of the first element insulating layer and a blocking effect of the first element insulating layer in preventing or reducing diffusion of impurities may be improved, and thus reliability of the light-emitting element may be improved.

[0041] In addition, when at least one of the plurality of semiconductor layers in the light-emitting element core includes a group III and group V semiconductor material, each of the first layer and the second layer included in the first element insulating layer may be a compound semiconductor layer including a III-V compound semiconductor. Therefore, the lattice constant difference between the materials included in the semiconductor layers of the light-emitting element core and the materials of the first layer and the second layer can be minimized or reduced, and a first element insulating layer having high quality can be included, thereby improving the element efficiency and reliability of the light-emitting element.

[0042] One or more aspects of the embodiments of the present disclosure further provide a display device having improved display quality by including a light-emitting element including a first element insulating layer as a single crystal insulating layer, or a light-emitting element including a first element insulating layer having a superlattice structure.

[0043] A display device according to one or more embodiments may include a light-emitting element having improved element efficiency and reliability to have improved display quality.

[0044] The effects of the present disclosure are not limited to the above effects, and various other effects are included in the specification.

Embodiment

[0046] The present disclosure will hereinafter describe embodiments of the present disclosure in more detail with reference to the accompanying drawings. However, the described embodiments may be implemented in various different forms and should not be construed as being limited only to the embodiments shown herein. On the contrary, these embodiments provided as examples will make the present disclosure more thorough and complete, and will fully convey the scope of the present disclosure to those of ordinary skill in the art.

[0047] It will be understood that when a layer is referred to as being "on" another layer or substrate, it may be directly on the other layer or substrate (e.g., without an intermediate layer therebetween), or there may be intervening elements or layers. Throughout the specification, like reference numerals denote like components.

[0048] Spatial relative terms such as "beneath", "below", "lower", "upper", "bottom", "top", and their like are used herein for convenience in describing the relationship between one element or feature shown in the drawings and another element or feature. It will be understood that, in addition to the directions depicted in the drawings, spatial relative terms are also intended to encompass different directions of the device in use or operation. For example, when the device in one of the drawings is flipped over, an element described as "below" or "beneath" other elements or features will be oriented "above" or "over" those other elements or features. Thus, the term "below" can encompass both upward and downward directions. The device may be otherwise oriented (e.g., rotated 90 degrees or other orientation), and the spatial relative terms used herein should be interpreted accordingly.

[0049] It will be understood that although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. For example, without departing from the scope of the teachings of this disclosure, a first element hereinbelow may be referred to as a second element. Similarly, a second element may be referred to as a first element.

[0050] As used herein, the singular forms "a", "an", and "the" are also intended to include the plural forms, unless the context clearly dictates otherwise.

[0051] It can be further understood that when the terms "include", "including", "comprises", and / or "comprising" are used in the specification, it means that the specified features, steps, operations, elements, and / or components are present, but do not preclude the presence or addition of one or more other features, steps, operations, elements, and / or components.

[0052] As used herein, the terms "use", "using", and "used" may be respectively synonymous with the terms "utilize", "utilizing", and "utilized". As used herein, when expressions such as "at least one of", "one of", and "selected from" appear before a list of elements, they modify the entire list of elements and do not modify individual elements in the list. For example, "at least one of a, b and c", "at least one of a, b or c", and "at least one selected from the group consisting of a, b and c" can be understood to mean only a, only b, only c, both a and b (e.g., simultaneously), both a and c (e.g., simultaneously), both b and c (e.g., simultaneously), all of a, b and c, or variants thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items. Further, when "may" is used in describing embodiments of the present disclosure, it means "one or more embodiments of the present disclosure". As used herein, the terms "substantially", "about", and other similar terms are used as approximate terms rather than as measuring terms, and are intended to account for the inherent errors in measured and calculated values, and may be recognized by those of ordinary skill in the art to which the present disclosure pertains. As used herein, "about" or "approximately" includes the stated value and represents an acceptable range of deviation from the specific value determined by those of ordinary skill in the art, taking into account the relevant measurements and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" may mean within one or more standard deviations, or within ±30%, 20%, 10%, 5% of the stated value.

[0056] Any numerical range recited herein is intended to include all sub-ranges having the same numerical precision within the recited range. For example, a range "1.0 to 10.0" is intended to include all sub-ranges between (and including) the recited minimum value 1.0 and the recited maximum value 10.0, that is, having a minimum value greater than or equal to 1.0 and a maximum value less than or equal to 10.0, e.g., 2.4 to 7.6. Any recited maximum numerical limitation can include all lower numerical limitations, and all recited minimum numerical limitations in this specification can include all higher numerical limitations. Accordingly, the applicant reserves the right to amend this specification (including the claims) to expressly recite any sub-ranges that are included within the ranges expressly recited herein.

[0057] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0058] FIG. 1 is a schematic perspective view of a light-emitting element according to one or more embodiments of the present disclosure. FIG. 2 is a cross-sectional view of the light-emitting element according to one or more embodiments of the present disclosure.

[0059] Referring to FIGS. 1 and 2, the light-emitting element ED is a particle type element (e.g., a particle element), and may have a rod shape and / or a cylindrical shape, and may have a set or predetermined aspect ratio. The light-emitting element ED may have a shape extending in one direction X, and the length of the light-emitting element ED in the extending direction (or the length direction X) may be greater than the diameter of the light-emitting element ED, and the aspect ratio of the light-emitting element ED may be from 1.2:1 to 100:1, but the present disclosure is not limited thereto. For example, the light-emitting element ED may have a shape such as a cylindrical shape, a rod shape, a linear shape, and / or a tubular shape, or may have a polygonal prism shape such as a cubic shape, a rectangular parallelepiped shape, and / or a hexagonal prism shape, or may have a shape extending in one direction and having a partially inclined outer surface. Hereinafter, in the drawings for explaining the shape of the light-emitting element ED, the terms "one direction X", "the extending direction X of the light-emitting element ED", and "the length direction X of the light-emitting element ED" may be used interchangeably.

[0060] The light-emitting element ED may have dimensions in the nanometer scale (e.g., greater than 1 nm and less than 1 μm) to the micrometer scale (e.g., greater than 1 μm and less than 1 mm). In one or more embodiments, the light-emitting element ED may have dimensions in the nanometer scale in both length and diameter or have dimensions in the micrometer scale. In some other embodiments, the diameter of the light-emitting element ED may have dimensions in the nanometer scale, while the length of the light-emitting element ED may have dimensions in the micrometer scale. In some embodiments, some light-emitting elements ED have a nanometer-scale diameter and / or length, while other light-emitting elements ED may have a micrometer-scale diameter and / or length.

[0061] In one or more embodiments, the light-emitting element ED may be an inorganic light-emitting diode. The inorganic light-emitting diode may include a plurality of semiconductor layers. For example, the inorganic light-emitting diode may include a first conductivity type (e.g., n-type) semiconductor layer, a second conductivity type (e.g., p-type) semiconductor layer, and an active semiconductor layer interposed between the first conductivity type semiconductor layer and the second conductivity type semiconductor layer. The active semiconductor layer may receive holes and electrons provided from the first conductivity type semiconductor layer and the second conductivity type semiconductor layer, respectively, and the holes and electrons reaching the active semiconductor layer may combine with each other to emit light. In addition, the inorganic light-emitting diode may be aligned between two electrodes, and a polarity will be formed when an electric field is formed in a set or specific direction between the two electrodes facing each other.

[0062] The light-emitting element ED may include a light-emitting element core 30, a first element insulating layer 39, and a second element insulating layer 38.

[0063] The light-emitting element core 30 may have a shape extending in one direction X. The light-emitting element core 30 may have a rod shape and / or a cylindrical shape. However, the present disclosure is not limited thereto, and the light-emitting element core 30 may have a polygonal prism shape such as a cube shape, a rectangular prism shape, and / or a hexagonal prism shape, or may have a shape extending in one direction and having a partially inclined outer surface.

[0064] The light-emitting element core 30 may include a first semiconductor layer 31, a second semiconductor layer 32, a light-emitting layer 33, and an element electrode layer 37. The first semiconductor layer 31, the light-emitting layer 33, the second semiconductor layer 32, and the element electrode layer 37 may be sequentially stacked in one direction X, which is the length direction of the light-emitting element core 30.

[0065] The first semiconductor layer 31 may be doped with a dopant of a first conductivity type. The first conductivity type may be n-type, and the dopant of the first conductivity type may be silicon (Si), germanium (Ge), tin (Sn), and / or the like. For example, the first semiconductor layer 31 may be an n-type semiconductor. In one or more embodiments, the first semiconductor layer 31 may be made of n-type gallium nitride (n-GaN) doped with n-type silicon (Si).

[0066] The second semiconductor layer 32 may be separated from the first semiconductor layer 31, and the light-emitting layer 33 may be interposed therebetween. The second semiconductor layer 32 may be doped with a dopant of a second conductivity type. The second conductivity type may be p-type, and the dopant of the second conductivity type may be magnesium (Mg), zinc (Zn), calcium (Ca), strontium (Sr), barium (Ba), and / or the like. For example, the second semiconductor layer 32 may be a p-type semiconductor. In one or more embodiments, the second semiconductor layer 32 may be made of p-type gallium nitride (p-GaN) doped with p-type magnesium (Mg).

[0067] Although each of the first semiconductor layer 31 and the second semiconductor layer 32 is shown as a single layer in FIGS. 1 and 2, the present disclosure is not limited thereto. Each of the first semiconductor layer 31 and the second semiconductor layer 32 may further include more layers, for example, a clad layer and / or a Tensile Strain Barrier Reducing (TSBR) layer, depending on the materials included in the light-emitting layer 33.

[0068] The light-emitting layer 33 may be disposed between the first semiconductor layer 31 and the second semiconductor layer 32. The light-emitting layer 33 may include a material having a single quantum well structure or a multi-quantum well structure. The light-emitting layer 33 may emit light through the combination of electron-hole pairs according to an electrical signal applied through the first semiconductor layer 31 and the second semiconductor layer 32. For example, when the light-emitting layer 33 is configured to emit light in a blue wavelength band, the light-emitting layer 33 may include materials such as aluminum gallium nitride (AlGaN) and / or aluminum indium gallium nitride (AlGaInN), but is not limited thereto.

[0069] In some embodiments, the light-emitting layer 33 may include a structure in which semiconductor materials having a large bandgap energy and semiconductor materials having a small bandgap energy are alternately stacked, and may include other group III-V semiconductor materials, depending on the wavelength band of the emitted light. The light emitted by the light-emitting layer 33 is not limited to the light in the blue wavelength band, and in some embodiments, the light-emitting layer 33 may emit light in the red and / or green wavelength bands.

[0070] The light emitted from the light-emitting layer 33 can be emitted not only in one direction X along the length direction of the light-emitting element ED toward the two end faces of the light-emitting element ED, but also toward the side surfaces of the light-emitting element ED. The emission direction of the light emitted from the light-emitting layer 33 is not limited to a single direction.

[0071] The element electrode layer 37 can be disposed between the second semiconductor layer 32 and the electrode, and can be used to reduce the resistance when the two ends of the light-emitting element ED and the electrodes are electrically connected (e.g., electrically coupled) to apply an electrical signal to the first semiconductor layer 31 and the second semiconductor layer 32. The element electrode layer 37 can include at least one of aluminum (Al), titanium (Ti), indium (In), gold (Au), silver (Ag), indium tin oxide (ITO), indium zinc oxide (IZO), or indium tin zinc oxide (ITZO). The element electrode layer 37 can also include an n-type or p-type doped semiconductor material. Although the element electrode layer 37 is shown on the second semiconductor layer 32 in FIGS. 1 and 2, the present disclosure is not limited thereto. For example, the element electrode layer 37 can also be further located on the first semiconductor layer 31 to be disposed between the first semiconductor layer 31 and the electrode.

[0072] The first element insulating layer 39 can surround the side surface (or outer peripheral surface) of the light-emitting element core 30. The first element insulating layer 39 can surround the side surfaces of a plurality of semiconductor layers and / or element electrode layers included in the light-emitting element core 30. The first element insulating layer 39 can at least surround the side surfaces of the first semiconductor layer 31, the light-emitting layer 33, and the second semiconductor layer 32, and can extend in one direction X in which the light-emitting element core 30 extends.

[0073] The first element insulating layer 39 can surround the side surface of the light-emitting element core 30, but can expose the two end faces of the light-emitting element core 30. The first element insulating layer 39 is not located on any of the end faces of the light-emitting element core 30 (the upper surface and the lower surface of the light-emitting element core 30 in FIG. 1), so that the element electrode layer 37 and the first semiconductor layer 31 of the light-emitting element core 30 can be at least partially exposed by the first element insulating layer 39.

[0074] In one or more embodiments, the first element insulating layer 39 can include an insulating material having a single crystal structure. For example, the first element insulating layer 39 can be a single crystal insulating layer 39. Hereinafter, for the sake of explanation, the terms "first element insulating layer 39" and "single crystal insulating layer 39" can be used interchangeably with respect to the same element symbol "39".

[0075] The first element insulating layer 39 may include an insulating material having a single crystal structure, and the insulating material included in the first element insulating layer 39 may be a material having a dielectric constant higher than that of the materials in the plurality of semiconductor layers included in the light emitting element core 30. For example, the dielectric constant of the material included in the first element insulating layer 39 may be greater than the dielectric constant of the materials in the plurality of semiconductor layers of the light emitting element core 30. Since the insulating material included in the first element insulating layer 39 has a single crystal structure and has a dielectric constant higher than that of the materials in the plurality of semiconductor layers, the first element insulating layer 39 can function to improve the surface defects of the plurality of semiconductor layers included in the light emitting element core 30, which will be described in more detail below.

[0076] In one or more embodiments in which the first semiconductor layer 31, the second semiconductor layer 32, and the light emitting layer 33 include gallium nitride, the first element insulating layer 39 may include a single crystal insulating material having a dielectric constant greater than that of gallium nitride. In one or more embodiments, the first element insulating layer 39 may include aluminum nitride (AlN) having a single crystal structure, aluminum oxide (AlxOy) having a single crystal structure, and / or the like.

[0077] The first element insulating layer 39 may be directly located on the side surface of the light emitting element core 30. The first element insulating layer 39 may be in direct contact with the side surface of the light emitting element core 30. Therefore, the inner surface of the first element insulating layer 39 may be in contact with the side surface of the light emitting element core 30. Since the first element insulating layer 39 includes an insulating material having a single crystal structure and is directly formed on the side surface of the light emitting element core 30, the first element insulating layer 39 can perform surface treatment on the side surfaces of the first semiconductor layer 31, the second semiconductor layer 32, and the light emitting layer 33 of the light emitting element core 30 to improve the surface defects formed on the side surfaces of the plurality of semiconductor layers of the light emitting element core 30. The surface defects formed on the side surface of the light emitting element core 30 may be defects that occur on the surface of the outermost semiconductor layer exposed in the etching process for forming the light emitting element core 30 in the process of manufacturing the light emitting element ED, as will be described in more detail below.

[0078] In one or more embodiments, the first element insulating layer 39 may be interposed between the light-emitting element core 30 and the second element insulating layer 38, and may be used to prevent or reduce defects formed inside the second element insulating layer 38, and / or prevent or reduce the diffusion of impurities from the second element insulating layer 38 to the plurality of semiconductor layers (e.g., the first semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 33) of the light-emitting element core 30. For example, the first element insulating layer 39 may be interposed between the light-emitting element core 30 and the second element insulating layer 38, and may be used to physically separate the light-emitting element core 30 and the second element insulating layer 38 from each other.

[0079] The first element insulating layer 39 may have a set or predetermined thickness d1, and may be formed on the side surface of the light-emitting element core 30. The first element insulating layer 39 formed on the side surface of the light-emitting element core 30 may be formed by forming a first insulating material layer 390 (refer to FIG. 14) having a single crystal structure on the side surface (or outer peripheral surface) of the light-emitting element core 30 and then successively removing a part of the first insulating material layer 390, as described in more detail below.

[0080] Meanwhile, in order for the first element insulating layer 39 formed on the side surface of the light-emitting element core 30 to maintain a single crystal structure, the first element insulating layer 39 should be formed to have a thickness d1 equal to or less than the critical thickness. In this specification, the "critical thickness" may be defined as the thickness at which a thin film maintains a single crystal structure during the process of forming the thin film. In one or more embodiments, the thickness d1 of the first element insulating layer 39 may be in the range equal to or less than the critical thickness of the material included in the first element insulating layer 39. For example, when the first element insulating layer 39 includes aluminum nitride (AlN) having a single crystal structure, the thickness d1 of the first element insulating layer 39 may be in the range of 5 nm or less. In this case, the first element insulating layer 39 may be formed to maintain a single crystal structure.

[0081] The second element insulating layer 38 may be disposed on the outer surface (or outer peripheral surface) of the first element insulating layer 39. The second element insulating layer 38 may surround the outer surface (or outer peripheral surface) of the first element insulating layer 39.

[0082] The second element insulating layer 38 may surround the outer surface (or outer peripheral surface) of the first element insulating layer 39 and may extend in a direction X. The second element insulating layer 38 may cover the side surfaces of the light-emitting element core 30, but may expose both end surfaces of the light-emitting element core 30 similarly to the first element insulating layer 39. In FIGS. 1 and 2, the second element insulating layer 38 is formed to extend in the length direction X of the light-emitting element ED to cover the side surfaces of the first semiconductor layer 31 to the element electrode layer 37, but the present disclosure is not limited thereto. For example, the second element insulating layer 38 may only cover the side surfaces of some semiconductor layers including the light-emitting layer 33, or may cover a partial area of the side surface of the element electrode layer 37 while exposing another partial area of the side surface of the element electrode layer 37.

[0083] The second element insulating layer 38 may be used to protect the first semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 33 of the light-emitting element core 30. The second element insulating layer 38 may prevent or reduce the risk of electrical short circuit that may occur when the light-emitting layer 33 is in direct contact with the electrode such that an electrical signal is transmitted to the light-emitting element ED through this electrode.

[0084] The second element insulating layer 38 may include a material having insulating properties. For example, the second element insulating layer 38 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlN), aluminum oxide (AlxOy), titanium oxide (TiOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and / or the like.

[0085] The light-emitting element ED according to one or more embodiments may include a first element insulating layer (or single-crystal insulating layer) 39 that surrounds (e.g., encloses) the side surfaces of the light-emitting element core 30 including a plurality of semiconductor layers, and the first element insulating layer 39 may include an insulating material having a single-crystal structure. Since the single-crystal insulating layer (the first element insulating layer 39) has a single-crystal structure and is provided to form a physical interface between the second element insulating layer 38 and the semiconductor layers of the light-emitting element core 30, the single-crystal insulating layer (the first element insulating layer 39) may prevent or reduce the diffusion of impurities from the second element insulating layer 38 to the plurality of semiconductor layers of the light-emitting element core 30 and may physically separate the internal defects of the second element insulating layer 38 and the plurality of semiconductor layers of the light-emitting element core 30 from each other.

[0086] According to one or more embodiments, in an etching process for forming a light-emitting element core 30 in a process of manufacturing a light-emitting element ED, defects of a semiconductor material may occur on surfaces of a plurality of semiconductor layers of the light-emitting element core 30 that are located on the outermost side and exposed to an etchant. Surface defects formed on side surfaces of the plurality of semiconductor layers of the light-emitting element core 30 may cause leakage of electrons injected into the semiconductor layer and / or capture of holes injected into the semiconductor layer, and may hinder recombination of electrons and holes, resulting in a reduction in light efficiency of the light-emitting element ED.

[0087] In the light-emitting element ED according to an embodiment, the first element insulating layer 39 may have a single crystal structure and may be directly located on a side surface of the light-emitting element core 30 where surface defects may occur during the manufacturing process of the light-emitting element ED. Therefore, the side surface of the light-emitting element core 30 may have an effect of surface treatment through (for example, due to) the first element insulating layer 39. For example, a single crystal insulating layer (the first element insulating layer 39) is formed on side surfaces of the plurality of semiconductor layers of the light-emitting element core 30, so that the dislocation density on the surface of the light-emitting element core 30 can be reduced. Therefore, by improving surface defects formed on the side surface of the light-emitting element core 30 through the first element insulating layer 39, the element efficiency and reliability of the light-emitting element ED can be improved.

[0088] In one or more embodiments, the first element insulating layer 39 may be formed to have a thickness equal to or less than a critical thickness of a material included in the first element insulating layer 39. Therefore, the first element insulating layer 39 can be formed as a single crystal insulating layer having good single crystallinity or appropriately maintained single crystallinity. Therefore, the first element insulating layer 39 as a single crystal insulating layer can further improve surface defects of the light-emitting element core 30 and can improve its effect of preventing or reducing diffusion of impurities from the second element insulating layer 38 to the outside of the plurality of semiconductor layers of the light-emitting element core 30.

[0089] FIG. 3 is a cross-sectional view of a light-emitting element according to one or more embodiments of the present disclosure.

[0090] Referring to FIG. 3, the light-emitting element ED according to an embodiment is different from the light-emitting element according to one or more embodiments of FIG. 2 in that it is not provided with a second element insulating layer 38.

[0091] In embodiments where the second element insulating layer 38 is not provided, the thickness of the first element insulating layer 39 may not be limited (for example, it may be any suitable thickness) such that the first element insulating layer 39 protects the plurality of semiconductor layers of the light-emitting element core 30. The thickness of the first element insulating layer 39 may be in the range of 2 nm to 5 nm (or 2 nm to less than 5 nm), but is not limited thereto. The thickness of the first element insulating layer 39 may be appropriately changed according to the formation method of the first element insulating layer 39.

[0092] FIG. 4 is a cross-sectional view of a light-emitting element according to one or more embodiments of the present disclosure.

[0093] Referring to FIG. 4, the light-emitting element ED according to an embodiment is different from the light-emitting element according to one or more embodiments of FIG. 2 in that its second element insulating layer 38_1 includes a plurality of element insulating films.

[0094] For example, the second element insulating layer 38_1 may include a first element insulating film 381 and a second element insulating film 382.

[0095] The first element insulating film 381 may be disposed on the outer surface (or outer peripheral surface) of the first element insulating layer 39. The first element insulating film 381 may surround the outer surface (or outer peripheral surface) of the first element insulating layer 39. The structure and materials included in the first element insulating film 381 may be substantially the same as the structure and materials of the second element insulating layer 38 described above. For example, the first element insulating film 381 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlN), aluminum oxide (AlxOy), titanium oxide (TiOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and / or the like.

[0096] The second element insulating film 382 may be disposed on the outer surface (or outer peripheral surface) of the first element insulating film 381. The second element insulating film 382 may surround the outer surface (or outer peripheral surface) of the first element insulating film 381 and may extend in one direction X. The second element insulating film 382 may cover the side surfaces of the light-emitting element core 30, but may expose the two end surfaces of the light-emitting element core 30 similarly to the first element insulating film 381. In FIG. 4, the second element insulating film 382 is formed to extend in the length direction X of the light-emitting element ED to cover the side surfaces of the first semiconductor layer 31 to the element electrode layer 37, but the present disclosure is not limited thereto.

[0097] The second element insulating film 382 can be used to protect the first element insulating film 381. For example, the second element insulating film 382 can surround the outer surface (or outer peripheral surface) of the first element insulating film 381 and can be used to prevent or reduce damage to the first element insulating film 381 or the light-emitting element core 30 during the process of forming the second insulating layer 520 (refer to FIG. 20) and / or other elements of the display device 10 (refer to FIG. 18).

[0098] The second element insulating film 382 can include, for example, silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlN), aluminum oxide (AlxOy), titanium oxide (TiOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and / or the like.

[0099] It has been illustrated in FIG. 4 that the second element insulating film 382 can completely (e.g., entirely) cover the outer surface (or outer peripheral surface) of the first element insulating film 381, but the present disclosure is not limited thereto. For example, the second element insulating film 382 can also expose a part of the outer surface (or outer peripheral surface) of the first element insulating film 381 at one end where the element electrode layer 37 of the light-emitting element ED is located.

[0100] FIG. 5 is a cross-sectional view of a light-emitting element according to one or more embodiments of the present disclosure. FIG. 6 is an enlarged view of region P in FIG. 5.

[0101] Referring to FIG. 5, the light-emitting element ED according to an embodiment is different from the light-emitting element according to one or more embodiments of FIG. 2 in that its first element insulating layer 39_1 has a superlattice structure.

[0102] Referring to FIGS. 5 and 6, the first element insulating layer 39_1 can include a compound semiconductor layer having a single crystal structure. For example, the first element insulating layer 39_1 can also have a superlattice structure in which a first layer 391 including a first compound semiconductor and a second layer 392 including a second compound semiconductor different from the first compound semiconductor are alternately and repeatedly stacked. Although it has been illustrated in FIGS. 5 and 6 that the first layer 391 and the second layer 392 are alternately stacked multiple times (e.g., three times) in the first element insulating layer 39_1, the present disclosure is not limited thereto. For example, the first element insulating layer 39_1 can also have a structure in which the first layer 391 and the second layer 392 are alternately stacked less than three times, or a structure in which the first layer 391 and the second layer 392 are alternately stacked more than three times.

[0103] The first layer 391 and the second layer 392 of the first element insulating layer 39_1 may be stacked alternately and sequentially starting from the side surface of the light-emitting element core 30 in a direction perpendicular to the side surface of the light-emitting element core 30. For example, the first layer 391 may be directly located on the side surface (or outer peripheral surface) of the light-emitting element core 30 and may surround the outer surface (or outer peripheral surface) of the light-emitting element core 30, and the second layer 392 may be located on the outer surface (or outer peripheral surface) of the first layer 391 and may surround the outer surface (or outer peripheral surface) of the first layer 391.

[0104] The first layer 391 may include a compound semiconductor having a single crystal structure. For example, the first layer 391 may be referred to as the first compound semiconductor layer 391 or the first single crystal insulating film 391. In this specification, for ease of explanation, the terms "first layer 391", "first compound semiconductor layer 391", or "first single crystal insulating film 391" may be used interchangeably with respect to the same component symbol "391".

[0105] In one or more embodiments, the first layer 391 may include a III-V semiconductor compound. The first layer 391 may include a semiconductor compound having the chemical formula AB (where A is a group III element and B is a group V element). For example, the first layer 391 may include aluminum nitride, but is not limited thereto.

[0106] In one or more embodiments, the first layer 391 may have a single crystal structure. In order for the first layer 391 to have a single crystal structure, the thickness d11 of the first layer 391 may be within a range equal to or less than the critical thickness of the material included in the first layer 391. For example, the thickness d11 of the first layer 391 may be within a range of 5 nm or less, for example, within a range of 2 nm to 3 nm. In this case, the first layer 391 may be the first single crystal insulating film 391 formed in a single crystal structure.

[0107] The second layer 392 may include a III-V semiconductor compound, but may include a material different from that of the first layer 391. The second layer 392 may include a chemical formula of AxC1-xB (where 0 ≤ x < 1, A and C are group III elements, and B is a group V element). For example, the second layer 392 may include aluminum gallium nitride (AlxGa1-xN), but is not limited thereto.

[0108] In one or more embodiments, the second layer 392 may have a single-crystalline structure. In order for the second layer 392 to have a single-crystalline structure, the thickness d12 of the second layer 392 may be within a range equal to or less than the critical thickness of the material included in the second layer 392. For example, the thickness d12 of the second layer 392 may be within a range of 5 nm or less, for example, within a range of 2 nm to 3 nm. In this case, the second layer 392 may be a second single-crystalline insulating film (second layer 392) formed to have a single-crystalline structure.

[0109] In one or more embodiments, the thickness d11 of the first layer 391 included in the first element insulating layer 39_1 and the thickness d12 of the second layer 392 may be the same as each other. However, the present disclosure is not limited thereto, and in some embodiments, the thickness d11 of the first layer 391 included in the first element insulating layer 39_1 and the thickness d12 of the second layer 392 may be different from each other.

[0110] In one or more embodiments, the first element insulating layer 39_1 may have an aluminum nitride (AlN) / aluminum gallium nitride (AlxGa1-xN) (0 ≤ x < 1) superlattice structure, in which the first layer 391 including aluminum nitride (AlN) and the second layer 392 including aluminum gallium nitride (AlxGa1-xN) are alternately stacked (e.g., multiple times). Since the first element insulating layer 39_1 has a superlattice structure, the total thickness d1 of the first element insulating layer 39_1 may be greater than the total thickness of the first element insulating layer 39_1 including a single-crystalline insulating film. Therefore, a plurality of layers having a single-crystalline structure are formed, so that surface defects of the light-emitting element core 30 can be effectively or appropriately improved, and moreover, the insulation reliability of the first element insulating layer 39_1 can be improved.

[0111] When the first element insulating layer 39_1 has a superlattice structure, each of the first layer 391 and the second layer 392 included in the first element insulating layer 39_1 may be formed by a metal organic chemical vapor deposition method (MOCVD) or atomic layer deposition (ALD). In one or more embodiments, each of the first layer 391 and the second layer 392 included in the first element insulating layer 39_1 may be formed by atomic layer deposition (ALD) performed at a low temperature. Therefore, each of the first layer 391 and the second layer 392 may include a III-V group semiconductor compound and may be formed as a layer having a single-crystalline structure.

[0112] In this embodiment, the first element insulating layer 39_1 has a superlattice structure in which a plurality of layers are alternately stacked, such that the first element insulating layer 39_1 can be formed to have a large (e.g., appropriate) thickness d1 while maintaining a single crystal structure. Accordingly, the first element insulating layer 39_1 can effectively or appropriately prevent or reduce the diffusion of impurities from the outside and / or the second element insulating layer 38 to the semiconductor layer of the light-emitting element core 30. Accordingly, the element efficiency and reliability of the light-emitting element ED can be improved.

[0113] FIG. 7 is a cross-sectional view of a light-emitting element according to one or more embodiments of the present disclosure.

[0114] Referring to FIG. 7, the light-emitting element ED according to an embodiment is different from the light-emitting element according to the embodiment of FIG. 5 in that its second element insulating layer 38_1 includes a plurality of element insulating films.

[0115] For example, the second element insulating layer 38_1 may include a first element insulating film 381 and a second element insulating film 382. The first element insulating film 381 and the second element insulating film 382 of the second element insulating layer 38_1 according to an embodiment may include the same structure and material as the first element insulating film 381 and the second element insulating film 382 of FIG. 4.

[0116] The first element insulating film 381 may surround the outer surface (or outer circumferential surface) of the second layer 392 that constitutes the outer surface (or outer circumferential surface) of the first element insulating layer 39_1. The first element insulating film 381 can protect the first semiconductor layer 31, the second semiconductor layer 32, and the light-emitting layer 33 of the light-emitting element core 30, and can prevent or reduce the risk of electrical short circuit that may occur when the light-emitting layer 33 is in direct contact with the electrode such that an electrical signal is transmitted to the light-emitting element ED through this electrode. The second element insulating film 382 can function to protect the first element insulating film 381.

[0117] FIG. 8 is a cross-sectional view of a light-emitting element according to one or more embodiments of the present disclosure.

[0118] Referring to FIG. 8, the light-emitting element ED according to an embodiment is different from the light-emitting element according to the embodiment of FIG. 7 in that its second element insulating layer 38_2 includes a first element insulating film 381 and a third element insulating film 383, and the first element insulating layer 39_1 having a superlattice structure is interposed between the first element insulating film 381 and the third element insulating film 383.

[0119] For example, the second element insulating layer 38_2 may include a first element insulating film 381 and a third element insulating film 383.

[0120] The third element insulating film 383 may surround the side surface of the light-emitting element core 30. The third element insulating film 383 may be directly located on the side surface of the light-emitting element core 30. The third element insulating film 383 may include a material having insulating properties. For example, the third element insulating film 383 may include silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum nitride (AlN), aluminum oxide (AlxOy), titanium oxide (TiOx), zirconium oxide (ZrOx), hafnium oxide (HfOx), and / or the like.

[0121] The first element insulating film 381 may be disposed on the outer surface (or outer circumferential surface) of the third element insulating film 383 and may surround the outer surface of the third element insulating film 383. The first element insulating film 381 may be separated from the third element insulating film 383.

[0122] The first element insulating layer 39_1 may be disposed between the first element insulating film 381 and the third element insulating film 383. The first element insulating layer 39_1 may be located on the outer surface of the third element insulating film 383, and the first element insulating film 381 may be located on the outer surface (or outer circumferential surface) of the first element insulating layer 39_1.

[0123] In one or more embodiments, the second element insulating layer 38_2 may further include an element insulating film located between the third element insulating film 383 and the first element insulating layer 39_1. In this case, the first element insulating layer 39_1 may be located on the outer surface (or outer circumferential surface) of the element insulating film additionally located on the third element insulating film 383.

[0124] FIG. 9 is a schematic perspective view of a light-emitting element according to one or more embodiments of the present disclosure. FIG. 10 is a schematic perspective view of a light-emitting element according to one or more embodiments of the present disclosure.

[0125] FIGS. 9 and 10 illustrate embodiments of the light-emitting element ED having various shapes. For example, the light-emitting element ED according to the embodiment of FIG. 9 may extend in one direction and may have a hexagonal column shape. The light-emitting element core 30 of the light-emitting element ED according to the embodiment of FIG. 9 may have a hexagonal column shape, and the first element insulating layer 39 and the second element insulating layer 38 may be located on a plurality of side surfaces of the light-emitting element core 30, thereby surrounding the plurality of side surfaces of the light-emitting element core 30. The light-emitting element ED according to the embodiment of FIG. 10 may extend in one direction X and may have a truncated cone shape. The light-emitting element ED according to the embodiment of FIG. 10 may have a truncated cone shape.

[0126] Hereinafter, with reference to the drawings, the manufacturing process of the light-emitting element ED according to one or more embodiments of FIG. 2 will be described in the order of its execution, but the embodiments of the present disclosure are not limited thereto.

[0127] FIGS. 11 to 17 are cross-sectional views of the steps of the manufacturing method of the light-emitting element.

[0128] Hereinafter, the first direction DR1, the second direction DR2, and the third direction DR3 are defined as shown in the drawings of the manufacturing process of the light-emitting element ED. The first direction DR1 and the second direction DR2 may be directions perpendicular (or substantially perpendicular) to each other, and the third direction DR3 may be a direction perpendicular to (or substantially perpendicular to) the plane in which the first direction DR1 and the second direction DR2 are located.

[0129] The third direction DR3 may be a direction parallel (or substantially parallel) to a direction X, and the direction X is the extending direction of the light-emitting element ED formed on the lower substrate 1000. In this specification, unless otherwise specified, "upper portion" may indicate one side in the third direction DR3 and may indicate the direction in which a plurality of semiconductor layers of the light-emitting element ED are stacked on one surface (or upper surface) of the lower substrate 1000, and "upper surface" may indicate the surface facing one side in the third direction DR3. In addition, "lower portion" may indicate the other side in the third direction DR3, and "lower surface" may indicate the surface facing the other side in the third direction DR3.

[0130] First, referring to FIG. 11, the lower substrate 1000 is prepared.

[0131] In one or more embodiments, the lower substrate 1000 may include a base substrate 1100 and a buffer material layer 1200 located on the base substrate 1100.

[0132] The base substrate 1100 may include a sapphire (AlxOy) substrate and a transparent substrate such as a glass substrate. However, the present disclosure is not limited thereto, and the base substrate 1100 may further include a conductive substrate made of gallium nitride (GaN), silicon carbide (SiC), zinc oxide (ZnO), silicon (Si), gallium phosphide (GaP), gallium arsenide (GaAs), and / or the like. In one or more embodiments, the base substrate 1100 may be a sapphire substrate (AlxOy).

[0133] A plurality of semiconductor layers may be formed on a substrate 1100. The plurality of semiconductor layers may be formed by growing a seed crystal on the substrate 1100 through an epitaxial method. The method of forming the semiconductor layer may be electron beam deposition, Physical Vapor Deposition (PVD), Chemical Vapor Deposition (CVD), Plasma Laser Deposition (PLD), dual-type thermal evaporation, sputtering, Metal Organic Chemical Vapor Deposition (MOCVD), and / or similar methods.

[0134] A buffer material layer 1200 may be formed on one surface (e.g., the upper surface) of the substrate 1100. The buffer material layer 1200 may be used to reduce the lattice constant difference between the substrate 1100 and the first semiconductor material layer 3100 (refer to FIG. 12), which will be described in more detail below. The buffer material layer 1200 may include an undoped semiconductor. The buffer material layer 1200 may include the same material as the first semiconductor material layer 3100 that will be described in more detail below, but may include a material that does not contain a first conductivity type dopant or a second conductivity type dopant, such as an n-type dopant or a p-type dopant. A single layer of the buffer material layer 1200 has been shown in FIG. 11, but the present disclosure is not limited thereto, and a plurality of buffer material layers 1200 may be further formed. Depending on the type (or kind) of the substrate 1100, the buffer material layer 1200 may not be provided.

[0135] Next, referring to FIG. 12, a first stacked structure 3000 is formed on the lower substrate 1000.

[0136] For example, a first stacked structure 3000 in which a first semiconductor material layer 3100, a light-emitting material layer 3300, a second semiconductor material layer 3200, and an electrode material layer 3700 are sequentially stacked is formed on the lower substrate 1000.

[0137] According to one or more embodiments, a plurality of layers included in the first stack structure 3000 may correspond to respective layers included in the light-emitting element core 30. For example, the first semiconductor material layer 3100, the light-emitting material layer 3300, the second semiconductor material layer 3200, and the electrode material layer 3700 of the first stack structure 3000 may correspond to the first semiconductor layer 31, the light-emitting layer 33, the second semiconductor layer 32, and the element electrode layer 37 of the light-emitting element core 30, respectively, and may include the same materials as those included in the respective layers.

[0138] Next, referring to FIG. 13, a plurality of light-emitting element cores 30 spaced apart from each other are formed by etching the first stack structure 3000.

[0139] For example, the light-emitting element cores 30 spaced apart from each other as shown in FIG. 13 may be formed by a process of etching the first stack structure 3000 in a direction perpendicular to (or substantially perpendicular to) the upper surface of the lower substrate 1000, for example, in the third direction DR3. The first stack structure 3000 may be etched by an appropriate patterning method. For example, the patterning method may be performed by forming an etching mask layer on the first stack structure 3000 and etching the first stack structure 3000 in the third direction DR3 along the etching mask layer.

[0140] For example, the process of etching the first stack structure 3000 may be a dry etching method, a wet etching method, a reactive ion etching (RIE) method, an inductively coupled plasma reactive ion etching (ICP-RIE) method, and / or a similar method. In the case of using dry etching, anisotropic etching is possible, and thus dry etching may be applicable to vertical etching. In one or more embodiments, the first stack structure 3000 may be etched using a dry etching method and a wet etching method. For example, the first stack structure 3000 is etched in the third direction DR3 by dry etching, and then etched by a wet etching method, which is an anisotropic etching method, such that the sidewalls after etching may be located in a plane perpendicular to (or substantially perpendicular to) the upper surface of the lower substrate 1000.

[0141] Due to the etchant used in the process of etching the first stacked structure 3000, defects may appear on the surfaces of the plurality of light-emitting element cores 30 formed by etching the first stacked structure 3000. For example, defects in the semiconductor material may occur on the surfaces of the semiconductor layers included in each of the plurality of light-emitting element cores 30. Defects formed on the outer surfaces of the light-emitting element cores 30 may cause leakage of electrons injected into the semiconductor layers and / or capture of holes injected into the semiconductor layers, and may hinder the recombination of electrons and holes, resulting in a decrease in the light efficiency of the light-emitting element ED. In addition, when the second element insulating layer (e.g., the second element insulating layer 38) is directly formed on the outer surface of the light-emitting element core 30 having surface defects, impurities may diffuse from the second element insulating layer to the semiconductor along the boundary between the second element insulating layer and the light-emitting element core 30, such that the element reliability and efficiency of the light-emitting element ED may decrease.

[0142] Next, referring to FIG. 14, a first insulating material layer 390 is formed on the plurality of light-emitting element cores 30.

[0143] As described above, in the process of etching the first stacked structure 3000 to form the light-emitting element cores 30, surface defects may occur on the outer surfaces of the semiconductor layers of the light-emitting element cores 30, and the first insulating layer material layer 390 having a single crystal structure can be directly formed on the side surfaces of the light-emitting element cores 30 to reduce surface defects.

[0144] The first insulating material layer 390 can be formed on the entire surface of the lower substrate 1000, which is not only formed on the outer surfaces of the light-emitting element cores 30, but also formed on the upper surface of the lower substrate 1000 exposed by the light-emitting element cores 30. The outer surfaces of the light-emitting element cores 30 can include the upper surfaces and side surfaces of the light-emitting element cores 30. The first insulating material layer 390 can correspond to (e.g., can be formed through subsequent processes later) the first element insulating layer 39 of the light-emitting element ED.

[0145] In one or more embodiments, the first insulating material layer 390 can include materials included in the first element insulating layer 39, e.g., an insulating material having a single crystal structure. In one or more embodiments, the first insulating material layer 390 can include aluminum nitride (AlN) having a single crystal structure, aluminum oxide (AlxOy) having a single crystal structure, and / or the like.

[0146] As described above, the first insulating material layer 390 needs to maintain a single crystal structure to maintain the reliability of the light-emitting element ED while improving the efficiency of the light-emitting element ED. Therefore, the first insulating material layer 390 can be formed to have a set or predetermined thickness suitable for maintaining a single crystal structure on the outer surface of the light-emitting element core 30. The thickness d1 of the first insulating material layer 390 can be in a range equal to or less than the critical thickness of the material contained in the first insulating material layer 390. For example, when the first element insulating layer 39 contains aluminum nitride (AlN) having a single crystal structure, the thickness d1 of the first element insulating layer 39 can be in a range of 5 nm or less. In this case, the first element insulating layer 39 can be formed to maintain a single crystal structure.

[0147] In one or more embodiments in which the first insulating material layer 390 contains an insulating material having a single crystal structure, the first insulating material layer 390 can be formed by atomic layer deposition (ALD), chemical vapor deposition (CVD), metalorganic chemical vapor deposition (MOCVD), and / or similar methods.

[0148] In one or more embodiments, the first insulating material layer 390 can correspond to the first element insulating layer 39_1 according to the embodiment of FIG. 5. In this case, the first insulating material layer 390 can be formed to have a superlattice structure. When the first insulating material layer 390 has a superlattice structure, the first insulating material layer 390 can be formed such that a plurality of layers containing a compound semiconductor having a single crystal structure are alternately stacked therein. In this case, each of the plurality of layers can be formed to have a thickness equal to or less than the critical thickness of the material contained in the plurality of layers.

[0149] In one or more embodiments in which the first insulating material layer 390 has a superlattice structure, the plurality of layers (e.g., a plurality of single crystal insulating films) of the first insulating material layer 390 can be formed by performing atomic layer deposition (ALD) at a low temperature.

[0150] Next, referring to FIG. 15, a second insulating material layer 380 is formed on the first insulating material layer 390. The second insulating material layer 380 can correspond to (e.g., can be formed later through subsequent processes) the second element insulating layer 38. Therefore, the second insulating material layer 380 can contain the material contained in the second element insulating layer 38. For example, the second insulating material layer 380 can be formed by atomic layer deposition (ALD) and / or chemical vapor deposition (CVD).

[0151] Next, referring to FIG. 16, the first element insulating layer 39 and the second element insulating layer 38 surrounding the side surface of the light-emitting element core 30 are formed by partially removing the first insulating material layer 390 and the second insulating material layer 380.

[0152] The process of forming the first element insulating layer 39 and the second element insulating layer 38 may include an etching process of partially removing the first insulating material layer 390 and the second insulating material layer 380, so that one end surface of the light-emitting element core 30, for example, the upper surface of the element electrode layer 37, is respectively exposed. The process of partially removing the first insulating material layer 390 and the second insulating material layer 380 may be performed through a process such as dry etching such as anisotropic etching and / or etch-back.

[0153] Next, referring to FIG. 17, a plurality of light-emitting elements ED are separated from the lower substrate 1000. The process of separating a plurality of light-emitting elements ED from the lower substrate 1000 is not particularly limited. For example, the process of separating a plurality of light-emitting elements ED may be performed through a physical separation method, a chemical separation method, and / or a similar method.

[0154] FIG. 18 is a plan view of a display device according to one or more embodiments of the present disclosure.

[0155] Referring to FIG. 18, the display device 10 displays dynamic images and / or static images. The display device 10 may represent all electronic devices suitable for providing a display screen. For example, a television, a notebook computer, a monitor, a billboard, the Internet of Things (IoT), a mobile phone, a smartphone, a tablet personal computer (PCs), an electronic watch, a smart watch, a watch phone, a head-mounted display, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMPs), a navigation device, a game machine, a digital camera, a video camera, and the like, which can provide a display screen and may be included in the display device 10.

[0156] The display device 10 includes a display panel that provides a display screen. Examples of the display panel may include an inorganic light-emitting diode display panel, an organic light-emitting display panel, a quantum dot light-emitting display panel, a plasma display panel, a field emission display panel, and the like. Hereinafter, a case where the above-described light-emitting element ED, such as an inorganic light-emitting diode display panel, is used as an example of the display panel will be described by way of example, but the present disclosure is not limited thereto, and the same technical spirit can be applied to other display panels as appropriate.

[0157] Hereinafter, the fourth direction DR4, the fifth direction DR5, and the sixth direction DR6 are defined to be the same as those shown in the drawings used to illustrate one or more embodiments of the display device 10. The fourth direction DR4 and the fifth direction DR5 may be directions perpendicular to each other in a plane (e.g., substantially perpendicular). The sixth direction DR6 may be a direction perpendicular to (e.g., substantially perpendicular to) the plane in which the fourth direction DR4 and the fifth direction DR5 are located. The sixth direction DR6 is perpendicular to (e.g., substantially perpendicular to) each of the fourth direction DR4 and the fifth direction DR5. In describing one or more embodiments of the display device 10, the sixth direction DR6 represents the thickness direction of the display device 10.

[0158] In a plan view, the display device 10 may have a rectangular shape including a long side and a short side and having a length in the fourth direction DR4 longer than a length in the fifth direction DR5. The corners where the long side and the short side of the display device 10 intersect in the plan view may be right angles, but are not limited thereto, and may have a rounded shape. The shape of the display device 10 in the plan view is not limited to the above shape, and may be other suitable shapes such as a square, a quadrilateral with rounded corners (vertices), a polygon, and / or a circle.

[0159] The display surface of the display device 10 may be provided on one side of the sixth direction DR6 which is the thickness direction. In the embodiments for explaining the display device 10, unless otherwise specified, "upper portion" may indicate one side in the sixth direction DR6 and may indicate the display direction, and "upper surface" indicates the surface facing that side in the sixth direction DR6. In addition, "lower portion" may indicate the other side of the sixth direction DR6 and may indicate the direction opposite to the display direction, and "lower surface" may indicate the surface facing the other side of the sixth direction DR6. In addition, "left", "right", "upper", and "lower" indicate the directions when the display device 10 is viewed from above. For example, "right side" indicates one side in the fourth direction DR4, "left side" indicates the other side in the fourth direction DR4, "upper side" indicates one side in the fifth direction DR5, and "lower side" indicates the other side in the fifth direction DR5.

[0160] The display device 10 may include a display area DPA and a non-display area NDA. The display area DPA is an area where a screen (e.g., an image) can be displayed, and the non-display area NDA is an area where a screen (e.g., an image) is not displayed.

[0161] The shape of the display area DPA may follow the shape of the display device 10. For example, in a plan view, the shape of the display area DPA may have a rectangular shape similar to the overall shape of the display device 10. The display area DPA may substantially occupy the center of the display device 10.

[0162] The display area DPA may include a plurality of pixels PX. The plurality of pixels PX may be arranged in a matrix direction (e.g., the matrix direction). In a plan view, the shape of each pixel PX may be rectangular or square. However, the present disclosure is not limited thereto, and the shape of each pixel PX may be a rhombus with sides inclined with respect to one direction. Each pixel PXL may be alternately arranged with each other in a stripe pattern or a PenTile® / PENTILE® pattern (PENTILE® is a registered trademark of Samsung Display Co., Ltd. in Korea).

[0163] The non-display area NDA can be around the display area DPA. The non-display area NDA can completely or partially surround the display area DPA. In one or more embodiments, the display area DPA can have a rectangular shape, and the non-display area NDA can be adjacent to the four sides of the display area DPA. The non-display area NDA can form the border of the display device 10. The wiring, circuit driver, and / or the pad portion where an external device is installed included in the display device 10 can be located in the non-display area NDA.

[0164] FIG. 19 is a plan layout diagram of a pixel of a display device according to one or more embodiments of the present disclosure. FIG. 20 is a cross-sectional view taken along line I-I' of FIG. 19 according to one or more embodiments of the present disclosure.

[0165] Referring to FIG. 19, each pixel PX of the display device 10 can include an emission area EMA and a non-emission area. The emission area EMA can be defined as the area where the light emitted from the light-emitting element ED is emitted, and the non-emission area can be defined as the area where the light emitted from the light-emitting element ED does not reach and thus no light is emitted therein.

[0166] The emission area EMA can include the area where the light-emitting element ED is disposed and the adjacent area thereto. In addition, the emission area can further include the area where the light emitted from the light-emitting element ED is reflected and / or refracted by other components and then continuously emitted.

[0167] Each pixel PX can further include a sub-area SA in the non-emission area. The light-emitting element ED may not be located in the sub-area SA. The sub-area SA can be disposed on the upper side of the emission area EMA in a plan view within one pixel PX. The sub-area SA can be disposed between the emission areas EMA of pixels PX arranged adjacent (e.g., adjacent) to each other along the fifth direction DR5. The sub-area SA can include the area where the electrode layer 200 and the contact electrode 700 are electrically connected (e.g., electrically coupled) to each other through the contacts CT1 and CT2.

[0168] The sub-area SA can include a separation part ROP. The separation part ROP of the sub-area SA can be the area where the first electrode 210 and the second electrode 220 in the electrode layer 200 included in each pixel PX adjacent to each other along the fifth direction DR5 are separated from each other.

[0169] Referring to FIGS. 19 and 20, the display device 10 can include a substrate SUB, a circuit element layer on the substrate SUB, and a light-emitting element layer on the circuit element layer.

[0170] The substrate SUB can be an insulating substrate. The substrate SUB can be made of an insulating material such as glass, quartz, and / or a polymer resin. The substrate SUB can be a rigid substrate, but can also be a flexible substrate capable of being bent, folded, and / or rolled.

[0171] The circuit element layer can be located on the substrate SUB. The circuit element layer can include a lower metal layer 110, a semiconductor layer 120, a first conductive layer 130, a second conductive layer 140, a third conductive layer 150, and a plurality of insulating films.

[0172] The lower metal layer 110 is located on the substrate SUB. The lower metal layer 110 can include a photoresistive pattern BML. The photoresistive pattern BML can be under the transistor TR to cover at least the channel region of the active layer ACT of the transistor TR. However, the present disclosure is not limited thereto, and the photoresistive pattern BML may not be provided.

[0173] The lower metal layer 110 can include a material capable of blocking or reducing light. For example, the lower metal layer 110 can be formed of an opaque metal material capable of blocking or reducing the transmission of light.

[0174] A buffer layer 161 can be provided on the lower metal layer 110. The buffer layer 161 can cover the entire surface of the substrate SUB where the lower metal layer 110 is located. The buffer layer 161 can function to protect the plurality of transistors to prevent moisture from penetrating into the substrate SUB vulnerable to moisture penetration.

[0175] The semiconductor layer 120 is located on the buffer layer 161. The semiconductor layer 120 can include the active layer ACT of the transistor TR. As described above, the active layer ACT of the transistor TR can overlap with the photoresistive pattern BML of the lower metal layer 110.

[0176] The semiconductor layer 120 can include polysilicon, single crystal silicon, an oxide semiconductor, and / or the like. In one or more embodiments, when the semiconductor layer 120 includes polysilicon, the polysilicon can be formed by crystallizing amorphous silicon. When the semiconductor layer 120 includes polysilicon, the active layer ACT of the transistor TR can include a plurality of doped regions doped with impurities and a channel region located between the plurality of doped regions. In one or more embodiments, the semiconductor layer 120 can include an oxide semiconductor. The oxide semiconductor can be, for example, indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), indium zinc tin oxide (IZTO), indium gallium zinc oxide (IGZO), indium gallium tin oxide (IGTO), indium gallium zinc tin oxide (IGZTO), and / or the like.

[0177] The gate insulating film 162 may be located on the semiconductor layer 120. The gate insulating film 162 may be used as the gate insulating film of the transistor. The gate insulating film 162 may be formed as multiple layers, including multiple layers of at least one inorganic material such as silicon oxide (SiOx), silicon nitride (SiNx), and / or silicon oxynitride (SiOxNy) stacked alternately.

[0178] The first conductive layer 130 may be located on the gate insulating film 162. The first conductive layer 130 may include the gate electrode GE of the transistor TR. The gate electrode GE may overlap with the channel region of the active layer ACT in the sixth direction DR6, and the sixth direction DR6 is the thickness direction of the substrate SUB.

[0179] The first interlayer insulating film 163 may be located on the first conductive layer 130. The first interlayer insulating film 163 may cover the gate electrode GE. The first interlayer insulating film 163 may be used as an insulating film between the first conductive layer 130 and other layers on the first conductive layer 130, and protect the first conductive layer 130.

[0180] The second conductive layer 140 may be located on the first interlayer insulating film 163. The second conductive layer 140 may include the drain electrode SD1 of the transistor TR and the source electrode SD2 of the transistor TR.

[0181] The drain electrode SD1 and the source electrode SD2 of the transistor TR may be electrically connected (e.g., electrically coupled) to both end regions (e.g., both ends) of the active layer ACT of the transistor TR through contact holes passing through the first interlayer insulating layer 163 and the gate insulating film 162, respectively. In addition, the source electrode SD2 of the transistor TR may be electrically connected to the photoresist blocking pattern BML of the lower metal layer 110 through another contact hole passing through the first interlayer insulating film 163, the gate insulating film 162, and the buffer layer 161.

[0182] The second interlayer insulating film 164 may be on the second conductive layer 140. The second interlayer insulating film 164 may cover the drain electrode SD1 of the transistor TR and the source electrode SD2 of the transistor TR. The second interlayer insulating film 164 may be used as an insulating film between the second conductive layer 140 and other layers on the second conductive layer 140, and protect the second conductive layer 140.

[0183] The third conductive layer 150 may be provided on the second interlayer insulating film 164. The third conductive layer 150 may include the first voltage line VL1, the second voltage line VL2, and the conductive pattern CDP.

[0184] The first voltage line VL1 may overlap at least a portion of the drain electrode SD1 of the transistor TR in the thickness direction of the substrate SUB. The high-potential voltage (or first source voltage) supplied to the transistor TR may be applied to the first voltage line VL1.

[0185] The second voltage line VL2 may be electrically connected (e.g., electrically coupled) to the second electrode 220 through a second electrode contact hole CTS passing through a via layer 166 and a passivation layer 165, which will be described in more detail below. A low-potential voltage (or second source voltage) lower than the high-potential voltage supplied to the first voltage line VL1 may be applied to the second voltage line VL2. For example, the high-potential voltage (or first source electrode voltage) supplied to the transistor TR may be applied to the first voltage line VL1, and a low-potential voltage (or second source voltage) lower than the high-potential voltage applied to the first voltage line VL1 may be applied to the second voltage line VL2.

[0186] The conductive pattern CDP may be electrically connected (e.g., electrically coupled) to the source electrode SD2 of the transistor TR. The conductive pattern CDP may be electrically connected to the source electrode SD2 of the transistor TR through a contact hole passing through the second interlayer insulating film 164. In addition, the conductive pattern CDP may be electrically connected to the first electrode 210 through a contact hole CTD passing through a via layer 166 and a passivation layer 165, which will be described in more detail below. The transistor TR may transmit the first source voltage applied from the first voltage line VL1 to the first electrode 210 through the conductive pattern CDP.

[0187] The passivation layer 165 may be located on the third conductive layer 150. The passivation layer 165 may cover the third conductive layer 150. The passivation layer 165 may be used to protect the third conductive layer 150.

[0188] Each of the above buffer layer 161, gate insulating film 162, first interlayer insulating film 163, second interlayer insulating film 164, and passivation layer 165 may be formed as a plurality of inorganic layers stacked alternately. For example, each of the above buffer layer 161, gate insulating film 162, first interlayer insulating film 163, second interlayer insulating film 164, and passivation layer 165 may be formed as a bilayer of inorganic layer stacks including at least one of silicon oxide (SiOx), silicon nitride (SiNx), or silicon oxynitride (SiOxNy), or a multilayer in which these layers are stacked alternately. However, the present disclosure is not limited thereto, and each of the above buffer layer 161, gate insulating film 162, first interlayer insulating film 163, second interlayer insulating film 164, and passivation layer 165 may also be formed as a single inorganic layer including the above insulating materials.

[0189] The via layer 166 may be located on the passivation layer 165. The via layer 166 may include an organic insulating material, for example, an organic material such as polyimide (PI). The via layer 166 may be used for planarizing (or substantially planarizing) the surface. Thus, the upper surface (or surface) of the via layer 166 on which the light-emitting element layer to be described in more detail herein will be disposed may be a substantially planar surface, regardless of the shape or presence or absence of the pattern below the via layer 166.

[0190] The light-emitting element layer may be located on the circuit element layer. The light-emitting element layer may be located on the via layer 166. The light-emitting element layer may include a first barrier wall 400, an electrode layer 200, a first insulating layer 510, a second barrier wall 600, a plurality of light-emitting elements ED, and a contact electrode 700.

[0191] The first barrier wall 400 may be located on the via layer 166 in the emission region EMA. The first barrier wall 400 may be directly located on one surface of the via layer 166. The first barrier wall 400 may have a structure in which at least a part thereof protrudes upward (e.g., toward one side in the sixth direction DR6) relative to one surface of the via layer 166. The protruding portion of the first barrier wall 400 may have an inclined side surface. The first barrier wall 400 may have an inclined surface and may be used to change the traveling direction of the light emitted from the light-emitting element ED and traveling toward the side surface of the first barrier wall 400 to an upward direction (e.g., the display direction).

[0192] The first barrier wall 400 may include a first sub-barrier wall 410 and a second sub-barrier wall 420 that are separated from each other. The first sub-barrier wall 410 and the second sub-barrier wall 420 that are separated from each other may provide a space for accommodating the light-emitting element ED, and may function as an auxiliary reflection partition wall to change the traveling direction of the light emitted from the light-emitting element ED to the display direction.

[0193] In the drawings, the side surface of the first barrier wall 400 is shown as a linear inclined shape, but the present disclosure is not limited thereto. For example, the side surface (or outer surface) of the first barrier wall 400 may have a curved semi-circular or semi-elliptical shape. In one or more embodiments, the first barrier wall 400 may include an organic insulating material such as polyimide (PI), but is not limited thereto.

[0194] The electrode layer 200 may have a shape extending in one direction and may intersect the emission region EMA and the sub-region SA. The electrode layer 200 may transmit the electrical signal applied from the circuit element layer to the light-emitting element ED to cause the light-emitting element ED to emit light. In addition, the electrode layer 200 may be used to generate an electric field used in the process of arranging a plurality of light-emitting elements ED.

[0195] The electrode layer 200 may be located on the first retaining wall 400 and the via layer 166 exposed by the first retaining wall 400. The electrode layer 200 may be located on the first retaining wall 400 in the emission area EMA, and may be located on the via layer 166 exposed by the first retaining wall 400 in the non-emission area.

[0196] The electrode layer 200 may include a first electrode 210 and a second electrode 220. The first electrode 210 and the second electrode 220 may be separated from each other.

[0197] In a plan view, the first electrode 210 may be located on the left side of each pixel PX. In the plan view, the first electrode 210 may have a shape extending in the fifth direction DR5. The first electrode 210 may pass through the emission area EMA and the sub-area SA. In the plan view, the first electrode 210 may extend in the fifth direction DR5, but may be separated from the first electrode 210 of the pixel PX adjacent (e.g., neighboring) in the fifth direction DR5 in the separation part ROP of the sub-area SA.

[0198] The second electrode 220 may be separated from the first electrode 210 in the fourth direction DR4. In the plan view, the second electrode 220 may be located on the right side of each pixel PX. In the plan view, the second electrode 220 may have a shape extending in the fifth direction DR5. The second electrode 220 may pass through the emission area EMA and the sub-area SA. In the plan view, the second electrode 220 may extend in the fifth direction DR5, but may be separated from the second electrode 220 of the pixel PX adjacent (e.g., neighboring) in the fifth direction DR5 in the separation part ROP of the sub-area SA.

[0199] For example, in the emission area EMA, the first electrode 210 may be located on the first sub-retaining wall 410, and the second electrode 220 may be located on the second sub-retaining wall 420. The first electrode 210 may extend outward from the first sub-retaining wall 410 to be located on the via layer 166 exposed (e.g., uncovered) by the first sub-retaining wall 410. Similarly, the second electrode 220 may extend outward from the second sub-retaining wall 420 to be located on the via layer 166 exposed (e.g., uncovered) by the second sub-retaining wall 420. The first electrode 210 and the second electrode 220 may be separated from each other and face each other in the separation area between the first sub-retaining wall 410 and the second sub-retaining wall 420. The via layer 166 may be exposed in the area where the first electrode 210 and the second electrode 220 are separated from each other and face each other.

[0200] The first electrode 210 may be separated from the first electrode 210 of another pixel PX adjacent in the fifth direction DR5 in the sub-region SA, and a separation portion ROP is interposed therebetween. Similarly, the second electrode 220 may be separated from the second electrode 220 of another pixel PX adjacent in the fifth direction DR5 in the sub-region SA, and a separation portion ROP is interposed therebetween. Accordingly, the first electrode 210 and the second electrode 220 may expose the via layer 166 in the separation portion ROP of the sub-region SA.

[0201] The first electrode 210 may be electrically connected (e.g., electrically coupled) to the conductive pattern CDP of the circuit element layer through a first electrode contact hole CTD passing through the via layer 166 and the passivation layer 165. For example, the first electrode 210 may contact the upper surface of the conductive pattern CDP exposed by the first electrode contact hole CTD. The first source voltage applied from the first voltage line VL1 may be transmitted to the first electrode 210 through the conductive pattern CDP.

[0202] The second electrode 220 may be electrically connected (e.g., electrically coupled) to the second voltage line VL2 of the circuit element layer through a second electrode contact hole CTS passing through the via layer 166 and the passivation layer 165. For example, the second electrode 220 may contact the upper surface of the second voltage line VL2 exposed by the second electrode contact hole CTS. The second source voltage applied from the second voltage line VL2 may be transmitted to the second electrode 220.

[0203] The electrode layer 200 may include a conductive material having a high reflectivity. For example, the electrode layer 200 may include a metal such as silver (Ag), copper (Cu), and / or aluminum (Al), or may contain an alloy including aluminum (Al), nickel (Ni), lanthanum (La), and / or the like as a material having a high reflectivity. The electrode layer 200 may reflect the light emitted from the light-emitting element ED and traveling in the upward direction of each pixel PX toward the side surface of the first barrier wall 400.

[0204] However, the present disclosure is not limited thereto, and the electrode layer 200 may further include a transparent conductive material. For example, the electrode layer 200 may include a material such as indium tin oxide (ITO), indium zinc oxide (IZO), and / or indium gallium oxide (IGO). In some embodiments, the electrode layer 200 may have a structure in which one or more layers made of a transparent conductive material and one or more layers made of a metal having a high reflectivity are stacked, or may be formed as one layer including a transparent conductive material and a metal having a high reflectivity. For example, the electrode layer 200 may have a stacked structure such as ITO / Ag / ITO, ITO / Ag / IZO, or ITO / Ag / ITZO / IZO.

[0205] The first insulating layer 510 may be located on the via layer 166 on which the electrode layer 200 is formed. The first insulating layer 510 may protect the electrode layer 200 and insulate the first electrode 210 and the second electrode 220 from each other.

[0206] The first insulating layer 510 may include an inorganic insulating material. For example, the first insulating layer 510 may include at least one of inorganic insulating materials such as silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiOxNy), aluminum oxide (AlxOy), and / or aluminum nitride (AlN). The first insulating layer 510 made of an inorganic insulating material may have a surface shape that reflects (e.g., corresponds to) the pattern shape of the electrode layer 200 located thereunder. For example, the first insulating layer 510 may have a stepped structure according to the shape of the electrode layer 200 under the first insulating layer 510. For example, the first insulating layer 510 may include a stepped structure, a part of the upper surface of which is recessed in a region where the first electrode 210 and the second electrode 220 are separated from each other and face each other. Accordingly, the height of the upper surface of the first insulating layer 510 located on the upper parts of the first electrode 210 and the second electrode 220 (e.g., the distance from the upper surface of the via layer 166 to the upper surface of the first insulating layer 510) may be greater than the height of the upper surface of the first insulating layer 510 located on the upper part of the via layer 166 where the first electrode 210 and the second electrode 220 are not provided thereon. In the present specification, the relative comparison of the upper surface height of any layer may be made through the height measured from a flat reference surface (e.g., the upper surface of the via layer 166) that does not have a lower stepped structure.

[0207] The first insulating layer 510 may include a first contact portion CT1 that exposes a part of the upper surface of the first electrode 210 in the sub-region SA, and a second contact portion CT2 that exposes a part of the upper surface of the second electrode 220 in the sub-region SA. The first electrode 210 may be electrically connected (e.g., electrically coupled) to a first contact electrode 710, which will be described in more detail below, through the first contact portion CT1 passing through the first insulating layer 510 in the sub-region SA, and the second electrode 220 may be electrically connected to a second contact electrode 720, which will be described in more detail below, through the second contact portion CT2 passing through the first insulating layer 510 in the sub-region SA.

[0208] The second barrier 600 may be located on the first insulating layer 510. The second barrier 600 may be formed as a lattice pattern by including portions extending in the fourth direction DR4 and the fifth direction DR5 in the plan view.

[0209] The second barrier wall 600 may extend across the boundaries between the respective pixels PX to divide adjacent pixels PX, and may divide the emission area EMA and the sub-areas SA. In addition, the second barrier wall 600 may be formed to have a height higher than that of the first barrier wall 400 to prevent or reduce the mixing of the inks of the plurality of light-emitting elements ED dispersed in adjacent pixels PX, and may assist in jetting the ink into the emission area EMA during the inkjet printing process during the manufacture of the display device 10 to align the light-emitting elements ED.

[0210] A plurality of light-emitting elements ED may be disposed in the emission area EMA. The plurality of light-emitting elements ED may not be disposed in the sub-areas SA.

[0211] The plurality of light-emitting elements ED may be located on the first insulating layer 510 between the first sub-barrier wall 410 and the second sub-barrier wall 420. The plurality of light-emitting elements ED may be located between the first electrode 210 and the second electrode 220 on the first insulating layer 510.

[0212] The light-emitting element ED may have a shape extending in one direction, and may be arranged such that its two ends are respectively placed on the first electrode 210 and the second electrode 220. For example, the plurality of light-emitting elements ED may be arranged such that one end (e.g., the first end) thereof is placed on the first electrode 210 and the other end (e.g., the second end) thereof is placed on the second electrode 220.

[0213] The length of each light-emitting element ED (i.e., in FIGS. 19 and 20, the length of the light-emitting element ED in the fourth direction DR4) may be less than the shortest interval between the first sub-barrier wall 410 and the second sub-barrier wall 420 separated from each other in the fourth direction DR4. In addition, the length of each light-emitting element ED may be greater than the shortest distance between the first electrode 210 and the second electrode 220 separated from each other in the fourth direction DR4. Since the interval between the first sub-barrier wall 410 and the second sub-barrier wall 420 in the fourth direction DR4 is greater than the length of each light-emitting element ED, and the interval between the first electrode 210 and the second electrode 220 in the fourth direction DR4 is less than the length of each light-emitting element ED, the plurality of light-emitting elements ED may be located in the area between the first sub-barrier wall 410 and the second sub-barrier wall 420 such that their two ends are respectively located on the first electrode 210 and the second electrode 220.

[0214] The plurality of light-emitting elements ED may be separated from each other along the fifth direction DR5 in which the first electrode 210 and the second electrode 220 extend, and may be arranged substantially parallel to each other.

[0215] The second insulating layer 520 may be disposed on the light-emitting element ED. The second insulating layer 520 may be partially located on the light-emitting element ED to expose both ends of the light-emitting element ED. The second insulating layer 520 may partially surround the outer surface of the light-emitting element ED and may be positioned so as not to cover one end (e.g., the first end) and the other end (e.g., the second end) of the light-emitting element ED.

[0216] In a plan view, the portion of the second insulating layer 520 on the light-emitting element ED may extend in the fifth direction DR5 on the first insulating layer 510 to form a linear or island-shaped pattern in each pixel PX. The second insulating layer 520 may protect the light-emitting element ED and fix (e.g., affix) the light-emitting element ED during the manufacturing process of the display device 10. In addition, the second insulating layer 520 may fill the space between the light-emitting element ED and the first insulating layer 510 below the light-emitting element ED.

[0217] The contact electrode 700 may be located on the second insulating layer 520. The contact electrode 700 may be located on the first insulating layer 510 on which the light-emitting element ED is located. The contact electrode 700 may include a first contact electrode 710 and a second contact electrode 720 separated from each other.

[0218] The first contact electrode 710 may be located on the first electrode 210 in the emission region EMA. The first contact electrode 710 may have a shape extending in the fifth direction DR5 on the first electrode 210. The first contact electrode 710 may contact each of the first electrode 210 and one end (e.g., the first end) of the light-emitting element.

[0219] The first contact electrode 710 may contact the first electrode 210 exposed by the first contact portion CT1 penetrating through the first insulating layer 510 in the sub-region SA, and may contact one end (e.g., the first end) of the light-emitting element ED in the emission region EMA. For example, the first contact electrode 710 may be used to electrically connect (e.g., electrically couple) the first electrode 210 and one end (e.g., the first end) of the light-emitting element ED to each other.

[0220] The second contact electrode 720 may be located on the second electrode 220 in the emission region EMA. The second contact electrode 720 may have a shape extending in the fifth direction DR5 on the second electrode 220. The second contact electrode 720 may contact each of the second electrode 220 and the other end (e.g., the second end) of the light-emitting element ED.

[0221] The second contact electrode 720 can contact the second electrode 220 exposed by the second contact portion CT2 penetrating through the first insulating layer 510 in the sub-region SA, and can contact the other end (e.g., the second end) of the light-emitting element ED in the emission region EMA. For example, the second contact electrode 720 can be used to electrically connect (e.g., electrically couple) the second electrode 220 and the other end (e.g., the second end) of the light-emitting element ED to each other.

[0222] The first contact electrode 710 and the second contact electrode 720 can be separated from each other on the light-emitting element ED. For example, the first contact electrode 710 and the second contact electrode 720 can be separated from each other, and the second insulating layer 520 is interposed therebetween. The first contact electrode 710 and the second contact electrode 720 can be electrically insulated from each other.

[0223] The first contact electrode 710 and the second contact electrode 720 can include the same material. For example, each of the first contact electrode 710 and the second contact electrode 720 can include a conductive material. For example, the first contact electrode 710 and the second contact electrode 720 can include indium tin oxide (ITO), indium zinc oxide (IZO), indium gallium oxide (IGO), aluminum (Al), and / or the like. As an example, each of the first contact electrode 710 and the second contact electrode 720 can include a transparent conductive material. Since each of the first contact electrode 710 and the second contact electrode 720 includes a transparent conductive material, the light emitted from the light-emitting element ED can pass through the first contact electrode 710 and the second contact electrode 720, and travel toward the first electrode 210 and the second electrode 220, and can be reflected from the surfaces of the first electrode 210 and the second electrode 220.

[0224] The first contact electrode 710 and the second contact electrode 720 can include the same material and can be formed as the same layer. The first contact electrode 710 and the second contact electrode 720 can be formed simultaneously through the same process.

[0225] The third insulating layer 530 can be disposed on the contact electrode 700. The third insulating layer 530 can cover the light-emitting element layer therebelow. The third insulating layer 530 can cover the first barrier wall 400, the electrode layer 200, the first insulating layer 510, the plurality of light-emitting elements ED, and the contact electrode 700. The third insulating layer 530 can be located on the second barrier wall 600 to cover the second barrier wall 600.

[0226] The third insulating layer 530 can be used to protect the light-emitting element layer therebelow from foreign substances such as moisture, oxygen, and / or dust particles. The third insulating layer 530 can be used to protect the first barrier wall 400, the electrode layer 200, the first insulating layer 510, the plurality of light-emitting elements ED, and the contact electrode 700.

[0227] FIG. 21 is an enlarged cross-sectional view of one or more embodiments of the Q region of FIG. 20.

[0228] Referring to FIG. 21, the light-emitting element ED can be placed such that the extending direction of the light-emitting element ED is parallel to (or substantially parallel to) a surface of the substrate SUB. The plurality of semiconductor layers included in the light-emitting element ED can be sequentially stacked along a direction parallel to (or substantially parallel to) the upper surface of the substrate SUB (or the upper surface of the via layer 166). For example, the first semiconductor layer 31, the light-emitting layer 33, and the second semiconductor layer 32 of the light-emitting element ED can be sequentially stacked to be parallel to (or substantially parallel to) the upper surface of the substrate SUB.

[0229] For example, in the light-emitting element ED, in a cross-section taken from both ends of the light-emitting element ED, the first semiconductor layer 31, the light-emitting layer 33, the second semiconductor layer 32, and the element electrode layer 37 can be sequentially formed in a direction horizontal to the upper surface of the substrate SUB.

[0230] The light-emitting element ED can be arranged such that one end thereof (e.g., the first end) is placed on the first electrode 210 and the other end thereof (e.g., the second end) is placed on the second electrode 220. However, the present disclosure is not limited thereto, and the light-emitting element ED can also be arranged such that one end thereof is placed on the second electrode 220 and the other end thereof is placed on the first electrode 210.

[0231] The second insulating layer 520 can be located on the light-emitting element ED. The second insulating layer 520 can surround (e.g., at least partially cover) the outer surface of the light-emitting element ED. The second insulating layer 520 can be on the second element insulating layer 38 of the light-emitting element ED and can surround (e.g., at least partially cover) the outer surface of the second element insulating layer 38 of the light-emitting element ED facing the display direction (the sixth direction DR6).

[0232] In the region where the light-emitting element ED is located, the second insulating layer 520 can surround (e.g., at least partially cover) the outer surface of the light-emitting element ED (e.g., the second element insulating layer 38 of the light-emitting element ED).

[0233] The first contact electrode 710 can be in contact with one end (e.g., the first end) of the light-emitting element ED exposed by the second insulating layer 520. For example, the first contact electrode 710 can surround (e.g., at least partially cover) one end face of the light-emitting element ED exposed by the second insulating layer 520. The first contact electrode 710 can be in contact with the second element insulating layer 38 and the element electrode layer 37 of the light-emitting element ED.

[0234] The second contact electrode 720 can be in contact with the other end (e.g., the second end) of the light-emitting element ED exposed by the second insulating layer 520. For example, the second contact electrode 720 can surround (e.g., at least partially cover) the other end face of the light-emitting element ED exposed by the second insulating layer 520. The second contact electrode 720 can be in contact with the second element insulating layer 38 and the first semiconductor layer 31 of the light-emitting element ED.

[0235] The first contact electrode 710 and the second contact electrode 720 can be separated from each other, and the second insulating layer 520 is interposed therebetween. The first contact electrode 710 and the second contact electrode 720 can expose at least a part of the upper surface of the second insulating layer 520.

[0236] The first contact electrode 710 and the second contact electrode 720 can be formed on the same layer and can include the same material. For example, the first contact electrode 710 and the second contact electrode 720 can be formed simultaneously through a mask process. Therefore, no additional mask process for forming the first contact electrode 710 and the second contact electrode 720 is required, and thus the efficiency of the manufacturing process of the display device 10 can be improved.

[0237] FIG. 22 is an enlarged cross-sectional view of one or more embodiments of the Q region of FIG. 20.

[0238] Referring to FIG. 22, the display device 10 according to an embodiment is different from the display device 10 according to the embodiment described above with reference to FIG. 21 in that the contact electrode 700_1 includes a first contact electrode 710 and a second contact electrode 720_1 formed on different layers, and further includes a fourth insulating layer 540.

[0239] For example, the contact electrode 700_1 can include a first contact electrode 710 and a second contact electrode 720_1 formed on different layers.

[0240] The first contact electrode 710 may be located on one end (e.g., the first end) of the first electrode 210 and the light-emitting element ED. The first contact electrode 710 may extend from one end of the light-emitting element ED toward the second insulating layer 520 to be located on a sidewall and the upper surface of the second insulating layer 520. The first contact electrode 710 may be located on the upper surface of the second insulating layer 520, but at least a part of the upper surface of the second insulating layer 520 may be exposed.

[0241] The fourth insulating layer 540 may be disposed on the first contact electrode 710. The fourth insulating layer 540 may completely (e.g., entirely) cover the first contact electrode 710. The fourth insulating layer 540 may completely (e.g., entirely) cover a sidewall and the upper surface of the second insulating layer 520, but may not be located on the other sidewall of the second insulating layer 520. One end of the fourth insulating layer 540 may be aligned with the other sidewall of the second insulating layer 520.

[0242] The second contact electrode 720_1 may be located on the second electrode 220 and the other end (e.g., the second end) of the light-emitting element ED. The second contact electrode 720_1 may extend from the other end of the light-emitting element ED toward the second insulating layer 520 to be located on the other sidewall and the upper surface of the fourth insulating layer 540.

[0243] The third insulating layer 530 may be located on the fourth insulating layer 540 and the second contact electrode 720_1. The third insulating layer 530 may be located on the fourth insulating layer 540 and the second contact electrode 720_1 to cover the fourth insulating layer 540 and the second contact electrode 720_1.

[0244] In an embodiment, the following process (e.g., action or step) is added in the manufacturing process of the display device 10, that is, a process of forming the first contact electrode 710 and the second contact electrode 720_1 on different layers and inserting the fourth insulating layer 540 between the first contact electrode 710 and the second contact electrode 720_1. This may reduce the manufacturing process efficiency of the display device 10, but may improve the reliability of the display device 10. For example, by forming the first contact electrode 710 and the second contact electrode 720_1 on different layers and further providing the fourth insulating layer 540 between the first contact electrode 710 and the second contact electrode 720_1, the risk of short circuit between the first contact electrode 710 and the second contact electrode 720_1 in the manufacturing process of the display device 10 can be minimized or reduced.

[0245] FIG. 23 is an enlarged cross-sectional view of one or more embodiments of the Q region of FIG. 20.

[0246] Referring to FIG. 23, the display device 10 according to the embodiment is different from the display device 10 according to the embodiment described with reference to FIG. 21 above in that it includes a light-emitting element according to the embodiment of FIG. 5.

[0247] For example, the light-emitting element according to the embodiment of FIG. 5 may include a first element insulating layer 39_1 having a superlattice structure, and in the light-emitting element ED on the first electrode 210 and the second electrode 220, the first element insulating layer 39_1 in which a plurality of first layers 391 and second layers 392 are alternately and repeatedly stacked may be interposed between the light-emitting element core 30 and the second element insulating layer 38.

[0248] FIG. 24 is an enlarged cross-sectional view of one or more embodiments of the Q region of FIG. 20.

[0249] Referring to FIG. 24, the display device 10 according to the embodiment is different from the display device 10 according to the embodiment described with reference to FIG. 21 above in that the thickness of the second element insulating layer 38_2 of the light-emitting element ED facing the display direction is different in each region.

[0250] For example, the second element insulating layer 38_2 of the light-emitting element ED aligned between the first electrode 210 and the second electrode 220 may have different thicknesses corresponding to different regions. For example, the second element insulating layer 38_2 of the light-emitting element ED aligned between the first electrode 210 and the second electrode 220 may have different thicknesses corresponding to different regions. In a cross-section passing through the light-emitting element ED (for example, in a direction substantially perpendicular to the extending direction of the light-emitting element ED), the second element insulating layer 38_2 located above the light-emitting element core 30 may have a first thickness d21 in a region overlapping with the second insulating layer 520, and the second element insulating layer 38_2 located above the light-emitting element core 30 in a cross-section passing through the light-emitting element ED may have a second thickness d22 smaller than the first thickness d21 in a region not overlapping with the second insulating layer 520. The second element insulating layer 38_2 located below the light-emitting element core 30 in a cross-section intersecting the light-emitting element ED may have a third thickness d23 equal to the first thickness d21. A part of the second element insulating layer 38_2 located above the light-emitting element core 30 may face the display direction, and another part of the second element insulating layer 38_2 located below the light-emitting element core 30 may face the first insulating layer 510.

[0251] For example, the second element insulating layer 38_2 that overlaps with the second insulating layer 520 and is located above the light-emitting element core 30, and the second element insulating layer 38_2 that is located below the light-emitting element core 30 may have the same thickness, and the second element insulating layer 38_2 may have the same thickness. Also, the element insulating layer 38_2 that does not overlap with the second insulating layer 520 and is located above the light-emitting element core 30 may have a thickness less than that of the second element insulating layer 38_2 that overlaps with the second insulating layer 520 and is located above the light-emitting element core 30. This can be formed by etching a part of the second element insulating layer 38_2 during the manufacturing process of the display device 10.

[0252] At the end of the detailed description, those of ordinary skill in the art will understand that many changes and modifications can be made to this embodiment without substantially departing from the principles of the present disclosure as set forth in the appended claims and their equivalents. Therefore, the embodiments disclosed in the present disclosure are for general and illustrative purposes only and not for the purpose of limitation.

Brief Description of the Drawings

[0045] The above and other aspects and features of the present disclosure will become clearer by referring to the accompanying drawings for a more detailed description of its embodiments, wherein: FIG. 1 is a schematic perspective view of a light-emitting element according to one or more embodiments of the present disclosure; FIG. 2 is a cross-sectional view of a light-emitting element according to one or more embodiments of the present disclosure; FIG. 3 is a cross-sectional view of a light-emitting element according to one or more embodiments of the present disclosure; FIG. 4 is a cross-sectional view of a light-emitting element according to one or more embodiments of the present disclosure; FIG. 5 is a cross-sectional view of a light-emitting element according to one or more embodiments of the present disclosure; FIG. 6 is an enlarged view of region P of FIG. 5; FIG. 7 is a cross-sectional view of a light-emitting element according to one or more embodiments of the present disclosure; FIG. 8 is a cross-sectional view of a light-emitting element according to one or more embodiments of the present disclosure; FIG. 9 is a schematic perspective view of a light-emitting element according to one or more embodiments of the present disclosure; FIG. 10 is a schematic perspective view of a light-emitting element according to one or more embodiments of the present disclosure; FIGS. 11 to 17 are cross-sectional views of the steps of a method for manufacturing a light-emitting element; FIG. 18 is a plan view of a display device according to one or more embodiments of the present disclosure; FIG. 19 is a plan layout diagram of one pixel of a display device according to one or more embodiments of the present disclosure; FIG. 20 is a cross-sectional view taken along line I-I' of FIG. 19 according to one or more embodiments of the present disclosure; FIG. 21 is an enlarged cross-sectional view of one or more embodiments of region Q of FIG. 20; FIG. 22 is an enlarged cross-sectional view of one or more embodiments of region Q of FIG. 20; FIG. 23 is an enlarged cross-sectional view of one or more embodiments of region Q of FIG. 20; and FIG. 24 is an enlarged cross-sectional view of one or more embodiments of region Q of FIG. 20.

Claims

1. A light-emitting element, comprising: a light-emitting element core, which includes a first semiconductor layer, a second semiconductor layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer; and a single-crystal insulating layer located on a side surface of the light-emitting element core, wherein the single-crystal insulating layer has a superlattice structure in which a plurality of first layers and a plurality of second layers comprising different materials are alternately stacked, and the plurality of first layers and the plurality of second layers are stacked in a direction substantially perpendicular to the side surface of the light-emitting element core.

2. The light-emitting element as claimed in claim 1, further comprising an element insulating layer located on the outer surface of the monocrystalline insulating layer.

3. The light-emitting element as claimed in claim 2, wherein the element insulating layer comprises a first element insulating film located on the outer surface of the monocrystalline insulating layer and a second element insulating film located on the outer surface of the first element insulating film.

4. The light-emitting element as claimed in claim 1, wherein each of the plurality of first layers and the plurality of second layers is a monocrystalline insulating film.

5. The light-emitting element as claimed in claim 4, wherein each of the plurality of first layers and the plurality of second layers has a thickness equal to or less than a critical thickness.

6. The light-emitting element as claimed in claim 1, wherein at least one of the plurality of first layers comprises a first compound semiconductor, and at least one of the plurality of second layers comprises a second compound semiconductor different from the first compound semiconductor.

7. The light-emitting element as claimed in claim 6, wherein each of the first compound semiconductor and the second compound semiconductor comprises a group III-V semiconductor compound.

8. The light-emitting element as claimed in claim 7, wherein the first compound semiconductor has the chemical formula AB, where A is a group III element and B is a group V element, and the second compound semiconductor has the chemical formula AxCl-xB, where 0 ≤ x < 1, A and C are group III elements, and B is a group V element.

9. The light-emitting element as claimed in claim 5, wherein each of the plurality of first layers and the plurality of second layers has a thickness greater than 0 and equal to or less than 5 nanometers.

10. The light-emitting element as claimed in claim 1, wherein the monocrystalline insulating layer is directly located on a side surface of the core of the light-emitting element, and the side surface of the core of the light-emitting element includes at least one of the side surface of the first semiconductor layer, the side surface of the second semiconductor layer, or the side surface of the light-emitting layer.

11. A light-emitting element, comprising: a light-emitting element core, which includes a first semiconductor layer, a second semiconductor layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer; and a first element insulating layer located on a side surface of the light-emitting element core, wherein the first element insulating layer has a superlattice structure in which a plurality of first layers comprising a first compound semiconductor and a plurality of second layers comprising a second compound semiconductor different from the first compound semiconductor are alternately stacked.

12. The light-emitting element as claimed in claim 11, wherein each of the first compound semiconductor and the second compound semiconductor comprises a group III-V semiconductor compound.

13. The light-emitting element as claimed in claim 12, wherein the first compound semiconductor has the chemical formula AB, where A is a group III element and B is a group V element, and the second compound semiconductor has the chemical formula AxCl-xB, where 0 ≤ x < 1, A and C are group III elements, and B is a group V element.

14. The light-emitting element as claimed in claim 11, wherein each of the plurality of first layers and the plurality of second layers is a single crystal layer.

15. The light-emitting element as claimed in claim 14, wherein each of the plurality of first layers and the plurality of second layers has a thickness greater than 0 and equal to or less than 5 nanometers.

16. The light-emitting element as claimed in claim 11, further comprising a second element insulating layer located on the first element insulating layer.

17. The light-emitting element as claimed in claim 16, wherein the second element insulating layer comprises a first element insulating film located on the outer surface of the first element insulating layer and a second element insulating film located on the outer surface of the first element insulating film.

18. The light-emitting element as claimed in claim 11, further comprising a first element insulating film located on a side surface of the core of the light-emitting element; and a second element insulating film located on the outer surface of the first element insulating film, wherein the first element insulating film is located between the first element insulating film and the second element insulating film.

19. A display device comprising: a first electrode and a second electrode, spaced apart from each other on a substrate; and a light-emitting element located between the first electrode and the second electrode, wherein the light-emitting element comprises: a light-emitting element core comprising a first semiconductor layer, a second semiconductor layer, a light-emitting layer located between the first semiconductor layer and the second semiconductor layer; and a single-crystal insulating layer located on a side surface of the light-emitting element core, wherein the single-crystal insulating layer has a superlattice structure comprising a plurality of alternating stacked first layers and a plurality of second layers comprising different materials, and the plurality of first layers and the plurality of second layers are stacked in a direction substantially perpendicular to the side surface of the light-emitting element core.

20. The display device as claimed in claim 19, wherein at least one of the plurality of first layers comprises a first compound semiconductor, and at least one of the plurality of second layers comprises a second compound semiconductor different from the first compound semiconductor.

21. The display device as claimed in claim 19, wherein each of the plurality of first layers and the plurality of second layers is a monocrystalline insulating film.

22. A display device comprising: a first electrode and a second electrode, spaced apart from each other on a substrate; and a light-emitting element located between the first electrode and the second electrode, wherein the light-emitting element comprises: a light-emitting element core comprising a first semiconductor layer, a second semiconductor layer, and a light-emitting layer located between the first semiconductor layer and the second semiconductor layer; and a first element insulating layer located on a side surface of the light-emitting element core, and the first element insulating layer having a superlattice structure in which a plurality of first layers comprising a first compound semiconductor and a plurality of second layers comprising a second compound semiconductor different from the first compound semiconductor are alternately stacked.

23. The display device as claimed in claim 22, wherein each of the first compound semiconductor and the second compound semiconductor comprises a group III-V semiconductor compound.

24. The display device as claimed in claim 23, wherein the first compound semiconductor has the chemical formula AB, wherein A is a group III element and B is a group V element, and the second compound semiconductor has the chemical formula AxCl-xB, wherein 0 ≤ x < 1, A and C are group III elements, and B is a group V element.

25. The display device as claimed in claim 22, wherein each of the plurality of first layers and the plurality of second layers is a single-crystal layer.

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