Semiconductor substrate manufacturing method

Abstract

The present invention aims to provide a method for manufacturing a semiconductor substrate capable of achieving adequate sensitivity or linewidth roughness performance. A method for manufacturing a semiconductor substrate includes: the steps of directly or indirectly vapor-depositing a metal compound or metal on a substrate to form a metal-containing resist film; and the step of exposing the resist film, wherein the metal compound or metal comprises Au atoms, Cr atoms, Ag atoms, In atoms, or any of these atoms.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing a semiconductor substrate. [Previous Technology]

[0002] In conventional pattern forming methods used in micro-processing using lithography, electromagnetic waves such as far-ultraviolet light (e.g., ArF excimer laser light, KrF excimer laser light, etc.), extreme ultraviolet light (EUV) or charged particle beams such as electron beams are used to expose a photoresist film formed by a radiosensitive linear composition for photoresist film formation, thereby generating acid in the exposed area. Then, through a chemical reaction catalyzed by this acid, a difference in the dissolution rate of the developer is created between the exposed and unexposed areas, thereby forming a pattern on the substrate. The formed pattern can be used as a mask in substrate processing, etc. For the aforementioned pattern forming method, with the miniaturization of processing technology, there is a demand for improved photoresist performance. In response to this demand, the types and molecular structures of organic polymers, acid generators, and other components used in the radiosensitive linear composition for photoresist film formation have been studied, and their combinations have also been studied in detail (for example, see Patent Document 1). In addition, the use of metal-containing compounds to replace organic polymers has also been studied. [Prior Art Documents] [Patent Documents]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2000-298347 [Summary of the Invention]

[0004] [The problem that the invention aims to solve]

[0005] In resist patterns formed using the metal-containing compound, sometimes the resist pattern collapses or the bottom edge of the pattern at the bottom of the resist film occurs.

[0006] The object of the present invention is to provide a method for manufacturing a semiconductor substrate that can fully utilize sensitivity or linewidth roughness (LWR) performance to solve the aforementioned problems. [Means for Solving the Problems]

[0007] In one embodiment, the present invention relates to a method for manufacturing a semiconductor substrate, comprising: directly or indirectly depositing a metal compound or metal in a vapor phase on a substrate to form a metal-containing resist film; and exposing the resist film, wherein the metal compound or metal comprises Au atoms, Cr atoms, Ag atoms, In atoms, or any of these atoms. [Effects of the Invention]

[0008] According to this semiconductor substrate manufacturing method, since a metal-containing resist film is formed by depositing a specific metal compound or metal vapor phase, a semiconductor substrate with a good pattern shape can be efficiently manufactured. Therefore, this semiconductor substrate manufacturing method is suitable for the manufacture of semiconductor devices that are expected to be further miniaturized in the future.

Implementation Method

[0010] Hereinafter, the manufacturing methods of semiconductor substrates according to various embodiments of the present invention will be described in detail.

[0011] Method for Manufacturing a Semiconductor Substrate This method for manufacturing a semiconductor substrate includes: a step of directly or indirectly depositing a metal compound or metal in a vapor phase on a substrate to form a metal-containing resist film (hereinafter also referred to as the "metal-containing resist film formation step"); and a step of exposing the metal-containing resist film formed by the metal-containing resist film formation step (hereinafter also referred to as the "exposure step"). Additionally, a step of preparing a developer solution (hereinafter also referred to as the "developer solution preparation step") may be included after the exposure step; or a step of using the developer solution to dissolve the exposed portion of the exposed metal-containing resist film to form a resist pattern (hereinafter also referred to as the "resist pattern formation step"). Furthermore, a step of directly or indirectly coating a composition for forming a resist underlayer film on the substrate (hereinafter also referred to as the "resist underlayer film formation composition coating step") may be included.

[0012] Hereinafter, each step of the method for manufacturing the semiconductor substrate will be described.

[0013] [Resist Underlayer Film Forming Composition Coating Step] When a resist underlayer film is formed directly or indirectly on a substrate, a resist underlayer film forming composition coating step may be included before the metal-containing resist film forming step. In this step, a resist underlayer film forming composition is directly or indirectly coated on the substrate. Known compositions can be appropriately used as the resist underlayer film forming composition. The coating method for the resist underlayer film forming composition is not particularly limited; for example, suitable methods such as spin coating, casting coating, and roller coating can be used. This forms a coating film, and the resist underlayer film is formed due to the evaporation of the solvent in the resist underlayer film forming composition, etc. Furthermore, the resist underlayer film forming composition will be described below.

[0014] Next, the coating film formed by the coating is heated. Heating the coating film can promote the formation of the resist underlayer film. More specifically, heating the coating film can promote the volatilization of the solvent in the composition for forming the resist underlayer film.

[0015] The heating of the coating film can be carried out in an atmospheric environment or in a nitrogen environment. The lower limit of the heating temperature is preferably 100°C, more preferably 150°C, and even more preferably 200°C. The upper limit of the heating temperature is preferably 400°C, more preferably 350°C, and even more preferably 280°C. The lower limit of the heating time is preferably 15 seconds, more preferably 30 seconds. The upper limit of the heating time is preferably 1,200 seconds, more preferably 600 seconds.

[0016] The lower limit of the average thickness of the formed resist underlayer film is preferably 0.5 nm, more preferably 1 nm, and even more preferably 2 nm. The upper limit of the average thickness is preferably 50 nm, more preferably 20 nm, even more preferably 10 nm, and particularly preferably 7 nm. Furthermore, the method for measuring the average thickness is based on the description in the examples.

[0017] [Metal-containing resist film formation step] In this step, a metal-containing resist film is formed on a resist underlayer film arbitrarily formed by the resist underlayer film forming composition coating step.

[0018] A metal-containing resist film can be formed by depositing a metal compound on the arbitrarily formed resist underlayer film.

[0019] The deposition of the metal compound can be performed by physical vapor deposition (PVD) or chemical vapor deposition (CVD). CVD is preferred, but plasma-enhanced (PE) CVD can also be used.

[0020] Vapor deposition using CVD can also be performed by atomic layer deposition (ALD). The deposition temperature using ALD can be 50°C to 600°C. The deposition pressure using ALD can be 100 mTorr to 6000 mTorr. The flow rate of the metal compound using ALD can be 0.01 ccm to 10 ccm, and the gas flow rate (CO 2, CO, Ar, N 2) can be 100 sccm to 10000 sccm. The plasma power using ALD can be 200 W to 1000 W per 300 mm wafer station using high-frequency plasma (e.g., 13.56 MHz, 27.1 MHz, or higher).

[0021] Suitable processing conditions for evaporation using CVD include: evaporation temperature of about 250°C to 350°C (e.g., 350°C), reactor pressure of less than 6 Torr (e.g., maintained at 1.5 Torr to 2.5 Torr at 350°C), plasma power / bias of 200 W per 300 mm wafer station using high-frequency plasma (e.g., 13.56 MHz or higher), metal compound flow rate of about 100 ccm to 500 ccm, and CO2 flow rate of about 1000 sccm to 2000 sccm.

[0022] The metal-containing resist film comprises Au atoms, Cr atoms, Ag atoms, In atoms, or any of these atoms. In other words, the metal-containing resist film of the present invention comprises at least one atom selected from the group consisting of Au atoms, Cr atoms, Ag atoms, and In atoms. Such a metal-containing resist film can be formed using a metal compound or metal monomer comprising Au atoms, Cr atoms, Ag atoms, In atoms, or any of these atoms.

[0023] As a metal compound, examples include: metal complexes, metal halides, or organometals.

[0024] As metal complexes, examples include: gold complexes, chromium complexes, silver complexes or indium complexes, etc.

[0025] As a halide metal, indium halide can be listed as an example.

[0026] As organometals, examples include alkyl indium, etc.

[0027] As a metal compound containing Au atoms, gold complexes such as chloro(triphenylphosphine)gold(I) can be listed as examples. Gold can also be used as a sputtering target.

[0028] Examples of chromium complexes containing Cr atoms include: chromium acetone (III), chromium acetate (III) hydroxide, tris(2,2,6,6-tetramethyl-3,5-heptadecane)chromium (III), hexacarbonyl chromium, bis(pentamethylcyclopentadienyl)chromium (III), etc. Chromium can also be used as a sputtering target.

[0029] Examples of silver complexes containing Ag atoms include silver acetate, silver trifluoroacetate, silver acetone, and (1,5-cyclooctadiene)(hexafluoroacetone)silver (I). Silver can also be used as a sputtering target.

[0030] Examples of metal compounds containing In atoms include: indium halides such as indium(III) chloride, indium complexes such as indium(III) acetone, indium(III) acetate, indium(III) acetate hydrate, and organoindium such as trimethylindium. Among organoindium, alkylindium such as trimethylindium is preferred. Indium or indium tin oxide (ITO) (a mixture of indium oxide and tin oxide) or indium gallium zinc oxide (IGZO) (a mixture of indium oxide, gallium oxide, and zinc oxide) can also be used as sputtering targets.

[0031] The metal-containing resist film of the present invention may also contain metal atoms other than Au atoms, Cr atoms, Ag atoms or In atoms. Examples of such other metal atoms include Sn atoms, Ge atoms, Pb atoms and Hf atoms, with Sn atoms being preferred.

[0032] [Exposure Step] In this step, the metal-containing photoresist film formed by the aforementioned metal-containing photoresist film formation step is exposed. Through this step, a difference in solubility in the developing solution arises between the exposed and unexposed portions of the metal-containing photoresist film, or a difference in the amount of material removed during development using heating arises between the exposed and unexposed portions.

[0033] The radiation used in the exposure can be appropriately selected based on the type of metal-containing resist film used. Examples include: visible light, ultraviolet light, far ultraviolet light, X-rays, gamma rays, and other electromagnetic waves; electron beams, molecular beams, ion beams, and other particle beams. Among these, far ultraviolet light is preferred, and more preferably KrF excimer laser light (wavelength 248 nm), ArF excimer laser light (wavelength 193 nm), F2 excimer laser light (wavelength 157 nm), Kr2 excimer laser light (wavelength 147 nm), ArKr excimer laser light (wavelength 134 nm), or extreme ultraviolet light (wavelength 13.5 nm, also known as "EUV"), and even more preferably EUV. In addition, the exposure conditions can be appropriately determined based on the type of metal-containing resist film used.

[0034] EUV exposure in the exposed portion of a metal-containing resist film causes chemical reactions such as dimerization or decomposition of the metal compound. For example, in the case of indium(III) chloride, which is an indium halide compound, a decomposition reaction such as 2InCl3→2In+3Cl2 occurs in the exposed portion.

[0035] In addition, in this step, after the exposure, in order to improve the performance of the resist film such as resolution, pattern outline, and developability, a post-exposure baking (hereinafter also referred to as "PEB") can be performed. The PEB temperature and PEB time can be appropriately determined according to the type of metal-containing resist film forming material used. The lower limit of the PEB temperature is preferably 50°C, more preferably 70°C. The upper limit of the PEB temperature is preferably 500°C, more preferably 300°C. The lower limit of the PEB time is preferably 10 seconds, more preferably 30 seconds. The upper limit of the PEB time is preferably 600 seconds, more preferably 300 seconds.

[0036] [Developer Preparation Steps] In this step, the developer is prepared. Examples of developers include: water, alcohol-based liquids, ether-based liquids, etc., and two or more can be used in combination.

[0037] Examples of alcohol-based liquids include: methanol, ethanol, n-propanol, isopropanol, n-butanol, isobutanol, dibutanol, terbutanol, n-pentanol, isopentanol, dipentanol, terpentanol, 2-methylpentanol, 4-methyl-2-pentanol, and other mono-alcohol liquids.

[0038] Examples of ether-based liquids include: ethylene glycol monomethyl ether, ethylene glycol monoethyl ether, ethylene glycol dimethyl ether, propylene glycol monoethyl ether, and other polyol partial ether solvents; ethylene glycol monomethyl ether acetate, ethylene glycol monoethyl ether acetate, propylene glycol monomethyl ether acetate (PGMEA), propylene glycol monoethyl ether acetate, and other polyol partial ether acetate liquids.

[0039] The developer is preferably a water-based or alcohol-based liquid, and more preferably a combination of water, ethanol, or the like.

[0040] [Resist Pattern Forming Step] In this step, the exposed metal-containing resist film is developed to form a resist pattern. For example, in the case of indium(III) chloride, which is an indium halide compound, the indium monomers generated in the exposed portion are not easily removed by developing solution or heating. In contrast, the indium(III) chloride in the unexposed portion can be removed by developing solution or heating. Therefore, a resist pattern can be formed by developing with developing solution or heating.

[0041] The temperature of the developer solution can be appropriately determined according to the type of metal-containing resist film forming material used. The lower limit of the developer solution temperature is preferably 20°C, more preferably 30°C. The upper limit of the developer solution temperature is preferably 70°C, more preferably 60°C. The lower limit of the development time is preferably 10 seconds, more preferably 30 seconds. The upper limit of the development time is preferably 600 seconds, more preferably 300 seconds.

[0042] The temperature for developing by heating can be appropriately determined according to the type of metal-containing resist film forming material used. The heating temperature can be 50°C to 600°C.

[0043] In this step, cleaning and / or drying can also be performed after development.

[0044] [Etching Step] In this step, etching is performed using the resist pattern as a mask. The number of etching operations can be one or multiple times, meaning that the pattern obtained by etching can be used as a mask to perform etching sequentially. Examples of etching methods include dry etching and wet etching. A semiconductor substrate with a predetermined pattern can be obtained through this etching.

[0045] As a dry etching process, a known dry etching apparatus can be used, for example. The etching gas used in the dry etching process can be appropriately selected based on the mask pattern, the elemental composition of the film being etched, etc. Examples include: fluorine-based gases such as CHF3, CF4, C2F6, C3F8, and SF6; chlorine-based gases such as Cl2 and BCl3; oxygen-based gases such as O2, O3, and H2O; reducing gases such as H2, NH3, CO, CO2, CH4, C2H2, C2H4, C2H6, C3H4, C3H6, C3H8, HF, HI, HBr, HCl, NO, NH3, and BCl3; and inert gases such as He, N2, and Ar. These gases can also be mixed. [Example]

[0046] Hereinafter, the present invention will be specifically described based on embodiments, but the present invention is not limited to these embodiments. Methods for measuring various physical properties are shown below.

[0047] <Preparation of Evaluation Substrate> [Example 1] A raw material for plasma CVD was prepared by mixing 2,4,6,8-tetramethylcyclotetrasiloxane with chloro(triphenylphosphine) gold (I) to achieve a gold concentration of 3 μg / L. Next, a substrate with a 20 nm thick silicon dioxide film formed on its surface was placed in a plasma CVD apparatus and vacuum degassing was performed. Subsequently, a 5 nm thick metal resist film containing Au atoms was fabricated on one side of the substrate using the aforementioned raw material for plasma CVD.

[0048] The metal-containing resist film was irradiated with extreme ultraviolet light using an EUV scanner (ASML's "TWINSCAN NXE:3300B" (NA 0.3, sigma 0.9, quadrupole illumination, 1-to-1 line and space mask with a linewidth of 16 nm on the wafer)). Subsequently, the substrate was developed using 4-methyl-2-pentanol and dried. Thus, an evaluation substrate with a resist pattern containing Au atoms was fabricated.

[0049] [Example 2] A substrate with a silicon dioxide film with a thickness of 20 nm formed on its surface was placed in a CVD apparatus and vacuum degassing was performed. Subsequently, a metal resist film containing Cr atoms with a thickness of 7 nm was formed on one side of the substrate using chromium hexacarbonyl.

[0050] The metal-containing resist film was irradiated with extreme ultraviolet light using the EUV scanner. Subsequently, the substrate was developed using 4-methyl-2-pentanol and dried. Thus, an evaluation substrate with a resist pattern containing Cr atoms was produced.

[0051] [Example 3] A substrate with a silicon dioxide film with a thickness of 20 nm formed on its surface was placed in an ALD device and vacuum degassing was performed. Subsequently, a metal resist film with a thickness of 3 nm containing Ag atoms was formed on one side of the substrate using a 0.1 M toluene solution of (1,5-cyclooctadiene)(hexafluoroacetyl acetone)silver (I).

[0052] The metal-containing resist film was irradiated with extreme ultraviolet light using the EUV scanner. Subsequently, it was developed for 60 seconds using n-propanol and by a coating method.

[0053] An etching solution with a phosphoric acid / nitric acid / acetic acid ratio of 45 / 2.2 / 30 (wt%) was prepared by mixing 85 wt% phosphoric acid, 70 wt% nitric acid, 99 wt% acetic acid, and ultrapure water. The developed substrate was immersed in the etching solution at 30°C for 60 seconds. Thus, an evaluation substrate with a resist pattern containing Ag atoms was obtained.

[0054] [Example 4] A substrate with a silicon dioxide film with a thickness of 20 nm formed on its surface was placed in a CVD apparatus and vacuum degassing was performed. Subsequently, a metal resist film containing In atoms with a thickness of 5 nm was formed on one side of the substrate using trimethylindium.

[0055] The metal-containing resist film was irradiated with extreme ultraviolet light using the EUV scanner. Subsequently, the substrate was developed by heating it at 150°C for 2 minutes. Thus, an evaluation substrate with a resist pattern containing In atoms was obtained.

[0056] [Example 5] In Example 4, indium(III) chloride was used instead of trimethylindium, and development with ultrapure water was performed instead of development based on heating at 150°C for 2 minutes. Otherwise, the operation was the same as in Example 4. Thus, an evaluation substrate with a resist pattern containing In atoms was obtained.

[0057] [Comparative Example 1] In Example 4, tetramethyltin was used instead of trimethylindium. Otherwise, an evaluation substrate with a resist pattern containing Sn atoms was obtained in the same manner as in Example 4.

[0058] [Comparative Example 2] A substrate with a silicon dioxide film with a thickness of 20 nm formed on its surface was placed in a plasma CVD apparatus and vacuum degassing was performed. Subsequently, a metal resist film containing Sn atoms with a thickness of 20 nm was formed on one side of the substrate by CVD of trimethyltin chloride and carbon dioxide.

[0059] The metal-containing resist film was irradiated with extreme ultraviolet light using the EUV scanner. Subsequently, the substrate was developed by heating it with ethanol at 60°C for 60 seconds. Thus, an evaluation substrate with a resist pattern containing Sn atoms was obtained.

[0060] <Evaluation> The rectangularity of the pattern is evaluated according to the following method. The evaluation results are shown in Table 1 below.

[0061] [LWR] 50 points of the pattern were measured, and the 3-sigma value was calculated based on the distribution of the measured values, and this value was set as LWR (nm). The smaller the LWR value, the better. Regarding LWR, the LWR value of Comparative Example 1 was set as the baseline value. Cases where the LWR is less than 95% of the baseline value were evaluated as "A", cases where the LWR exceeds 95% but is less than 99% of the baseline value were evaluated as "B", and cases where the LWR exceeds 99% of the baseline value were evaluated as "C". In Table 1 below, in the "LWR" row, "***" indicates the baseline for LWR evaluation.

[0062] [Table 1] LWR Example 1 A Example 2 B Example 3 A Example 4 B Example 5 B Comparative Example 1 *** Comparative Example 2 C

[0063] [Example 6] 2,4,6,8-Tetramethylcyclotetrasiloxane, chloro(triphenylphosphine) gold (I) and tris(dimethylamino)methyltin (IV) were mixed to prepare raw materials for plasma CVD with the concentrations of gold and tin being 1 μg / L and 4 μg / L, respectively.

[0064] In addition to using the same raw material, an evaluation substrate with a resist pattern containing Au atoms and Sn atoms and a film thickness of 5 nm was prepared in the same manner as in Example 1. The evaluation was performed in the same manner as described above, and the result LWR was "A".

[0065] Based on the results in Table 1 and Example 6, it is evident that the LWR is superior to that formed from a metal-containing resist film containing Au atoms, Cr atoms, Ag atoms, In atoms, or any of these atoms, compared to a resist pattern formed from a metal-containing resist film lacking these atoms. [Industrial Applicability]

[0066] According to the semiconductor substrate manufacturing method of the present invention, a resist pattern with excellent LWR can be formed. Therefore, this semiconductor substrate manufacturing method is suitable for the manufacture of semiconductor devices that are expected to be further miniaturized in the future. [Simplified Explanation of the Diagram]

[0009] None

Claims

1. A method for manufacturing a semiconductor substrate, comprising: The step of directly or indirectly depositing metal compounds or metals in the vapor phase on a substrate to form a metal-containing resist film; The method includes a step of exposing the resist film, and in the semiconductor substrate manufacturing method, the metal compound or metal contains Au atoms and / or Cr atoms.

2. A method for manufacturing a semiconductor substrate as claimed in claim 1, wherein the exposure step includes a step of developing the exposed resist film.

3. A method for manufacturing a semiconductor substrate as described in claim 1 or claim 2, wherein the deposition is performed by physical vapor deposition or chemical vapor deposition.

4. A method for manufacturing a semiconductor substrate as described in claim 1 or claim 2, wherein the metal compound comprises a metal complex, a metal halide, or an organometallic compound.

5. A method for manufacturing a semiconductor substrate as claimed in claim 4, wherein the metal complex comprises a gold complex or a chromium complex.

6. A method for manufacturing a semiconductor substrate as described in claim 1 or claim 2, wherein the exposure is performed using extreme ultraviolet light.