Method for manufacturing bonding semiconductor wafers

Abstract

This invention discloses a method for manufacturing a bonding semiconductor wafer, comprising the following steps: a step of fabricating an epitaxial wafer, wherein a sacrificial layer and an epitaxial layer having a semiconductor functional layer are epitaxially grown on a starting substrate, thereby fabricating an epitaxial wafer; a step of forming a device separation trench, wherein a device separation trench is formed by selective etching to expose the aforementioned sacrificial layer; a step of forming a passivation film, wherein a passivation film is formed on at least the surface exposing the aforementioned sacrificial layer; a step of fabricating a bonding substrate, wherein the aforementioned epitaxial layer is bonded to a transparent bonding substrate through a thermosetting bonding material, thereby fabricating a bonding substrate; a step of etching and removing, wherein the aforementioned passivation film of the aforementioned bonding substrate is etched and removed; and a separation step, wherein an etching solution is supplied to the aforementioned device separation trench of the aforementioned bonding substrate to etch the aforementioned sacrificial layer, thereby separating the aforementioned starting substrate and the aforementioned epitaxial layer. This provides a method for manufacturing a bonding semiconductor wafer that prevents bonding material from overflowing into the device separation trench and hindering the etching of the sacrificial layer. The bonding semiconductor wafer is formed on an epitaxial wafer with device separation trenches and is bonded to a substrate through a flexible bonding material.

Description

[Technical Field]

[0001] This invention relates to a method for manufacturing a bonding type semiconductor wafer. [Previous Technology]

[0002] The technique of separating and transferring semiconductor functional layers such as epitaxial functional layers from the starting substrate to other substrates is a technique that can alleviate the constraints caused by the physical properties of the starting substrate and is crucial in improving the design freedom of the device system.

[0003] To achieve such transfer, a technique is needed to bond the epitaxial functional layer to the permanent substrate and then remove the starting substrate to achieve the transfer.

[0004] Patent document 1 discloses a technique for hot-pressing a semiconductor epitaxial substrate and a temporary support substrate through a dielectric layer, and a technique for separating the temporary support substrate and the epitaxial functional layer by wet etching.

[0005] Patent document 2 discloses a technique in which, after forming an element separation trench and exposing a sacrificial layer, bonding is performed and sacrificial layer etching is carried out to separate the starting substrate.

[0006] However, in these technologies, the bonding material must be a solid material. When a soft or liquid material is used to form the bonding interface, the bonding layer can deform due to the pressure during bonding, and sometimes overflows into the component separation trench. The overflowed bonding material fills the component separation trench, resulting in the following problem: the purpose of forming the component separation trench, i.e., the sacrificial layer, is covered by the bonding material, making sacrificial layer etching impossible. [Prior Art Documents] (Patent Documents)

[0007] Patent Document 1: Japanese Patent Application Publication No. 2021-27301. Patent Document 2: International Publication No. WO2014 / 020906. [Summary of the Invention]

[0008] [Problem to be Solved by the Invention] The present invention has been made in view of the above-mentioned problems, and aims to provide a method for manufacturing a bonding semiconductor wafer that prevents bonding material from overflowing into the device separation trench and hindering the etching of the sacrificial layer. This bonding semiconductor wafer is manufactured by forming device separation trenches on an epitaxial wafer and bonding it to a substrate with a flexible bonding material in between. [Technical Means for Solving the Problem]

[0009] The present invention is made to achieve the above-mentioned objective, and provides a method for manufacturing a bonding semiconductor wafer, characterized by comprising the following steps: an epitaxial growth step, wherein a sacrificial layer is epitaxially grown on a starting substrate; a step for fabricating an epitaxial wafer, wherein an epitaxial layer having a semiconductor functional layer is epitaxially grown on the aforementioned sacrificial layer, thereby fabricating an epitaxial wafer; a step for forming a device separation trench, wherein a device separation trench is formed by selective etching to expose the aforementioned sacrificial layer in a portion of the aforementioned epitaxial wafer; a step for forming a passivation film, wherein a passivation film is formed on at least the surface of the aforementioned device separation trench where the aforementioned sacrificial layer is exposed; a step for fabricating a bonding substrate, wherein the aforementioned epitaxial layer of the aforementioned epitaxial wafer is bonded to a bonding substrate that is transparent to visible light through a thermosetting bonding material, thereby fabricating a bonding substrate; an etching and removal step, wherein the aforementioned passivation film of the aforementioned bonding substrate is etched and removed; and a separation step, wherein an etching solution is supplied to the aforementioned device separation trench of the aforementioned bonding substrate to etch the aforementioned sacrificial layer, thereby separating the aforementioned starting substrate and the aforementioned epitaxial layer.

[0010] In any such bonding semiconductor wafer manufacturing method, a passivation (PSV) film is formed on at least the surface of the sacrificial layer in the device separation trench during bonding, so as to prevent the sacrificial layer etching from being hindered due to the bonding material overflowing into the device separation trench and covering the surface of the sacrificial layer.

[0011] At this time, it is preferable that the aforementioned substrate to be bonded is made of any one of the following materials: sapphire, synthetic quartz, quartz (natural quartz), glass, SiC, LiTaO3, and LiNbO3.

[0012] Such a substrate can be selected in a way that improves the penetration of lasers, and is suitable for the bonding type semiconductor wafer manufacturing method of the present invention.

[0013] Furthermore, it is preferable that the aforementioned thermosetting bonding material is one or more of the following materials: silicone resin, epoxy resin, benzocyclobutene, spin-coated glass, polyimide, and fluororesin.

[0014] Such thermosetting bonding materials are suitable for use as bonding materials in bonding semiconductor wafer manufacturing methods.

[0015] Furthermore, it is preferable to set the thickness of the aforementioned thermosetting bonding material to be 0.01 μm or more and 0.6 μm or less.

[0016] As long as the adhesive layer thickness is this, there will be no problem of thickness deviation caused by excessive thickness, and it can ensure the necessary and sufficient thickness when bonding.

[0017] Furthermore, the aforementioned thermosetting bonding material can be configured to be unthermosetting.

[0018] Thus, as long as the thermosetting bonding material is set to not be thermosetting, it can be easily peeled off when peeling is performed.

[0019] In addition, it is preferable to set the aforementioned passivation film as a silicon oxide film.

[0020] Thus, as long as the passivation film used in this invention is a silicon oxide film, it can be more easily formed and removed. In addition, the silicon oxide film removal etching can also take into account the etching of the sacrificial layer by using a fluorine-based solution.

[0021] Furthermore, it is preferable to use the aforementioned bonding semiconductor wafer as a micro light-emitting diode (Micro LED).

[0022] Thus, the method for manufacturing the bonding-type semiconductor wafer of the present invention is particularly advantageous when manufacturing small-sized devices such as Micro LEDs. [Effects of the Invention]

[0023] In any bonding semiconductor wafer manufacturing method of the present invention, the presence of a passivation film can prevent bonding material from overflowing into the device separation trench and hindering the etching of the sacrificial layer. This bonding semiconductor wafer is formed on an epitaxial wafer with device separation trenches and is bonded to a substrate via a flexible bonding material. Therefore, the yield of device manufacturing can be improved for bonding semiconductor wafers.

Implementation Method

[0025] The present invention will now be described in detail, but the present invention is not limited thereto.

[0026] The present invention is a method for manufacturing a bonding semiconductor wafer, characterized by comprising the following steps: an epitaxial growth step in which a sacrificial layer is epitaxially grown on a starting substrate; a step for fabricating an epitaxial wafer in which an epitaxial layer having a semiconductor functional layer is epitaxially grown on the aforementioned sacrificial layer, thereby fabricating an epitaxial wafer; a step for forming a device separation trench in which a device separation trench is formed by selective etching to expose the aforementioned sacrificial layer in a portion of the aforementioned epitaxial wafer; a step for forming a passivation film in which a passivation film is formed on at least the surface of the aforementioned device separation trench where the aforementioned sacrificial layer is exposed; a step for fabricating a bonding substrate in which the aforementioned epitaxial layer of the aforementioned epitaxial wafer is bonded to a bonding substrate that is transparent to visible light through a thermosetting bonding material, thereby fabricating a bonding substrate; a step for etching and removing the aforementioned passivation film of the aforementioned bonding substrate; and a separation step in which an etching solution is supplied to the aforementioned device separation trench of the aforementioned bonding substrate to etch the aforementioned sacrificial layer, thereby separating the aforementioned starting substrate and the aforementioned epitaxial layer.

[0027] Hereinafter, embodiments one through four will be used to illustrate the present invention. Similar constituent elements in each embodiment will be given the same reference numerals in the drawings. Furthermore, repeated descriptions will be partially omitted.

[0028] [First Embodiment] The first embodiment will be described. First, as shown in Figure 1, epitaxial growth is performed sequentially on a starting substrate 11 to form each layer, thereby fabricating an epitaxial wafer 20. This fabricates an epitaxial layer having a sacrificial layer 12 and a semiconductor functional layer 18. More specifically, the epitaxial growth of each layer is performed as follows.

[0029] As shown in Figure 1, a sacrificial layer 12 is epitaxially grown on a first conductivity type, for example, a GaAs base substrate 11. The sacrificial layer 12 can be formed, for example, by depositing a first conductivity type GaAs buffer layer, followed by growing a first conductivity type GaInP first etch stop layer and a first conductivity type GaAs second etch stop layer. Further, on the sacrificial layer 12, for example, a first conductivity type AlGaInP first cladding layer 13, an undoped AlGaInP active layer 14, a second conductivity type AlGaInP second cladding layer 15, a second conductivity type GaInP intermediate layer (not shown), and a second conductivity type GaP window layer 16 are grown sequentially to prepare an epitaxial wafer 20 having a light-emitting element structure as a semiconductor functional layer (epithelial functional layer) 18. Here, the section from the first cladding layer 13 to the second cladding layer 15 is referred to as a double-heterostructure (DH) section (Figure 1). Furthermore, the material of the semiconductor functional layer (epitaxy functional layer) 18 is not limited to this. The semiconductor functional layer 18 can be configured as having a light-emitting element structure as described above, in which case the bonding semiconductor wafer manufacturing method of the present invention is particularly suitable.

[0030] Subsequently, as shown in Figure 2, a device separation trench 21 is formed by selective etching to expose the sacrificial layer 12 in a portion of the epitaxial wafer 20. More specifically, a photomask is formed using photolithography, and etching (selective etching) is performed from the GaP window layer 16 to at least the first cladding layer 13 to perform the device separation step of forming the device separation trench 21 (Figure 2).

[0031] Furthermore, Figure 2 illustrates a state where the sacrificial layer 12 is exposed (exposed portion 12a) and has not been etched, but this is not the only possible state. For example, the sacrificial layer 12 may be etched in a manner that extends throughout the component separation pattern, or the depth of the etch trench may reach the starting substrate 11. Even in such a state, the sacrificial layer 12 will still be exposed as part of the side of the component separation pattern. The present invention can still be applied in this case.

[0032] Subsequently, as shown in Figure 3, a passivation film 22 is formed on the surface of the device separation trench 21 where at least the sacrificial layer 12 is exposed (exposed portion 12a). More specifically, as shown in Figure 3, a passivation (PSV) film 22 such as SiO2 (silicon oxide film) can be formed on the outermost surface constituting the wafer (the surface of the window layer 16 in Figure 3) and inside the device separation trench 21 (Figure 3).

[0033] Next, as shown in Figure 4, a PSV patterned substrate is fabricated by removing the passivation film 22 from the area outside the interior of the element separation trench 21 (Figure 4).

[0034] By forming the passivation film 22 in the device separation trench 21 in this way, it is possible to prevent the following situation: when bonding substrates (bonded wafers) are bonded with bonding material in between, the bonding material overflows into the device separation trench 21, causing the trench to be blocked by the bonding material and the etching of the sacrificial layer to be hindered.

[0035] Next, as shown in Figures 5 and 6, the epitaxial layer of the epitaxial wafer 20 having the semiconductor functional layer 18 is bonded to the substrate 31, which is transparent to visible light, through a thermosetting bonding material 24, to fabricate the bonding substrate 30. More specifically, first, as shown in Figure 5, a thermosetting bonding material, such as benzocyclobutene (BCB), is spin-coated onto the epitaxial wafer (Figure 5). Next, as shown in Figure 6, it is overlapped with the substrate 31, such as a sapphire wafer, and the bonding substrate (epithelial bonding substrate) 30 is fabricated by thermoforming, which is formed by bonding the epitaxial wafer 20 and the sapphire wafer 31 through a thermosetting bonding material 24 (BCB) (Figure 6). When spin-coating the thermosetting bonding material (BCB), the film thickness is preferably designed to be 0.01 μm or more and 0.6 μm or less. Furthermore, the thermosetting bonding material 24 can also be configured not to undergo thermosetting. As long as the thermosetting bonding material 24 is not thermosetting, it can be easily peeled off during the peeling process.

[0036] Furthermore, the substrate 31 to be bonded is not limited to sapphire; any material that ensures flatness and has low absorption of excimer laser light can be selected. In addition to sapphire, synthetic quartz, quartz (natural quartz), glass, SiC, LiTaO3, and LiNbO3 can be selected.

[0037] Furthermore, the thermosetting bonding material 24 is not limited to BCB; any material with thermosetting properties can be selected. Besides BCB, silicone resin, epoxy resin, spin-on-glass (SOG), polyimide (PI), fluoropolymers, etc., can also be used. As a fluoropolymer, amorphous fluoropolymers such as CYTOP (registered trademark) can be used.

[0038] Next, as shown in Figure 7, the passivation film 22 of the bonding substrate 30 is etched and removed. More specifically, for example, the passivation film 22 can be etched using a fluorine-based solution (Figure 7). In the example of Figure 7, the etching solution can be supplied from a direction nearly perpendicular to the paper surface. By this etching, the passivation film 22 can be removed, and the component separation trench 21 appears.

[0039] Next, as shown in Figure 8, an etching solution is supplied to the device separation trench 21 of the bonding substrate 30 to etch the sacrificial layer 12, thereby separating the starting substrate 11 from the epitaxial layer (with the semiconductor functional layer 18). More specifically, by etching the sacrificial layer 12 using a fluorine-based solution, the starting substrate 11 can be peeled off (Figure 8). Furthermore, as shown in Figures 7 and 8, although the passivation film removal step and the sacrificial layer etching step are described as separate steps, by selecting materials that can be selectively etched using a fluorine-based solution for both the passivation film 22 and the sacrificial layer 12, it can be implemented as a series of steps. As the passivation film 22, the material that can be selectively etched using a fluorine-based solution is, for example, SiO2 as described above. As the sacrificial layer 12, the material that can be selectively etched using a fluorine-based solution is, for example, GaInP and GaAs as described above.

[0040] By operating as described above, a bonding semiconductor wafer 35 can be manufactured. The bonding semiconductor wafer 35 shown in Figure 8 can be used for Micro LEDs. Furthermore, as shown below, electrodes for various components can then be formed.

[0041] First, as shown in Figure 9, a portion of the second cladding layer 15 is exposed using photolithography (Figure 9).

[0042] Next, as shown in Figure 10, a passivation (PSV) film 42 of SiO2 or the like is formed on the surface to create a PSV patterned film. It is processed in such a way that the end of the element separation trench 21, the side of the exposed active layer 14 are covered, and a portion of the first coating layer 13 and the second coating layer 15 are exposed (Figure 10).

[0043] Subsequently, as shown in Figure 11, an electrode 44 is formed on the exposed portion of the passivation film 42, and heat treatment is applied to achieve ohmic contact (Figure 11).

[0044] [Second Embodiment] Next, a second embodiment of the present invention will be described. First, similar to the first embodiment, epitaxial growth is sequentially performed on a starting substrate 11 to form each layer, thereby fabricating an epitaxial wafer 20. This epitaxial wafer 20 has a sacrificial layer 12 and an epitaxial layer having a semiconductor functional layer 18. More specifically, the epitaxial growth of each layer can be performed as follows.

[0045] First, as shown in Figure 12, a sacrificial layer 12 is epitaxially grown on a first conductivity type, for example, a GaAs-based starter substrate 11. The sacrificial layer 12 can be formed, for example, by depositing a first conductivity type GaAs buffer layer, followed by growing a first conductivity type GaInP etch stop layer and a second conductivity type GaAs etch stop layer. Further, on the sacrificial layer 12, for example, a first conductivity type AlGaInP cladding layer 13, an undoped AlGaInP active layer 14, a second conductivity type AlGaInP cladding layer 15, a second conductivity type GaInP intermediate layer (not shown), and a second conductivity type GaP window layer 16 are grown sequentially to prepare an epitaxial wafer 20 having a light-emitting element structure as a semiconductor functional layer (epithelial functional layer) 18. Here, the portion from the first cladding layer 13 to the second cladding layer 15 is referred to as a double-layer heterostructure (DH) section (Figure 12). Furthermore, the material of the semiconductor functional layer (epterctic functional layer) 18 is not limited to this. The semiconductor functional layer 18 can be configured as having a light-emitting element structure as described above.

[0046] Next, as shown in Figure 13, a device separation trench 21 is formed by selective etching to expose the sacrificial layer 12 in a portion of the epitaxial wafer 20. More specifically, a photomask is formed using photolithography, and etching (selective etching) is performed from the GaP window layer 16 to at least the first cladding layer 13 to perform the device separation step of forming the device separation trench 21 (Figure 13). Here, the sacrificial layer 12 is exposed (exposed portion 12a).

[0047] Subsequently, as shown in Figure 14, a thermosetting bonding material, such as benzocyclobutene (BCB), is spin-coated on the epitaxial wafer 20 (Figure 14), and the BCB film is hardened by applying heat at 250°C for 1 hour (in the figure, the hardened thermosetting bonding material is labeled as hardened bonding material 25).

[0048] Subsequently, as shown in Figure 15, by means of photolithography, a portion of the hardened bonding material (hardened BCB portion) 25 of the element separation groove 21 is removed to form an opening 26, thereby exposing the exposed portion 12a of the sacrificial layer 12 (Figure 15).

[0049] Next, as shown in Figure 16, a passivation (PSV) film 22 of SiO2 or the like is formed on the surface (Figure 16), and as shown in Figure 17, a PSV patterned substrate is fabricated, which is a passivation film 22 in areas other than the element separation trench 21 that has been removed (Figure 17).

[0050] Subsequently, as shown in Figure 18, a thermosetting bonding material 24, such as benzocyclobutene (BCB), is spin-coated onto the epitaxial wafer (Figure 18).

[0051] Next, as shown in Figure 19, the substrate is overlapped with the substrate 31 to be bonded, such as a sapphire wafer, and a bonding substrate (epithelial bonding substrate) 50 is fabricated by thermoforming. This substrate is formed by bonding the epitaxial wafer 20 and the sapphire wafer 31 with a thermosetting bonding material 24 (BCB) in between (Figure 19). When the thermosetting bonding material (BCB) is applied by spin coating, the film thickness is preferably designed to be 0.01 μm or more and 0.6 μm or less.

[0052] Furthermore, the substrate 31 to be bonded is not limited to sapphire; any material that ensures flatness and has low absorption of excimer laser light can be selected. In addition to sapphire, synthetic quartz, quartz (natural quartz), glass, SiC, LiTaO3, and LiNbO3 can be selected.

[0053] Furthermore, the thermosetting bonding material 24 is not limited to BCB; any material with thermosetting properties can be selected. In addition to BCB, silicone resin, epoxy resin, spin-on-glass (SOG), polyimide (PI), fluororesin, etc., can also be used.

[0054] Next, as shown in Figure 20, the passivation film 22 of the bonding substrate 50 is etched and removed. More specifically, for example, the passivation film 22 can be etched using a fluorine-based solution (Figure 20). In the example of Figure 20, the etching solution is supplied from a direction nearly perpendicular to the paper surface. By this etching, the passivation film 22 can be removed, thus creating the element separation trench 21.

[0055] Next, as shown in Figure 21, an etching solution is supplied to the device separation trench 21 of the bonding substrate 50 to etch the sacrificial layer 12, thereby separating the starting substrate 11 from the epitaxial layer (having a semiconductor functional layer 18). More specifically, as shown in Figure 21, the starting substrate 11 can be peeled off by etching the sacrificial layer 12 using a fluorine-based solution (Figure 21). Furthermore, as shown in Figures 21 and 22, although the passivation film removal step and the sacrificial layer etching step are described as separate steps, by selecting materials that can be selectively etched using a fluorine-based solution for both the passivation film 22 and the sacrificial layer 12, it can be implemented as a series of steps.

[0056] By operating as described above, a bonding semiconductor wafer 55 can be manufactured. The bonding semiconductor wafer 55 shown in Figure 21 can be used for Micro LEDs. Furthermore, as shown below, electrodes for each element can then be formed.

[0057] First, as shown in Figure 22, a portion of the second coating layer 15 is exposed using photolithography (Figure 22). Then, as shown in Figure 23, the hardened bonding material 25 (BCB hardened portion) that has become spikes is physically removed using a lift-off method (Figure 23). Here, the spiked hardened bonding material 25 (BCB hardened portion) can be removed by a liquid flow with a pressure of about 5 kgf / cm², but this method is not limited to this; ashing and RIE (reactive ion etching) methods can also be used. In ashing and RIE methods, the hardened bonding material 25 is etched isotropically, but the etch rate of the spiked BCB hardened portion is faster than that of the film-like BCB hardened portion. Therefore, by adjusting the timing conditions, only the spiked BCB hardened portion can be removed.

[0058] Next, as shown in Figure 24, a passivation (PSV) film 42 of SiO2 or the like is formed on the surface to create a PSV patterned film. It is processed in such a way that the side of the exposed active layer 14 is covered and a portion of the first coating layer 13 and the second coating layer 15 are exposed (Figure 24).

[0059] Subsequently, as shown in Figure 25, an electrode 44 is formed on the exposed portion of the passivation film 42, and heat treatment is applied to achieve ohmic contact (Figure 25).

[0060] [Third Embodiment] Next, a third embodiment of the present invention will be described. First, similar to the first and second embodiments, epitaxial growth is sequentially performed on a starting substrate 11 to form each layer, thereby fabricating an epitaxial wafer 20. This epitaxial wafer 20 has a sacrificial layer 12 and an epitaxial layer having a semiconductor functional layer 18. More specifically, the epitaxial growth of each layer can be performed as follows.

[0061] First, as shown in Figure 26, a sacrificial layer 12 is epitaxially grown on a first conductivity type, for example, a GaAs-based starter substrate 11. The sacrificial layer 12 can be formed, for example, by depositing a first conductivity type GaAs buffer layer, followed by growing a first conductivity type GaInP etch stop layer and a second conductivity type GaAs etch stop layer. Further, on the sacrificial layer 12, for example, a first conductivity type AlGaInP cladding layer 13, an undoped AlGaInP active layer 14, a second conductivity type AlGaInP cladding layer 15, a second conductivity type GaInP intermediate layer (not shown), and a second conductivity type GaP window layer 16 are grown sequentially to prepare an epitaxial wafer 20 having a light-emitting element structure as a semiconductor functional layer (epithelial functional layer) 18. Here, the portion from the first cladding layer 13 to the second cladding layer 15 is referred to as a double-layer heterostructure (DH) section (Figure 26). Furthermore, the material of the semiconductor functional layer (epterctic functional layer) 18 is not limited to this. The semiconductor functional layer 18 can be configured to have a light-emitting element structure as described above.

[0062] Next, as shown in Figure 27, a device separation trench 21 is formed by selective etching to expose the sacrificial layer 12 in a portion of the epitaxial wafer 20. More specifically, a photomask is formed using photolithography, and etching (selective etching) is performed from the GaP window layer 16 to at least the first cladding layer 13 to perform the device separation step of forming the device separation trench 21 (Figure 27). Here, the sacrificial layer 12 is exposed (exposed portion 12a).

[0063] Next, as shown in Figure 28, a thermosetting bonding member, such as benzocyclobutene (BCB), is spin-coated onto the epitaxial wafer 20 (Figure 28), and heat is applied at 250°C for 1 hour to harden the BCB film (in the figure, the hardened thermosetting bonding material is labeled as hardened bonding material 25). Furthermore, as a general tendency, when the aspect ratio of the width and depth of the element separation trench 21 is greater than 0.1 (deeper), the BCB will not reach the bottom of the element separation trench, and the bottom of the element separation trench 21 will show a part of the DH structure and the sacrificial layer 12 exposed.

[0064] Subsequently, as shown in Figure 29, by means of photolithography, a portion of the hardened bonding material 25 (hardened BCB portion) of the element separation groove 21 is removed to form an opening 26, thereby exposing the sacrificial layer 12 (Figure 29).

[0065] Next, as shown in Figure 30, a passivation (PSV) film 22 of SiO2 or the like is formed on the surface (Figure 30), and as shown in Figure 31, a PSV patterned substrate is fabricated, which is a passivation film 22 in areas other than the element separation trench 21 that has been removed (Figure 31).

[0066] Next, as shown in Figure 32, benzocyclobutene (BCB), which serves as a thermosetting bonding material 24, is spin-coated onto the epitaxial wafer 20 (Figure 32). Then, as shown in Figure 33, it is overlapped with the substrate 31 to be bonded, such as a sapphire wafer, and a bonding substrate (epithelial bonding substrate) 60 is formed by thermoforming. The epitaxial wafer 20 and the sapphire wafer 31 are bonded together with the thermosetting bonding material (BCB) in between. When spin-coating the thermosetting bonding material (BCB), the film thickness is preferably designed to be 0.01 μm or more and 0.6 μm or less (Figure 33).

[0067] Furthermore, the substrate 31 to be bonded is not limited to sapphire; any material that ensures flatness and has low absorption of excimer laser light can be selected. In addition to sapphire, synthetic quartz, quartz (natural quartz), glass, SiC, LiTaO3, and LiNbO3 can be selected.

[0068] Furthermore, the thermosetting bonding material 24 is not limited to BCB; any material with thermosetting properties can be selected. In addition to BCB, silicone resin, epoxy resin, spin-on-glass (SOG), polyimide (PI), fluororesin, etc., can also be used.

[0069] Next, as shown in Figure 34, the passivation film 22 of the bonding substrate 60 is etched and removed. More specifically, for example, the passivation film 22 can be etched using a fluorine-based solution (Figure 34). In the example of Figure 34, the etching solution is supplied from a direction nearly perpendicular to the paper surface. By this etching, the passivation film 22 can be removed, thus creating the element separation trench 21.

[0070] Next, as shown in Figure 35, an etching solution is supplied to the device separation trench 21 of the bonding substrate 60 to etch the sacrificial layer 12, thereby separating the starting substrate 11 from the epitaxial layer (having a semiconductor functional layer 18). More specifically, as shown in Figure 35, the starting substrate 11 can be peeled off by etching the sacrificial layer 12 using a fluorine-based solution (Figure 35). Furthermore, as shown in Figures 34 and 35, although the passivation film removal step and the sacrificial layer etching step are described as separate steps, by selecting materials that can be selectively etched using a fluorine-based solution for both the passivation film 22 and the sacrificial layer 12, it can be implemented as a series of steps.

[0071] By operating as described above, a bonding semiconductor wafer 65 can be manufactured. The bonding semiconductor wafer 65 shown in Figure 35 can be used for Micro LEDs. Furthermore, as shown below, electrodes for various components can then be formed.

[0072] First, as shown in Figure 36, a portion of the second cladding layer 15 is exposed using photolithography (Figure 36).

[0073] Next, as shown in Figure 37, a passivation (PSV) film 42 of SiO2 or the like is formed on the surface to create a PSV patterned film. It is processed in such a way that the end of the element separation trench 21, the side of the exposed active layer 14 are covered, and a portion of the first coating layer 13 and the second coating layer 15 are exposed (Figure 37).

[0074] Subsequently, as shown in Figure 38, an electrode 44 is formed on the exposed portion of the passivation film 42, and heat treatment is applied to achieve ohmic contact (Figure 38).

[0075] [Fourth Embodiment] Next, a fourth embodiment of the present invention will be described. First, similar to the first to third embodiments, epitaxial growth is sequentially performed on a starting substrate 11 to form each layer, thereby fabricating an epitaxial wafer 20. This epitaxial wafer 20 has a sacrificial layer 12 and an epitaxial layer having a semiconductor functional layer 18. More specifically, the epitaxial growth of each layer can be performed as follows.

[0076] First, as shown in Figure 39, a sacrificial layer 12 is epitaxially grown on a first conductivity type, for example, a GaAs-based starter substrate 11. The sacrificial layer 12 can be formed, for example, by depositing a first conductivity type GaAs buffer layer, followed by growing a first conductivity type GaInP first etch stop layer and a first conductivity type GaAs second etch stop layer. Further, on the sacrificial layer 12, for example, a first conductivity type AlGaInP first cladding layer 13, an undoped AlGaInP active layer 14, a second conductivity type AlGaInP second cladding layer 15, a second conductivity type GaInP intermediate layer (not shown), and a second conductivity type GaP window layer 16 are grown sequentially to prepare an epitaxial wafer 20 having a light-emitting element structure as a semiconductor functional layer (epithelial functional layer) 18. Here, the portion from the first cladding layer 13 to the second cladding layer 15 is referred to as a double-layer heterostructure (DH) section (Figure 39). Furthermore, the material of the semiconductor functional layer (epterctic functional layer) 18 is not limited to this. The semiconductor functional layer 18 can be configured to have a light-emitting element structure as described above.

[0077] Next, as shown in Figure 40, a device separation trench 21 is formed by selective etching to expose the sacrificial layer 12 in a portion of the epitaxial wafer 20. More specifically, a photomask is formed using photolithography, and etching (selective etching) is performed from the GaP window layer 16 to at least the first cladding layer 13 to perform the device separation step of forming the device separation trench 21 (Figure 40). Here, the sacrificial layer 12 is exposed (exposed portion 12a).

[0078] Subsequently, as shown in Figure 41, a thermosetting bonding material, such as benzocyclobutene (BCB), is spin-coated on the epitaxial wafer 20 (Figure 41), and the BCB film is hardened by applying heat at 250°C for 1 hour (in the figure, the hardened thermosetting bonding material is labeled as hardened bonding material 25).

[0079] As a general tendency, when the aspect ratio of the width and depth of the component separation trench 21 is greater than 0.1 (deeper), the BCB will appear to be in a state where the component separation trench is not completely buried.

[0080] Subsequently, as shown in Figure 42, by means of photolithography, a portion of the hardened bonding material 25 (hardened BCB portion) of the element separation groove 21 is removed to form an opening 26, thereby exposing the sacrificial layer 12 (Figure 42).

[0081] Next, as shown in Figure 43, a passivation (PSV) film 22 of SiO2 or the like is formed on the surface (Figure 43), and as shown in Figure 44, a PSV patterned substrate is fabricated, which is a passivation film 22 in areas other than the element separation trench 21 that has been removed (Figure 44).

[0082] Next, as shown in Figure 45, benzocyclobutene (BCB), which serves as a thermosetting bonding material 24, is spin-coated onto the epitaxial wafer 20 (Figure 45). Then, as shown in Figure 46, it is overlapped with the substrate 31 to be bonded, such as a sapphire wafer, and a bonding substrate (epithelial bonding substrate) 70 is fabricated by thermoforming. This substrate is formed by bonding the epitaxial wafer 20 and the sapphire wafer 31 with the thermosetting bonding material (BCB) in between. When spin-coating the thermosetting bonding material (BCB), the film thickness is preferably designed to be 0.01 μm or more and 0.6 μm or less (Figure 46).

[0083] Furthermore, the substrate 31 to be bonded is not limited to sapphire; any material that ensures flatness and has low absorption of excimer laser light can be selected. In addition to sapphire, synthetic quartz, quartz (natural quartz), glass, SiC, LiTaO3, and LiNbO3 can be selected.

[0084] Furthermore, the thermosetting bonding material 24 is not limited to BCB; any material with thermosetting properties can be selected. In addition to BCB, silicone resin, epoxy resin, spin-on-glass (SOG), polyimide (PI), fluororesin, etc., can also be used.

[0085] Next, as shown in Figure 47, the passivation film 22 of the bonding substrate 70 is etched and removed. More specifically, for example, the passivation film 22 can be etched using a fluorine-based solution (Figure 47). In the example of Figure 47, the etching solution is supplied from a direction nearly perpendicular to the paper surface. By this etching, the passivation film 22 can be removed, thus creating the element separation trench 21.

[0086] Next, as shown in Figure 48, an etching solution is supplied to the device separation trench 21 of the bonding substrate 70 to etch the sacrificial layer 12, thereby separating the starting substrate 11 from the epitaxial layer (having a semiconductor functional layer 18). More specifically, as shown in Figure 48, the starting substrate 11 can be peeled off by etching the sacrificial layer 12 using a fluorine-based solution (Figure 48). Furthermore, as shown in Figures 47 and 48, although the passivation film removal step and the sacrificial layer etching step are described as separate steps, by selecting materials that can be selectively etched using a fluorine-based solution for both the passivation film 22 and the sacrificial layer 12, it can be implemented as a series of steps.

[0087] By operating as described above, a bonding semiconductor wafer 75 can be manufactured. The bonding semiconductor wafer 75 shown in Figure 48 can be used for Micro LEDs. Furthermore, as shown below, electrodes for each element can then be formed.

[0088] First, as shown in Figure 49, a portion of the second cladding layer 15 is exposed using photolithography (Figure 49).

[0089] Next, as shown in Figure 50, the hardened bonding material 25 (BCB hardened portion) that has become spiked is physically removed using a method such as excavation (Figure 50). In this embodiment, the BCB hardened portion can be removed by a liquid flow with a pressure of about 5 kgf / cm², but it is not limited to this method. Ashing or RIE can be used. In both ashing and RIE methods, the hardened bonding material 25 (BCB hardened portion) is eroded isotropically, but the erosion rate of the spiked BCB hardened portion is faster than that of the film-like BCB hardened portion. Therefore, by adjusting the time conditions, only the spiked BCB hardened portion can be removed.

[0090] Next, as shown in Figure 51, a passivation (PSV) film 42 of SiO2 or the like is formed on the surface to create a PSV patterned film. It is processed in such a way that the side of the exposed active layer 14 is covered and a portion of the first coating layer 13 and the second coating layer 15 are exposed (Figure 51).

[0091] Subsequently, as shown in Figure 52, an electrode 44 is formed on the exposed portion of the passivation film 42, and heat treatment is applied to achieve ohmic contact (Figure 52). [Example]

[0092] Hereinafter, embodiments and comparative examples are given to illustrate the present invention in detail, but the present invention is not limited thereto.

[0093] (Example 1) First, as shown in Figure 1, after depositing a GaAs buffer layer of the first conductivity type on the GaAs starter substrate 11, a 0.3 μm first etch stop layer of the first conductivity type Ga xIn 1-xP (0.4≦x≦0.6) and a 0.3 μm second etch stop layer of the first conductivity type GaAs are epitaxially grown to form a sacrificial layer 12. Further, an epitaxial wafer 20 (Figure 1) having a light-emitting element structure as a semiconductor functional layer (epithelial functional layer) 18 is prepared by sequentially growing a 1.0 μm first conductive type (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0<y≦1) first cladding layer 13, an undoped (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0≦y≦0.6) active layer 14, a 1.0 μm second conductive type (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0<y≦1) second cladding layer 15, a 0.1 μm second conductive type GaInP intermediate layer (not shown), and a 4 μm second conductive type GaP window layer 16.

[0094] Subsequently, a resist mask is formed using photolithography, and a dry etching method using chlorine plasma is used to etch from the first cladding layer 13 to the GaP window layer 16 to perform the device separation step of forming the device separation trench 21 (Figure 2).

[0095] Subsequently, a SiO2 film is formed on the surface of the window layer 16 and inside the element separation trench 21 as a passivation film 22 (Figure 3), and the passivation film 22 (SiO2 film) is removed in the area outside the element separation trench 21 (Figure 4).

[0096] Next, benzocyclobutene (BCB), serving as a thermosetting bonding material 24, is spin-coated onto the epitaxial wafer 20 (Figure 5). This is then overlapped with the sapphire wafer 31, the substrate to be bonded, and a bonding substrate (epithelial bonding substrate) 30 is fabricated by thermoforming. The epitaxial wafer 20 and the sapphire wafer 31 are bonded together with BCB 24 in between. When spin-coating BCB, the designed film thickness is 0.6 μm (Figure 6). After reaching the softening point of BCB, i.e., temperature 150°C, the temperature is lowered to room temperature for bonding. Next, the SiO 2 film inside the element separation trench 21 is etched using a fluorine-based solution (Figure 7). Then, the sacrificial layer 12 is etched using a fluorine-based solution to peel off the GaAs starting substrate 11 (Figure 8). Subsequently, a mask is formed using photolithography, and a portion of the second coating layer 15 is exposed using a dry etching method with chlorine-based plasma (Figure 9).

[0097] Subsequently, a SiO2 film is formed on the surface as a passivation film 42, and the process is carried out in such a way that the end of the separation trench 21 of the element is covered, the side of the exposed active layer 14 is exposed, and a portion of the first coating layer 13 and the second coating layer 15 are exposed (Figure 10).

[0098] Subsequently, at the exposed portion of the passivation film 42, i.e., the SiO2 film, an AuBe alloy layer is disposed in a region of 0.1 μm near the P-type layer, and an AuGe alloy layer is disposed in a region of 0.2 μm near the N-type layer to serve as electrode 44. Ohmic contact is achieved by applying heat treatment (Figure 11).

[0099] (Example 2) First, as shown in Figure 12, after depositing a GaAs buffer layer of the first conductivity type on the GaAs starter substrate 11, a 0.3 μm first etch stop layer of the first conductivity type Ga xIn 1-xP (0.4≦x≦0.6) and a 0.3 μm second etch stop layer of the first conductivity type GaAs are epitaxially grown to form a sacrificial layer 12. Further, an epitaxial wafer 20 (Figure 12) having a light-emitting element structure as a semiconductor functional layer (epithelial functional layer) 18 is prepared by sequentially growing a 1.0 μm first conductive type (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0<y≦1) first cladding layer 13, an undoped (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0≦y≦0.6) active layer 14, a 1.0 μm second conductive type (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0<y≦1) second cladding layer 15, a 0.1 μm second conductive type GaInP intermediate layer (not shown), and a 4 μm second conductive type GaP window layer 16.

[0100] Subsequently, a mask is formed by photolithography, and the device separation step of forming the device separation trench 21 is performed by etching from the first cladding layer 13 to the GaP window layer 16 using a dry etching method with chlorine plasma (Figure 13).

[0101] Next, benzocyclobutene (BCB) is spin-coated on the epitaxial wafer 20 to supply BCB to the surface and the interior of the component separation trench 21 (Figure 14), and heat is applied at 250°C for 1 hour to harden the BCB film (hardening bonding material 25).

[0102] Subsequently, by photolithography, a portion of the hardened bonding material 25 (hardened BCB portion) of the element separation groove 21 is removed to expose the sacrificial layer 12 (Figure 15).

[0103] Then, a SiO2 film is formed on the surface of the window layer 16 and inside the element separation trench 21 as a passivation film 22 (Figure 16), and the passivation film 22 (SiO2 film) is removed in the area outside the element separation trench 21 (Figure 17).

[0104] Next, benzocyclobutene (BCB), serving as a thermosetting bonding material 24, is spin-coated onto the epitaxial wafer 20 (Figure 18). This is then overlapped with the sapphire wafer 31, which is the substrate to be bonded, and a bonding substrate (epithelial bonding substrate) 50 is fabricated by thermoforming. This substrate is formed by bonding the epitaxial wafer 20 and the sapphire wafer 31 with BCB 24 in between. When spin-coating BCB, the designed film thickness is 0.6 μm (Figure 19).

[0105] Subsequently, the SiO2 film inside the element separation trench 21 is etched using a fluorine-based solution (Figure 21).

[0106] Next, the sacrificial layer 12 is etched using a fluorine-based solution to remove the GaAs starting substrate 11 (Figure 21). A mask is formed using photolithography, and a portion of the second coating layer 15 is exposed using a dry etching method using chlorine-based plasma (Figure 22).

[0107] Then, the hardened bonding material 25 (BCB hardened part) that has become spiked is removed by a liquid flow with a pressure of about 5 kgf / cm 2 (Figure 23).

[0108] A SiO2 film is formed on the surface as a passivation film 42, and the process is performed in such a way that it covers the side of the exposed active layer 14 and exposes a portion of the first coating layer 13 and the second coating layer 15 (Figure 24).

[0109] Subsequently, at the exposed portion of the passivation film 42, i.e., the SiO2 film, an AuBe alloy layer is disposed in a region 0.1 μm near the P-type layer, and an AuGe alloy layer is disposed in a region 0.2 μm near the N-type layer to serve as electrode 44. Ohmic contact is achieved by applying heat treatment (Figure 25).

[0110] (Example 3) First, as shown in Figure 26, after depositing a GaAs buffer layer of the first conductivity type on the GaAs starter substrate 11, a 0.3 μm first etch stop layer of the first conductivity type Ga xIn 1-xP (0.4≦x≦0.6) and a 0.3 μm second etch stop layer of the first conductivity type GaAs are epitaxially grown to form a sacrificial layer 12. Further, an epitaxial wafer 20 (Figure 26) having a light-emitting element structure as a semiconductor functional layer (epithelial functional layer) 18 is prepared by sequentially growing a 1.0 μm first conductive type (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0<y≦1) first cladding layer 13, an undoped (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0≦y≦0.6) active layer 14, a 1.0 μm second conductive type (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0<y≦1) second cladding layer 15, a 0.1 μm second conductive type GaInP intermediate layer (not shown), and a 4 μm second conductive type GaP window layer 16.

[0111] A device separation step (Fig. 27) is performed by forming a mask using photolithography and etching from the first cladding layer 13 to the GaP window layer 16 using a dry etching method with chlorine plasma to form the device separation trench 21.

[0112] Benzocyclobutene (BCB) is spin-coated on the epitaxial wafer 20, thereby supplying BCB to the surface and a portion of the interior of the component separation trench 21 (Figure 28), and the BCB film is hardened (hardened bonding material 25) by applying heat at 250°C for 1 hour.

[0113] A mask is formed by photolithography, and a portion of the hardened bonding material 25 (hardened BCB portion) of the component separation trench 21 is removed by dry etching using chlorine plasma to expose the sacrificial layer 12 (Figure 29).

[0114] Then, a SiO2 film is formed on the surface of the window layer 16 and inside the element separation trench 21 as a passivation film 22 (Figure 30), and the passivation film 22 (SiO2 film) is removed in the area outside the element separation trench 21 (Figure 31).

[0115] Next, benzocyclobutene (BCB), serving as a thermosetting bonding material 24, is spin-coated onto the epitaxial wafer 20 (Figure 32). This is then overlapped with the substrate 31 (sapphire wafer) to be bonded, and a bonding substrate (epithelial bonding substrate) 60 is fabricated by thermoforming. This substrate is formed by bonding the epitaxial wafer 20 and the sapphire wafer 31 with BCB 24 in between. When spin-coating BCB, the designed film thickness is 0.6 μm (Figure 33).

[0116] Subsequently, the passivation film 22 (SiO 2 film) inside the element separation trench 21 is etched using a fluorine-based solution (Figure 34).

[0117] Subsequently, the sacrificial layer 12 is etched using a fluorine-based solution to remove the GaAs starting substrate 11 (Figure 35).

[0118] Subsequently, a mask is formed using photolithography, and a portion of the second coating layer 15 is exposed using a dry etching method using chlorine-based plasma (Figure 36).

[0119] A SiO2 film is formed on the surface as a passivation film 42, and the process is performed in such a way that the end of the element separation trench 21, the side of the exposed active layer 14 are covered, and a portion of the first coating layer 13 and the second coating layer 15 are exposed (Figure 37).

[0120] Subsequently, at the exposed portion of the passivation film 42, i.e., the SiO2 film, an AuBe alloy layer is disposed in a region of 0.1 μm near the P-type layer, and an AuGe alloy layer is disposed in a region of 0.2 μm near the N-type layer to serve as electrode 44. Ohmic contact is achieved by applying heat treatment (Figure 38).

[0121] (Example 4) First, as shown in Figure 39, after depositing a GaAs buffer layer of the first conductivity type on the GaAs starter substrate 11, a 0.3 μm first etch stop layer of the first conductivity type Ga xIn 1-xP (0.4≦x≦0.6) and a 0.3 μm second etch stop layer of the first conductivity type GaAs are epitaxially grown to form a sacrificial layer 12. Further, an epitaxial wafer 20 (Figure 39) having a light-emitting element structure as a semiconductor functional layer (epithelial functional layer) 18 is prepared by sequentially growing a 1.0 μm first conductive type (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0<y≦1) first cladding layer 13, an undoped (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0≦y≦0.6) active layer 14, a 1.0 μm second conductive type (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0<y≦1) second cladding layer 15, a 0.1 μm second conductive type GaInP intermediate layer (not shown), and a 4 μm second conductive type GaP window layer 16.

[0122] A device separation step (Figure 40) is performed by forming a mask using photolithography and etching from the first cladding layer 13 to the GaP window layer 16 using a dry etching method with chlorine plasma to form the device separation trench 21.

[0123] Benzocyclobutene (BCB) is spin-coated on the epitaxial wafer 20 to supply BCB to the surface and the interior (walls) of the component separation trench 21 (Figure 41). The BCB film is hardened (hardened bonding material 25) by applying heat at 250°C for 1 hour.

[0124] A mask is formed by photolithography, and a portion of the hardened bonding material 25 (hardened BCB portion) of the component separation trench 21 is removed by dry etching using chlorine plasma to expose the sacrificial layer 12 (Figure 42).

[0125] Subsequently, a SiO2 film is formed as a passivation film 22 by coating a sacrificial layer 12 on the surface of the window layer 16 and the element separation trench 21 (Figure 43), and the passivation film 22 (SiO2 film) is removed in the area outside the element separation trench 21 (Figure 44).

[0126] Next, benzocyclobutene (BCB), serving as a thermosetting bonding material 24, is spin-coated onto the epitaxial wafer 20, thereby supplying BCB to the surface and a portion of the interior of the component separation trench 21 (Figure 45). This BCB is then overlapped with the substrate 31 (sapphire wafer) to be bonded, and a bonding substrate (epithelial bonding substrate) 70 is fabricated by thermoforming. This substrate is formed by bonding the epitaxial wafer 20 and the sapphire wafer 31 with BCB 24 in between. When spin-coating BCB, the designed film thickness is 0.6 μm (Figure 46).

[0127] Subsequently, the passivation film 22 (SiO 2 film) inside the element separation trench 21 is etched using a fluorine-based solution (Figure 47).

[0128] Subsequently, the sacrificial layer 12 is etched using a fluorine-based solution to remove the GaAs starting substrate 11 (Figure 48).

[0129] Subsequently, a shield is formed, and a portion of the second coating layer 15 is exposed using a dry etching method using chlorine-based plasma (Figure 49).

[0130] Subsequently, the hardened BCB portion that had become spiked was removed by a liquid flow with a pressure of about 5 kgf / cm 2 (Figure 50).

[0131] A SiO2 film is formed on the surface as a passivation film 42, and the process is performed in such a way that the exposed active layer side is covered and a portion of the first coating layer 13 and the second coating layer 15 are exposed (Figure 51).

[0132] Subsequently, at the exposed portion of the passivation film 42, i.e., the SiO2 film, an AuBe alloy layer is disposed in a region of 0.1 μm near the P-type layer, and an AuGe alloy layer is disposed in a region of 0.2 μm near the N-type layer to serve as an electrode 44. Ohmic contact is achieved by applying heat treatment (Figure 52).

[0133] (Comparative Example) As shown in Figure 53, after depositing a GaAs buffer layer of the first conductivity type on the GaAs starter substrate 111, a 0.3 μm first etch stop layer of the first conductivity type Ga xIn 1-xP (0.4≦x≦0.6) and a 0.3 μm second etch stop layer of the first conductivity type GaAs are epitaxially grown to form a sacrificial layer 12. Further, an epitaxial wafer 120 (Figure 53) with a light-emitting element structure having a semiconductor functional layer (epithelial functional layer) 118 is prepared by sequentially growing a 1.0 μm first conductive type (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0<y≦1) first cladding layer 113, an undoped (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0≦y≦0.6) active layer 114, a 1.0 μm second conductive type (Al yGa 1-y) xIn 1-xP (0.4≦x≦0.6, 0<y≦1) second cladding layer 115, a 0.1 μm second conductive type GaInP intermediate layer (not shown), and a 4 μm second conductive type GaP window layer 116.

[0134] A mask is formed using photolithography, and a dry etching method using chlorine-based plasma is used to etch from the first cladding layer 113 to the GaP window layer 116 to perform the device separation step of forming the device separation trench 121 (Figure 54). Here, the surface 112a of the sacrificial layer 112 is exposed.

[0135] Next, BCB122 is spin-coated onto the sapphire wafer 131 (Figure 55), and then overlapped with the epitaxial wafer on which the component separation trench 121 is formed and thermo-pressed to create an epitaxial bonding substrate, which is formed by bonding the epitaxial wafer and the sapphire wafer with BCB in between. When spin-coating BCB, the film thickness is designed to be 0.6 μm (Figure 56).

[0136] During bonding, the amount of BCB bonding agent 122 that penetrates the element separation trench 121 cannot be controlled, so there will be some buried areas, and on the other hand, there will be areas where the BCB bonding agent 122 is buried up to the surface of the exposed sacrificial layer 112 (see Figure 56).

[0137] The GaAs starter substrate 111 and the epitaxial layer are separated by removing the sacrificial layer 112 using wet etching. The BCB binder 122 covers the part separation trench 121 so that no sacrificial layer etching penetrates, and therefore the sacrificial layer 112 is not etched and is partially retained (Figure 57). The partially retained sacrificial layer is marked as symbol 162.

[0138] When the GaAs start substrate 111 is peeled off from the epitaxial layer, a portion of the GaAs start substrate 111 in the unetched area of ​​the sacrificial layer 112 will remain (Figure 58). The portion of the start substrate that is partially remaining is marked as symbol 161.

[0139] Subsequently, a portion of the BCB122 of the buried element separation trench 121 is removed to form a separation trench (Figure 59).

[0140] A portion of the first coating layer 113 and the active layer 114 is removed to expose the second coating layer 115 (Figure 60). After exposing the second coating layer 115, the BCB bonding agent 122, which has become spiked, is selectively removed using a burr-like method (Figure 61). Subsequently, a passivation (PSV) film 42 of SiO2 or the like is formed on the surface, and the process is performed in such a way that the separation end of the element, the side of the exposed active layer 114, and a portion of the first coating layer 113 and the second coating layer 115 are exposed (Figure 62). At this time, a portion 192 of SiO2 adheres to the remaining starting substrate 161.

[0141] Next, at the exposed portion of the SiO2 film, an AuBe alloy layer is formed in a region of 0.1 μm near the P-type layer, and an AuGe alloy layer is formed in a region of 0.2 μm near the N-type layer to serve as electrode 144. An ohmic contact is achieved by applying heat treatment (Figure 63). At this time, a portion 194 of the electrode material adheres to the remaining starting substrate 161.

[0142] (Comparison between the Example and the Comparative Example) After etching the sacrificial layer, the area where the starting substrate (GaAs) does not adhere to the epitaxial layer and the epitaxial layer is completely separated from the starting substrate is defined as the area of ​​good quality, and the ratio of this area to the designed area is set as the yield. Then, Figure 64 shows the comparison between the Example and the Comparative Example.

[0143] As shown in Figure 61, when implemented in the embodiments, areas with good peel quality exceeding 90% are displayed. On the other hand, in the comparative examples, the yield is significantly reduced. This difference in yield is also due to the difference in the time required for the sacrificial layer to be etched due to the presence of component separation trenches. In all embodiments with separation trenches, the sacrificial layer etching time is less than 1 hour. On the other hand, in the comparative examples, the sacrificial layer etching time requires tens of hours at room temperature.

[0144] In this embodiment, the etchant can easily penetrate through the component separation trench, so etching is performed simultaneously across the entire wafer. As a result, the sacrificial layer experiences less stress during the etching process, and the epitaxial layer is less likely to be damaged. Therefore, the yield after sacrificial layer etching is good.

[0145] On the other hand, in the comparative example, etching is performed from the outer periphery of the wafer, which can easily apply biased stress to the epitaxial layer during the etching of the sacrificial layer. As a result, cracks are more likely to form in the epitaxial layer, leading to a decrease in yield.

[0146] Furthermore, the present invention is not limited to the embodiments described above. The embodiments described above are examples, and all those that have substantially the same structure and perform the same function as the technical concept described in the claims of the present invention are included in the technical scope of the present invention. [Simplified Explanation of the Diagram]

[0024] Figure 1 is a schematic cross-sectional view showing a portion of a first embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 2 is a schematic cross-sectional view showing another portion of the first embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 3 is a schematic cross-sectional view showing another portion of the first embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 4 is a schematic cross-sectional view showing another portion of the first embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 5 is a schematic cross-sectional view showing another portion of the first embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 6 is a schematic cross-sectional view showing another portion of the first embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 7 is a schematic cross-sectional view showing another portion of the first embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 8 is a schematic cross-sectional view showing another portion of the first embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 9 is a schematic cross-sectional view showing another portion of the first embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 10 is a schematic cross-sectional view showing another part of the first embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 11 is a schematic cross-sectional view showing an example of a bonding semiconductor wafer obtained using the first embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 12 is a schematic cross-sectional view showing a part of the second embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 13 is a schematic cross-sectional view showing another part of the second embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 14 is a schematic cross-sectional view showing another part of the second embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 15 is a schematic cross-sectional view showing another part of the second embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 16 is a schematic cross-sectional view showing another part of the second embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 17 is a schematic cross-sectional view showing another part of the second embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 18 is a schematic cross-sectional view showing another part of the second embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 19 is a schematic cross-sectional view showing another portion of a second embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 20 is a schematic cross-sectional view showing another portion of a second embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 21 is a schematic cross-sectional view showing another portion of a second embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 22 is a schematic cross-sectional view showing another portion of a second embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention.Figure 23 is a schematic cross-sectional view showing another part of the second embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 24 is a schematic cross-sectional view showing another part of the second embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 25 is a schematic cross-sectional view showing an example of a bonding semiconductor wafer obtained using the second embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 26 is a schematic cross-sectional view showing a part of the third embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 27 is a schematic cross-sectional view showing another part of the third embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 28 is a schematic cross-sectional view showing another part of the third embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 29 is a schematic cross-sectional view showing another part of the third embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 30 is a schematic cross-sectional view showing another part of the third embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 31 is a schematic cross-sectional view showing another part of the third embodiment of the bonding semiconductor wafer manufacturing method of the present invention. Figure 32 is a schematic cross-sectional view showing another portion of the third embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 33 is a schematic cross-sectional view showing another portion of the third embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 34 is a schematic cross-sectional view showing another portion of the third embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 35 is a schematic cross-sectional view showing another portion of the third embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 36 is a schematic cross-sectional view showing another portion of the third embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 37 is a schematic cross-sectional view showing another portion of the third embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 38 is a schematic cross-sectional view showing an example of a bonding-type semiconductor wafer obtained using the third embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 39 is a schematic cross-sectional view showing a portion of the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 40 is a schematic cross-sectional view showing another portion of the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 41 is a schematic cross-sectional view showing another portion of the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 42 is a schematic cross-sectional view showing another portion of the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 43 is a schematic cross-sectional view showing another portion of the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 44 is a schematic cross-sectional view showing another portion of the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention.Figure 45 is a schematic cross-sectional view showing another part of the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 46 is a schematic cross-sectional view showing another part of the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 47 is a schematic cross-sectional view showing another part of the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 48 is a schematic cross-sectional view showing another part of the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 49 is a schematic cross-sectional view showing another part of the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 50 is a schematic cross-sectional view showing another part of the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 51 is a schematic cross-sectional view showing another part of the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 52 is a schematic cross-sectional view showing an example of a bonding-type semiconductor wafer obtained using the fourth embodiment of the method for manufacturing a bonding-type semiconductor wafer according to the present invention. Figure 53 is a schematic cross-sectional view showing a portion of the manufacturing method of the bonding semiconductor wafer of the comparative example. Figure 54 is a schematic cross-sectional view showing another portion of the manufacturing method of the bonding semiconductor wafer of the comparative example. Figure 55 is a schematic cross-sectional view showing another portion of the manufacturing method of the bonding semiconductor wafer of the comparative example. Figure 56 is a schematic cross-sectional view showing another portion of the manufacturing method of the bonding semiconductor wafer of the comparative example. Figure 57 is a schematic cross-sectional view showing another portion of the manufacturing method of the bonding semiconductor wafer of the comparative example. Figure 58 is a schematic cross-sectional view showing another portion of the manufacturing method of the bonding semiconductor wafer of the comparative example. Figure 59 is a schematic cross-sectional view showing another portion of the manufacturing method of the bonding semiconductor wafer of the comparative example. Figure 60 is a schematic cross-sectional view showing another portion of the manufacturing method of the bonding semiconductor wafer of the comparative example. Figure 61 is a schematic cross-sectional view showing another portion of the manufacturing method of the bonding semiconductor wafer of the comparative example. Figure 62 is a schematic cross-sectional view showing another part of the manufacturing method of the bonding semiconductor wafer of the comparative example. Figure 63 is a schematic cross-sectional view showing an example of the bonding semiconductor wafer obtained by the manufacturing method of the bonding semiconductor wafer of the comparative example. Figure 64 is a graph showing the yield of Examples 1 to 4 and the comparative example. [Biomaterial Storage]

[0148] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A method for manufacturing a bonding semiconductor wafer, characterized by comprising the following steps: an epitaxial growth step, wherein a sacrificial layer is epitaxially grown on a starting substrate; a step for fabricating an epitaxial wafer, wherein an epitaxial layer having a semiconductor functional layer is epitaxially grown on the aforementioned sacrificial layer, thereby fabricating an epitaxial wafer; a step for forming a device separation trench, wherein a device separation trench is formed by selective etching to expose the aforementioned sacrificial layer in a portion of the aforementioned epitaxial wafer; a step for forming a passivation film, wherein a passivation film is formed on at least the surface of the aforementioned device separation trench where the aforementioned sacrificial layer is exposed; a step for fabricating a bonding substrate, wherein the aforementioned epitaxial layer of the aforementioned epitaxial wafer is bonded to a bonding substrate that is transparent to visible light through a thermosetting bonding material, thereby fabricating a bonding substrate; an etching and removal step, wherein the aforementioned passivation film of the aforementioned bonding substrate is etched and removed; and a separation step, wherein an etching solution is supplied to the aforementioned device separation trench of the aforementioned bonding substrate to etch the aforementioned sacrificial layer, thereby separating the aforementioned starting substrate and the aforementioned epitaxial layer.

2. The method for manufacturing a bonding-type semiconductor wafer as described in claim 1, wherein, The aforementioned substrate to be bonded is made of any one of the following materials: sapphire, synthetic quartz, quartz, glass, SiC, LiTaO3, and LiNbO3.

3. The method for manufacturing a bonding-type semiconductor wafer as described in claim 1, wherein, The aforementioned thermosetting bonding material is one or more of the following materials: silicone resin, epoxy resin, benzocyclobutene, spin-coated glass, polyimide, and fluororesin.

4. The method for manufacturing a bonding-type semiconductor wafer as described in claim 2, wherein, The aforementioned thermosetting bonding material is one or more of the following materials: silicone resin, epoxy resin, benzocyclobutene, spin-coated glass, polyimide, and fluororesin.

5. A method for manufacturing a bonding-type semiconductor wafer as described in claim 1, wherein, The thickness of the aforementioned thermosetting bonding material is set to be above 0.01 μm and below 0.6 μm.

6. A method for manufacturing a bonding-type semiconductor wafer as described in claim 2, wherein, The thickness of the aforementioned thermosetting bonding material is set to be above 0.01 μm and below 0.6 μm.

7. A method for manufacturing a bonding-type semiconductor wafer as described in claim 3, wherein, The thickness of the aforementioned thermosetting bonding material is set to be above 0.01 μm and below 0.6 μm.

8. A method for manufacturing a bonding-type semiconductor wafer as described in claim 4, wherein, The thickness of the aforementioned thermosetting bonding material is set to be above 0.01 μm and below 0.6 μm.

9. A method for manufacturing a bonding-type semiconductor wafer as described in any one of claims 1 to 8, wherein, The aforementioned thermosetting bonding materials were not thermosetting.

10. A method for manufacturing a bonding-type semiconductor wafer as described in any one of claims 1 to 8, wherein, The aforementioned passivation film is set as a silicon oxide film.

11. A method for manufacturing a bonding-type semiconductor wafer as described in any one of claims 1 to 8, wherein, The aforementioned bonding semiconductor wafer is used to make a miniature light-emitting diode.

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