Semiconductor memory device

Abstract

A semiconductor memory device includes: a wire stack including a plurality of first wires stacked on the substrate in a direction perpendicular to the surface of the substrate; conductive pads extending laterally from the edges of the first wires; and contact plugs coupled to the conductive pads.

Description

Technical Field

[0001] Embodiments of the present invention relate to a semiconductor device, and more specifically, to a semiconductor memory device including a three-dimensional (3D) memory cell. Intersection of related applications

[0002] This application claims priority to Korean Patent Application No. 10-2021-0160546, filed on November 19, 2021, the entirety of which is incorporated herein by reference. Prior Technology

[0003] To increase the net die size of memory devices, the size of memory cells has been reduced. With the miniaturization of memory cells, it is necessary to reduce parasitic capacitance (Cb) and increase capacitance. However, due to structural limitations of memory cells, it is difficult to increase the net die size.

[0004] Recently, a three-dimensional semiconductor memory device comprising three-dimensionally arranged memory cells has been proposed. Summary of the Invention

[0005] Embodiments of the present invention relate to a semiconductor memory device comprising highly integrated memory cells.

[0006] According to one embodiment of the present invention, a semiconductor memory device includes: a wire stack including a plurality of first wires stacked on the substrate in a direction perpendicular to the surface of the substrate; conductive pads extending laterally from the edges of the first wires; and contact plugs coupled to the conductive pads.

[0007] According to another embodiment of the present invention, a semiconductor memory device includes: a plurality of active layers stacked vertically on a substrate; bit lines commonly coupled to a first end of the active layers and extending in a direction perpendicular to the surface of the substrate; capacitors respectively coupled to a second end of the active layers; word line stacks including stacked double word lines extending laterally in a direction intersecting each of the active layers; word line pads extending laterally from the edges of each of the double word lines; and contact plugs respectively coupled to the word line pads.

[0008] According to another embodiment of the present invention, a semiconductor memory device includes: a plurality of bit lines that are vertically stacked in a first direction and laterally oriented in a second direction intersecting the first direction; bit line pads that extend laterally from the edges of the bit lines; contact plugs that are respectively coupled to the bit line pads; an active layer that is laterally oriented from the bit lines in a third direction intersecting the first and second directions; word lines that are vertically oriented in the first direction, and the active layer is inserted between the word lines; and capacitors that are respectively coupled to the ends of the active layer.

[0009] According to one embodiment of the present invention, a semiconductor memory device may include: dual conductors stacked on a substrate in a first direction, each of the dual conductors including a first sub-conductor and a second sub-conductor that are parallel to and spaced apart from each other; a conductive pad extending laterally from a first end of each of the first sub-conductors in a second direction; contact plugs extending from the landing surface of the conductive pads in the first direction; and an active layer inserted between the first and second sub-conductors of each of the dual conductors, wherein the length of the conductive pads gradually varies in the first direction. Simple Explanation of the Diagram

[0010] [Figure 1] is a schematic perspective view showing a semiconductor memory device according to an embodiment of the present invention.

[0011] [Figure 2] is a schematic plan view illustrating a semiconductor memory device according to an embodiment of the present invention.

[0012] [Figure 3] is a cross-sectional view taken along line A-A' shown in Figure 2.

[0013] [Figure 4] is a cross-sectional view taken along line B-B' shown in Figure 3.

[0014] Figures 5 through 7 are schematic cross-sectional views illustrating semiconductor memory devices according to other embodiments of the present invention.

[0015] [Figure 8] is a schematic plan view illustrating a semiconductor memory device according to another embodiment of the present invention.

[0016] [Figure 9] and [Figure 10] are schematic cross-sectional views illustrating a semiconductor memory device according to another embodiment of the present invention.

[0017] [Figure 11A] and [Figure 11B] are schematic perspective views illustrating a semiconductor memory device according to another embodiment of the present invention.

[0018] [Figure 12A] and [Figure 12B] are schematic perspective views illustrating a semiconductor memory device according to another embodiment of the present invention. Implementation

[0019] Embodiments of the invention will now be described in more detail with reference to the accompanying drawings. However, the invention may be embodied in different forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to make this disclosure comprehensive and complete, and to fully convey the scope of the invention to those skilled in the art. Throughout this disclosure, the same reference numerals refer to the same parts in various figures and embodiments of the invention.

[0020] The accompanying drawings are not necessarily drawn to scale, and in some cases, the scale may have been exaggerated to clearly show the features of the embodiments. When the first layer is referred to as being "on" the second layer or "on" the substrate, it refers not only to the case where the first layer is formed directly on the second layer or the substrate, but also to the case where the third layer exists between the first layer and the second layer or the substrate.

[0021] According to the embodiments of the present invention described below, the density of memory cells can be increased and parasitic capacitance can be reduced by vertically stacking memory cells.

[0022] Figure 1 is a schematic perspective view illustrating a semiconductor memory device according to an embodiment of the present invention. Figure 2 is a schematic plan view illustrating a semiconductor memory device according to an embodiment of the present invention. Figure 3 is a cross-sectional view taken along line A-A' shown in Figure 2. Figure 4 is a cross-sectional view taken along line B-B' shown in Figure 2.

[0023] Referring to Figures 1 to 4, a three-dimensional semiconductor memory device 100 according to an embodiment of the present invention may include: a wire stack WLS comprising a plurality of first wires DWL1 to DWL4 stacked on the substrate SUB in a direction perpendicular to the surface of the substrate SUB; conductive pads WLP extending laterally from the edges of the first wires DWL1 to DWL4 respectively; contact plugs WC respectively coupled to the conductive pads WLP; second wires BL extending on the substrate SUB in a direction perpendicular to the surface of the substrate SUB; and an active layer ACT laterally oriented in a direction intersecting with the first wires DWL1 to DWL4. Each of the first wires DWL1 to DWL4 may include a pair of first sub-wires WL1 and second sub-wires WL2.

[0024] Semiconductor memory device 100 may include an array of memory cells of dynamic random access memory (DRAM). Hereinafter, first conductors DWL1 to DWL4 may correspond to double word lines DWL1 to DWL4, and second conductor BL may correspond to bit line BL. The conductor stack WLS may be simply referred to as the word line stack WLS, and the conductive pad WLP may be simply referred to as the word line pad WLP. The first sub-conductor WL1 and the second sub-conductor WL2 may be referred to as the first word line WL1 and the second word line WL2. Therefore, each of the double word lines DWL1 to DWL4 may include a pair of first word lines WL1 and second word lines WL2.

[0025] The semiconductor memory device 100 may include bit lines BL, transistors TR, and capacitors CAP. The transistor TR may include an active layer ACT and a double word line DWL, wherein the double word line DWL may include a first word line WL1 and a second word line WL2 opposite to each other, and the active layer ACT is interposed between the first word line WL1 and the second word line WL2. The capacitor CAP may include a memory node SN, a dielectric layer DE, and a board node PN.

[0026] The bit line BL can be cylindrical, extending in a first direction D1. The active layer ACT can be a long strip extending in a second direction D2, intersecting the first direction D1. The double word line DWL can be linear, extending in a third direction D3, intersecting the first and second directions D1. The plate node PN of the capacitor CAP can be coupled to the plate line PL.

[0027] The bit line BL can be vertically oriented in the first direction D1. The bit line BL can be referred to as a vertically oriented bit line or a cylindrical bit line. The bit line BL can include a conductive material. The bit line BL can include silicon-based materials, metal-based materials, or combinations thereof. The bit line BL can include silicon, metal, metal nitride, metal silicate, or combinations thereof. The bit line BL can include polycrystalline silicon, titanium nitride, tungsten, or combinations thereof. For example, the bit line BL can include polycrystalline silicon or titanium nitride (TiN) doped with N-type impurities. The bit line BL can include a TiN / W stack comprising titanium nitride and tungsten on top of titanium nitride.

[0028] The dual word line (DWL) can extend considerably in the third direction (D3), and the active layer (ACT) can extend in the second direction (D2). The active layer (ACT) can be arranged laterally from the bit line (BL) in the second direction (D2). The dual word line (DWL) can include a pair of word lines, namely, a first word line (WL1) and a second word line (WL2). The first word line (WL1) and the second word line (WL2) can face each other in the first direction (D1), and the active layer (ACT) is interposed between the first word line (WL1) and the second word line (WL2). The gate dielectric layer (GD) can be formed on the upper and lower surfaces of the active layer (ACT).

[0029] The active layer ACT can comprise a semiconductor material or an oxide semiconductor material. For example, the active layer ACT can comprise silicon, germanium, silicon-germanium, or indium gallium zinc oxide (IGZO). The active layer ACT can comprise polycrystalline silicon or monocrystalline silicon. The active layer ACT can comprise: a channel CH, a first source / drain region SR between the channel CH and the bit line BL, and a second source / drain region DR between the channel CH and the capacitor CAP. The channel CH can be defined between the first source / drain region SR and the second source / drain region DR.

[0030] The first source / drain region SR and the second source / drain region DR can be doped with impurities of the same conductivity type. The first source / drain region SR and the second source / drain region DR can be doped with N-type impurities or P-type impurities. The first source / drain region SR and the second source / drain region DR can include at least one impurity selected from arsenic (As), phosphorus (P), boron (B), indium (In), and combinations thereof.

[0031] The transistor TR can be a single-cell transistor and can have a dual-word line (DWL). In the dual-word line DWL, the first word line WL1 and the second word line WL2 can have the same potential. For example, the first word line WL1 and the second word line WL2 can form a pair, and the same word line drive voltage can be applied to the first word line WL1 and the second word line WL2. As described above, according to an embodiment of the present invention, the transistor TR can have a dual-word line DWL, wherein the first word line WL1 and the second word line WL2 are arranged adjacent to a channel CH.

[0032] According to another embodiment of the present invention, the first word line WL1 and the second word line WL2 may have different potentials. For example, a word line driving voltage may be applied to the first word line WL1, and a ground voltage may be applied to the second word line WL2. The second word line WL2 may be referred to as a back word line or a masked word line. According to another embodiment of the present invention, a ground voltage may be applied to the first word line WL1, and a word line driving voltage may be applied to the second word line WL2.

[0033] The active layer ACT can have a thickness less than that of the first word line WL1 and the second word line WL2. In other words, the vertical thickness of the active layer ACT in the first direction D1 can be thinner than the vertical thickness of each of the first word line WL1 and the second word line WL2 in the first direction D1. The thin active layer ACT can be referred to as a thin-body active layer. The thin active layer ACT may include a thin-body channel CH, and the thin-body channel CH can have a thickness of approximately 10 nm or less. According to another embodiment of the invention, the channel CH can have the same vertical thickness as the first word line WL1 and the second word line WL2.

[0034] The upper and lower surfaces of the active layer ACT can be flat. In other words, the upper and lower surfaces of the active layer ACT can be parallel to each other in the second direction D2.

[0035] The gate dielectric layer (GD) may include silicon oxide, silicon nitride, metal oxides, metal nitrides, metal silicates, high-k materials, ferroelectric materials, antiferroelectric materials, or combinations thereof. The gate dielectric layer (GD) may include SiO₂, Si₃N₄, HfO₂, Al₂O₃, ZrO₂, AlON, HfON, HfSiO, HfSiON, or HfZrO.

[0036] Double word line (DWL) materials can include metals, metal mixtures, metal alloys, or semiconductor materials. Double word line DWL materials can include titanium nitride, tungsten, polycrystalline silicon, or combinations thereof. For example, a double word line DWL can include a TiN / W stack of titanium nitride and tungsten stacked sequentially. Double word line DWL materials can include N-type work function materials or P-type work function materials. N-type work function materials can have a low work function of approximately 4.5 eV or less, while P-type work function materials can have a high work function of approximately 4.5 eV or greater.

[0037] A capacitor CAP can be laterally disposed from a transistor TR in the second direction D2. The capacitor CAP may include a storage node SN extending laterally from the active layer ACT in the second direction D2. The capacitor CAP may also include a plate node PN and a dielectric layer DE above the storage node SN. The storage node SN, dielectric layer DE, and plate node PN can be laterally arranged in the second direction D2. The storage node SN may have a laterally oriented cylindrical shape. The dielectric layer DE may conformally cover the inner and outer walls of the cylindrical storage node SN. The plate node PN may have a shape extending above the dielectric layer DE to the inner and outer walls of the cylindrical storage node SN. The plate nodes PN of the capacitor CAP can be coupled to each other, and the plate nodes PN can be coupled to a plate line PL. The plate nodes PN and the plate line PL can be collectively referred to as a shared plate node. The storage node SN can be electrically connected to a second source / drain region DR.

[0038] The storage node SN can have a three-dimensional structure, and the three-dimensional storage node SN can have a lateral three-dimensional structure oriented in the second direction D2. As an example of a three-dimensional structure, the storage node SN can be cylindrical. According to another embodiment of the invention, the storage node SN can be cylindrical or pylinder-shaped. Pylinder-shaped can refer to a structure combining cylindrical and pylinder shapes.

[0039] A board node PN can include internal nodes and external nodes. Internal and external nodes can be coupled to each other. Internal nodes can be located inside the cylindrical memory node SN. External nodes can be located outside the cylindrical memory node SN, with a dielectric layer DE inserted between the external node and the memory node SN. External nodes can be configured to surround the outer wall of the cylindrical memory node SN.

[0040] Storage nodes (SN) and board nodes (PN) can include metals, noble metals, metal nitrides, conductive metal oxides, conductive noble metal oxides, metal carbides, metal silicides, or combinations thereof. For example, storage nodes (SN) and board nodes (PN) can include: titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), ruthenium (Ru), ruthenium oxide (RuO₂), iridium (Ir), iridium oxide (IrO₂), platinum (Pt), molybdenum (Mo), molybdenum oxide (MoO), titanium nitride / tungsten nitride (TiN / W) stacks, and tungsten nitride / tungsten nitride (WN / W) stacks. Board nodes (PN) can include combinations of metal-based and silicon-based materials. For example, a board node (PN) can be a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack. In a titanium nitride / silicon germanium / tungsten nitride (TiN / SiGe / WN) stack, silicon germanium can be the gap filler material filling the interior of the cylindrical storage node SN on top of titanium nitride, and titanium nitride (TiN) can be used as the plate node (PN) of the capacitor CAP, and tungsten nitride can be a low-resistance material.

[0041] The dielectric layer DE can be referred to as a capacitor dielectric layer. The dielectric layer DE can include silicon oxide, silicon nitride, high-k materials, or combinations thereof. High-k materials can have a higher dielectric constant than silicon oxide. Silicon oxide (SiO₂) can have a dielectric constant of approximately 3.9, and the dielectric layer DE can include high-k materials with a dielectric constant of approximately 4 or greater. High-k materials can have a dielectric constant of approximately 20 or greater. High-k materials can include: hafnium oxide (HfO₂), zirconium oxide (ZrO₂), aluminum oxide (Al₂O₃), lanthanum oxide (La₂O₃), titanium oxide (TiO₂), tantalum oxide (Ta₂O₅), niobium oxide (Nb₂O₅), or strontium titanium oxide (SrTiO₃). According to another embodiment of the invention, the dielectric layer DE can be formed from a composite layer comprising two or more layers of the aforementioned high-k materials.

[0042] The dielectric layer DE can be formed from a zirconium (Zr)-based oxide. The dielectric layer DE can have a stacked structure comprising at least zirconium oxide (ZrO₂). The stacked structure comprising zirconium oxide (ZrO₂) can include a ZA (ZrO₂ / Al₂O₃) stack or a ZAZ (ZrO₂ / Al₂O₃ / ZrO₂) stack. The ZA stack can have a structure in which alumina (Al₂O₃) is stacked on top of zirconium oxide (ZrO₂). The ZAZ stack can have a structure in which zirconium oxide (ZrO₂), alumina (Al₂O₃), and zirconium oxide (ZrO₂) are stacked sequentially. The ZA and ZAZ stacks can be referred to as a zirconium oxide (ZrO₂) base layer. According to another embodiment of the invention, the dielectric layer DE can be formed from a hafnium (Hf)-based oxide. The dielectric layer DE can have a stacked structure comprising at least hafnium oxide (HfO₂). Stacked structures including hafnium oxide (HfO₂) can include HA (HfO₂ / Al₂O₃) stacks or HAH (HfO₂ / Al₂O₃ / HfO₂) stacks. HA stacks can have a structure where alumina (Al₂O₃) is stacked on top of hafnium oxide (HfO₂). HAH stacks can have a structure where hafnium oxide (HfO₂), alumina (Al₂O₃), and hafnium oxide (HfO₂) are stacked sequentially. HA and HAH stacks can be referred to as hafnium oxide (HfO₂) substrates. In ZA, ZAZ, HA, and HAH stacks, alumina (Al₂O₃) can have a larger band gap energy (hereinafter referred to as band gap) than zirconium oxide (ZrO₂) and hafnium oxide (HfO₂). Alumina (Al₂O₃) can have a lower dielectric constant than zirconium oxide (ZrO₂) and hafnium oxide (HfO₂). Therefore, the dielectric layer DE can include a stack of high-k materials and high-bandgap materials having a larger bandgap than the high-k materials. The dielectric layer DE can include silicon oxide (SiO₂) as a high-bandgap material other than alumina (Al₂O₃). Because the dielectric layer DE includes high-bandgap materials, leakage current can be suppressed. The high-bandgap materials can be thinner than the high-k materials. According to another embodiment of the invention, the dielectric layer DE can include a laminated structure in which high-k materials and high-bandgap materials are stacked alternately. For example, ZAZA(ZrO 2 / Al 2O 3 / ZrO 2 / Al 2O 3) stacked components, ZAZAZ(ZrO 2 / Al 2O 3 / ZrO 2 / Al 2O 3 / ZrO 2) stacked components, HAHA(HfO 2 / Al 2O 3 / HfO 2 / Al 2O 3) stacked components, or HAHAH(HfO 2 / Al 2O 3 / HfO 2 / Al 2O 3 / HfO 2) stacked components.In the above laminated structure, aluminum oxide (Al₂O₃) can be thinner than zirconium oxide (ZrO₂) and hafnium oxide (HfO₂).

[0043] According to another embodiment of the present invention, the dielectric layer DE may include a stacked structure, a laminated structure, or a hybrid structure including zirconium oxide, hafnium oxide and aluminum oxide.

[0044] According to another embodiment of the present invention, the dielectric layer DE may include a ferroelectric material or an antiferroelectric material.

[0045] According to another embodiment of the invention, an interface control layer (not shown) for improving leakage current can be further formed between the storage node SN and the dielectric layer DE. The interface control layer may include titanium oxide (TiO2), niobium oxide, or niobium nitride. The interface control layer may also be formed between the plate node PN and the dielectric layer DE.

[0046] Capacitors (CAP) can include metal-insulator-metal (MIM) capacitors. Storage nodes (SN) and board nodes (PN) can include metal-based materials.

[0047] Capacitors (CAPs) can be replaced by other data storage materials. For example, the data storage material can be a phase change material, a magnetic tunnel junction (MTJ), or a variable resistance material.

[0048] Referring back to Figures 1, 2, and 3, the semiconductor memory device 100 may include a word line stack (WLS), and the word line stack (WLS) may include a plurality of dual word lines (DWL1 to DWL4). The dual word lines DWL1 to DWL4 may be stacked vertically in a first direction D1. The dual word lines DWL1 to DWL4 may extend laterally in a third direction D3.

[0049] Semiconductor memory device 100 may include a memory cell array MCA and a contact region CA. Word line stacks (WLS) may be located within the memory cell array MCA, and word line pads (WLP) may be located within the contact region CA. The memory cell array MCA may include a plurality of memory cells, which may be vertically stacked in a first direction D1. Each memory cell may include a bit line (BL), a transistor (TR), and a capacitor (CAP). In the memory cell array MCA, a plurality of transistors (TR) may be stacked in the first direction D1. In the memory cell array MCA, a plurality of capacitors (CAP) may be stacked in the first direction D1. In the memory cell array MCA, the bit line (BL) may extend vertically in the first direction D1. In the memory cell array MCA, dual word lines (DWL1 to DWL4) may extend laterally in a third direction D3.

[0050] Referring back to Figure 3, the word line pad portion WLP may include a first edge portion VL and a second edge portion ST. The first edge portion VL of the word line pad portion WLP may be coupled to the end of the word line stack WLS, and the second edge portion ST of the word line pad portion WLP may have a stepped shape. Multiple word line pads WLP1 to WLP4 may be located in the contact area CA. The word line pads WLP1 to WLP4 may extend laterally in the third direction D3. The lateral length may gradually increase from the lowermost word line pad WLP1 to the uppermost word line pad WLP4. Contact plugs WC may be coupled to word line pads WLP1 to WLP4 respectively, and metal wires ML may be coupled to contact plugs WC respectively. The edges of the dual word lines DWL1 to DWL4 may be self-aligned at the same vertical level. Here, the same vertical level may correspond to the first edge portion VL of the word line pad portion WLP. The first edge portions VL of word line pads WLP1 to WLP4 can be self-aligned at the same vertical level. An interlayer dielectric layer ILD can be located between the dual word lines DWL1 to DWL4. The dual word lines DWL1 to DWL4 can have the same lateral length in the third direction D3. Word line pads WLP1 to WLP4 can have different lateral lengths in the third direction D3. The first word line WL1 and the second word line WL2 of each of the dual word lines DWL1 to DWL4 can be thinner than the word line pads WLP1 to WLP4. For example, when comparing the vertical height in the first direction D1, the first word line WL1 and the second word line WL2 can have a thickness less than the thickness of the word line pads WLP1 to WLP4. Each of the word line pads WLP1 to WLP4 can have a height that couples the first word line WL1 and the second word line WL2 to each other. An interlayer dielectric layer ILD can be located between the vertically stacked word line pads WLP1 to WLP4.

[0051] Word line pads WLP1 to WLP4 can be coupled to the ends of double word lines DWL1 to DWL4, respectively. For example, the first double word line DWL1 can be coupled to the first word line pad WLP1, and the second double word line DWL2 can be coupled to the second word line pad WLP2. The third double word line DWL3 can be coupled to the third word line pad WLP3, and the fourth double word line DWL4 can be coupled to the fourth word line pad WLP4. Word line pads WLP1 to WLP4 can also be coupled to the first word line WL1 and the second word line WL2 simultaneously, respectively.

[0052] As mentioned above, the word line resistance can be increased due to the formation of a thick word line pad (WLP).

[0053] The semiconductor memory device 100 may further include a substrate SUB, and the substrate SUB may include peripheral circuitry. The bit lines BL of the memory cell array MCA may be oriented perpendicular to the surface of the substrate SUB in a first direction D1, and the double word lines DWL may be oriented parallel to the surface of the substrate SUB in a third direction D3.

[0054] The peripheral circuitry can be located at a lower level than the memory cell array (MCA) and the contact area (CA). This can be referred to as a Cell over Periphery (COP) structure. The peripheral circuitry may include at least one control circuit for driving the memory cell array (MCA). The at least one control circuit of the peripheral circuitry may include an N-channel transistor, a P-channel transistor, a CMOS circuit, or a combination thereof. The at least one control circuit of the peripheral circuitry may include an address decoder circuit, a read circuit, a write circuit, etc. The at least one control circuit of the peripheral circuitry may include a planar channel transistor, a concave channel transistor, a buried gate transistor, a FinFET, etc.

[0055] According to another embodiment of the present invention, in the semiconductor memory device 100, the peripheral circuitry portion may be located at a higher level than the memory cell array (MCA). This may be referred to as a periphery over cell (POC) structure.

[0056] Figure 5 is a schematic cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention. In Figure 5, detailed descriptions of the constituent elements that also appear in Figures 1 to 4 will be omitted.

[0057] Referring to Figure 5, the semiconductor memory device 110 may include a word line stack (WLS), which may include multiple dual word lines (DWL1 to DWL4). The dual word lines DWL1 to DWL4 may be stacked vertically in a first direction D1. The dual word lines DWL1 to DWL4 may also extend laterally in a third direction D3.

[0058] The semiconductor memory device 110 may include a memory cell array MCA and a contact area CA. A word line stack WLS may be located in the memory cell array MCA, and a word line pad WLP10 may be located in the contact area CA.

[0059] The word line pad portion WLP10 may include a first edge portion VL and a second edge portion ST. The first edge portion VL of the word line pad portion WLP10 may be coupled to the end of the word line stack WLS, and the second edge portion ST of the word line pad portion WLP10 may have a stepped shape. Multiple word line pads WLP1 to WLP4 may be located in the contact area CA. The word line pads WLP1 to WLP4 may extend laterally in the third direction D3. The lateral length of the word line pads WLP1 to WLP4 may gradually decrease from the bottommost word line pad WLP1 to the topmost word line pad WLP4. Contact plugs WC may be coupled to the word line pads WLP1 to WLP4 respectively, and metal lines ML may be coupled to the contact plugs WC respectively. The edges of the dual word lines DWL1 to DWL4 may be self-aligned in the same vertical level. An interlayer dielectric layer ILD may be located between the dual word lines DWL1 to DWL4. The dual word lines DWL1 to DWL4 may have the same lateral length in the third direction D3. The word line pads WLP1 to WLP4 may have different lateral lengths in the third direction D3. The first word line WL1 and the second word line WL2 of each of the dual word lines DWL1 to DWL4 may be thinner than the word line pads WLP1 to WLP4. For example, when comparing the vertical height in the first direction D1, the first word line WL1 and the second word line WL2 may have a thickness less than the thickness of the word line pads WLP1 to WLP4. Each of the word line pads WLP1 to WLP4 may have a height that couples the first word line WL1 and the second word line WL2 to each other. An interlayer dielectric layer (ILD) may be located between the vertically stacked word line pads WLP1 to WLP4.

[0060] Word line pads WLP1 to WLP4 can be coupled to the ends of double word lines DWL1 to DWL4, respectively. For example, the first double word line DWL1 can be coupled to the first word line pad WLP1, the second double word line DWL2 can be coupled to the second word line pad WLP2, the third double word line DWL3 can be coupled to the third word line pad WLP3, and the fourth double word line DWL4 can be coupled to the fourth word line pad WLP4. Each of the word line pads WLP1 to WLP4 can be simultaneously coupled to the first word line WL1 and the second word line WL2 of the corresponding double word lines DWL1 to DWL4.

[0061] Each of the word line pads WLP1 to WLP4 may further include a metal liner TL and a metal bulk WB. The metal liner TL and the metal bulk WB may be electrically coupled to the edges of the dual word lines DWL1 to DWL4. The metal liner TL may be directly coupled to the edges of the dual word lines DWL1 to DWL4. The metal liner TL may include titanium nitride, and the metal bulk WB may include tungsten. The contact plug WC may directly contact the metal liner TL. The first word line WL1 and the second word line WL2 of the dual word lines DWL1 to DWL4 may directly contact the metal liner TL.

[0062] Figure 6 is a schematic cross-sectional view illustrating a semiconductor memory device 120 according to another embodiment of the present invention. In Figure 6, detailed descriptions of the constituent elements that also appear in Figures 1 to 5 will be omitted.

[0063] Referring to Figure 6, the semiconductor memory device 120 may include a word line stack (WLS), and the word line stack (WLS) may include a plurality of dual word lines (DWL1 to DWL4). The dual word lines (DWL1 to DWL4) may be stacked vertically in a first direction D1. The dual word lines (DWL1 to DWL4) may extend laterally in a third direction D3.

[0064] The semiconductor memory device 120 may include a memory cell array MCA and a contact area CA. A word line stack WLS may be located in the memory cell array MCA, and a word line pad WLP20 may be located in the contact area CA.

[0065] The word line pad portion WLP20 may include a first edge portion VL and a second edge portion ST. The first edge portion VL of the word line pad portion WLP20 may be coupled to the end of the word line stack WLS, and the second edge portion ST of the word line pad portion WLP20 may have a stepped shape. Multiple word line pads WLP1 to WLP4 may be located in the contact area CA. The word line pads WLP1 to WLP4 may extend laterally in the third direction D3. The lateral length may gradually decrease from the lowermost word line pad WLP1 to the uppermost word line pad WLP4. Contact plugs WC may be coupled to the word line pads WLP1 to WLP4 respectively, and metal lines ML may be coupled to the contact plugs WC respectively. The edges of the dual word lines DWL1 to DWL4 may be self-aligned in the same vertical level. An interlayer dielectric layer ILD may be located between the dual word lines DWL1 to DWL4. The dual word lines DWL1 to DWL4 may have the same lateral length in the third direction D3. The word line pads WLP1 to WLP4 may have different lateral lengths in the third direction D3. The first word line WL1 and the second word line WL2 of each of the dual word lines DWL1 to DWL4 may be thinner than the word line pads WLP1 to WLP4. For example, when comparing the vertical height in the first direction D1, the thickness of the first word line WL1 and the second word line WL2 may be less than the thickness of the word line pads WLP1 to WLP4. Each of the word line pads WLP1 to WLP4 may have a height that couples the first word line WL1 and the second word line WL2 to each other. An interlayer dielectric layer (ILD) may be located between the vertically stacked word line pads WLP1 to WLP4.

[0066] Each of the word line pads WLP1 through WLP4 can be coupled to the end of each of the double word lines DWL1 through DWL4. For example, the first double word line DWL1 can be coupled to the first word line pad WLP1, and the second double word line DWL2 can be coupled to the second word line pad WLP2. The third double word line DWL3 can be coupled to the third word line pad WLP3, and the fourth double word line DWL4 can be coupled to the fourth word line pad WLP4. Each of the word line pads WLP1 through WLP4 can be simultaneously coupled to the first word line WL1 and the second word line WL2 of the corresponding double word lines DWL1 through DWL4.

[0067] Each of the word line pads WLP1 to WLP4 may include a protrusion PP and a landing portion LP. The protrusion PP may be coupled to the edge of the double word lines DWL1 to DWL4. For example, the protrusion PP may extend into the gap between the edge of the first word line WL1 and the edge of the second word line WL2. A contact plug WC may be coupled to the landing portion LP. The height of the landing portion LP may be greater than the gap between the edge of the first word line WL1 and the edge of the second word line WL2 (i.e., the vertical thickness of the protrusion).

[0068] Figure 7 is a schematic cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention. In Figure 7, detailed descriptions of the constituent elements that also appear in Figures 1 to 6 will be omitted.

[0069] Referring to Figure 7, the semiconductor memory device 130 may include a word line stack (WLS), and the word line stack (WLS) may include a plurality of dual word lines (DWL1 to DWL4). The dual word lines (DWL1 to DWL4) may be stacked vertically in a first direction D1. The dual word lines (DWL1 to DWL4) may extend laterally in a third direction D3.

[0070] The semiconductor memory device 130 may include a memory cell array MCA and a contact area CA. A word line stack WLS may be located in the memory cell array MCA, and a word line pad WLP30 may be located in the contact area CA.

[0071] The word line pad portion WLP30 may include a first edge portion VL and a second edge portion ST. The first edge portion VL of the word line pad portion WLP30 may be coupled to the end of the word line stack WLS, and the second edge portion ST of the word line pad portion WLP30 may have a stepped shape. Multiple word line pads WLP1 to WLP4 may be located in the contact area CA. The word line pads WLP1 to WLP4 may extend laterally in the third direction D3. The lateral length may gradually decrease from the lowermost word line pad WLP1 to the uppermost word line pad WLP4. Contact plugs WC may be coupled to the word line pads WLP1 to WLP4 respectively, and metal lines ML may be coupled to the contact plugs WC respectively. The edges of the dual word lines DWL1 to DWL4 may be self-aligned in the same vertical level. An interlayer dielectric layer ILD may be located between the dual word lines DWL1 to DWL4. The dual word lines DWL1 to DWL4 may have the same lateral length in the third direction D3. The word line pads WLP1 to WLP4 may have different lateral lengths in the third direction D3. The first word line WL1 and the second word line WL2 of each of the dual word lines DWL1 to DWL4 may be thinner than the word line pads WLP1 to WLP4. For example, when comparing the vertical height in the first direction D1, the first word line WL1 and the second word line WL2 may have a thickness less than the thickness of the word line pads WLP1 to WLP4. Each of the word line pads WLP1 to WLP4 may have a height that couples the first word line WL1 and the second word line WL2 to each other. An interlayer dielectric layer (ILD) may be located between the vertically stacked word line pads WLP1 to WLP4.

[0072] Each of the word line pads WLP1 through WLP4 can be coupled to the end of each of the double word lines DWL1 through DWL4. For example, the first double word line DWL1 can be coupled to the first word line pad WLP1, and the second double word line DWL2 can be coupled to the second word line pad WLP2. The third double word line DWL3 can be coupled to the third word line pad WLP3, and the fourth double word line DWL4 can be coupled to the fourth word line pad WLP4. Word line pads WLP1 through WLP4 can be coupled to both the first word line WL1 and the second word line WL2 simultaneously.

[0073] Each of the word line pads WLP1 to WLP4 may include a protrusion PP and a landing portion LP. The protrusion PP may be coupled to the edge of the dual word lines DWL1 to DWL4. For example, the protrusion PP may extend into the space between the edge of the first word line WL1 and the edge of the second word line WL2. A contact plug WC may be coupled to the landing portion LP.

[0074] Each of the word line pads WLP1 to WLP4 may further include a metal liner TL and a metal block WB. The metal liner TL and the metal block WB may be electrically coupled to the edges of the dual word lines DWL1 to DWL4. The metal liner TL may be directly coupled to the edges of the dual word lines DWL1 to DWL4. The metal liner TL may include titanium nitride, and the metal block WB may include tungsten. The contact plug WC may directly contact the metal liner TL. The first word line WL1 and the second word line WL2 of the dual word lines DWL1 to DWL4 may directly contact the metal liner TL.

[0075] Figure 8 is a schematic plan view illustrating a semiconductor memory device according to another embodiment of the present invention.

[0076] Referring to Figures 1, 2, 3, and 8, the semiconductor memory device 200 may include a word line stack (WLS), and the word line stack (WLS) may include a plurality of dual word lines (DWL1 to DWL4). The dual word lines (DWL1 to DWL4) may be stacked vertically in a first direction D1. The dual word lines (DWL1 to DWL4) may extend laterally in a third direction D3.

[0077] The semiconductor memory device 200 of Figure 8 may include a memory cell array MCA and a contact area CA. A word line stack WLS may be located in the memory cell array MCA, and a word line pad WLP' may be located in the contact area CA.

[0078] The letter line pad portion WLP' may include multiple letter line pads (WLP1 to WLP4 shown in Figure 3). From a top view perspective, the letter line pad portion WLP' may have a cross-shaped WLPE, thus ensuring the structural stability of the letter line pad portion WLP'.

[0079] According to the above embodiment, the resistance of the double letter lines can be increased because a thick letter line pad is formed.

[0080] To form word line pads WLP1 to WLP4, sacrificial material between interlayer dielectric layers (ILDs) can be removed from the contact region CA to form gaps, which can then be filled with a metallic material. Here, the sacrificial material can include nitrides, monocrystalline silicon, polycrystalline silicon, or combinations thereof. The interlayer dielectric layer (ILD) can include silicon oxide. For example, a method of forming word line pads WLP1 to WLP4 in the contact region CA can include: repeatedly forming a die stack wherein a first interlayer dielectric layer, a first sacrificial layer, a silicon layer, a second sacrificial layer, and a second interlayer dielectric layer are stacked in the aforementioned order; forming slots by etching the die stack; forming gaps by selectively removing the first sacrificial layer, the silicon layer, and the second sacrificial layer via the slots; and forming a metallic material to fill the gaps. A method for forming dual word lines DWL1 to DWL4 in a memory cell array (MCA) may include: repeatedly forming a die stack wherein a first interlayer dielectric layer, a first sacrificial layer, a silicon layer, a second sacrificial layer, and a second interlayer dielectric layer are stacked in the order stated therein; forming slits by etching the die stack; forming gaps in the upper and lower portions of the silicon layer by selectively removing portions of the first and second sacrificial layers via the slits; forming a gate dielectric layer on the silicon layer surface exposed by the gaps; and forming first word lines WL1 and second word lines WL2 to fill the gaps above the gate dielectric layer. After repeatedly forming the die stack, the dual word lines DWL1 to DWL4 of the memory cell array (MCA) may be formed, and then word line pads WLP1 to WLP4 may be formed in the contact region CA. In the die stack, the first and second sacrificial layers may include silicon-germanium layers.

[0081] Figure 9 is a schematic cross-sectional view illustrating a semiconductor memory device according to another embodiment of the present invention.

[0082] Referring to Figures 1, 2, 3, and 9, the semiconductor memory device 300 may include a word line stack (WLS), and the WLS may include multiple single word lines SWL1 to SWL4. The single word lines SWL1 to SWL4 may be vertically stacked in a first direction D1. The single word lines SWL1 to SWL4 may extend laterally in a third direction D3. A gate dielectric layer GD may be located between the single word lines SWL1 to SWL4 and the active layer ACT.

[0083] The semiconductor memory device 300 may include a memory cell array MCA and a contact area CA. A word line stack (WLS) may be located in the memory cell array MCA, and a word line pad (WLP) may be located in the contact area CA.

[0084] The word line pad portion WLP may include a first edge portion VL and a second edge portion ST. The first edge portion VL of the word line pad portion WLP may be coupled to the end of the word line stack WLS, and the second edge portion ST of the word line pad portion WLP may have a stepped shape. Multiple word line pads WLP1 to WLP4 may be located in the contact area CA. The word line pads WLP1 to WLP4 may extend laterally in the third direction D3. The lateral length may gradually decrease from the lowermost word line pad WLP1 to the uppermost word line pad WLP4. Contact plugs WC may be coupled to the word line pads WLP1 to WLP4 respectively, and metal wires ML may be coupled to the contact plugs WC respectively. The edges of the individual word lines SWL1 to SWL4 may be self-aligned in the same vertical level. An interlayer dielectric layer (not shown) may be located between the individual word lines SWL1 to SWL4. The individual word lines SWL1 to SWL4 may have the same lateral length in the third direction D3. The word line pads WLP1 to WLP4 may have different lateral lengths in the third direction D3. Each of the single word lines SWL1 to SWL4 may be thinner than the word line pads WLP1 to WLP4. For example, when comparing the vertical height in the first direction D1, the single word lines SWL1 to SWL4 may have a thickness less than that of the word line pads WLP1 to WLP4.

[0085] Figure 10 is a schematic cross-sectional view illustrating a semiconductor memory device 400 according to another embodiment of the present invention.

[0086] Referring to Figures 1, 2, 3, and 10, the semiconductor memory device 400 may include a word line stack (WLS), and the word line stack (WLS) may include a plurality of fully encircled gate word lines (GAA-WL1 to GAA-WL4). The fully encircled gate word lines GAA-WL1 to GAA-WL4 may be vertically stacked in a first direction D1. The fully encircled gate word lines GAA-WL1 to GAA-WL4 may extend laterally in a third direction D3. The fully encircled gate word lines GAA-WL1 to GAA-WL4 may surround the active layer ACT, and the gate dielectric layer GD may surround the active layer ACT.

[0087] The semiconductor memory device 400 may include a memory cell array MCA and a contact area CA. A word line stack (WLS) may be located in the memory cell array MCA, and a word line pad (WLP) may be located in the contact area CA.

[0088] The word line pad portion WLP may include a first edge portion VL and a second edge portion ST. The first edge portion VL of the word line pad portion WLP may be coupled to the end of the word line stack WLS, and the second edge portion ST of the word line pad portion WLP may have a stepped shape. Multiple word line pads WLP1 to WLP4 may be located in the contact area CA. The word line pads WLP1 to WLP4 may extend laterally in the third direction D3. The lateral length may gradually decrease from the lowermost word line pad WLP1 to the uppermost word line pad WLP4. Contact plugs WC may be coupled to the word line pads WLP1 to WLP4 respectively, and metal wires ML may be coupled to the contact plugs WC respectively. The edges of the fully encircling gate word lines GAA-WL1 to GAA-WL4 may be self-aligned in the same vertical level. An interlayer dielectric layer (not shown) may be located between the fully encircling gate word lines GAA-WL1 to GAA-WL4. The full-wrap gate word lines GAA-WL1 to GAA-WL4 can have the same lateral length in the third direction D3. The word line pads WLP1 to WLP4 can have different lateral lengths in the third direction D3. Each of the full-wrap gate word lines GAA-WL1 to GAA-WL4 can have the same vertical height as the word line pads WLP1 to WLP4.

[0089] Figures 11A and 11B are schematic perspective views illustrating a semiconductor memory device according to another embodiment of the present invention. Figure 11B is a partial perspective view of the double word line DWL1.

[0090] Referring to Figure 11A, the semiconductor memory device 500 may include: a plurality of bit lines stacked on a substrate (not shown) in a first direction D1 perpendicular to the surface of the substrate and laterally oriented in a second direction D2 intersecting the first direction D1; a bit line pad BLP extending laterally from the edge of the bit line BL; a contact plug coupled to the bit line pad BLP; an active layer ACT laterally oriented from the bit line BL in a third direction D3 intersecting the first direction D1 and the second direction D2; double word lines DWL1 to DWL4 vertically oriented in the first direction D1, wherein the active layer ACT is inserted between the double word lines DWL1 to DWL4; and a capacitor CAP coupled to an end of the active layer ACT.

[0091] Referring to Figure 11B, the first word line WL1 and the second word line WL2 can extend perpendicularly, and the active layer ACT is inserted between the first word line WL1 and the second word line WL2. In other words, the first word line WL1 and the second word line WL2 can be parallel to each other to form a double word line DWL1. A gate dielectric layer GD surrounding the active layer ACT can be formed between the active layer ACT and the double word line DWL1.

[0092] Figures 12A and 12B are schematic perspective views illustrating a semiconductor memory device 510 according to another embodiment of the present invention. Figure 12B is a partial perspective view showing the fully surrounding gate word line GAA-WL1.

[0093] Referring to Figure 12A, the semiconductor memory device 510 may include: a plurality of bit lines BL stacked on a substrate (not shown) in a first direction D1 perpendicular to the surface of the substrate and laterally oriented in a second direction D2 intersecting the first direction D1; bit line pads BLP extending laterally from the edges of the bit lines BL; contact plugs coupled to the bit line pads BLP; an active layer ACT laterally oriented from the bit lines BL in a third direction D3 intersecting the first direction D1 and the second direction D2; full-circle gate word lines GAA-WL1 to GAA-WL4 vertically oriented in the first direction D1; and a capacitor CAP coupled to an end of the active layer ACT. Contact plugs BC may be coupled to metal lines ML.

[0094] Referring to Figure 12B, a portion of the first word line WL1 can extend between the active layers ACT to contact the second word line WL2. In other words, the first word line WL1 and the second word line WL2 can be coupled to each other and integrated to form a fully encircling gate word line GAA-WL1. A gate dielectric layer GD surrounding the active layer ACT can be formed between the active layer ACT and the fully encircling gate word line GAA-WL1.

[0095] The bit line pads BLP in Figures 11A and 12A can be modified to have various shapes as shown in Figures 3, 5, 6, 7 and 8.

[0096] The semiconductor memory devices 500 and 510 of Figures 11A and 12A may include word lines of a single structure.

[0097] According to an embodiment of the present invention, the resistance of the word lines can be improved by forming a thick word line pad coupled to the edge of the double word lines.

[0098] The effects expected to be obtained by the embodiments of the present invention are not limited to the effects described above, and those skilled in the art to which this invention pertains can clearly understand from the above description other effects not mentioned above.

[0099] Although the invention has been described with reference to specific embodiments, it will be apparent to those skilled in the art that various changes and modifications may be made without departing from the spirit and scope of the invention as defined in the appended claims.

[0100] 100: Semiconductor memory devices 110: Semiconductor memory devices 120: Semiconductor memory device 130: Semiconductor memory devices 200: Semiconductor memory devices 300: Semiconductor memory devices 400: Semiconductor memory device 500: Semiconductor memory devices 510: Semiconductor memory devices A-A': line ACT: Active Layer B-B': line BC: Contact plug BL: Second Conductor / Bit Line BLP: Bitline Pad CA: Contact Area CAP: Capacitor CH: Channel D1: First Direction D2: Second Direction D3: Third direction DE: Dielectric layer DR: Second source / drain region DWL1: First Conductor / Double Character Line / First Double Character Line DWL2: First conductor / Double character line / Second double character line DWL3: First conductor / Double character line / Third double character line DWL4: First conductor / Double character line / Fourth double character line GAA-WL1: A fully encircling gate word line GAA-WL2: A fully encircling gate word line GAA-WL3: A fully encircling gate word line GAA-WL4: A fully encircling gate word line GD: Gate Dielectric Layer ILD: Interlayer Dielectric Layer LP: Landing section MCA: Memory Cell Array ML: Metal wire PERI: Surrounding Area PL: Board Line PN: Plate node PP: Protrusion SN: Storage Node SR: First Source / Drain Region ST: Second Edge SUB:Substrate SWL1: Single-line SWL2: Single-word line SWL3: Single-word line SWL4: Single-line TL: Metal Liner TR: Transistor VL: First edge WB: Metal block WC: Contact plug WL1: First Sub-Wire / First Word Line WL2: Second Sub-Wire / Second Word Line WLP: Conductive Pad / Line Pad WLP': Line Pad WLP1: Letter Pad / First Letter Pad WLP2: Letter Pad / Second Letter Pad WLP3: Letter Pad / Third Letter Pad WLP4: Letter Pad / Fourth Letter Pad WLP10: Line Pad WLP20: Line Pad WLP30: Line Pad WLPE: cross WLS: Wire Stacking / Word Line Stacking

Claims

1. A semiconductor memory device, comprising: A wire stack comprising a plurality of first wires stacked on the substrate in a direction perpendicular to the surface of the substrate; A conductive pad extending laterally from the edge of the first conductor; and a contact plug coupled to the conductive pad, wherein each first conductor includes a pair of first sub-conductors and second sub-conductors, and each conductive pad extends to be located in the gap between the edge of the first sub-conductor and the edge of the second sub-conductor.

2. The semiconductor memory device according to claim 1, wherein, The conductive pads have different lateral lengths.

3. The semiconductor memory device according to claim 1, wherein, The edge portion of the first conductor is self-aligned.

4. The semiconductor memory device according to claim 1, wherein, The edge portions of the first conductor are in direct contact with the conductive pad.

5. The semiconductor memory device according to claim 1, wherein, The conductive pad includes: a first edge portion coupled to the edge portion of the first wire; and a second edge portion coupled to the contact plug, wherein the second edge portion has a stepped shape.

6. The semiconductor memory device according to claim 1, wherein, Each of the first wire and the conductive pad comprises a metal-based material.

7. The semiconductor memory device according to claim 1, wherein, Each of the conductive pads further includes an inner liner and a bulk layer, with the inner liner directly contacting the edge portion of the first conductor.

8. The semiconductor memory device according to claim 1, wherein, Each of the conductive pads further includes a protrusion, and the protrusion has a shape that fills the gap between the edge portion of the first sub-conductor and the edge portion of the second sub-conductor.

9. The semiconductor memory device according to claim 1, wherein, Each of the conductive pads includes a landing portion and a protrusion, the landing portion being coupled to the contact plug, the protrusion being coupled to the edge portion of the first sub-conductor and the edge portion of the second sub-conductor, each protrusion being located in the gap between the edge portion of the first sub-conductor and the edge portion of the second sub-conductor, and the height of the landing portion being greater than the height of the gap between the edge portion of the first sub-conductor and the edge portion of the second sub-conductor.

10. The semiconductor memory device according to claim 1, further comprising: An active layer is laterally oriented in a direction parallel to the surface of the substrate, wherein the active layer is laterally spaced from the conductive pad and located between the first sub-conductor and the second sub-conductor.

11. The semiconductor memory device according to claim 10, further comprising: A second conductive wire is coupled to one side of the active layer and extends in a direction perpendicular to the surface of the substrate; And a capacitor, which is coupled to the other side of the active layer.

12. A semiconductor memory device, comprising: Multiple active layers are stacked vertically on a substrate; Bit lines, which are commonly coupled to the first end of the active layer and extend in a direction perpendicular to the surface of the substrate; A capacitor, each coupled to a second end of the active layer; a word line stack comprising stacked double word lines extending laterally in a direction intersecting each of the active layers; word line pads extending laterally from the edges of each double word line; and contact plugs coupled to the word line pads, wherein each double word line comprises a pair of first and second word lines, and each word line pad extends to be located in a gap between the edges of the first and second word lines.

13. The semiconductor memory device according to claim 12, wherein, The edge portion of the double-line is self-aligned.

14. The semiconductor memory device according to claim 12, wherein, The edge of the double letter line is in direct contact with the letter line pad.

15. The semiconductor memory device according to claim 12, wherein, The letter line pad includes: a first edge portion coupled to the edge portion of the double letter line; and a second edge portion coupled to the contact plug, wherein the second edge portion has a stepped shape.

16. The semiconductor memory device according to claim 12, wherein, Each of the double letter bar and the letter bar pad comprises a metal-based material.

17. The semiconductor memory device according to claim 12, wherein, Each of the word line pads also includes an inner liner layer and a block layer, with the inner liner layer directly contacting the edge of the double word line.

18. The semiconductor memory device according to claim 12, wherein, Each of the word line pads also includes a protrusion, and the protrusion has a shape that fills the gap between the edge portion of the first word line and the edge portion of the second word line.

19. The semiconductor memory device according to claim 12, wherein, Each of the word line pads includes: a landing portion coupled to the contact plug; and a protrusion coupled to the edge portion of the first word line and the edge portion of the second word line, wherein each protrusion is located in the gap between the edge portion of the first word line and the edge portion of the second word line, and the height of the landing portion is greater than the height of the gap between the edge portion of the first word line and the edge portion of the second word line.

20. The semiconductor memory device according to claim 12, wherein, The active layer is laterally spaced from the letter pad and is located between the first letter and the second letter.

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