Data processing device

Abstract

The purpose of this disclosure is to improve security. The data processing apparatus disclosed herein includes: a register having a setting area for storing setting information sent from a host, a storage data area for storing storage data for the setting information, and a communication information area for storing communication information between the host and the register, which serves as an address area; and a communication unit for performing register communication between the host and the register.

Description

Technical Field

[0001] This disclosure relates to a data processing device. Prior Technology

[0002] Regarding the transmission of image data from a camera connected to a network, there are technologies to improve security (for example, see Patent Documents 1 and 2). On the other hand, a register is provided in the camera to store various setting information related to the image sensor's shooting conditions, or various setting information related to the transmission of image data from the image sensor inside the camera to the host computer. [Previous Technical Documents] [Patent Literature]

[0003] [Patent Document 1] Japanese Patent Application Publication No. 2019-33368 [Patent Document 2] Japanese Patent Publication No. 2018-525866 Summary of the Invention

[0004] [The problem the invention aims to solve]

[0005] The goal is to develop a technology that improves the security of temporary communication between the image sensor and the host computer within the camera.

[0006] The aim is to provide a data processing device that can improve security. [Technical means to solve the problem]

[0007] The data processing apparatus of one embodiment of this disclosure includes: a register having a setting area for storing setting information sent from a host, a storage data area for storing data for storing the setting information, and a communication information area for storing communication information between the host and the host, which serves as an address area; and a communication unit for performing register communication between the host and the register.

[0008] In one embodiment of the data processing apparatus disclosed herein, there is a data storage area for storing data for storing setting information and a communication information area for storing communication information between the data processing apparatus and the host computer, which serves as the address area of ​​a temporary storage device for the data processing apparatus; and the temporary storage device communicates with the host computer. Simple Explanation of the Diagram

[0009] Figure 1 is a block diagram that schematically shows an example of the overall structure of a data transmission system according to one embodiment of this disclosure. Figure 2 is a schematic diagram illustrating a communication method using CRC (Cyclic Redundancy Check) codes as a general security and protection technique. Figure 3 is a schematic diagram illustrating a communication method that includes a message authentication code, serving as a general illustration of security and protection techniques. Figure 4 is a schematic diagram illustrating one example of encrypted communication as a general security and preservation technique. Figure 5 is an explanatory diagram showing an example of the configuration of a temporary register in one embodiment of the technology (temporary register diagram). Figure 6 is a sequence diagram showing an example of register communication in one embodiment of the technology. Figure 7 is a sequence diagram showing an example of temporary communication in one embodiment of the technology. Figure 8 is a sequence diagram showing an example of register communication when a portion of the communication information is omitted during transmission. Figure 9 is a sequence diagram showing an example of register communication when a portion of the communication information is omitted during transmission. Figure 10 is a block diagram schematically showing a first configuration example of a data processing device CIS as an implementation. Figure 11 is a block diagram showing a specific example of the write determination unit of the CIS shown in Figure 10. Figure 12 is a sequence diagram showing an example of register communication implemented using the configuration example shown in Figure 10. Figure 13 is a sequence diagram showing an example of register communication in one embodiment of the technology. Figure 14 is a block diagram schematically showing a second configuration example of a data processing device CIS as one embodiment. Figure 15 is a block diagram showing a specific example of the write determination unit of the CIS shown in Figure 14. Figure 16 is a sequence diagram showing an example of register communication in CRC mode implemented using the configuration example shown in Figure 15. Figure 17 is a sequence diagram showing an example of a temporary communication in an encrypted mode of a technology implementation. Figure 18 is a sequence diagram showing an example of register communication during readout using a specific implementation technique. Figure 19 is a sequence diagram showing an example of register communication during encrypted mode reading using a certain implementation of the technology. Figure 20 is a sequence diagram showing an example of temporary communication in one embodiment of the technology. Figure 21 is a sequence diagram showing an example of register communication for the operation of a write counter in a technology including one embodiment. Figure 22 is a sequence diagram showing an example of register communication for the operation of a read counter in a technology including one embodiment. Figure 23 is a sequence diagram showing an example of register communication for reading a counter in a technology including one embodiment. Figure 24 is a block diagram schematically showing a third configuration example of a data processing device CIS as one embodiment. Figure 25 is a sequence diagram showing an example of register communication in which the write counter of a technology including one embodiment operates. Figure 26 is a block diagram schematically showing the fourth configuration example of a data processing device CIS as one embodiment. Figure 27 is a sequence diagram showing an example of register communication in which the write counter of a technology including one embodiment operates. Figure 28 is an explanatory diagram showing a variation of the configuration of a temporary register in one embodiment of the technology (temporary register diagram). Figure 29 is a sequence diagram showing an example of register communication in which the write counter of a technology including one embodiment operates. Figure 30 is a sequence diagram showing an example of temporary communication in one embodiment of the technology. Figure 31 is a sequence diagram showing an example of temporary communication in one embodiment of the technology. Figure 32 is a sequence diagram showing an example of temporary communication in one embodiment of the technology. Figure 33 is a sequence diagram showing an example of register communication in which the write counter of a technology including one embodiment operates. Figure 34 is a sequence diagram showing an example of register communication in which the write counter of a technology including one embodiment operates. Figure 35 is a sequence diagram showing an example of temporary communication in one embodiment of the technology. Figure 36 is a sequence diagram showing an example of register communication in which the write counter of a technology including one embodiment operates. Figure 37 is a sequence diagram showing an example of temporary communication in one embodiment of the technology. Figure 38 is a sequence diagram showing an example of temporary communication in one embodiment of the technology. Figure 39 is a sequence diagram showing an example of register communication in which the write counter of a technology including one embodiment operates. Figure 40 is a sequence diagram showing an example of register communication involving the operation of a read counter and a write counter in a technology including one embodiment. Implementation

[0010] The following is a detailed description of the embodiments disclosed herein, with reference to the drawings. The description will proceed in the following order. 1. Implementation Form 1.1 Overall Structure and Problems of Data Transmission Systems (Figures 1-4) 1.2 Security and preservation technologies of one implementation form (Figures 5-40) 1.2.1 Overview of Security and Protection Technologies 1.2.2 Specific Examples of Security and Preservation Technologies 1.3 Effects 2. Other implementation forms

[0011] <1. Implementation Form> [1.1 Overall Structure and Problems of Data Transmission Systems] (Example of the overall structure of a data transmission system) Figure 1 schematically shows an example of the overall structure of a data transmission system according to one embodiment of this disclosure.

[0012] One implementation of the data transmission system is, for example, a technology for improving the security of temporary storage communication between the image sensor (CIS (Complementary Metal-Oxide Semiconductor) 1) inside the camera and the host 2.

[0013] One embodiment of the data transmission system includes a CIS1 as a data processing device, a host 2, a transmission path 3, and a transmission path 4.

[0014] CIS1 includes a communication unit 110, an upper layer 113, a communication unit 120, a data processing unit 123, and a sensor unit 124.

[0015] Communication unit 110 has a physical layer (PHY) 111 and a link layer (LINK) 112. Communication unit 120 has a physical layer (PHY) 121 and a link layer (LINK) 122.

[0016] The upper layer 113 includes a temporary register 130, a CPU (Central Processing Unit) 131, and hardware (HW) 132. Alternatively, the upper layer 113 can be configured to omit the CPU 131.

[0017] The host 2 includes a communication unit 210, an upper layer 213, a communication unit 220, and a data processing unit 223.

[0018] Communication unit 210 has a physical layer (PHY) 211 and a link layer (LINK) 212. Communication unit 220 has a physical layer (PHY) 221 and a link layer (LINK) 222.

[0019] The upper layer 213 has a temporary register 230, a CPU 231, and hardware (HW) 232.

[0020] Generally speaking, CIS1 has: a communication IF (Interface) (snapshot IF), which uses CIS1 as a slave device and the host 2 as a master device for communication; and a high-speed IF (data output IF), which outputs large data such as image data acquired by the sensor unit 124.

[0021] The communication unit 110 of CIS1 and the communication unit 110 of host 2 respectively constitute a communication IF (scrambled register IF) that enables communication between their respective scratchpads 130 and 230 via transmission path 3 (scrambled register communication). The scratchpad IF can also carry multiple IFs with different protocols, and multiple IFs can be switched to form a configuration. For example, it can also carry two types of IFs, SPI (Serial Peripheral Interface) and I2C (Inter Integrated Circuit), and can be switched to form a configuration.

[0022] The communication unit 120 of CIS1 constitutes a high-speed IF (data output IF) that outputs large amounts of data, such as image data, obtained from the sensor unit 124 to the communication unit 220 of the host 2 via the transmission path 4. Examples of high-speed IFs include MIPI (Mobile Industry Processor Interface), SLVS-EC (Scalable Low Voltage Signaling with Embedded Clock), and SLVS (Scalable Low Voltage Signaling).

[0023] The CIS1's register 130 stores setting information sent from the host 2 via register IF. The processing actions of each component within the CIS1 are determined based on the values ​​set in register 130 as setting information. This setting information includes, for example, exposure time, gain, resolution (pixel addition, line skipping), frame rate, ROI (Region of Interest), and other operating modes. Furthermore, the CIS1's register 130 stores various state information and environmental information within the CIS1. This state information and environmental information stored in register 130 can be read from the host 2 via register IF. Examples of this state information and environmental information include, for example, the internal temperature information of the CIS1, metadata from image information from sensor unit 124 processed by data processing unit 123, and error or alarm detection information.

[0024] In host 2, the upper layer 213 determines the behavior of CIS1 and sends the value of the behavior determined by the register IF as setting information. Host 2 changes the value of the setting information based on various status information or environmental information read from the register 130 of CIS1. Since the behavior of CIS1 varies depending on the use case, the SW (software) of CPU 231 of host 2 is usually configured to be relatively easy to rewrite. When the upper layer 213 is configured as an FPGA (Field Programmable Gate Array), both CPU 231 and hardware 232 become variable configurations.

[0025] By standardizing the specifications of the physical layers 111 and 211 or the link layers 112 and 212 that constitute the register IF, communication between CIS1 and host 2 can be achieved without considering the physical layer. For example, the specific parts of the physical layer 113 and 213 only need to determine the style (address and value definition) of registers 130 and 230. For instance, the method of sending setting information in the register IF can be standardized as a style of the physical layers 111 and 211 or the link layers 112 and 212. Therefore, as long as the upper layers 113 and 213 define the addresses of registers 130 and 230 and the actions when setting values ​​for register 130, control information or other information can be exchanged between CIS1 and host 2 via the register IF.

[0026] (General security and protection technologies) Figure 2 illustrates a typical example of communication supplemented with CRC (Error Detection Code) as a general security and protection technique.

[0027] Functions that detect data reversals caused by electromagnetic noise include CRC (Error Detection) and ECC (Error Correction). For example, in CRC, in addition to the data of the communication object, a CRC code is added to determine if the data has not been reversed. On the data output side, a CRC code is generated based on the data, appended to the CRC code generated on the data, and output. On the data input side, a CRC code is generated based on the input data, compared with the CRC code appended to the data, thereby determining whether the data is reversed.

[0028] Figure 3 illustrates a typical example of communication with a Message Authentication Code (MAC) attached, as a general security and protection technique.

[0029] There are technologies that attach MCA or signatures to detect data tampering or fraudulent data transmission. For communications requiring real-time processing, such as IF communications, MAC (signatures can also be used) is generally employed. When using MAC, a common encryption private key K (KB) is used on both the data output and data input sides. On the data output side, a MAC is generated using the common encryption private key K (KB), appended to the data of the communication target, and then output. Depending on the MAC algorithm, IV (Initialization Vector) information is also appended and output. For example, in the case of CMAC (Cipher-based Message Authentication Code), IV information is not needed because it is calculated using IV0, but in the case of GMAC (Galois Message Authentication Code), IV information is appended and output. On the data input side, a MAC is generated using the common encryption private key K (KB), compared with the MAC appended to the data, thereby authenticating the data.

[0030] Figure 4 illustrates a general example of encrypted communication as a common security and preservation technique.

[0031] To prevent data from being viewed by others, encryption technology is sometimes used. In cases where encryption is used, for example, a common encryption private key K (KB) is used on both the data output and data input sides. On the data output side, the common encryption private key K (KB) and the IV (Initialization Vector) are used to encrypt the data of the communicating party, generating encrypted data which is then output. On the data input side, the common encryption private key K (KB) and the IV are used to decode the encrypted data.

[0032] (question) For example, in the data transmission system configuration shown in Figure 1, security requirements for CIS1 begin to appear, but not all CIS1 customers have the same security requirements. Furthermore, it is difficult to simultaneously modify industrial machines and other products with longer lifespans to make the host 2 (FPGA or ASIC) compatible with the CIS1 security protocol for all products. The register IF can carry multiple IFs with different protocols, and can be configured by switching between multiple IFs. However, in this case, it is necessary to maintain the security of the register IF without changing the protocols of each IF. The required functions vary depending on the application integrated into CIS1. As mentioned above, security technologies include CRC, MAC, and encryption, each providing different functions. If the register IF protocol is defined differently for each required function, it is difficult to expand the technology, requiring continuous updates to the physical layer 111, 211 or link layer 112, 212 protocols of the register IF based on the content, incurring costs.

[0033] Therefore, it is desired to implement security and protection functions within the existing specifications and styles of the temporary register IF. It is hoped that the security and protection functions of the temporary register IF can be achieved through style changes to the upper-level layers 113 and 213 (which offer a higher degree of freedom and can be implemented by modifying the software or adding hardware 132, 232, etc.) rather than the temporary register IF itself. This will improve security while maintaining the existing temporary register IF functionality.

[0034] [1.2 Security and preservation technologies of an implementation form] Next, details of the security and protection technologies of a data transmission system in one implementation form will be explained.

[0035] (1.2.1 Overview of Security and Protection Technologies) Figure 5 shows an example of the configuration of a temporary register 130 in one embodiment (temporary register diagram). Furthermore, the addresses shown in Figure 5 are an example and can be changed as needed.

[0036] The register 130 of CIS1 has a setting area (sensor register 311) for storing setting information sent from the host 2, which serves as an address area. In one embodiment, in addition to the sensor register 311, it further has a security data area (functional safety and security data area 313) for storing data for storing setting information, and a communication information area (communication information register 312) for storing communication information between the host 2, which serves as a security and security address area.

[0037] In one embodiment, security and protection address areas in register 130 are used between CIS1 and host 2 to exchange security and protection information in upper layers 113 and 213. This can be configured by selecting or subsequently changing the functions corresponding to the objects that can be connected to the existing register IF, allowing security and protection checks to be performed in upper layers 113 and 213, rather than being determined by the rules of the register IF protocol. Another embodiment may also have the function of determining whether an address area is for security and protection, or the function of selecting whether to access the address area for security and protection.

[0038] The functional safety and security data area 313, as described later, may, for example, store error detection codes (CRC codes) or message authentication codes (MAC codes) related to configuration information, as security data. Furthermore, the functional safety and security data area 313, as described later, may, for example, store encrypted data containing configuration information, as security data. The functional safety and security data area 313 may, for example, be a 256-byte × n address area. The functional safety and security data area 313 may also include a write register for writing security data and a read register for reading security data.

[0039] The communication information register 312 is a mode setting register for security and protection purposes. For example, the communication information register 312 stores communication mode information, communication start status information, and communication end status information, as communication information. This communication information is represented by FS_S_STATE, as described later. For example, FS_S_STATE=0 indicates communication end, and FS_S_STATE≠0 indicates communication start.

[0040] Alternatively, the CPU code or fuse in CIS1 can be used to switch between using the functional safety and security data area 313 and the communication information register 312 of register 130. Furthermore, the CPU code or fuse can be used to switch between using one of the multiple functions of the safety and security technology. By using the communication information register 312 and the functional safety and security data area 313 for multiple functions, the size of the register area can be reduced. The choice of which of the multiple functions to use can be made later through settings at product startup, software changes, or fuse switching.

[0041] The address areas of the communication information register 312 and the functional safety and security data area 313 only need to be prepared for the functions required by the corresponding operating modes of the plurality of security and security technologies. For example, if only CRC is required, the address areas of the communication information register 312 and the functional safety and security data area 313 can also be small in size. If CIS1 can correspond to both CRC and MAC, only the larger of the address areas required for CRC or MAC needs to be prepared. If it can correspond to both CRC and MAC, it is not necessary to prepare both address areas for CRC and address areas for MAC.

[0042] In one embodiment, the technology includes a function to notify the slave device, i.e., the CIS1, of safety and security-related notification information. The notification information, as described later, may be a processing status displaying the processing status in the register 130, or error information generated during processing in the register 130. The processing status, as described later, is represented by the processing status FS_S_ACT. The error information, as described later, is represented by the error status FS_S_ERR. The CIS1 has a notification unit that outputs notification information. The notification unit may, for example, be the write determination unit 410, 410A and the register information memory 420 (Figures 10 and 14 described later). As shown in Figures 10 and 14 described later, the notification information may also be output to the host 2 via dedicated terminals (processing status output terminal 501 and error output terminal 502). As a temporary register IF or other IF, it may also have an IF with interrupt function on the slave device side, such as I3C (Improved Inter Integrated Circuits), and use the IF with interrupt function to output notification information to the host 2. Furthermore, in the communication unit 120, which is a data output unit, notification information from the notification unit may be added to the sensor data output from the self-sensing unit 124, and output to the host 2 along with the sensor data. The notification method for the notification information may also be a combination of the above methods.

[0043] (1.2.2 Specific examples of security and protection technologies) Hereinafter, the communication mode using MAC will be referred to as MAC mode, the communication mode using CRC will be referred to as CRC mode, and the communication mode using encryption will be referred to as encryption mode.

[0044] (Example of writing configuration information in MAC mode) Figure 6 is a sequence diagram showing an example of register communication in one embodiment of the technology. Figure 6 shows an example of register communication when writing setting information to sensor register 311 via MAC mode.

[0045] First, the host 2 sends a status message FS_S_STATE=MAC_REGW indicating a write start request to the sensor register 311 in MAC mode via register IF, displaying setting information. In CIS1, the action mode value (MAC_REGW) is written in a single pass to register FS_S_STETE in communication information register 312. Next, the host 2 sends setting information to the sensor register 311 via register IF. This setting information includes, for example, the address of the setting value to be changed in sensor register 311 and a group of setting values ​​(multiple values ​​can be combined). In CIS1, the setting information is written to sensor register 311. In this way, various register settings are completed in sensor register 311. Sensor register 311 can also combine single-pass writes and continuous writes to write to the register group that needs to be written.

[0046] Next, host 2 sends the status FS_S_STATE=0 of the write completion request to sensor register 311 in MAC mode via register IF, display setting information, as communication information. In CIS1, the operation mode value of the FS_S_STETE register of communication information register 312 is set to 0.

[0047] Next, the host 2 sends a status message FS_S_STATE=MAC_DATAW indicating the start of writing security data in MAC mode via the register IF, as communication information. In CIS1, the operation mode value (MAC_DATAW) is written to the FS_S_STETE register of the communication information register 312. Next, the host 2 sends the security data (MAC data) in MAC mode via the register IF. In CIS1, MAC data is written to the functional safety and security data area 313. MAC data can also be sent via burst transmission, which has a faster transmission speed. As security data, information required for processing other than MAC can also be sent. For example, MAC mode information when there are multiple algorithms or IV information when using GMAC can also be sent. In the case of multiple algorithms, the operation mode can also be fixed in advance at the time of product startup or by means of fuses, etc.

[0048] Next, host 2 sends a status message FS_S_STATE=0 indicating the end of the write request for the data used for MAC mode preservation via the register IF, as communication information. In CIS1, the operation mode value of the FS_S_STETE register of the communication information register 312 is set to 0.

[0049] As described above, in one embodiment of the technology, the communication mode is notified by the host 2 as communication information, and multiple transmission modes can correspond to the CIS1. As described above, in one embodiment of the technology, since the communication information register 312 stores and displays the status information of the start and end of communication as communication information, communication can be performed without affecting burst transmissions by sending data blocks from the host 2, regardless of the address area to be set in the register 130. Furthermore, the start of data transmission between the host 2 and the CIS1 can be clearly defined. In one embodiment of the technology, multiple addresses and data can be uniformly set as CRC, MAC, or encrypted objects. In one embodiment of the technology, data can be transmitted more efficiently than sending CRC or MAC data according to each transmission unit.

[0050] (Example of writing configuration information in CRC mode) Figure 7 is a sequence diagram showing an example of register communication in one embodiment of the technology. Figure 7 shows an example of register communication when writing setting information to sensor register 311 using CRC mode. Figure 7 also shows an example comparing the time taken from sending the setting information to sending the CRC data.

[0051] Additionally, the only difference between CRC mode and MAC mode is the computational processing performed on the data of the object to be maintained; the motion images are basically the same.

[0052] First, the host 2 sends a status message FS_S_STATE=CRC_REGW indicating a write start request to the sensor register 311 via register IF, displaying CRC mode setting information. This status message serves as communication information. The setting information includes, for example, the address of the setting value to be changed in the sensor register 311 and a group of setting values ​​(multiple combinations are possible). In CIS1, the operation mode value (CRC_REGW) is written in a single operation to the FS_S_STETE register in the communication information register 312. Next, the host 2 sends setting information to the sensor register 311 via register IF. In CIS1, the setting information is written to the sensor register 311. In this way, various register settings are completed in the sensor register 311. The sensor register 311 can also combine single-operation writes and continuous writes to write to the required register group.

[0053] Next, the host 2 sends the CRC mode setting information to the sensor register 311 via the register IF, indicating that the write end request is FS_S_STATE=0, as communication information. In CIS1, the operation mode value of the FS_S_STETE register of the communication information register 312 is set to 0.

[0054] Next, the host 2 sends a status message FS_S_STATE=CRC_DATAW indicating the start of writing security data in CRC mode via the register IF, as communication information. In CIS1, the action mode value (CRC_DATAW) is written to the FS_S_STETE register of the communication information register 312. Then, the host 2 sends the security data (CRC data) in CRC mode via the register IF. In CIS1, CRC data is written to the functional safety, security data area 313. CRC data can also be sent via burst transmission, which has a faster transmission speed. As security data, information required for processing other than CRC can also be sent. For example, CRC mode information with multiple algorithms can also be sent. In cases involving multiple algorithms, the action mode can be fixed in advance at product startup or by using a fuse, etc. Furthermore, in CIS1, CRC data is generated between the time the state FS_S_STATE=CRC_REGW is sent and the time the setting information used for various register settings is sent.

[0055] Next, host 2 sends a status message FS_S_STATE=0 indicating the end of writing the data for preservation in CRC mode via the register IF, as communication information. In CIS1, the operation mode value of the FS_S_STETE register of the communication information register 312 is set to 0.

[0056] (Example of sending some communication information omitted) When performing register communication in the first communication mode and then proceeding to register communication in the second communication mode, the display of the communication termination status information of the first communication mode can be omitted. For example, in the register communication examples shown in Figures 6 and 7, the display of the communication termination status FS_S_STATE=0 can also be omitted.

[0057] Figures 8 and 9 are sequence diagrams illustrating an example of register communication when a portion of the communication information is omitted during transmission. Figures 8 and 9 show examples of situations where no time is consumed between the transmission of setting information and the transmission of CRC data.

[0058] Figure 8 shows an example of register communication when writing setting information to the sensor register 311 using CRC mode. For example, as shown in Figure 8, if the communication mode (CRC_REG mode) for writing setting information to the sensor register 311 using CRC mode can be immediately switched to the second communication mode (CRC_DATA mode) for writing data for data preservation using CRC mode, the state indicating the end of communication in CRC_REG mode (FS_S_STATE=0) can also be omitted.

[0059] Figure 9 illustrates an example of register communication when the host 2 sends information specifying the CRC algorithm as communication information during the writing of setting information to the sensor register 311 in CRC mode. In the example of Figure 9, after the host 2 sends the status FS_S_MODE=CRC_REG indicating the start request of CRC_REG mode, the host 2 sends the status FS_S_MODE=CRC16 indicating that the CRC operation mode is CRC16. Subsequently, various register setting data are sent, and after omitting the status indicating the end of communication in CRC_REG mode (FS_S_STATE=0), the system immediately transitions to CRC_DATA mode.

[0060] (Circuit Configuration Example 1) Figure 10 schematically shows a first configuration example of a data processing device CIS1 as one embodiment.

[0061] In the first configuration example shown in Figure 10, the CIS1 includes a communication unit 110, a communication unit 120, a data processing unit 123, a sensor unit 124, a temporary register 130, a write determination unit 410, a processing status output terminal 501, and an output terminal 502.

[0062] The processing status output terminal 501 outputs the processing status (processing status FS_S_ACT) indicating the processing status of the register 130 to the host 2 as notification information. The error output terminal 502 outputs error information (error status FS_S_ERR) generated during the processing of the register 130 to the host 2 as notification information.

[0063] The data processing unit 123 performs various data processing on the sensor data output from the self-sensing unit 124. The communication unit 120 adds error information and other notification information to the sensor data after various data processing is performed in the data processing unit 123, and outputs the sensor data to the host 2.

[0064] Figure 10 shows a configuration example where, after a setting value is written to the sensor register 311, the correct value is determined, for example, by using a CRC check. The setting values ​​from the host 2 are sequentially reflected in the sensor register 311 via the communication unit 100. Alternatively, the setting values ​​of each part of the CIS1 can also be reflected after being latched in the frame synchronization signal of the sensor data. In this configuration example, since there is no need for a memory (register information memory 420) that temporarily stores the setting values ​​of the sensor register 311 in the configuration example shown later in Figure 14, no communication limit is set. In this configuration example, it is possible to write an unexpected value to the register 130, but in this case, the host 2 can be notified of the setting value error by outputting error information to the sensor data or error output terminal 502. Alternatively, the error information or processing status can be read from the register 130 instead of being output to the host 2 via the error output terminal 502 or the processing status output terminal 501 (communication can also be achieved using the register).

[0065] Figure 11 shows a specific example of the write determination unit 410 of the CIS1 shown in Figure 10.

[0066] The write determination unit 410 includes a temporary register communication detection unit 411, a data processing unit 412, an error detection unit 413, and a write counter 414.

[0067] The register communication detection unit 411 detects register communication. The data processing unit 412 performs CRC, MAC, and encryption-related calculations. The error detection unit 413 performs error detection based on the calculation results of the data processing unit 412. The write counter 414 counts write requests to register 130 based on the detection results of the register communication detection unit 411.

[0068] After the write determination unit 410 writes the setting information reflected in the sensor register 311, it determines the correctness of the setting information reflected in the sensor register 311 based on the security data. The write determination unit 410 is notified of the start and completion timing of the operation by the communication information register 312. Furthermore, the write determination unit 410 is notified of the completion (determination timing) of the writing of security data such as CRC or MAC data to the functional safety and security data area 313 by the communication information register 312.

[0069] Figure 12 is a sequence diagram showing an example of register communication implemented using the configuration shown in Figure 10. Figure 12 shows an example of register communication when writing setting information to sensor register 311 using CRC mode.

[0070] Furthermore, Figure 12 shows an example of register communication when a setting value is written to the sensor register 311, and the CRC check is used to determine whether the written value is correct. Figure 12 also shows an example of synchronizing with the frame synchronization signal of the sensor data, adding error information such as setting value notification to the sensor data output from the sensor unit 124, and outputting it. Even if the setting value is not reflected in the register 130 after determining whether it is correct, error information is still added to the sensor data and output. Therefore, if the reliability of the setting value is determined, it can be processed in a later stage. It also has the advantage of being able to reflect the register 130 as quickly as possible before the register write determination.

[0071] The processing state FS_S_ACT indicates, for example, that it is active when it is high. The error state FS_S_ERR indicates, for example, that it is active when it is low. An example of a frame format for sensor data is shown at the bottom of Figure 12. In MIPI or SLVS-EC, as a frame format for image data, embedded data (EBD) that can be used as a data area outside the image is defined. The communication unit 120, which is a data output unit, outputs status information (notification information) from the write determination unit 410, which is a notification unit, to the embedded data of the sensor data, for example, in a timing synchronized with the frame synchronization signal (Frame Sync).

[0072] In the example of Figure 12, it can be seen whether the sensor data in the second frame is reliable when the processing state FS_S_ACT changes to negative. By observing the error state FS_S_ERR when the processing state FS_S_ACT changes to low, the host 2 can determine whether the setting information was successfully sent.

[0073] In the example of Figure 12, in the first frame, the processing status FS_S_ACT is negative and the error status FS_S_ERR is negative, which can be judged as reliable data (no abnormality in register communication).

[0074] In the second frame, the processing status FS_S_ACT is active and the error status FS_S_ERR is negative, which indicates that the data is of uncertain reliability (under review).

[0075] In the third frame, the processing status FS_S_ACT is negative and the error status FS_S_ERR is negative, indicating that the data is reliable (there is no abnormality in the temporary register communication).

[0076] Figure 13 is a sequence diagram showing an example of register communication in one embodiment of the technology. Figure 13 shows an example of register communication when writing setting information to sensor register 311 using CRC mode.

[0077] Figure 13 shows an example of register communication before writing the setting value to the sensor register 311, where a CRC check is used to determine if the setting value is correct, followed by writing the setting value to the sensor register 311. Similarly, in MAC mode, a MAC check can be used to determine if the setting value is correct before writing the setting value to the sensor register 311, followed by writing the setting value to the sensor register 311.

[0078] The lower part of Figure 13 shows the processing image within CIS1. In CIS1, CRC data (or MAC data in MAC mode) is generated based on the setting information sent by host 2 (step S11). Furthermore, the write counter 414 counts write requests to sensor register 311. Next, CIS1 compares the CRC data sent by host 2 as security data with the CRC data generated internally in CIS1 (step S12). Afterward, CIS1 reflects the setting value to sensor register 311 (step S13). Furthermore, CIS1 sends a processing completion notification for processing status FS_S_ACT (step S14). Also, in the event of an error, an error message notification for error status FS_S_ERR is sent (step S14).

[0079] (Circuit Configuration Example 2) Figure 14 schematically shows a second configuration example of a data processing device CIS1 as one embodiment.

[0080] In the second configuration example shown in Figure 14, the CIS1 includes a communication unit 110, a communication unit 120, a data processing unit 123, a sensor unit 124, a temporary register 130, a write determination unit 410A, a temporary register information memory 420, a processing status output terminal 501, and an output terminal 502.

[0081] The temporary storage information memory 420 is a temporary memory unit that temporarily stores the setting information sent from the host 2. The write determination unit 410A determines the correctness of the setting information stored in the temporary storage information memory 420 based on data for protection such as CRC or MAC. When the setting information is determined to be correct, the setting information is written to the sensor temporary storage 311.

[0082] Figure 14 shows an example where the write information to the sensor register 311 is temporarily stored in the memory (register information memory 420) within CIS1, and is only reflected when it matches the CRC or MAC value. Since the sensor register 311 is only reflected with the set value when the CRC or MAC value matches, CIS1 does not operate with any assumed value. Notification information such as processing status FS_S_ACT or error status FS_S_ERR can also be output to the read register of the functional safety and security data area 313, instead of the processing status output terminal 501 or the error output terminal 502. Alternatively, notification information can also be output to the embedded data in the sensor data.

[0083] Figure 15 shows a specific example of the write determination unit 410A in the CIS1 shown in Figure 14.

[0084] The write determination unit 410A includes a register communication detection unit 411, a data processing unit 412, an error detection unit 413, a write counter 414, and a register response determination unit 415.

[0085] The register communication detection unit 411 detects register communication. The data processing unit 412 performs CRC, MAC, and encryption-related calculations. The error detection unit 413 performs error detection based on the calculation results of the data processing unit 412. The write counter 414 counts write requests to register 130 based on the detection results of the register communication detection unit 411. The register response determination unit 415 determines whether to respond to the write information in the sensor register 311 based on the detection results of the error detection unit 413.

[0086] Figure 16 is a sequence diagram showing an example of register communication using CRC mode implemented by the configuration example shown in Figure 15.

[0087] By observing that the processing state FS_S_ACT goes low, it can be known that the writing of the setting value to the sensor register 311 has ended. If no error is detected while the error state FS_S_ERR remains low, then the response of the setting value to the sensor register 311 ends when the processing state FS_S_ACT goes low.

[0088] (Example of writing encryption mode settings information) Figure 17 is a sequence diagram showing an example of a temporary communication in an encrypted mode of a technology implementation.

[0089] Figure 17 shows an example of register communication when the setting information of the write object to the sensor register 311 is encrypted using an encryption mode. The lower right section of Figure 17 shows the processing image within the CIS1. The CIS1 is equipped with a decoding unit 430 for decoding encrypted data.

[0090] First, the host 2 sends the display encryption mode setting information to the sensor register 311 via the register IF, indicating the state of the write start request FS_S_STATE=USERDEF_DATAW, as communication information. In CIS1, the FS_S_STETE register of the communication information register 312 is used to write the action mode value (USERDEF_DATAW) once.

[0091] Next, the decoded setting information is sent from host 2 as encrypted data via the register IF. Alternatively, the setting value of state FS_S_STATE=USERDEF_DATAW can also be included, and MAC data or IVs can be encrypted and sent together. In CIS1, encrypted data is written to the functional safety and security data area 313. Next, in CIS1, the encrypted data is decoded by the decoding unit 430, and the decoded setting information (register address and setting value) is written to the sensor register 311. Generally, authentication is also performed during decoding (to confirm that the data has not been tampered with). Furthermore, in CIS1, a processing completion notification (step S21) is displayed indicating that decoding is complete via the processing state FS_S_ACT. Also, in the event of an error, an error message with error state FS_S_ERR is notified (step S21).

[0092] (Example of reading configuration information in CRC mode) Figure 18 is a sequence diagram showing an example of register communication during readout using a specific implementation technique.

[0093] Figure 18 illustrates an example of register communication when a request to read configuration information stored in sensor register 311 from host 2 is made using CRC mode. When a request to read configuration information from host 2 is made, in CIS1, the configuration information stored in sensor register 311 and related security data stored in functional safety and security data area 313 are read, and the read data is sent to host 2 via register IF. The operation is essentially the same when reading in MAC mode.

[0094] First, host 2 sends a status message FS_S_STATE=CRC_REGR to the register IF, indicating a read start request for displaying CRC mode setting information, as communication information. In CIS1, the action mode value (CRC_REGR) is written to the FS_S_STETE register of communication information register 312. In CIS1, the setting information stored in sensor register 311 is read, and the read data is sent to host 2 via register IF. The setting information includes, for example, the register address and setting value of sensor register 311, which is the target of the read.

[0095] Next, host 2 sends a status message FS_S_STATE=0 indicating the end of reading the CRC mode setting information via register IF, as communication information. In CIS1, the operation mode value of register FS_S_STETE in communication information register 312 is set to 0. Then, in CIS1, for example, a completion notification indicating the completion of the read processing is displayed based on the processing status FS_S_ACT. The notification can also be sent using the processing status output terminal 501 or register IF.

[0096] Next, host 2 sends a status message FS_S_STATE=CRC_DATAR indicating the start of reading security data in CRC mode via register IF, as communication information. In CIS1, a single write operation mode value (CRC_DATAR) is applied to the FS_S_STETE register of communication information register 312. Next, in CIS1, CRC data is generated and written to the functional safety and security data area 313. Then, in CIS1, CRC data is read from the functional safety and security data area 313 and sent to host 2 via register IF as security data. The CRC data may also include the register address and CRC value of the sensor register 311 to be read. As security data, other processing information besides CRC may also be sent. For example, CRC mode information with multiple algorithms may also be sent.

[0097] Next, host 2 sends a status message FS_S_STATE=0 indicating the end of the read request for the data used for preservation in display CRC mode via the IF register, as communication information. In CIS1, the operation mode value of the FS_S_STETE register of the communication information register 312 is set to 0.

[0098] (Example of reading encryption mode settings information) Figure 19 is a sequence diagram showing an example of register communication during encrypted mode reading using a certain implementation of the technology.

[0099] Figure 19 illustrates an example of register communication when the host 2 requests to read the setting information stored in the sensor register 311 using encrypted mode. When the host 2 makes a request to read the setting information in encrypted mode, in CIS1, the setting information stored in the sensor register 311 is encrypted and written as encrypted data to the functional safety and security data area 313, and then the encrypted data is read from the functional safety and security data area 313.

[0100] First, the host 2 sends the configuration information for displaying the encryption mode to the functional safety and security data area 313 via the register IF, indicating a write start request status FS_S_STATE=USERDEF_DATAW, as communication information. In CIS1, the FS_S_STETE register of the communication information register 312 is used for a single-shot write operation mode value (USERDEF_DATAW). In CIS1, the configuration information stored in the sensor register 311 is read, encrypted, and written as encrypted data to the functional safety and security data area 313. The encrypted data may also include an encrypted read request command, or the address and data size of the sensor register 311 that is the object of the encrypted read request. Preferably, there is no address. Whether an address is included varies depending on the product.

[0101] Next, host 2 sends a status message FS_S_STATE=0 indicating the completion of the write request via the register IF, as communication information. In CIS1, the operation mode value of the FS_S_STETE register in the communication information register 312 is set to 0. Then, in CIS1, for example, a completion notification indicating the completion of the write process is sent based on the processing status FS_S_ACT. The notification can also be sent using the processing status output terminal 501 or the register IF.

[0102] Next, host 2 sends a read start request (encryption read request command) for displaying encryption mode setting information via register IF, with the status FS_S_STATE=USERDEF_DATAR, as communication information. In CIS1, the FS_S_STETE register of communication information register 312 is written to the action mode value (USERDEF_DATAR). In CIS1, encrypted data is read from the functional safety and security data area 313 and sent to host 2 via register IF.

[0103] Next, host 2 sends a status message FS_S_STATE=0 indicating the end of the read request via the register IF, as communication information. In CIS1, the operation mode value of the FS_S_STETE register of the communication information register 312 is set to 0.

[0104] (Notification methods for information dissemination) Figure 20 is a sequence diagram illustrating an example of register communication in one embodiment of the technology. Figure 20 shows an example of a status notification within CIS1 when writing CRC mode setting information.

[0105] As described above, the processing status FS_S_ACT, error status FS_S_ERR, and counter information can be held by the register 130 or output from the processing status output terminal 501 or the error output terminal 502. Alternatively, they can be output as embedded data when outputting sensor data from the communication unit 120. A combination of these methods is also possible.

[0106] The processing status FS_S_ACT can also be displayed within CIS1 as the status of accepting and processing various requests. The error status FS_S_ERR can also be a status indicating that an error has been detected within CIS1. Multiple error statuses FS_S_ERR can exist depending on the error classification method. This can also be changed depending on the product.

[0107] (Communication counter) As shown in Figures 24 and 26 below, the CIS1 may also include a communication counter 416. The communication counter 416 may also include a write counter and a read counter. The write counter, for example, counts write requests from the host 2 to the sensor register 311 when setting information is received. The read counter, for example, counts read requests from the host 2 when setting information is received. By having separate write and read counters, the polling process for reading processing status or error information from the register 130 of the CIS1 can be monitored, allowing for monitoring of write operations to the register 130 when the CIS1's operation is changed. However, the write counter and read counter may also be combined into a single communication counter 416.

[0108] (Example of writing to a counter) Figure 21 is a sequence diagram showing an example of register communication in the operation of a write counter of a technology including one embodiment. Figure 21 shows an example of register communication when writing setting information to sensor register 311 using CRC mode.

[0109] The write counter (REG_COUNTW) increments its value, for example, when a register communication (FS_S_STATE=CRC_REGW) is detected that indicates a write request.

[0110] Additionally, if the CRC or MAC check result is incorrect and does not reflect the setting value of the sensor register 311, the write counter can also be incremented. Assuming that, depending on the product, there are instances where "the setting value is reflected if the CRC or MAC check result is OK" or "the setting value is reflected if it is sent, but the CRC check result in the camera result is notified to be incorrect", the corresponding examples are differentiated according to the product.

[0111] (Example of the read counter action when making a read request) Figure 22 is a sequence diagram showing an example of register communication in which the read counter of a technology including one embodiment operates. Figure 22 shows an example of register communication when a request to read the setting information stored in the sensor register 311 from the host 2 is made using CRC mode.

[0112] The read counter (REG_COUNTR) increments its value, for example, at the start of reading the setting information corresponding to the read request (FS_S_STATE=CRC_REGR). For instance, even if it's a single setting value, it can be incremented after read preparation is complete. Additionally, the read counter can be incremented if the CRC or MAC check result is incorrect.

[0113] (Example of the read counter action when reading in encrypted mode) Figure 23 is a sequence diagram showing an example of register communication in which the read counter of a technology including one embodiment operates. Figure 23 shows an example of register communication when a request to read setting information stored in sensor register 311 from host 2 is made using an encrypted mode.

[0114] The read counter (REG_COUNTR) increments before reading the encrypted data from the functional safety and security data area 313 after encrypting the setting information stored in the sensor register 311 and writing it as encrypted data.

[0115] (Circuit Configuration Example 3) Figure 24 schematically shows a third configuration example of the CIS1 data processing device as one embodiment. Figure 24 shows a configuration example where, after a setting value is written to the sensor register 311, the correct value is determined, for example, by using CRC.

[0116] In the third configuration example shown in Figure 24, the CIS1 includes a communication unit 110, a communication unit 120, a data processing unit 123, a sensor unit 124, a register 130, a write determination unit 410, a processing status output terminal 501, and an output terminal 502. Furthermore, the CIS1 includes an overall control unit 40, a register communication detection unit 411, a data processing unit 412, an error detection unit 413, and a communication counter 413.

[0117] The communication counter 416 has a write counter and a read counter. The sensor unit 124 has a pixel unit 41, an ADC (analog-to-digital converter) 42, and a pixel control unit 43.

[0118] In the third configuration example shown in Figure 24, the temporary storage communication detection unit 411, the data processing unit 412, and the error detection unit 413 are easy to construct even for the CPU 131 (Figure 1), and are easy to modify afterwards.

[0119] The communication unit 120, acting as a data output unit, adds error information and other notification information, along with the counter value from the communication counter 416, to the sensor data processed by the data processing unit 123, and outputs the sensor data to the host 2. For example, the communication unit 120 adds notification information and a counter value to the embedded data in the sensor data using a timing synchronized with the synchronization timing signal for the sensor data. Furthermore, the counter value of the communication counter 416 can also be output to the temporary register 130.

[0120] When the sensor register 311 is used to reflect the set value before CRC or MAC checks, the host 2 can determine the operating status of CIS1 by adding notification information, counter values, and status to the sensor data and outputting them. While reflecting the set value after CRC or MAC checks is ideal, a configuration that only confirms the correctness of communication after the set value reflection is performed normally can further reduce the processing load inside CIS1.

[0121] (Example of writing to a counter) (Circuit Configuration Example 4) Figure 25 is a sequence diagram showing an example of register communication in the operation of a write counter including one embodiment of the technology. Figure 25 shows an example of register communication when writing setting information to sensor register 311 using CRC mode.

[0122] Furthermore, Figure 26 schematically shows a configuration example for implementing the processing shown in Figure 25, which is the fourth configuration example of the data processing device CIS1 as an embodiment.

[0123] In the fourth configuration example shown in Figure 26, the CIS1 includes a communication unit 110, a communication unit 120, a data processing unit 123, a sensor unit 124, a register 130, a write determination unit 410, a processing status output terminal 501, and an output terminal 502. Furthermore, the CIS1 includes an overall control unit 40, a register communication detection unit 411, a data processing unit 412, an error detection unit 413, a communication counter 413, and a register response determination unit 415.

[0124] In the fourth configuration example shown in Figure 26, the register communication detection unit 411, data processing unit 412, error detection unit 413, and register response determination unit 415 are easy to construct even for CPU 131 (Figure 1), and are easy to modify afterwards.

[0125] Figure 25 shows an example where the write information to the sensor register 311 is temporarily stored in the memory within CIS1, and the set value is reflected in the sensor register 311 only when it matches the CRC value or MAC value. The operation is the same in MAC mode.

[0126] Notification information such as processing status FS_S_ACT or error status FS_S_ERR can also be output to the read register of the functional safety and security data area 313, instead of the processing status output terminal 501 or the error output terminal 502. Alternatively, the notification information can also be output to the embedded data in the sensor data.

[0127] The write counter (REG_COUNTW) increments its value, for example, when a register communication (FS_S_STATE=CRC_REGW) is detected that indicates a write request.

[0128] The bottom section of Figure 25 shows an example of the frame format for sensor data. The communication unit 120, acting as a data output unit, adds error information and other notification information, along with the counter value from the communication counter 416, to the sensor data processed by the data processing unit 123, and outputs the sensor data to the host 2. For example, the communication unit 120 adds notification information and a counter value to the embedded data in the sensor data using a timing synchronized with the synchronization timing signal for the sensor data. Furthermore, the counter value of the communication counter 416 can also be output to the temporary storage 130. By outputting notification information and the counter value, it can be determined whether the host 2 has reflected a new setting value in the CIS1.

[0129] In the example of Figure 25, it can be seen whether the sensor data in the second frame is reliable when the processing state FS_S_ACT changes to negative. By observing the error state FS_S_ERR when the processing state FS_S_ACT changes to low, the host 2 can determine whether the setting information was successfully sent.

[0130] In the example of Figure 25, in the first frame, the processing status FS_S_ACT is negative, the error status FS_S_ERR is negative, and the register counter remains unchanged. Therefore, it can be concluded that the set value is not reflected in the sensor register 311.

[0131] In the second frame, it can be seen that the processing status FS_S_ACT is active, the error status FS_S_ERR is negative, and the setting value of sensor register 311 has not been updated.

[0132] In the third frame, the processing status FS_S_ACT is negative and the error status FS_S_ERR is negative, indicating that the data is reliable (there is no abnormality in the temporary register communication).

[0133] (Example of writing to a counter) Figure 27 is a sequence diagram showing an example of register communication in which the write counter of a technology including one embodiment operates. Figure 27 shows an example of register communication when writing setting information to sensor register 311 via MAC mode.

[0134] The write counter (REG_COUNTW) increments its value, for example, when a register communication (FS_S_STATE=MAC_REGW) is detected that indicates a write request.

[0135] Furthermore, the write counter can also increment the value of the communication counter 416 by the communication transmission unit of the register communication when there is register communication between the host 2 and the register 130 without configured communication information (FS_S_STATE). This allows for the detection of communications not protected by functional safety and security functions. However, this alone would raise security and security concerns. Therefore, it is desirable to determine the communication OK mode based on either CIS1 or each register area of ​​the register 130, so that the register 130 cannot be updated and installed when this mode is not used.

[0136] (Example of a variation of the temporary register diagram) Figure 28 shows a variation of the configuration (snapshot diagram) of a temporary register 130 in one embodiment of the technology.

[0137] In the register 130, the sensor register 311 can also be configured to include areas that become security objects for specific security processing. When performing specific security processing, it allows setting information to be written to or read from the areas that become security objects. It is desirable that the settings of each area are predetermined at the time of product startup or manufacturing, and cannot be changed dynamically.

[0138] For example, it is also possible to "write with MAC or encryption" or "write with CRC or MAC", allowing multiple writes to a single area. The area designation can be fixed during CIS1 design, can be switched during fuse or product manufacturing, or can be set at startup.

[0139] In the case of "MAC or encrypted write," for example, when decoding encrypted data, authentication is also performed. Therefore, the area where authentication (MAC check) is performed can also be used for accessing encrypted data. Furthermore, in the case of "CRC or MAC write," even MAC can detect changes in data caused by data noise.

[0140] For example, as shown in Figure 28, a portion of the sensor register 311 can also be designated as the MAC area. The MAC area can also store data such as data written to the CIS1 by the host 2 based on environmental factors like exposure time, or read data such as temperature information.

[0141] Furthermore, for example, the communication information register 312 can also be used as a read-write area even without MAC or encryption. In this case, as long as there are no restrictions, CRC or MAC checks can be performed, for example, when verifying the correctness of a value during reading.

[0142] Alternatively, a portion of the sensor register 311 can be set as an encrypted area. For example, data read from the AI ​​(Artificial Intelligence)-equipped functional sensors, such as dictionary information or environmental information like temperature information, as well as motion pattern information, can also be encrypted and stored in the encrypted area, depending on the set environment, and these can become private information.

[0143] (Example of writing to a counter) Figure 29 is a sequence diagram showing an example of register communication in which the write counter of a technology including one embodiment operates. Figure 29 shows an example of register communication when writing setting information to sensor register 311 via MAC mode.

[0144] The write counter can also be configured to increment the value of the communication counter 416 by the number of communication transmission units during register communication between the host 2 and the register 130 when register communication without configured communication information (FS_S_STATE). This allows for the detection of communication not protected by functional safety and security functions. Alternatively, it can be configured to, in conjunction with this function, not reflect the writing of configuration information to the sensor register 311 when register communication without configured communication information occurs between the host 2 and the register 130. This enables more secure and reliable communication.

[0145] Figure 29 shows an example where CIS1 is pre-set to MAC mode, and the set value is not reflected when the MAC is incorrect. When register communication is performed in MAC mode, the counter is incremented regardless of whether the MAC value is correct or not. In this case, if the MAC value is correct, the value is reflected in register 130; if it is incorrect, the value is not reflected in register 130.

[0146] When communicating with a register not set in the communication mode (FS_S_STATE), the counter is incremented by the number of communication transmissions. In this case, since it is not MAC mode, the value is not reflected in register 130.

[0147] (Example of sending pattern information) Figure 30 is a sequence diagram showing an example of register communication in one embodiment of the technology. Figure 30 shows an example of register communication when writing setting information to sensor register 311 using CRC mode.

[0148] In one embodiment of the technology, it can also be configured such that, before writing or reading setting information to the sensor register 311, the host 2 sends communication mode information containing information of an algorithm corresponding to the desired security processing as communication information.

[0149] Figure 30 shows an example of register communication where the CRC operation mode changes according to the amount of data sent with "various register settings". By pre-sending information about the CRC operation mode, processing corresponding to the data length can be selected in CIS1. The CRC operation mode information can also be information such as the selection of the CRC algorithm (e.g., switching information between CRC16 and CRC32).

[0150] To notify mode information, the bit width of FS_S_STATE can be expanded as a mode register, or a new register area can be added to the register area of ​​the communication information register 312, such as a register area for remembering FS_S_MODE, as a mode register. That is, it can also have two register areas for remembering FS_S_STATE and FS_S_MODE as a mode register.

[0151] (Extended example of a mode register) Figure 31 is a sequence diagram showing an example of register communication in one embodiment of the technology. Figure 31 shows an example of register communication when writing setting information to sensor register 311 using CRC mode.

[0152] Alternatively, host 2 can send a notification containing notification mode information as communication information. For example, when the communication mode information is notified via a mode register, host 2 can also notify CIS1 whether a mode register exists in the FS_S_STATE bit.

[0153] Figure 31 shows an example of whether there is a mode register in FS_S_STATE[7] (1: mode register present, 0: mode register absent). The upper part of Figure 31 shows an example of FS_S_STATE[7]=0.

[0154] The example of FS_S_STATE[7]=1 is shown in the lower part of Figure 31. Host 2 sends FS_S_STATE={1'b1,CRC_REGW} and FS_S_MODE≠0 as instructions. In CIS1, when FS_S_STATE[7]=1'b1 is sent, it waits for FS_S_MODE to change from 0 to other values ​​(FS_S_MODE≠0) and then starts processing. At the point when FS_S_STATE=0, the mode register is returned to 0.

[0155] (Example of sending security documents first) Figure 32 is a sequence diagram showing an example of register communication in one embodiment of the technology. Figure 32 shows an example of register communication when writing setting information to sensor register 311 via MAC mode.

[0156] In CIS1, before the host 2 sends communication information, the host 2 can send information for the desired security processing, and write the information for the desired security processing as security data into the functional safety and security data area 313.

[0157] For example, host 2 can also send information required for processing other than MAC as security data. For example, it can also send MAC mode information when there are multiple algorithms or IV information when using GMAC. In this case, host 2 can also send IV information first. When the security data is large data of more than digits, by pre-writing a portion of the data to the functional safety and security data area 313, the register area can be used effectively, and MAC calculation can be performed in parallel with register communication (in parallel with the communication time of various registers).

[0158] (Example with a value register) Figure 33 is a sequence diagram showing an example of register communication in the operation of a write counter including one embodiment of the technology. Figure 33 shows an example of register communication when writing setting information to sensor register 311 using CRC mode.

[0159] The configuration information sent from host 2 may also include the expected value of the write counter. The register 130 may also include a write counter expectation register that stores the expected value of the write counter.

[0160] In CIS1, for example, when FS_S_STATE changes from non-zero to zero, the value of the write counter is compared with the expected value of the write counter. If FS_S_STATE changes from non-zero to zero, the counter in the expected value register of the write counter is incremented, and the expected value is also set. In this way, the expected value register of the write counter can be set as the object of CRC or MAC checks, just like a normal register area.

[0161] Figure 34 is a sequence diagram illustrating an example of register communication in an embodiment of the technology. Figure 34 is also a sequence diagram illustrating an example of register communication including the operation of a write counter in an embodiment of the technology.

[0162] The CIS1 may also include a temporary storage unit 420, which serves as a temporary storage unit for storing setting information sent from the host 2 (Figure 14). In the write determination unit 410A of the CIS1, the correctness of the setting information stored in the temporary storage unit can also be determined based on the data for preservation. When the setting information is determined to be correct and the counter value of the write counter is consistent with the expected counter value stored in the write counter expected value temporary storage unit, the setting information is reflected in the sensor temporary storage unit 311.

[0163] For example, the set value (reflecting the register value) can be written only when the CRC value or MAC value is consistent and the expected value of the write counter is also consistent.

[0164] (Example 1 of the variation in error detection) Figure 35 is a sequence diagram illustrating an example of register communication in one embodiment of the technology. Figure 35 shows an example of a status notification within CIS1 when writing CRC mode setting information.

[0165] Figure 35 shows an example of error detection during normal operation. In CIS1, by observing the processing state FS_S_ACT go low, it can be known that the writing of the set value to the sensor register 311 has ended. If no error is detected while the error state FS_S_ERR remains low, then the response of the set value to the sensor register 311 ends when the processing state FS_S_ACT goes low.

[0166] In CIS1, the correctness of the setting information is determined based on the data used for security (CRC data or MAC data). When the setting information is determined to be incorrect, the error information is output as a notification message through the error status FS_S_ERR.

[0167] (Example 2 of the variation in error detection) Figure 36 is a sequence diagram showing an example of register communication in which the write counter of a technology including one embodiment operates.

[0168] In CIS1, when communication information is not set between host 2 and register 130 and accidental register communication occurs, error information can also be output as notification information.

[0169] For example, when there is a write or read request for a specified or limited communication mode in the register 130, error information can also be output as a handler for unconventional or undefined operations.

[0170] Figure 36 shows an example of unintentional register communication after the host 2 intentionally writes the MAC mode setting information to the register of CIS1. For example, when register communication is performed without setting MAC_REGW for FS_S_STATE, an error is detected in CIS1.

[0171] The write counter (REG_COUNTW) increments its value, for example, when a write request is detected in register communication (FS_S_STATE=MAC_REGW). Furthermore, when register communication (FS_S_STATE) without configured communication information occurs between host 2 and register 130, the write counter 416 is also incremented by the number of register communication transmission units. This allows for the detection of communications not protected by functional safety and security functions. The counter value can also be output to embedded data in the sensor data. Alternatively, the counter value can be output to register 130. This allows host 2 to indirectly detect unintentional writes. Furthermore, by observing the counter value, the number of unintentional register writes can be determined. This can help determine if there is a DoS attack on host 2.

[0172] (Example 3 of the variation in error detection) Figure 37 is a sequence diagram showing an example of register communication in one embodiment of the technology. Figure 37 shows an example of register communication when writing setting information to sensor register 311 using CRC mode.

[0173] In CIS1, when there is unintentional communication between the host 2 and the register 130 using a register with an instruction different from the instruction indicated by the communication information, error information can also be output as notification information.

[0174] Figure 37 shows an example of sequence violation error detection. A sequence violation could occur, for example, after a register is written, a CRC or MAC write command is not generated, and other commands are issued instead. When a sequence violation is detected, as shown in Figure 37, the processing before the process terminates can be reset, prioritizing subsequent processing. Figure 37 shows an example where a CRC write command (FS_S_STATE=CRC_REGW) is issued to request a write request for displaying configuration information, but no CRC write command (FS_S_STATE=CRC_DATAW) is generated.

[0175] (Example 4 of the variation in error detection) Figure 38 is a sequence diagram showing an example of register communication in one embodiment of the technology. Figure 38 shows an example of register communication when writing setting information to sensor register 311 via MAC mode.

[0176] In CIS1, if no instruction for register communication is sent from host 2 within a specific period, error information can also be output as notification information.

[0177] For example, as a timer for setting the maximum processing time (MAX), the CIS1 can also have a WDT (watchdog timer) to detect when the maximum time is exceeded and issue an error notification. The maximum value can be fixed during the design of the CIS1, can be switched during fuse manufacturing, or can be set at startup.

[0178] Error detection can be performed by setting the upper limit time for each process using WDT and other methods. In cases where there are erroneous actions such as control or communication IF transmission on both sides of the host, and normal instructions cannot be sent, errors can be detected indirectly.

[0179] In the example of Figure 38, the processing of FS_S_STATE=MAC_REGW was detected as not having finished. This indirectly indicates that FS_S_STATE=0 was not sent from host 2, or that data did not reach CIS1 due to noise or obstruction to the register IF.

[0180] Furthermore, in the example of Figure 38, it was detected that although the setting value of register 130 was sent, the MAC (CRC) value was not sent. This can indirectly detect that FS_S_STATE=MAC_DATAW was not sent from host 2, or that data did not reach CIS1 due to noise or obstruction to register IF.

[0181] (Example 5 of the variation in error detection) Figure 39 is a sequence diagram showing an example of register communication in which the write counter of a technology including one embodiment operates. Figure 33 shows an example of register communication when writing setting information to sensor register 311 using CRC mode.

[0182] The configuration information sent from host 2 may also include the expected value of the write counter. The register 130 may also include a write counter expectation register that stores the expected value of the write counter.

[0183] In CIS1, for example, when FS_S_STATE changes from non-zero to zero, the write counter value is compared with the expected write counter value. If FS_S_STATE changes from non-zero to zero, the counter in the expected write counter value register is incremented, and the expected value is also set. In this way, the expected write counter value register can be used as a check object for CRC or MAC, just like a normal register area.

[0184] In CIS1, when the value of the write counter is inconsistent with the expected value stored in the expected value register, an error message can be output as a notification via the error status FS_S_ERR. This mechanism can be performed not only during writing but also during reading. This helps to counter replay attacks, etc.

[0185] (Error detection related, others) Figure 40 is a sequence diagram showing an example of register communication in which the read counter and write counter of a technology including one embodiment operate. Figure 40 shows an example of register communication when writing setting information to sensor register 311 via MAC mode.

[0186] CIS1 can also be configured to perform a readout process (register read) of setting information different from the setting information of the writing target from the sensor register 311 during the writing process of setting information based on the write request (e.g., FS_S_STATE=MAC_REGW) from the host 2.

[0187] In CIS1, during the write-association process of the register, the status information in the register 130 can be confirmed from the host 2 during the write-association process by reading the register 130, which is normally read OK, and has no effect on the data in the write process (MAC value or CRC value is calculated only for the write process).

[0188] For example, after writing the CRC or MAC mode setting value to register 130, but before writing the CRC or MAC data, the normal read of the register value during the write process can be set to an error-free operation. This assumes, for example, functional safety, error protection, or reading the status of polling registers for other states. Furthermore, the normal readable register area pattern is always assumed. Error detection can also be performed on the read of register 130 in areas that cannot be read in CRC, MAC, or unencrypted states, and no value will be output.

[0189] [1.3 Effects] As explained above, according to one embodiment of the data transmission system, the address area of ​​the register 130 of the CIS1, which serves as a data processing device, includes a functional safety data area 313 for storing data for preserving setting information, and a communication information register 312 for storing communication information between the CIS1 and the host 2, enabling register communication between the CIS1 and the host 2. This improves security.

[0190] Furthermore, according to one implementation of the data transmission system, security and protection functions can be implemented within the existing specifications / communication IF style. Security and protection of the communication IF can be achieved through changes to the higher-level layers 113 and 213, which offer greater flexibility in software implementation. Hardware-level security can be incorporated into the development sequence of CIS1 and host 2.

[0191] Furthermore, the effects described in this specification are merely illustrative and not limiting; other effects may also occur. The same applies to the effects of the other implementations described below.

[0192] <2. Other Implementation Forms> The technology disclosed herein is not limited to the above-described embodiment and various variations are possible.

[0193] For example, this technology can also be configured as follows. According to the present technology, the address area of ​​the temporary storage of the data processing device has a data storage area for storing data for storing setting information and a communication information area for storing communication information between the data processing device and the host, and performs temporary storage communication between the data processing device and the host. This can improve security.

[0194] (1) A data processing device comprising: The temporary register includes a setting area for storing setting information sent from the host, a storage area for storing data for storing the setting information, and a communication information area for storing communication information with the host, which serves as an address area; and The communication unit performs temporary storage communication between the aforementioned host and the aforementioned temporary storage. (2) As described in (1) above, the data processing device, It includes communication mode information that displays the communication mode of the aforementioned register communication, communication start status information that displays the aforementioned register communication, and communication end status information that displays the aforementioned register communication, as the aforementioned communication information. (3) As described in (1) or (2) above, the data processing device, It includes at least one of the following: encrypted data containing the aforementioned setting information, error detection code related to the aforementioned setting information, and message authentication code related to the aforementioned setting information, as the aforementioned security data. (4) The data processing apparatus described in any of (1) to (3) above further includes: The notification unit outputs at least one of the processing status of the aforementioned temporary register and the error information generated by the processing of the aforementioned temporary register, as notification information. (5) The data processing apparatus described in (4) above further includes: The processing status output terminal outputs the aforementioned processing status to the aforementioned host computer; and The error output terminal outputs the aforementioned error information to the aforementioned host. (6) The data processing apparatus described in (4) or (5) above further includes: Sensor section; and The data output unit adds the notification information from the notification unit to the sensor data output from the sensor unit and outputs the sensor data to the host computer. (7) The data processing device described in any of (1) to (6) above, It is configured to communicate between the host and the register in multiple communication modes, and the register can be configured to communicate in any of the multiple communication modes. (8) As described in (2) above, the data processing device, When the configuration is such that after the first communication mode of register communication is performed, the second communication mode of register communication is performed, the status information of the end of the first communication mode of register communication can be omitted. (9) The data processing apparatus described in any of (1) to (8) above further comprises: The decoding unit decodes the encrypted data; and After writing encrypted data containing the above-mentioned setting information into the above-mentioned data area for security purposes, the above-mentioned decoding unit decodes the above-mentioned encrypted data and writes the above-mentioned setting information obtained by the decoding into the above-mentioned setting area. (10) The data processing device described in any of (1) to (9) above, wherein When there is a request to read the aforementioned configuration information from the aforementioned host, the aforementioned configuration information stored in the aforementioned configuration area and the aforementioned security data related to the aforementioned configuration information stored in the aforementioned security data area are read. (11) The data processing apparatus described in any of (1) to (10) above, wherein When the host requests to read the encrypted configuration information, the configuration information stored in the configuration area is encrypted and written as encrypted data to the security data area, and then the encrypted data is read from the security data area. (12) The data processing apparatus described in any of (1) to (11) above further comprises: The communication counter includes: a write counter that counts write requests for the aforementioned configuration information from the host to the aforementioned configuration area; and a read counter that counts read requests for the aforementioned configuration information from the host. (13) The data processing apparatus described in (12) above further includes: Sensor section; and The data output unit adds a counter value from the communication counter to the sensor data output from the sensor unit, and outputs the sensor data to the host computer; and The aforementioned data output unit adds the aforementioned counter value from the aforementioned communication counter to the aforementioned sensor data at a timing synchronized with the synchronization timing signal for the aforementioned sensor data. (14) The data processing apparatus described in (13) above further includes: The notification unit will output at least one of the following as notification information: the processing status of the aforementioned temporary register and the error information generated by the processing of the aforementioned temporary register; and The aforementioned data output unit adds the aforementioned notification information from the aforementioned notification unit and the aforementioned counter value from the aforementioned communication counter to the aforementioned sensor data in a timing sequence synchronized with the synchronization timing signal for the aforementioned sensor data. (15) The data processing device described in any of (1) to (14) above, It is configured to include a region that becomes the object of a specific security process, which serves as the aforementioned setting region. When the aforementioned specific security process is performed, the aforementioned setting information is allowed to be written to the region that becomes the object of the security process, or the aforementioned setting information is allowed to be read from the region that becomes the object of the security process. (16) The data processing device described in any of (12) to (14) above, The configuration is such that when the host and the register communicate with each other without the aforementioned communication information being set, the writing of the aforementioned setting information to the aforementioned setting area is not reflected. (17) The data processing apparatus described in any of (12) to (14) above, wherein The configuration information sent from the aforementioned host includes the expected value of the counter for the aforementioned write counter. The aforementioned temporary register includes a temporary register for the expected value of the aforementioned counter. (18) The data processing apparatus described in (17) above further includes: The temporary memory unit temporarily stores the aforementioned setting information sent from the aforementioned host; and The write determination unit determines the correctness of the setting information stored in the temporary memory unit based on the aforementioned data for preservation. When the setting information is determined to be correct and the counter value of the write counter matches the expected value of the counter stored in the expected value register, the writing of the setting information is reflected in the setting area. (19) The data processing device described in any of (4) to (6) above, wherein The notification department determines the correctness of the setting information based on the aforementioned security data. If the setting information is determined to be incorrect, the error information is output as the notification information. (20) The data processing apparatus described in (17) or (18) above further includes: The notification unit outputs error information as notification information when the counter value written to the above-mentioned counter is inconsistent with the expected value of the above-mentioned counter stored in the above-mentioned expected value register. (twenty one) The data processing device described in any of (1) to (20) above, Its configuration allows for switching between using the aforementioned data area for data preservation and the aforementioned communication information area in the aforementioned temporary storage. (twenty two) The data processing apparatus described in any of (1) to (21) above further comprises: The write determination unit, after writing the setting information to the setting area, determines the correctness of the setting information reflected in the setting area based on the data to be stored. (twenty three) As described in (6) above, the data processing device, in which The aforementioned data output unit adds the aforementioned notification information from the aforementioned notification unit to the aforementioned sensor data at a timing synchronized with the synchronization timing signal for the aforementioned sensor data. (twenty four) The data processing apparatus described in any of (1) to (23) above further includes: The temporary memory unit temporarily stores the aforementioned setting information sent from the aforementioned host; and The write determination unit, based on the aforementioned data for preservation, determines the correctness of the aforementioned setting information stored in the aforementioned temporary memory unit. If the setting information is determined to be correct, the write of the aforementioned setting information is reflected in the aforementioned setting area. (25) The data processing apparatus described in any of (12) to (14) above, wherein The aforementioned write counter is incremented to detect the timing of register communication that displays the aforementioned write request. (26) The data processing apparatus described in any of (12) to (14) above, wherein The aforementioned readout counter increments its value to begin reading the aforementioned setting information in accordance with the readout request. (27) The data processing apparatus described in any of (12) to (14) above, wherein When there is an encrypted read request, the above-mentioned read counter will encrypt the setting information stored in the setting area and write it as encrypted data to the security data area. Before reading the encrypted data from the security data area, the counter value will be incremented. (28) The data processing apparatus described in any of (12) to (14) above, wherein When the aforementioned host and the aforementioned register are communicating with the aforementioned register without the aforementioned communication information being set, the counter value of the aforementioned communication counter is incremented by the communication transmission unit of the aforementioned register communication. (29) The data processing apparatus described in any of (1) to (28) above, wherein Before writing or reading the above-mentioned configuration information to the above-mentioned configuration area, communication mode information containing information of the algorithm corresponding to the desired security processing is sent from the above-mentioned host as the above-mentioned communication information. (30) The data processing device described above (29), wherein The information sent by the aforementioned host, which includes the aforementioned communication mode information, shall be used as the aforementioned communication information. (31) The data processing apparatus described in (29) or (30) above, wherein Prior to sending the aforementioned communication information from the aforementioned host, information used for the desired security processing is sent from the aforementioned host, and the information used for the desired security processing is written as the aforementioned security data into the aforementioned security data area. (32) The data processing device described in any of (4) to (6) above, wherein When the aforementioned notification unit unintentionally communicates with the aforementioned register without setting the aforementioned communication information, it outputs the aforementioned error information as the aforementioned notification information. (33) The data processing device described in any of (4) to (6) above, wherein When the aforementioned notification unit unintentionally communicates with the aforementioned register using an instruction different from the instruction indicated in the aforementioned communication information, it outputs the aforementioned error information as the aforementioned notification information. (34) The data processing device described in any of (4) to (6) above, wherein If the aforementioned notification unit fails to send the aforementioned register communication instruction from the aforementioned host within a specific period, it outputs the aforementioned error information as the aforementioned notification information. (35) The data processing device described in any of (1) to (34) above, Its configuration is such that, during the writing process of the setting area based on the setting information from the writing request from the host, it is possible to read setting information different from the setting information of the writing object from the setting area. (36) A data transmission system comprising: Host; and Data processing device; and The aforementioned data processing device includes: The temporary register includes a setting area for storing setting information sent from the host, a storage area for storing data for storing the setting information, and a communication information area for storing communication information with the host, which serves as an address area; and The communication unit performs temporary storage communication between the aforementioned host and the aforementioned temporary storage.

[0195] 1: CIS (CMOS (Complementary Metal-Oxide Semiconductor) image sensor, slave device, data processing device) 2: Main unit (main control device) 3: Transmission path (communication IF (SPI / I2C)) 4: Transmission path (High-speed IF (Data output IF (MIPI / SLVS-EC / SLVS))) 40: Overall Control Department 41: Pixel section 42: ADC (Analog-to-Digital Converter) 43: Pixel Control Unit 110: Communications Department (Communications IF, Temporary Memory IF) 111: Physical Layer (PHY) 112: Link Layer 113: Upper level 120: Communications Department (Data Output Department, High-Speed ​​IF (Data Output IF (MIPI / SLVS-EC / SLVS))) 121: Physical Layer (PHY) 122: Link Layer 123: Data Processing Department 124: Sensor Section 130: Temporary Register 131: CPU 132: Hardware (HW) 210: Communications Department (Communications IF, Temporary Register IF) 211: Physical Layer (PHY) 212: Link Layer 213: Upper level 220: Ministry of Communications (High-speed IF (MIPI / SLVS-EC / SLVS)) 221: Physical Layer (PHY) 222: Link Layer 223: Data Processing Department 230: Temporary Register 231: CPU 232: Hardware (HW) 233: Data Processing Department 311: Sensor temporary storage (setting area) 312: Communication Information Temporary Registry (Communication Information Area, Mode Temporary Registry) 313: Functional safety and data security area (data security area, read register, write register) 410, 410A: Write to the decision-making unit (notification unit) 411: Temporary Registry Communication Detection Department 412: Data processing unit (CRC / MAC / encryption, etc.) 413: Error Detection Department 414: Write Counter 415: Temporary Registry Reflects Judgment Section 416: Communication Counter (Write Counter / Read Counter) 420: Temporary Memory Register (Notification Section, Temporary Memory Section) 430: Decoding Department 501: Processing status output terminal 502: Error output terminal S11~S14: Steps S21: Steps

Claims

1. A data processing apparatus comprising: a register having: a setting area for storing setting information transmitted from a host, a storage data area for storing storage data for the setting information, and a communication data area for storing communication information with the host, serving as an address area; a communication unit for communicating between the host and the register; a communication counter comprising: a write counter for counting write requests from the host to write the setting information to the setting area; and a read counter for counting read requests from the host to read the setting information; a sensor unit; and a data output unit for appending a counter value from the communication counter to sensor data output from the sensor unit and outputting the sensor data to the host; and the data output unit appending the counter value from the communication counter to the sensor data at a timing synchronized with a synchronization timing signal for the sensor data.

2. The data processing apparatus of claim 1, comprising communication mode information for displaying the communication mode of the aforementioned register communication, communication start status information for displaying the aforementioned register communication, and communication end status information for displaying the aforementioned register communication, as the aforementioned communication information.

3. The data processing apparatus of claim 1 includes at least one of the following: encrypted data containing the above-mentioned setting information, an error detection code related to the above-mentioned setting information, and a message authentication code related to the above-mentioned setting information, as the aforementioned security data.

4. The data processing apparatus of claim 1 further comprises: a notification unit that outputs at least one of a processing status indicating the processing status of the aforementioned register and error information generated during the processing of the aforementioned register as notification information.

5. The data processing apparatus of claim 4 further comprises: a processing status output terminal that outputs the processing status to the host computer; and an error output terminal that outputs the error information to the host computer.

6. The data processing apparatus of claim 4 further comprises: a sensor unit; and a data output unit that adds the notification information from the notification unit to the sensor data output from the sensor unit, and outputs the sensor data to the host computer.

7. The data processing apparatus of claim 1, configured to communicate between the host and the register in a plurality of communication modes, and configured to select any one of the plurality of communication modes for communication with the register.

8. If the data processing apparatus of claim 2 is configured to perform register communication in the first communication mode and then perform register communication in the second communication mode, the status information indicating the end of the register communication in the first communication mode may be omitted.

9. The data processing apparatus of claim 1 further comprises: a decoding unit that decodes encrypted data; and after writing encrypted data containing the setting information into the aforementioned security data area, the decoding unit decodes the encrypted data and writes the setting information obtained by the decoding into the aforementioned setting area.

10. The data processing apparatus of claim 1, wherein when there is a request from the host to read the setting information, the setting information stored in the setting area and the security data related to the setting information stored in the security data area are read.

11. The data processing apparatus of request item 1, wherein when there is a request from the host to read the encrypted setting information, the setting information stored in the setting area is encrypted and written as encrypted data to the security data area, and then the encrypted data is read from the security data area.

12. The data processing apparatus of claim 1 further comprises: a notification unit that outputs at least one of a processing state indicating the processing state of the aforementioned register and error information generated during the processing of the aforementioned register as notification information; and the data output unit, in a timing synchronized with a synchronization timing signal for the aforementioned sensor data, adds the aforementioned notification information from the aforementioned notification unit and the aforementioned counter value from the aforementioned communication counter to the aforementioned sensor data.

13. The data processing apparatus of claim 1 is configured to include a region that becomes a security object in a specific security process, which serves as the setting region, and when the specific security process is performed, allows the writing of the setting information to the region that becomes the security object or the reading of the setting information from the region that becomes the security object.

14. The data processing apparatus of claim 1 is configured such that when the host and the register communicate with the register without the aforementioned communication information being set, the writing of the aforementioned setting information to the aforementioned setting area is not reflected.

15. The data processing apparatus of claim 1, wherein the setting information sent from the host includes a counter expectation value for the counter value of the write counter, and the register includes an expectation value register that stores the counter expectation value.

16. The data processing apparatus of claim 15 further comprises: a temporary memory unit that temporarily stores the setting information sent from the host computer; and a write determination unit that, based on the storage data, determines the correctness of the setting information stored in the temporary memory unit, and when it determines that the setting information is correct and the counter value of the write counter is consistent with the expected value of the counter stored in the expected value register, reflects the writing of the setting information to the setting area.

17. The data processing apparatus of claim 4, wherein the notification unit determines the correctness of the setting information based on the security data, and when the setting information is determined to be incorrect, outputs the error information as the notification information.

18. The data processing apparatus of claim 15 further comprises: a notification unit that outputs error information as notification information when the counter value of the write counter is inconsistent with the expected value of the counter stored in the expected value register.

Images