Microelectronic die including swappable phy circuitry and semiconductor package including same

Abstract

A microelectronic device, including a semiconductor package of the device, an IC device assembly including the package, and a method of manufacturing the device. The device includes a substrate; a physical layer (PHY) circuitry on the substrate, including a plurality of receiver (RX) circuits and a plurality of transmitter (TX) circuits; electrical contact structures at the bottom surface of the device; signal routing paths extending, on one hand, between the electrical contact structures, and on the other hand, between at least some of the RX circuits or at least some of the TX circuits; and electrical pathways leading to the PHY circuitry and configured to satisfy at least one of the following conditions: an enable signal input to the device passes through at least some of the electrical pathways to enable a portion of the PHY circuitry; or a disable signal input to the device passes through at least some of the electrical pathways to disable a corresponding portion of the PHY circuitry.

Description

Technical Field

[0001] []

[0002] This invention relates generally to die-to-die (D2D) interconnect technologies within a package, such as Fast Interconnect (CXi) interconnects. [[] [Comparison with related applications] []]

[0003] This application claims the benefit and priority of Indian Patent Application No. 202141061702, filed on December 30, 2021, the entire disclosure of which is incorporated herein by reference. [] [] Prior Technology

[0004] In-package die-to-die (D2D) interconnect technologies, at a high level, include standard interconnect mechanisms and advanced interconnect mechanisms to provide signal connectivity between two dies disposed on the top surface of a package substrate. Standard interconnect mechanisms involve providing signal routing traces, typically within an organic multilayer of the package substrate, to couple the two dies to each other. Advanced interconnect mechanisms provide silicon bridge structures embedded within the package substrate, wherein the silicon bridge structure includes signal routing traces therein to couple the two dies to each other. Examples of silicon bridge structures used for advanced package interconnect mechanisms include embedded multi-die interconnect bridges (EMIBs) or wafer-on-wafer-on-board (CoWoS). A given D2D interconnect technology or mechanism can be selected based on many factors, such as, for example, bandwidth density requirements (e.g., bandwidth per millimeter (BW / mm) and / or BW / ), the layout planning required for the die / package, and the available form factor. Summary of the Invention

[0005] and Simple Explanation of the Diagram

[0006] []

[0007] Embodiments of the invention will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the invention. However, these embodiments should not be construed as limiting the invention to the specific embodiments, but are merely for illustration and understanding. [] []

[0008] [Figure 1] is a cross-sectional view of a microelectronic assembly including an example of a standard interconnect mechanism. [] []

[0009] [Figure 2] is a cross-sectional view of a microelectronic assembly including an example of an advanced interconnect mechanism. [] []

[0010] [Figure 3] is a cross-sectional view of the microelectronic assembly according to the embodiment. [] []

[0011] [Figure 4A] is a bottom plan view of a first die including C4 bumps according to an advanced interconnect mechanism, based on an embodiment. [] []

[0012] [Figure 4B] is a bottom plan view of a first die including C4 bumps according to an advanced interconnect mechanism, based on an embodiment. [] []

[0013] [Figure 5] illustrates an example layout 500 of a bump for a data rate of 16 billion transfers per second (GT / s) on a standard package trace (e.g., on a package with a pitch of approximately 110 micrometers) according to various embodiments. [] []

[0014] [Figure 6] illustrates an example layout 600 of a bump for a data rate of 32 GT / s on a standard package trace (e.g., on a package with a pitch of approximately 110 micrometers) according to various embodiments. [] []

[0015] [Figure 7] illustrates an example layout 700 of a bump for a data rate of 16 GT / s on a standard package trace (e.g., on a package with a pitch of approximately 110 micrometers) according to various embodiments. [] []

[0016] [Figure 8] illustrates an example layout 800 of a bump for a data rate of 32 GT / s on a standard package trace (e.g., on a package with a pitch of approximately 110 micrometers) according to various embodiments. [] []

[0017] [Figure 9] illustrates example bumps for advanced packaging (e.g., in EMIB or some other similar packaging with a pitch of approximately 45 micrometers) according to various embodiments. [] []

[0018] [Figure 10] illustrates example bumps on advanced packaging traces (e.g., on a package with a pitch of approximately 45 micrometers) according to various embodiments. [] []

[0019] [Figure 11] is a flowchart of the process according to some embodiments. [] []

[0020] [Figure 12] is a cross-sectional side view of an integrated circuit device assembly that may include microelectronic structures, according to any embodiment disclosed herein. [] []

[0021] [Figure 13] is a block diagram of an example electrical device that may include a microelectronic structure according to any embodiment disclosed herein. [] Implementation

[0022] []

[0023] The following description and accompanying drawings fully illustrate specific embodiments to enable those skilled in the art to practice them. Other embodiments may include variations in structure, logic, electrical properties, processing, and other aspects. Parts and features of some embodiments may be included in or substitute for parts and features of other embodiments. The embodiments set forth in the claims cover available equivalents of those claims. In the following description, various viewpoints of exemplary implementations will be described using terminology commonly used by those skilled in the art to convey the essence of their work to others skilled in the art. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced only in some of the viewpoints described. Specific figures, materials, and configurations are set forth for illustrative purposes to provide a thorough understanding of exemplary implementations. However, it will be apparent to those skilled in the art that embodiments of the invention may be practiced without specific details. In other instances, well-known features have been omitted or simplified to avoid obscuring exemplary implementations.

[0024] In the following detailed description, reference is made to the accompanying drawings, which form a part thereof, wherein the same characters consistently indicate the same components, and wherein exemplary embodiments are shown by way of example in which the subject matter of the invention can be practiced. It should be understood that other embodiments may be utilized and structural or logical changes may be made without departing from the scope of the invention. Therefore, the following description should not be regarded as limiting, and the scope of the embodiments is defined by the appended claims and their equivalents.

[0025] The techniques described herein can be implemented in one or more electronic devices. Non-limiting examples of electronic devices that can utilize the techniques described herein include any kind of mobile and / or fixed device, such as microelectromechanical systems (MEMS) based electrical systems, gyroscopes, advanced driver assistance systems (ADAS), 5G communication systems, cameras, mobile phones, computer terminals, desktop computers, e-readers, fax machines, information stations, netbooks, laptops, internet devices, payment terminals, personal digital assistants, media players and / or recorders, servers (e.g., blade servers, rack-mount servers, combinations thereof, etc.), set-top boxes, smartphones, tablets, ultra-portable personal computers, wired phones, combinations thereof, etc. These devices can be portable or fixed. In some embodiments, the techniques described herein can be used with desktop computers, laptops, smartphones, tablets, netbooks, laptops, personal digital assistants, servers, combinations thereof, etc. More generally, the techniques described herein can be used in any of a variety of electronic devices, including semiconductor packages having a passive heat sink, interface layer, TIM, top die, side die, substrate, and packaging substrate.

[0026] As used herein, the terms “top,” “bottom,” “above,” “below,” “lowest,” and “topmost,” when used in relation to one or more elements, are intended to convey a relationship rather than an absolute entity configuration. Therefore, when the device is inverted, an element described as the “topmost element” or “first element” in the device may alternatively form the “bottommost element” or “last element” in the device. Similarly, when the device is inverted, an element described as the “bottommost element” or “last element” in the device may alternatively form the “topmost element” or “first element” in the device.

[0027] Compared to advanced packaged interconnect technologies, microelectronic assemblies, including standard interconnect technologies, often suffer from lower interconnect wire density. The use of silicon bridges in advanced interconnect mechanisms allows for tighter-pitch interconnects, enabling greater signal bandwidth through higher density and tighter-pitch conductivity structures (e.g., C4 bumps, smaller solder bumps, or Cu-Cu connections) provided under each die.

[0028] Existing technologies envision D2D physical layer configurations (PHYs) that, due to various factors including bump pitch differences and connections for a given PHY region, are suitable for in-package interconnect mechanisms in both standard and advanced packaging substrates.

[0029] As used herein, the term "PHY" may refer to the physical layer architecture within a die, including the circuitry therein, such as receive (RX) and transmit (TX) circuitry. That is, "PHY" may refer to the logic and circuitry architecture within a given die.

[0030] As used herein, the term “die” is intended to refer broadly to a die, a chip, or any other integrated circuit structure that includes circuitry and is supported on a substrate.

[0031] According to existing technology, the PHY within a given die is configured differently depending on whether the die is to be coupled to another die on the package using a standard interconnect mechanism or an advanced interconnect mechanism. According to existing technology, the PHY used for standard interconnect mechanisms in a die differs from the PHY used for advanced interconnect mechanisms. Therefore, according to existing technology, a die coupled to another die via in-package interconnect has a PHY configuration such that each different PHY circuit (e.g., each RX or TX circuit of the die) is connected to one or more electrical contact structures at the bottom region of the die (facing the package).

[0032] Some embodiments herein advantageously provide a plurality of dies (including wafers) having the same PHY circuit design as each other, wherein one die may have electrical contact structures corresponding to standard package interconnects on the receive package (e.g., controlled knocking down for die connection (C4) bumps), while another die may have electrical contact structures corresponding to advanced package interconnects on the receive package. The embodiments advantageously enable the provision of identical dies for D2D signal interconnects through the package, wherein any given die may be fitted with conductive structures corresponding to standard package interconnects or conductive structures corresponding to advanced package interconnects. According to some embodiments, the dies are configured to allow mapping of signal paths (i.e., traces or vias) to suit standard or advanced bump configurations, including bump spacing.

[0033] The prior art will now be explained in relation to the situations shown in Figures 1 and 2.

[0034] Figure 1 is a cross-sectional view of an example microelectronic assembly or semiconductor package 100 including a package substrate 104 and two dies 108 and 116 supported on the top surface 112 of the package substrate 104. In Figure 1, the package substrate 104 is shown as including signal routing traces 136 coupling dies 108 to dies 116. The substrate 104 may include a core layer comprising sublayers of non-conductive materials such as glass, silicon, or organic materials, and traces 136 extending through these sublayers for conducting electrical signals therein. Dies 108 and 116 are each electrically coupled to the top surface 112 of the package substrate 104 via electrical contact structures or connectors 156, such as C4 bumps, connected to die conductive contacts and substrate conductive contacts (not shown) of the respective dies. The C4 bump is coupled to dies 108 and 116 together by traces 136, which extend through the package substrate 104 and provide a conductive path between dies 108 and 116. An additional conductive structure 159 is disposed on the bottom surface of the package substrate.

[0035] Figure 2 is a cross-sectional view of an example microelectronic assembly or semiconductor package 200 including an interconnect bridge 222 embedded within a package substrate 204 and two dies 208 and 216 supported on the top surface 212 of the package substrate 204. In Figure 2, the combination of the package substrate 204 and the interconnect bridge 222 will be referred to together as the microelectronic structure 201. The substrate 204 may include a core layer comprising sublayers of non-conductive materials such as glass, silicon, or organic materials, and conductive traces 244 extending through these sublayers for conducting electrical signals therein. The first integrated circuit die 208 is attached to the top surface 212 of the package substrate 204 via an electrical contact structure or connector 256 connecting the die conductive contact 264 and the substrate conductive contact 210. The second integrated circuit die 216 is attached to the surface 212 via a coupling assembly 260 connected to the die conductive contact 266 and the substrate conductive contact 220.

[0036] Bridging conductive contacts 224 and 226 are located on face 228 of bridge 222. Bridging via 232 and bridging conductive trace 236 provide conductive pathways between conductive contacts 224 and 226. Substrate via 240 and substrate conductive trace 244 provide conductive pathways from substrate conductive contact 210 to bridging conductive contact 224, and substrate via 248 and substrate conductive trace 244 provide conductive pathways from substrate conductive contact 220 to bridging conductive contact 226. Simultaneously, conductive contacts 210, 220, 224, 226, vias 232, 240, 248, and conductive traces 236, 244 provide conductive pathways between integrated circuit dies 208 and 216, thereby allowing them to be communicatively coupled.

[0037] Although the embedded interconnect bridge 222 is shown as being fully embedded within the substrate assembly 204, in some embodiments it may be partially embedded, with the bridge surface 228 being a portion of surface 212 of the first substrate assembly 204. In these embodiments, bridging conductive contacts 224 and 226 may be located at surface 212 of the substrate assembly 204, and integrated circuit chips 208 and 216 may be connected to the bridging conductive contacts 224 and 226, respectively, via coupling components 256 and 260.

[0038] Many of the elements of the semiconductor package 100 or 200 of Figure 1 or Figure 2 are included in other figures related to certain embodiments, such as Figures 3, 4A, and 4B. Therefore, descriptions of some elements may not be repeated when discussing the figures described below, and any of such elements may take any form disclosed herein.

[0039] Furthermore, in the following description of Figures 3, 4A and 4B, although the reference to C4 bump refers to an electrical contact structure that couples the die to the package substrate, the embodiments are not limited thereto, and within their scope include providing electrical contact structures that do not include C4 bumps or bumps, such as electrical contact structures in the form of contact pads, leads or wire bonding, depending on the application requirements.

[0040] Figure 3 is a cross-sectional view of an example microelectronic assembly or semiconductor package 300 according to some embodiments. In the embodiments of Figure 3, the dies on the package all include the same set of PHY circuitry, but still allow mapping of signal paths (i.e., traces or vias) to suit electrical contact structures corresponding to standard or advanced electrical contact configurations.

[0041] In Figure 3, the microelectronic assembly 300 includes a package substrate 304, which includes electrical contact structures 359 on its bottom surface for contacting a motherboard or larger system (in the example shown, the electrical contact structures 359 are implemented as C4 bumps, although other examples are within the scope of this embodiment), and four dies 308a, 316a, 308b, 316b, supported on the top surface of the package substrate 304. The four dies, in pairs, are coupled to each other via in-package D2D interconnects arranged in the package substrate 304 with corresponding bumps including C4 bumps 356a and 356b. The package substrate 304 may include a core layer comprising sublayers of a non-conductive material such as glass, silicon, or organic materials. Regarding the PHY circuitry, the four dies 308a, 316a, 308b, 316b are identical to each other because they each contain the same RX and TX circuitry, as will be further explained below. However, while dies 308a and 316a are configured to be coupled to each other via a signal routing path (standard interconnect mechanism) including an electrical contact structure 356a (such as a C4 bump) on their bottom surface through a trace 336a extending through the material of the package substrate 304, dies 308b and 316b are configured to be coupled to each other via a signal routing path (advanced interconnect mechanism) including a trace 33bb extending through a silicon bridge embedded in the package substrate 304.

[0042] Therefore, the microelectronic assembly 300 includes a standard interconnect portion 301a and an advanced interconnect portion 301b. The standard interconnect portion 301a, in addition to the corresponding lower layer portion of the package substrate 304, also includes a first die 308a and a second die 316a supported on the top surface 312a of the package substrate 304. Dies 308a and 316a are coupled to each other in the same manner as dies 108 and 116 in FIG. 1, that is, using a standard interconnect mechanism. The advanced interconnect portion 301b, in addition to the corresponding lower layer portion of the package substrate 304, also includes a first die 308b and a second die 316b supported on the top surface 312b of the package substrate 304. Dies 308b and 316b are coupled to each other in the same manner as dies 208 and 216 in FIG. 2, that is, using an advanced interconnect mechanism.

[0043] For the standard interconnect portion 301a, the package substrate 304 is shown as containing a signal routing path including traces 336a that couple dies 308a to dies 316a and extend through sublayers of the substrate to conduct electrical signals therein. Dies 308a and 316a are each electrically coupled to the top surface 312a of the package substrate 304 via electrical contact structures or connectors 356a, such as C4 bumps, connected to die conductive contacts and substrate conductive contacts (not shown) of the respective dies. Each of dies 308a and 316a includes a set of PHY circuitry.

[0044] The first die of the standard interconnect portion, die 308a, includes a PHY circuit comprising an RX circuit 309a and a TX circuit 311a. The RX circuit 309a includes a separate RX circuit 309a', and the TX circuit 311a includes a separate TX circuit 311a'. The second die of the standard interconnect portion, die 316a, includes a PHY circuit comprising an RX circuit 317a and a TX circuit 319a. The RX circuit 317a includes a separate RX circuit 317a', and the TX circuit 319a includes a separate TX circuit 319a'. Dies 308a and 316a are identical to each other in terms of their respective PHY circuits (as shown in Figure 3), although the description shows the TX circuit of die 308a facing to the left of the figure, and the TX circuit of die 316a facing to the right of the figure.

[0045] In the standard interconnect portion 301a, each die 308a and 316a includes at least one PHY circuit (RX circuit and / or TX circuit) that is not coupled to any C4 bump. Thus, each die 308a and 316a has at least one PHY circuit that is not electrically coupled to any C4 bump. Therefore, redundant or non-functional PHY circuits exist in the standard interconnect portion 301a.

[0046] For the advanced interconnect portion 301b, the package substrate 304 is shown as including an interconnect bridge 322 comprising a signal routing path including traces 336b coupling dies 308b to dies 316b and extending through the bridge to conduct electrical signals therein. Dies 308b and 316b are each electrically coupled to the top surface 312b of the package substrate 304 via electrical contact structures or connectors 356b, such as C4 bumps, connected to die conductive contacts and substrate conductive contacts (not shown) of the respective dies. Each of dies 308b and 316b includes a set of PHY circuitry.

[0047] Although the embedded interconnect bridge 322 is shown as being fully embedded within the substrate package 304, in some embodiments it may be partially embedded, with the upper surface of the bridge 322 extending substantially together with the upper surface 312 of the substrate package 304.

[0048] The first die of the advanced interconnect portion, die 308b, includes a PHY circuit comprising an RX circuit 309b and a TX circuit 311b. The RX circuit 309b includes a separate RX circuit 309b', and the TX circuit 311b includes a separate TX circuit 311b'. The second die of the advanced interconnect portion, die 316b, includes a PHY circuit comprising an RX circuit 317b and a TX circuit 319b. The RX circuit 317b includes a separate RX circuit 317b', and the TX circuit 319b includes a separate TX circuit 319b'. Dies 308b and 316b are identical to each other in terms of their respective PHY circuits (as shown in Figure 3), although the description shows the TX circuit of die 308b facing to the left of the figure, and the TX circuit of die 316b facing to the right of the figure.

[0049] In the advanced interconnect portion 301b, all PHY circuits in each die 308b and 316b are connected to the corresponding C4 bump. Thus, each die 308b and 316b includes electrical coupling between all its PHY circuits and the corresponding C4 bump. Therefore, there are no redundant or non-functional PHY circuits in the advanced interconnect portion 301b.

[0050] In the microelectronic assembly of FIG3, in which the first die and the second die are coupled to each other through in-package interconnects, each active RX circuit of the first die is coupled to the corresponding active TX circuit of the second die through in-package D2D interconnects, and each active TX circuit of the first die is coupled to the corresponding active RX circuit of the second die through in-package D2D interconnects.

[0051] Figure 4A shows a bottom plan view of a die, including bumps corresponding to dies 308a / 316a (hereinafter referred to as 308a, as dies 308a and 316a are the same), while Figure 4B shows a bottom plan view of a die, including bumps corresponding to dies 308b / 316b (hereinafter referred to as 308b, as dies 308b and 316b are the same). Therefore, Figure 4A is a bottom plan view of a die 308a with C4 bumps on its bottom surface, where the C4 bumps correspond to a standard electrical contact configuration equivalent to the standard electrical contact configuration shown in the standard interconnect portion 301a of Figure 3, while Figure 4B is a bottom plan view of a die 308b with a predetermined PHY circuit and C4 bumps on its bottom surface, where the C4 bumps correspond to a standard or advanced electrical contact configuration equivalent to the standard or advanced electrical contact configuration shown in the standard interconnect portion 301a of Figure 3.

[0052] In Figures 4A and 4B, the portions of chips 308a and 308b corresponding to the positions within the RX circuits 309a / 309b are shown as solid shaded areas, while the portions of chips 308a and 308b corresponding to the TX circuits 311a / 311b are shown as striped shaded areas. Since chips 308a and 308b are identical, as mentioned earlier, they include the same RX and TX circuit architectures.

[0053] In Figures 4A and 4B, for the illustrated embodiments, the bumps for C4 bumps on the bottom surfaces of dies 308a and 308b are suitably depicted as circular areas with some marked and some unmarked circular regions. The unmarked circular regions correspond to C4 bumps for the VCC (power) or VSS (ground) signals of the die, and the marked circular regions correspond to C4 bumps that provide signal paths to and from the PHY circuitry within the die. In the illustrated example, the TX circuits 311a / 311b overlap (i.e., are physically superimposed) with their corresponding C4 bumps, as shown by the complete overlap between the TX circuits 311a / 311b and the C4 bump 356b, while the RX circuits 309a / 309b and their corresponding C4 bumps are shown as partially overlapping. The RX circuits do not exhibit significant distance sensitivity relative to their C4 bumps, thus allowing for configurations such as those shown in Figures 4A and 4B. However, embodiments are not limited to these, and the positioning of the RX or TX circuits relative to their corresponding conductive structures (e.g., C4 bumps) can be included in any manner required by the application. The illustrated die may further include non-PHY circuitry, such as non-PHY logic circuitry, which, in the examples shown in Figures 4A and 4B, can be positioned in an unmasked region of the die.

[0054] According to an embodiment, the die includes enable / de-enable electrical paths connected to the PHY circuitry, such that enable / de-enable signals input to the die cause these enable / de-enable electrical paths to enable / de-enable at least one RX circuit or a portion of a TX circuit in the die (i.e., a portion (not all) of the RX circuit and / or a portion (not all) of the TX circuit). Therefore, for a die having a predetermined configuration of RX and TX circuits according to an embodiment, the electrical paths enable a portion of the RX and / or TX circuits by an enable signal input to the die. Similarly, for the same die, the electrical paths de-enable a portion, but not all, of the RX and / or TX circuits by a de-enable signal input to the die. For example, the electrical paths may include electrical paths extending to each RX circuit and each TX circuit. In this case, an enable or de-enable signal can be input into a portion of the electrical paths to enable or de-enable the corresponding RX or TX circuit. Alternatively, the electrical path can extend to different RX circuit groups and different TX circuit groups, in which case each group can be enabled / de-enabled simultaneously. In this case, an enable signal or a de-enabled signal can be input to the electrical path corresponding to the RX circuit or TX circuit group to enable / de-enabled the corresponding RX circuit or TX circuit of that group. Regardless of the configuration of the enable / de-enabled conductive path, the die according to the embodiment can be further configured such that the enable / de-enabled signal input to the die enables / de-enabled all PHY circuits of the die. Enabling one part of the PHY circuit and de-enabled another part of the PHY circuit corresponds to a die with bumps or protrusions according to a standard interconnect mechanism, such as that shown in the standard interconnect portion 301a of FIG. 3. Enabling all PHY circuits corresponds to a die with bumps or protrusions according to an advanced interconnect mechanism, such as that shown in the advanced interconnect portion 301b of FIG. 3.

[0055] According to one embodiment, the enable / de-enable conductivity path of the die according to the embodiment may include respective fuses or registers for being burned off to de-enable or enable a corresponding associated PHY circuit in the conductivity path.

[0056] According to the embodiments, the boot logic configuration can determine how much PHY circuitry to enable or disable.

[0057] The embodiments described herein can implement a superset PHY circuit design (e.g., a PHY circuit with 64 transmitters (TX) and 64 receivers (RX)) on the same die containing all signaling and logic supporting advanced package interconnects, and use the same PHY circuit design with some disabled RX and TX circuits, and die bumps (e.g., only changes to the top metal and bumps) to support standard package interconnects (e.g., a PHY circuit with 16 TX + 16 RX), thereby disabling unused channels.

[0058] In some embodiments, aside from the presence of enable / de-enable conductive paths within the die that allow enabling / de-enable only a portion of the PHY circuitry, if the die's bump layer and overlying redistribution layer (RDL) are stripped, it is possible to observe separate TX and RX PHY circuits (one per bump), as suggested above. When assembled in an advanced package, a 1:1 connection relative to the signaling bump may be observed between TX / RX circuits (or circuit blocks). When assembled in a standard package (e.g., in the x64 vs. x16 examples above), a 4:1 TX / RX circuit block ratio relative to the signaling bump may be observed, meaning one out of every four PHY circuits on the die is connected to a bump.

[0059] The embodiments described herein propose providing a common PHY circuit within the die, through which electrical contact structures compatible with standard interconnect mechanisms, or with advanced interconnect mechanisms (e.g., EMIB, CoWoS, etc.), can be configured via a package substrate to provide D2D interconnects. These electrical contact structures may include bumps such as C4 bumps, although other electrical contact configurations are within the scope of these embodiments.

[0060] As an example, referring again to Figures 4A and 4B, standard package bumps for signaling may have a pitch of approximately 110 micrometers (μm or “microns”), while advanced package bumps may have a pitch of approximately 45 to approximately 55 micrometers. With this example, an advanced interconnect mechanism may have approximately four bumps in the same area as a standard interconnect mechanism bump.

[0061] It should be noted that the pitch values ​​used for standard and advanced packages, and the ratio between them, may vary in different embodiments. For example, the pitch may be higher or lower than described above. In one embodiment, the pitch of the standard package may be between approximately 110 micrometers and approximately 130 micrometers, and the pitch of the advanced package may be between approximately 36 micrometers and approximately 55 micrometers. This can make the ratio of the standard package pitch to the advanced package pitch approximately 2:1, although in some real-world embodiments it may be on the level of approximately 2.4:1. As noted, other embodiments may present a higher or lower ratio between the advanced package pitch and the standard package pitch.

[0062] Furthermore, as bump pitch decreases (e.g., to approximately 25 micrometers or 16 micrometers or smaller), the ratio of bumps in a standard package to those in an advanced package may change. For example, an advanced package might have 64 bumps in a given area, while a standard package might have only 4 bumps in that area. Alternatively, a standard package might have 16 bumps in a given area, while an advanced package might have 128 bumps in that area, 256 bumps in that area, and so on. In other words, a swappable ratio of 16 standard bumps to 64 advanced bumps can be a suitable value for a range of bump pitches, and as the pitch ratio widens, the scalar ratio can similarly track this change.

[0063] The embodiments offer numerous advantages. One such advantage is that the embodiments allow the same die or wafer base (requiring only new bump layers, bump via layers, and one or two underlying metal layers for interconnection, depending on the specific implementation) to be reused in advanced and standard packages. The embodiments also allow shared logic interfaces and I / O protocols to operate in both advanced and standard packages. The embodiments increase die reusability and lifetime / duty by designing PHY circuitry on the die so that the die can be interchanged between various package interconnect mechanisms, thereby giving the dies according to the embodiments a technical advantage over prior art dies. This reusability can further reduce significant pre- and post-silicon development costs and allow for faster time-to-market customization of different hybrid and matched wafer / system-on-a-chip (SoC) solutions for different market segments.

[0064] Figure 5 illustrates an example layout 500 of a bump for a data rate of 16 billion transfers per second (GT / s) on a standard package trace (e.g., on a package with a pitch of approximately 110 micrometers) according to various embodiments. Specifically, Figure 5 depicts two example bumps. The bump on the left (as shown in Figure 5) may be suitable for use with four package routing layers, while the bump on the right (as shown in Figure 5) may be suitable for use with two package routing layers (therefore the signal is only half that of the left bump).

[0065] Figure 6 illustrates an example layout 600 of a bump for a data rate of 32 GT / s on a standard package trace (e.g., on a package with a pitch of approximately 110 micrometers) according to various embodiments. Specifically, Figure 6 depicts two example bumps. The bump on the left (as shown in Figure 6) may be suitable for use with four package routing layers, while the bump on the right (as shown in Figure 6) may be suitable for use with two package routing layers (therefore the signal is only half that of the left bump).

[0066] Figure 7 illustrates an example layout 700 of bumps for a data rate of 16 GT / s on a standard package trace (e.g., on a package with a pitch of approximately 110 micrometers) according to various embodiments. Figure 7 specifically depicts two example bumps. The bottom bump (as shown in Figure 7) may be suitable for use with four package routing layers, while the top bump (as shown in Figure 7) may be suitable for use with two package routing layers (thus only half the signal of the bottom bump).

[0067] Figure 8 illustrates an example layout 800 of bumps for a data rate of 32 GT / s on a standard package trace (e.g., on a package with a pitch of approximately 110 micrometers) according to various embodiments. Figure 8 specifically depicts two example bumps. The bottom bump (as shown in Figure 8) may be suitable for use with four package routing layers, while the top bump (as shown in Figure 8) may be suitable for use with two package routing layers (thus only half the signal of the bottom bump).

[0068] The difference between the embodiments shown in Figures 5 and 6 and those shown in Figures 7 and 8 lies in the fact that these paired diagrams illustrate different ways of implementing the removable PHY with different sets of constraints on the package routing. The pairings in Figures 7 and 8 are better for channel-to-channel skew within a channel because of better length matching and all TX and RX signals being on the same layer, but worse for on-die clock distribution and power delivery.

[0069] Figure 9 illustrates an example layout 900 of a bump for advanced packaging (e.g., an EMIB with approximately 45 micrometer pitch or some other similar package) according to various embodiments. It should be noted that one can begin with the bump of Figure 9 and convert it to operate on organic traces (e.g., standard package bumps), as described herein. Alternatively, one can begin with the bumps of any of Figures 5 through 8 and convert those bumps to operate on advanced package bumps, as described herein.

[0070] Typically, for bumps described in advanced packaging, the bottom left corner of the bump map can be considered the "origin" or starting point of the bump matrix. The following rules apply to advanced packaging bump matrices: • Signals within a row can be preserved. For example, row 0 can contain the signals: txdataRD0, txdata0, txdata1, txdata2, txdata3, txdata4, txdata5, rxdata58, rxdata59, rxdata60, rxdata61, rxdata62, rxdata63, rxdataRD3, and txdatasb; and • The power and VSS patterns shown in the bump matrix can be implemented. Sufficient VSS and power bumps will be configured to meet channel characteristics (FEXT and NEXT) and power delivery requirements.

[0071] For one or two standard module packages, different bump matrices can be configured as described herein. The lower left corner of the bump diagram can be considered the "origin" or starting point of the bump matrix. The signal exit sequence for the bump matrices used in x16 and x32 standard packages can be as shown in this document.

[0072] The following rules can be implemented for standard package bump matrices: • Signals within a row can be preserved. For example, for the x16 (a standard module package interface) shown in Figure 7, row 1 can contain the signals: txdata0, txdata1, txdata9, txdata9, and txdatasb1. • Signals can exit the bump field. Layer 1 and Layer 2 are two different signal routing layers in the standard package. • The power and VSS patterns shown in the bump matrix can be followed. It can be ensured that sufficient VSS and power bumps will be configured to meet the channel characteristics (FEXT and NEXT) and power delivery requirements.

[0073] Figure 10 illustrates an example layout 1000 of a bump for an advanced packaging trace (e.g., on a package with a pitch of approximately 45 micrometers) according to various embodiments.

[0074] For packages with standard pitch (e.g., the package of Figure 7 or 8, or other packages such as those of Figure 5 or 6), a unidirectional PHY can be created by placing the TX on one side of the package and the RX on the other side. This embodiment is possible if it is known that data always flows through the package in one direction. As a result, for embodiments such as those described in Figure 7 or 8 (or other embodiments herein), such embodiments can operate on a single-layer package, thereby optimizing bandwidth, area, and / or cost. The corresponding replaceable advanced package may only include TX or RX, thus enabling unidirectional data flow with optimized cost, area, and / or bandwidth.

[0075] Figure 11 illustrates a method 1100 for manufacturing a microelectronic device, such as a die, according to some embodiments. In operation 1102, the process includes providing a substrate. In operation 1104, the process includes providing a physical layer (PHY) circuit on the substrate, the physical layer (PHY) circuit including a plurality of receive (RX) circuits and a plurality of transmit (TX) circuits. In operation 1106, the process includes providing electrical contact structures at the bottom surface of the device. In operation 1108, the process includes providing signal routing paths extending, on one hand, between the electrical contact structures, and on the other hand, between at least some of the RX circuits or at least some of the TX circuits. In operation 1110, the process includes providing an electrical path to the PHY circuit. In operation 1112, the process includes at least one of: providing an enable signal into the device, enabling a portion of the PHY circuit through at least some of the electrical paths; or providing a disable signal into the device, disabling a corresponding portion of the PHY circuit through at least some of the electrical paths.

[0076] Figures 12 and 13 show some examples of an architecture that may include one or more microelectronic assemblies, similar to the microelectronic assemblies described above in the context of the embodiments illustrated by examples in Figures 3, 4A and 4B.

[0077] Figure 12 is a cross-sectional side view of an integrated circuit assembly 1200 that may include one or more integrated circuit structures, each of which includes any MCP package of the embodiments described herein. The integrated circuit assembly 1200 includes a number of components disposed on a circuit board 1202 (which may be a motherboard, system board, motherboard, etc.). The integrated circuit assembly 1200 includes components disposed on a first surface 1240 and an opposing second surface 1242 of the circuit board 1202; typically, components may be disposed on one or both of surfaces 1240 and 1242. Any integrated circuit assembly discussed below with reference to the integrated circuit assembly 1200 may include an integrated circuit structure including cascaded MCPs as disclosed herein.

[0078] In some embodiments, circuit board 1202 may be a printed circuit board (PCB) comprising multiple metal (or interconnect) layers, which are spaced apart from each other by dielectric material layers and interconnected by conductive vias. Individual metal layers include conductive traces. Any one or more metal layers may be formed in a desired circuit pattern to route electrical signals between components coupled to circuit board 1202 (optionally in conjunction with other metal layers). In other embodiments, circuit board 1202 may be a non-PCB substrate. The integrated circuit assembly 1200 shown in FIG. 12 includes an interposer-on-a-package (IPA) structure 1236, which is coupled to a first surface 1240 of circuit board 1202 via coupling component 1216. The coupling assembly 1216 can electrically and mechanically couple the on-intermediate package structure 1236 to the circuit board 1202, and may include solder balls (as shown in FIG12), pins (e.g., as part of a pin grid array (PGA), contacts (e.g., as part of a ground grid array (LGA)), male and female portions of a socket, adhesive, underfill material, and / or any other suitable electrical and / or mechanical coupling structure.

[0079] The on-intermediate package structure 1236 may include an integrated circuit assembly 1220 coupled to the intermediate layer 1204 via coupling components 1218. These coupling components 1218 may take any suitable form for application, such as those discussed above with reference to coupling component 1216. Although a single integrated circuit assembly 1220 is shown in FIG. 12, multiple integrated circuit assemblies may be coupled to the intermediate layer 1204; in fact, additional intermediaries may be coupled to the intermediate layer 1204. The intermediate layer 1204 may provide an intermediate substrate for bridging the circuit board 1202 and the integrated circuit assembly 1220.

[0080] Integrated circuit assembly 1220 may be a packaged or unpackaged integrated circuit product comprising one or more integrated circuit dies. A packaged integrated circuit assembly includes one or more integrated circuit dies mounted on a package substrate, wherein the integrated circuit dies and the package substrate are encapsulated in a casting material such as metal, plastic, glass, or ceramic. In one example of an unpackaged integrated circuit assembly 1220, a single monolithic integrated circuit die includes solder bumps attached to contacts on the die. These solder bumps allow the die to be directly attached to the interposer 1204. Integrated circuit assembly 1220 may include one or more computing system components, such as one or more processor units (e.g., system-on-a-chip (SOC), processor core, graphics processing unit (GPU), accelerator, chipset processor), I / O controller, memory, or network interface controller. In some embodiments, the integrated circuit assembly 1220 may include one or more additional active or passive devices, such as capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices.

[0081] In embodiments where the integrated circuit assembly 1220 includes a plurality of integrated circuit dies, these dies may be of the same type (homogeneous multi-die integrated circuit assembly) or two or more different types (heterogeneous multi-die integrated circuit assembly). A multi-die integrated circuit assembly may be referred to as a multi-chip package (MCP) or a multi-chip module (MCM).

[0082] In addition to including one or more processor units, the integrated circuit assembly 1220 may include additional components such as embedded DRAM, stacked high-bandwidth memory (HBM), shared cache memory, input / output (I / O) controller, or memory controller. Any of these additional components may be located on the same integrated circuit die as the processor unit, or on one or more integrated circuit dies spaced apart from the integrated circuit die including the processor unit. These separate integrated circuit dies may be referred to as “chiplets.” In embodiments where the integrated circuit assembly includes multiple integrated circuit dies, interconnections between the dies may be provided by a package substrate, one or more silicon interposers, one or more silicon bridges embedded in the package substrate (such as Intel® Embedded Multi-Die Interconnect Bridges (EMIBs)), or a combination thereof.

[0083] Typically, interposer 1204 can extend connections to wider spacing or reroute connections to different connections. For example, interposer 1204 can couple integrated circuit assembly 1220 to a set of ball grid array (BGA) conductive contacts for coupling assembly 1216 of circuit board 1202. In the embodiment shown in FIG12, integrated circuit assembly 1220 and circuit board 1202 are attached to opposite sides of interposer 1204; in other embodiments, integrated circuit assembly 1220 and circuit board 1202 may be attached to the same side of interposer 1204. In some embodiments, three or more components may be interconnected via interposer 1204.

[0084] In some embodiments, the interposer 1204 may be formed as a PCB comprising multiple metal layers spaced apart from each other by dielectric material layers and interconnected by conductive vias. In some embodiments, the interposer 1204 may be formed of epoxy resin, glass fiber reinforced epoxy resin, epoxy resin with inorganic fillers, ceramic material, or polymeric material such as polyimide. In some embodiments, the interposer 1204 may be formed of alternating rigid or flexible materials, which may include the same materials described above for use in semiconductor substrates, such as silicon, germanium, and other group III-V and group IV materials. Intermediate layer 1204 may include metal interconnects 1208 and vias 1210, including but not limited to through-hole vias 1210-1 (extending from the first side 1250 of the intermediate layer 1204 to the second side 1254 of the intermediate layer 1204), blind vias 1210-2 (extending from the first or second side 1250 or 1254 of the intermediate layer 1204 to the inner metal layer), and buried vias 1210-3 (connecting to the inner metal layer).

[0085] In some embodiments, intermediary layer 1204 may include a silicon intermediary layer. Through-silicon vias (TSVs) extending through the silicon intermediary layer may connect to an opposite second surface of the silicon intermediary layer on a first surface. In some embodiments, intermediary layer 1204 including the silicon intermediary layer may further include one or more routing layers for routing connections on the first surface of intermediary layer 1204 to the opposite second surface of the intermediary layer 1204.

[0086] Intermediate layer 1204 may also include embedded devices 1214 comprising both passive and active devices. These devices may include, but are not limited to, capacitors, decoupling capacitors, resistors, inductors, fuses, diodes, transformers, sensors, electrostatic discharge (ESD) devices, and memory devices. Further composite devices, such as radio frequency devices, power amplifiers, power management devices, antennas, arrays, sensors, and microelectromechanical systems (MEMS) devices, may also be formed on intermediate layer 1204. The on-intermediate package structure 1236 may take the form of any on-intermediate package structure known in the art. In this embodiment, the intermediate layer is not a printed circuit board.

[0087] The integrated circuit assembly 1200 may include an integrated circuit component 1224 coupled to a first surface 1240 of a circuit board 1202 via a coupling component 1222. The coupling component 1222 may take the form of any embodiment discussed above with reference to coupling component 1216, and the integrated circuit component 1224 may take the form of any embodiment discussed above with reference to integrated circuit component 1220.

[0088] The integrated circuit assembly 1200 shown in Figure 12 may include a stacked structure 1234 coupled to a second surface 1242 of a circuit board 1202 via a coupling component 1228. The stacked structure 1234 may include integrated circuit components 1226 and 1232 coupled together via a coupling component 1230, such that integrated circuit component 1226 is disposed between the circuit board 1202 and integrated circuit component 1232. Coupling components 1228 and 1230 may take the form of any embodiment of coupling component 1216 discussed above, and integrated circuit components 1226 and 1232 may take the form of any embodiment of integrated circuit component 1220 discussed above. The stacked structure 1234 may be configured according to any form of stacked structure known in the art.

[0089] Figure 13 is a block diagram of an example electrical device 1300 that may include one or more of the MCPs of the embodiments disclosed herein. For example, any suitable component of computing device 1300 may include one or more of the integrated circuit device assembly 1200, integrated circuit component 1220, and / or MCPs of the embodiments disclosed herein. Multiple components are shown in Figure 13 as included in electrical device 1300, but any one or more of these components may be omitted or duplicated to suit an application. In some embodiments, some or all of the components included in electrical device 1300 may be attached to one or more motherboards, motherboards, or system boards. In some embodiments, one or more of these components are manufactured onto a single system-on-a-chip (SoC) die.

[0090] Furthermore, in various embodiments, electrical device 1300 may not include one or more of the components shown in FIG. 13, but electrical device 1300 may include interface circuitry for coupling to the one or more components. For example, electrical device 1300 may not include display device 1306, but may include display device interface circuitry (e.g., connector and driver circuitry) that can be coupled to display device 1306. In another set of examples, electrical device 1300 may not include audio input device 1324 or audio output device 1308, but may include audio input or audio output device interface circuitry (e.g., connector and support circuitry) that can be coupled to audio input device 1324 or audio output device 1308.

[0091] Electrical device 1300 may include one or more processor units 1302 (e.g., one or more processor units). As used herein, the terms "processor unit," "processing unit," or "processor" may mean any device or part of a device that processes electronic data from registers and / or memory to convert that electronic data into other electronic data that may be stored in registers and / or memory. Processor unit 1302 may include one or more digital signal processors (DSPs), application-specific integrated circuits (ASICs), central processing units (CPUs), graphics processing units (GPUs), general-purpose GPUs (GPGPUs), accelerated processing units (APUs), field-programmable gate arrays (FPGAs), neural network processing units (NPUs), data processing units (DPUs), accelerators (e.g., graphics accelerators, compression accelerators, artificial intelligence accelerators), controlled cryptographic processors (dedicated processors that execute cryptographic algorithms in hardware), server processors, controllers, or any other suitable type of processing unit. For this reason, a processor unit may be referred to as an XPU (or xPU).

[0092] Electrical device 1300 may include memory 1304, which may itself include one or more memory devices, such as volatile memory (e.g., dynamic random access memory (DRAM), static random access memory (SRAM)), non-volatile memory (e.g., read-only memory (ROM), flash memory, chalcogen-phase-change non-voltage memory), solid-state memory, and / or hard disk. In some embodiments, memory 1304 may include memory located on the same integrated circuit die as processor unit 1302. This memory may be used as cache memory (e.g., level 1 (L1) cache, level 2 (L2) cache, level 3 (L3) cache, level 4 (L4) cache, final level cache (LLC)), and may include embedded dynamic random access memory (eDRAM) or spin-transfer torque magnetic random access memory (STT-MRAM).

[0093] In some embodiments, the electrical device 1300 may include one or more processor units 1302, which are heterogeneous or asymmetric with other processor units 1302 in the electrical device 1300. Various differences exist between the processor units 1302 in the system in terms of a range of advantages, including architecture, microarchitecture, thermal and power consumption characteristics, etc. These differences can be effectively manifested as the asymmetry and heterogeneity between the processor units 1302 in the electrical device 1300.

[0094] In some embodiments, the electrical device 1300 may include a communication component 1312 (e.g., one or more communication components). For example, the communication component 1312 may manage wireless communication for the transmission of data to and from the electrical device 1300. The term "wireless" and its derivatives are used to describe circuits, devices, systems, methods, techniques, communication channels, etc., that can transmit data using modulated electromagnetic radiation through a non-solid-state medium. The term "wireless" does not imply that the associated device does not contain any wires, although they may be absent in some embodiments.

[0095] Communication component 1312 can implement any of a variety of wireless standards or protocols, including but not limited to IEEE standards, such as Wi-Fi (IEEE 802.11 series), IEEE 802.16 standards (e.g., IEEE 802.16-2005 amendments), Long Term Evolution (LTE) projects, and any amendments, updates, and / or revisions (e.g., Advanced LTE projects, Ultra Mobile Broadband (UMB) projects (also known as "3GPP2"), etc.). IEEE 802.16 Compatible Broadband Wireless Access (BWA) networks are commonly referred to as WiMAX networks, an acronym for Global Microwave Access Interoperability, which is a certification mark for products that have passed conformance and interoperability testing for the IEEE 802.16 standard. Communication component 1312 may operate based on Global System for Mobile Communications (GSM), Universal Packet Radio Service (GPRS), Universal Mobile Telecommunications System (UMTS), High-Speed ​​Packet Access (HSPA), Evolved HSPA (E-HSPA), or LTE networks. Communication component 1312 may operate based on Enhanced Data for GSM Evolution (EDGE), GSM EDGE Radio Access Network (GERAN), Universal Terrestrial Radio Access Network (UTRAN), or Evolved UTRAN (E-UTRAN). Communication component 1312 may operate based on Code Division Multiple Access (CDMA), Time Division Multiple Access (TDMA), Digital Enhanced Wireless Telecommunications (DECT), Evolved Data Optimization (EV-DO), and derivatives thereof, as well as any other radio protocol designated for 3G, 4G, 5G, and higher versions. In other embodiments, communication component 1312 may operate based on other radio protocols. Electrical device 1300 may include one or more antennas 1322 for facilitating wireless communication and / or for receiving other wireless communications (e.g., AM or FM radio transmissions).

[0096] In some embodiments, communication component 1312 can manage wired communications, such as electrical, optical, or any other suitable communication protocol (e.g., the IEEE 802.3 Ethernet standard). As described above, communication component 1312 may include multiple communication components. For example, a first communication component 1312 may be dedicated to short-range wireless communications such as Wi-Fi or Bluetooth, and a second communication component 1312 may be dedicated to longer-range wireless communications such as Global Positioning System (GPS), EDGE, GPRS, CDMA, WiMAX, LTE, EV-DO, etc. In some embodiments, the first communication component 1312 may be dedicated to wireless communications, and the second communication component 1312 may be dedicated to wired communications.

[0097] Electrical device 1300 may include battery / power circuit 1314. Battery / power circuit 1314 may include one or more energy storage devices (e.g., batteries or capacitors) and / or circuitry for coupling components of electrical device 1300 to a power source (e.g., AC line power) separate from electrical device 1300.

[0098] Electrical device 1300 may include display device 1306 (or corresponding interface circuitry, as discussed above). For example, display device 1306 may include one or more embedded or wired or wirelessly connected visual indicators, such as head-up displays, computer monitors, projectors, touch screen displays, liquid crystal displays (LCDs), light-emitting diode displays, or flat panel displays.

[0099] Electrical device 1300 may include audio output device 1308 (or corresponding interface circuitry, as discussed above). For example, audio output device 1308 may include any embedded or wired or wirelessly connected external device that generates a sound indicator, such as a speaker, headphones, or earphones.

[0100] Electrical device 1300 may include audio input device 1324 (or corresponding interface circuitry, as discussed above). For example, audio input device 1324 may include any embedded or wired or wirelessly connected device that generates a signal representing sound, such as a microphone, microphone array, or digital instrument (e.g., an instrument with a Musical Instrument Digital Interface (MIDI) output). Electrical device 1300 may include Global Navigation Satellite System (GNSS) device 1318 (or corresponding interface circuitry, as discussed above), such as a Global Positioning System (GPS) device. As known in this art, GNSS device 1318 can communicate with satellite-based systems and can determine the geographical location of electrical device 1300 based on information received from one or more GNSS satellites.

[0101] Electrical device 1300 may include additional output device 1310 (or corresponding interface circuitry, as discussed above). Examples of additional output device 1310 may include audio codecs, video codecs, printers, wired or wireless transmitters for providing information to other devices, or additional storage devices.

[0102] Electrical device 1300 may include additional input device 1320 (or corresponding interface circuitry, as discussed above). Examples of additional input device 1320 may include accelerometer, gyroscope, compass, image capture device (e.g., single-image or stereo camera), trackball, trackpad, touchpad, keyboard, cursor control device such as mouse, pen, touch screen, proximity sensor, microphone, barcode reader, quick-response (QR) code reader, electrocardiogram (ECG) sensor, PPG (photoplethysmography) sensor, skin current response sensor, any other sensor, or radio frequency identification (RFID) reader.

[0103] Electrical device 1300 can have any desired form factor, such as handheld or mobile electrical devices (e.g., mobile phones, smartphones, mobile internet devices, music players, tablets, laptops, 2-in-1 convertibles, portable all-in-ones, mini-laptops, ultra-laptops, personal digital assistants (PDAs), ultra-mobile PCs, portable game consoles, etc.), desktop electrical devices, servers, rack-mount computing solutions (e.g., blade, tray, or slide computing systems), workstations or other network computing components, printers, scanners, monitors, set-top boxes, game control units, stationary game consoles, smart TVs, vehicle control units, digital cameras, digital video recorders, wearable electrical devices, or embedded computing systems (e.g., computing systems as part of vehicles, smart appliances, consumer electronics products or equipment, or manufacturing equipment). In some embodiments, electrical device 1300 can be any other electronic device for processing data. In some embodiments, electrical device 1300 can include multiple discrete physical components. Given the range of devices that the electrical device 1300 may be represented in various embodiments, in some embodiments the electrical device 1300 may be referred to as a computing device or computing system.

[0104] Figure 10 is a flowchart of process 1000 according to some embodiments. In operation 1002, the process includes providing a plurality of first dies. In operation 1004, the process includes providing an encapsulation layer on the first dies to form a first layer of a semiconductor sub-assembly. In operation 1006, the process includes providing a first dielectric layer on the first layer to form a first layer and a first dielectric layer sub-assembly. In operation 1008, the process includes providing a passive heat sink interposer layer. In operation 1010, the process includes providing a second dielectric layer on the passive heat sink interposer layer to form a passive heat sink interposer layer and a second dielectric layer sub-assembly. In operation 1012, the process includes forming and mechanically coupling an interface layer between the passive heat sink interposer and the first layer, the interface layer providing direct dielectric-to-dielectric bonding, including a first dielectric sublayer formed directly adjacent to the first layer and by the first dielectric layer, and a second dielectric sublayer formed directly adjacent to the first dielectric sublayer and by a second dielectric layer, comprising an amorphous material. In operation 1014, the process includes providing a second layer comprising a substrate. In operation 1016, the process includes electrically coupling the substrate to the first grains.

[0105] Throughout this specification, multiple instances may implement components, operations, or structures described as single instances. While individual operations of one or more methods are illustrated and described as separate operations, one or more separate operations may be performed simultaneously, and they need not be performed in the order shown. Structures and functions presented as individual components in the example configurations may be implemented as combined structures or components. Similarly, structures and functions presented as single components may be implemented as separate components. These and other variations, modifications, additions, and improvements fall within the scope of the subject matter herein.

[0106] While an overview of the embodiments has been described with reference to specific exemplary embodiments, various modifications and changes may be made to such embodiments without departing from the broader scope of the embodiments of the invention. Such embodiments of the subject matter of the invention may be referred to herein, individually or collectively, by the term "invention," merely for convenience and not intended to voluntarily limit the scope of this application to the concept of any single disclosure or invention, if in fact more than one is disclosed.

[0107] The embodiments shown herein have been described in sufficient detail to enable those skilled in the art to practice the teachings disclosed. Other embodiments may be used and derived therefrom, such that structural and logical substitutions and changes may be made without departing from the scope of the invention. Therefore, the detailed description should not be considered limiting, and the scope of the various embodiments is defined only by the full scope of the appended claims together with the equivalents conferred by such claims.

[0108] It should also be understood that while the terms "first," "second," etc., may be used herein to describe various elements, such elements should not be limited by these terms. These terms are used only to distinguish one element from another. For example, without departing from the scope of this exemplary embodiment, a first contact may be referred to as a second contact, and similarly, a second contact may be referred to as a first contact. Both the first contact and the second contact are contacts, but they are not the same contact.

[0109] As used in the description of the exemplary embodiments and additional examples, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein means and covers any and all possible combinations of one or more of the associated listed items. It should also be understood that the terms “comprising” and / or “including,” when used in this specification, indicate the presence of the stated features, integrals, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components, and / or groups thereof.

[0110] For the purposes of this invention, the phrase "A and / or B" means (A), (B), or (A and B). For the purposes of this invention, the phrase "A, B, and / or C" means (A), (B), (C), (A and B), (A and C), (B and C), or (A, B, and C).

[0111] In the embodiments, the phrase "A is located on B" means that at least a portion of A and at least a portion of B are in direct physical contact or indirect physical contact (with one or more other features between A and B).

[0112] In this specification, "A and B are adjacent" means that at least a portion of A and at least a portion of B are in direct physical contact.

[0113] In this specification, "B is between A and C" means that at least a portion of B is in or along the space separating A and C, and that at least a portion of B is in direct or indirect physical contact with A and C.

[0114] In this specification, "A is attached to B" means that at least a portion of A is mechanically attached to at least a portion of B, directly or indirectly (with one or more other features between A and B).

[0115] Use reference numbers separated by " / ", such as, for example, "102 / 104", to mean 102 or 104 where applicable. Otherwise, as used herein, a forward slash (" / ") means "and / or".

[0116] Tools such as the following can be used to detect the use of the techniques and structures presented herein: electron microscopy, including scanning / transmission electron microscopy (SEM / TEM), scanning transmission electron microscopy (STEM), nanobeam electron diffraction (NBD or NBED), and reflection electron microscopy (REM); composition mapping; X-ray crystallography or diffraction (XRD); energy-dispersive X-ray spectroscopy (EDX); secondary ion mass spectrometry (SIMS); time-of-flight SIMS (ToF-SIMS); atomic probe imaging or tomography; local electrode atomic probe (LEAP) technology; 3D tomography; high-resolution physical or chemical analysis, to name just a few suitable analytical tools. In particular, such tools can indicate an integrated circuit comprising at least one MCP, the MCP including an interlayer bonded to the MCP sub-assembly via direct dielectric-to-dielectric bonding as described above.

[0117] In some embodiments, the techniques, processes, and / or methods described herein can be detected based on the structures formed therein. Furthermore, in some embodiments, the techniques and structures described herein can be detected based on the benefits derived therefrom. Given the present invention, many configurations and variations will become apparent.

[0118] The description may use perspective-based descriptions, such as top / bottom, inside / outside, above / below, etc. Such descriptions are only used to facilitate discussion and are not intended to limit the application of the embodiments described herein to any particular orientation.

[0119] The description may use phrases such as "in one embodiment," "according to some embodiments," "according to an embodiment," or "in an embodiment," each of which may refer to one or more of the same or different embodiments. Furthermore, terms such as "comprising," "including," "having," etc., as used in relation to embodiments of the invention are synonyms.

[0120] As used herein, “coupled” means that two or more components are in direct physical contact, or that two or more components are in indirect physical contact but still cooperate or interact with each other (i.e., one or more other components are coupled or connected between components that are said to be coupled to each other). The term “directly coupled” means that two or more components are in direct contact.

[0121] As used herein, the term "module" means, as part of or including, an ASIC, electronic circuitry, a system-on-a-chip, a processor (shared, dedicated, or grouped), a solid-state device, memory (shared, dedicated, or grouped) executing one or more software or firmware programs, combinational logic circuitry, and / or other suitable components that provide the aforementioned functionality.

[0122] As used herein, in some examples the term "conductivity" may mean having a conductivity greater than or equal to that per meter at 20 degrees Celsius. The electrical conductivity (S / m) of Siemens materials is related to their material properties. Examples of such materials include Cu, Ag, Al, Au, W, Zn, and Ni.

[0123] As used herein, an "integrated circuit structure" may include one or more microelectronic chips.

[0124] In the corresponding diagrams of the embodiments, signals, currents, electrical biases, or magnetic or electrical polarities may be represented by lines. Some lines may be thicker to indicate multiple component signal paths and / or have arrows at one or more ends to indicate the direction of main information flow. Such indications are not intended to be limiting. Rather, the lines are used in conjunction with one or more exemplary embodiments to facilitate easier understanding of the circuit or logic unit. Any represented signal, polarity, current, voltage, etc., may practically include one or more signals, which may travel in either direction and may be implemented in any suitable type of signaling scheme, as specified by design requirements or preferences.

[0125] Throughout this specification and within the scope of the claims, the term "connection" means a direct connection, such as an electrical, mechanical, or magnetic connection between connected elements, without any intermediate means. The term "coupled" means a direct or indirect connection, such as a direct electrical, mechanical, or magnetic connection between connected elements, or an indirect connection through one or more passive or active intermediate means. The term "signal" can mean at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a," "an," and "the" include plural references. The meaning of "in" includes "inside" and "on top."

[0126] The terms “substantially,” “close to,” “approximately,” “near,” and “about” generally mean within + / - 10% of the target value (unless specifically specified). Unless otherwise specified, the ordinal adjectives “first,” “second,” and “third,” etc., used to describe common objects only indicate different instances of similar objects and do not imply that the objects described must be in a given sequence, whether in time, space, rank, or any other way.

[0127] For illustrative purposes, the transistor systems described herein include metal-oxide-semiconductor (MOS) transistors or derivatives thereof in various circuits and logic blocks, wherein the MOS transistor includes a drain, source, gate, and body terminal. Transistors and / or MOS transistor derivatives also include tri-gate and FinFET transistors, gate-all-around cylindrical transistors, tunneling FETs (TFETs), square-wire or rectangular stripe transistors, ferroelectric FETs (FeFETs), or other devices implementing transistor functions, such as carbon nanotubes or spintronic devices. MOSFETs have symmetrical source and drain terminals, i.e., identical terminals and are interchangeable herein. On the other hand, TFET devices have asymmetrical source and drain terminals. Those skilled in the art will understand that other transistors, such as bipolar junction transistors (BJTs), PNP / NPN, BiCMOS, CMOS, eFETs, etc., can be used without departing from the scope of the invention. The term "MN" refers to an n-type transistor (e.g., nMOS, NPN BJT, etc.), and the term "MP" refers to a p-type transistor (e.g., pMOS, PNP BJT, etc.).

[0128] For illustrative purposes, the foregoing description has been carried out with reference to specific exemplary embodiments. However, the illustrative discussion above is not intended to be all-encompassing or to limit the possible exemplary embodiments to the precise forms disclosed. In view of the above teachings, many modifications and variations are possible. The exemplary embodiments were chosen and described in order to best explain the principles involved and their practical applications, thereby enabling others skilled in the art to best utilize the various exemplary embodiments with various modifications suitable for the intended particular purpose.

[0129] Example

[0130] The following describes some non-limiting example embodiments.

[0131] Example 1 includes a microelectronic device comprising a substrate; a physical layer (PHY) circuitry on the substrate, including a plurality of receiver (RX) circuits and a plurality of transmitter (TX) circuits; electrical contact structures at the bottom surface of the device; signal routing paths extending, on one hand, between the electrical contact structures and on the other hand, between at least some of the RX circuits or at least some of the TX circuits; and electrical pathways leading to the PHY circuitry and configured to satisfy at least one of the following conditions: an enable signal input to the device passes through at least some of the electrical pathways to enable a portion of the PHY circuitry; and a disable signal input to the device passes through at least some of the electrical pathways to disable a corresponding portion of the PHY circuitry.

[0132] Example 2 includes the object of Example 1, wherein the equivalent electrical path includes at least one fuse or register for enabling or deactivating at least one of the corresponding portion of the PHY circuit.

[0133] Example 3 includes the object of Example 1, wherein the electrical paths leading to the PHY circuit are configured to satisfy at least one of the following conditions: an enable signal input to the device passes through at least some of the electrical paths to enable 1 / 2 of the RX circuit and 1 / 2 of the TX circuit; and a disable signal input to the device passes through at least some of the electrical paths to disable the remaining 1 / 2 of the RX circuit and 1 / 2 of the TX circuit.

[0134] Example 4 includes the object of Example 1, wherein the electrical paths leading to the PHY circuit are configured to satisfy at least one of the following conditions: an enable signal input to the device passes through at least some of the electrical paths to enable 1 / 4 of the RX circuit and 1 / 4 of the TX circuit; and a disable signal input to the device passes through at least some of the electrical paths to disable the remaining 3 / 4 of the RX circuit and 3 / 4 of the TX circuit.

[0135] Example 5 includes the objects of Example 1, wherein some of the signal routing paths extend between the corresponding electrical contact structures and all of the RX circuits, and some of the signal routing paths extend between the corresponding electrical contact structures and all of the TX circuits.

[0136] Example 6 includes the objects of Example 1, wherein some of the signal routing paths extend between the corresponding electrical contact structures and portions of the RX circuits, and some of the signal routing paths extend between the corresponding electrical contact structures and portions of the TX circuits.

[0137] Example 7 includes the object of Example 6, wherein: the RX circuit of this portion includes 1 / 2 of the RX circuit and the TX circuit of this portion includes 1 / 2 of the TX circuit; or the RX circuit of this portion includes 1 / 4 of the RX circuit and the TX circuit of this portion includes or 1 / 4 of the TX circuit.

[0138] Example 8 includes the object of Example 1, wherein the RX circuits are located in a first region of the device, and the TX circuits are located in a second region of the device that is different from the first region.

[0139] Example 9 includes the object of Example 1, wherein the signal routing paths include conductive traces and vias of the device.

[0140] Example 10 includes the object of Example 1, wherein the isoelectric contact structure includes bumps.

[0141] Example 11 includes the object of Example 10, wherein the bumps include C4 bumps.

[0142] Example 12 includes the object of Example 1, wherein the spacing between the isoelectric contact structures is between approximately 110 micrometers and approximately 130 micrometers.

[0143] Example 13 includes the object of Example 1, wherein the spacing between the isoelectric contact structures is between approximately 36 micrometers and approximately 55 micrometers.

[0144] Example 14 includes a semiconductor package comprising: a package substrate; two pairs of dies on the package substrate, including a first pair of dies and a second pair of dies, the first pair of dies including a first die and a second die, and the second pair of dies including a third die and a fourth die, wherein: each of the dies includes: a die substrate; a physical layer (PHY) circuit on the die substrate, including a plurality of receive (RX) circuits and a plurality of transmit (TX) circuits; electrical contact structures at the bottom surface of the die; each of the first and second dies includes a signal routing path extending, on one hand, between its electrical contact structures, and on the other hand, on all its electrical contact structures. The X circuit extends between all of the TX circuits; individual dies of the third and fourth dies include signal routing paths extending, on the one hand, between their equivalent electrical contact structures, and on the other hand, between a portion of their RX circuits and a portion of their TX circuits; wherein the package substrate includes a first package signal routing path and a second package signal routing path, the first package signal routing path extending between the first die and the second die to provide device-to-device (D2D) signal interconnection between them, and the second package signal routing path extending between the first die and the second die to provide device-to-device (D2D) signal interconnection between them.

[0145] Example 15 includes the object of Example 14, wherein the RX circuit of this portion includes 1 / 2 of the RX circuit, and the TX circuit of this portion includes 1 / 2 of the TX circuit.

[0146] Example 16 includes the object of Example 14, wherein the RX circuit of this portion includes 1 / 4 of the RX circuit, and the TX circuit of this portion includes 1 / 4 of the TX circuit.

[0147] Example 17 includes the subject matter of Example 14, wherein, for an individual die of the dies, the RX circuits are located in a first region of the die, and the TX circuits are located in a second region of the die that is different from the first region.

[0148] Example 18 includes the object of Example 14, wherein, for each individual die of the dies, the signal routing paths include conductive traces and vias of the die.

[0149] Example 19 includes the object of Example 14, wherein, for each individual grain of the grains, the electrical contact structure includes bumps.

[0150] Example 20 includes the subject matter of Example 19, wherein, for each individual grain of the grains, the electrical contact structure includes controlled chipping wafer collection bumps.

[0151] Example 21 includes the subject matter of Example 14, wherein, for individual grains of the first grain and the second grain, the spacing between the isoelectric contact structures is between approximately 110 micrometers and approximately 130 micrometers, and for individual grains of the third grain and the fourth grain, the spacing between the isoelectric contact structures is between approximately 36 micrometers and approximately 55 micrometers.

[0152] Example 22 includes the object of Example 14, wherein at least one of the first package signal routing paths and the second package signal routing paths extends through and contacts a material layer of the package substrate.

[0153] Example 23 includes the object of Example 22, wherein the material layers comprise organic materials.

[0154] Example 24 includes the object of Example 14, wherein the package substrate defines a cavity therein, the package substrate further includes an interconnect bridge within the cavity, and at least one of the first package signal routing paths and the second package signal routing paths extends within the interconnect bridge.

[0155] Example 25 includes the object of Example 14, wherein the first grain, the second grain, the third grain, and the fourth grain are identical to each other.

[0156] Example 26 includes the object of Example 14, wherein individual dies of the dies include electrical paths leading to the PHY circuit and are configured to satisfy at least one of the following conditions: an enable signal input to an individual die of the dies enables a portion of the PHY circuit through at least some of the electrical paths; or a disable signal input to an individual die of the dies disables a corresponding portion of the PHY circuit through at least some of the electrical paths.

[0157] Example 27 includes the subject matter of Example 26, wherein, for each individual die of the such dies, the such electrical path includes at least one fuse or register for enabling or deactivating at least one of the corresponding portion of the PHY circuit.

[0158] Example 28 includes an integrated circuit (IC) device assembly comprising: a printed circuit board; and a plurality of integrated circuit components coupled to the printed circuit board, each of the integrated circuit components including one or more semiconductor packages, each of the semiconductor packages including: a package substrate; a plurality of dies on the package substrate, each of the dies including: a die substrate; a physical layer (PHY) circuit on the die substrate including a plurality of receive (RX) circuits and a plurality of transmit (TX) circuits; an electrical contact structure at the bottom surface of the die; and a signal routing path extending between the electrical contact structures. The package extends, on the other hand, between at least some of the RX circuits or at least some of the TX circuits; an electrical path leads to the PHY circuit and is configured to satisfy at least one of the following conditions: an enable signal input to the die passes through at least some of the electrical paths to enable a portion of the PHY circuit; and a disable signal input to the die passes through at least some of the electrical paths to disable a corresponding portion of the PHY circuit; and wherein the package substrate includes a package signal routing path extending between the first die of the plurality of dies and the second die of the plurality of dies to provide device-to-device (D2D) signal interconnection between them.

[0159] Example 29 includes the subject matter of Example 28, wherein, for each individual die of the such dies, the such electrical path includes at least one fuse or register for enabling or deactivating at least one of the corresponding portion of the PHY circuit.

[0160] Example 30 includes the object of Example 28, wherein, for an individual die of the dies, the electrical paths to the PHY circuit are configured to satisfy at least one of the following conditions: an enable signal input to the die passes through at least some of the electrical paths to enable 1 / 2 of the RX circuits and 1 / 2 of the TX circuits; and a disable signal input to the die passes through at least some of the electrical paths to disable the remaining 1 / 2 of the RX circuits and 1 / 2 of the TX circuits.

[0161] Example 31 includes the object of Example 28, wherein, for an individual die of the dies, the electrical paths to the PHY circuit are configured to satisfy at least one of the following conditions: an enable signal input to the die passes through at least some of the electrical paths to enable 1 / 4 of the RX circuits and 1 / 4 of the TX circuits; and a disable signal input to the die passes through at least some of the electrical paths to disable the remaining 3 / 4 of the RX circuits and 3 / 4 of the TX circuits.

[0162] Example 32 includes the object of Example 28, wherein, for an individual die of the dies, some of the signal routing paths extend between the corresponding electrical contact structures and all of the RX circuits, and some of the signal routing paths extend between the corresponding electrical contact structures and all of the TX circuits.

[0163] Example 33 includes the object of Example 28, wherein, for an individual die of the dies, some of the signal routing paths extend between the corresponding electrical contact structures and a portion of the RX circuits, and some of the signal routing paths extend between the corresponding electrical contact structures and a portion of the TX circuits.

[0164] Example 34 includes the subject matter of Example 33, wherein, for an individual die of the dies, the portion of the RX circuits includes 1 / 2 of the RX circuits and the portion of the TX circuits includes 1 / 2 of the TX circuits; or the portion of the RX circuits includes 1 / 4 of the RX circuits and the portion of the TX circuits includes or 1 / 4 of the TX circuits.

[0165] Example 35 includes the subject matter of Example 28, wherein, for an individual die of the dies, the RX circuits are located in a first region of the die, and the TX circuits are located in a second region of the die that is different from the first region.

[0166] Example 36 includes the object of Example 28, wherein, for each individual die of the dies, the signal routing paths include conductive traces and vias of the die.

[0167] Example 37 includes the object of Example 28, wherein, for each individual grain of the grains, the electrical contact structure includes bumps.

[0168] Example 38 includes the subject matter of Example 37, wherein, for each individual grain of the grains, the electrical contact structure includes controlled chipping wafer collection bumps.

[0169] Example 39 includes the subject matter of Example 28, wherein, for the individual grains of such grains, the spacing between the isoelectric contact structures is between approximately 110 micrometers and approximately 130 micrometers.

[0170] Example 40 includes the subject matter of Example 28, wherein, for the individual grains of such grains, the spacing between the isoelectric contact structures is between approximately 36 micrometers and approximately 55 micrometers.

[0171] Example 41 includes the object of Example 28, wherein the packaged signal routing paths extend through and contact the material layer of the package substrate.

[0172] Example 42 includes the subject matter of Example 41, wherein the material layers comprise organic materials.

[0173] Example 43 includes the object of Example 28, wherein the package substrate defines a cavity therein, and the package further includes an interconnect bridge within the cavity, wherein package signal routing paths extend within the interconnect bridge.

[0174] Example 44 includes the object of Example 28, wherein the first grain and the second grain are identical to each other.

[0175] Example 45 includes the object of Example 28, wherein: the package signal routing paths are first package signal routing paths; the plurality of dies further includes a third die and a fourth die, disposed on the package substrate; the package substrate further includes a second package signal routing path extending between the third die and the second die for providing device-to-device (D2D) signal interconnection between them; for individual dies of the first die and the second die: the signal routing paths of the first group extend between the corresponding electrical contact structures and all of the RX circuits; and the signal routing paths of the second group, unlike the first group, extend between the corresponding electrical contact structures and all of the TX circuits; and for individual dies of the third die and the fourth die: the signal routing paths of the first group extend between the corresponding electrical contact structures and a portion of the RX circuits; and the signal routing paths of the second group, unlike the first group, extend between the corresponding electrical contact structures and a portion of the TX circuits.

[0176] Example 46 includes a method of manufacturing a microelectronic device, comprising: providing a substrate; providing a physical layer (PHY) circuit on the substrate, the physical layer (PHY) circuit including a plurality of receiver (RX) circuits and a plurality of transmitter (TX) circuits; providing electrical contact structures at the bottom surface of the device; providing signal routing paths extending, on the one hand, between the electrical contact structures, and on the other hand, between at least some of the RX circuits or at least some of the TX circuits; and providing electrical pathways to the PHY circuit; and at least one of the following: providing an enable signal into the device to enable a portion of the PHY circuit through at least some of the electrical pathways; and providing a disable signal into the device to disable a corresponding portion of the PHY circuit through at least some of the electrical pathways.

[0177] Example 47 includes the object of Example 46, wherein the equivalent electrical path includes at least one fuse or register for enabling or deactivating at least one of the corresponding portion of the PHY circuit.

[0178] Example 48 includes the object of Example 46, wherein the electrical paths leading to the PHY circuit are configured to satisfy at least one of the following conditions: an enable signal input to the device passes through at least some of the electrical paths to enable 1 / 2 of the RX circuit and 1 / 2 of the TX circuit; and a disable signal input to the device passes through at least some of the electrical paths to disable the remaining 1 / 2 of the RX circuit and 1 / 2 of the TX circuit.

[0179] Example 49 includes the object of Example 46, wherein the electrical paths leading to the PHY circuit are configured to satisfy at least one of the following conditions: an enable signal input to the device passes through at least some of the electrical paths to enable 1 / 4 of the RX circuit and 1 / 4 of the TX circuit; and a disable signal input to the device passes through at least some of the electrical paths to disable the remaining 3 / 4 of the RX circuit and 3 / 4 of the TX circuit.

[0180] Example 50 includes the object of Example 46, wherein some of the signal routing paths extend between the corresponding electrical contact structures and all of the RX circuits, and some of the signal routing paths extend between the corresponding electrical contact structures and all of the TX circuits.

[0181] Example 51 includes the object of Example 46, wherein some of the signal routing paths extend between the corresponding electrical contact structures and portions of the RX circuits, and some of the signal routing paths extend between the corresponding electrical contact structures and portions of the TX circuits.

[0182] Example 52 includes the object of Example 51, wherein: the RX circuit of this portion includes 1 / 2 of the RX circuit and the TX circuit of this portion includes 1 / 2 of the TX circuit; or the RX circuit of this portion includes 1 / 4 of the RX circuit and the TX circuit of this portion includes or 1 / 4 of the TX circuit.

[0183] Example 53 includes the object of Example 46, wherein the RX circuits are located in a first region of the device, and the TX circuits are located in a second region of the device that is different from the first region.

[0184] Example 54 includes the object of Example 46, wherein the signal routing paths include conductive traces and vias of the device.

[0185] Example 55 includes the object of Example 46, wherein the isoelectric contact structure includes bumps.

[0186] Example 56 includes the object of Example 55, wherein the isoelectric contact structure includes controlled chipping wafer collection bumps.

[0187] Example 57 includes the object of Example 46, wherein the spacing between the isoelectric contact structures is between approximately 110 micrometers and approximately 130 micrometers.

[0188] Example 58 includes the object of Example 46, wherein the spacing between the isoelectric contact structures is between approximately 36 micrometers and approximately 55 micrometers.

[0189] 100, 200, 300: Microelectronic Assembly 104, 204, 304: Packaging substrate 108, 116, 208, 216, 308a, 308b, 316a, 316b: Grain sizes 112, 212, 312a, 312b: Top surface 136, 336a, 336b: Traces 159: Conductive Structure 204: Substrate Assembly 210, 220: Substrate conductive contacts 222: Interconnect bridge 224, 226: Bridging conductive contacts 228: Bridge surface 232: Bridged Through Hole 236: Bridging conductive traces 244: Conductive contact 256: Electrical contact structure or connector 260, 1216, 1218, 1222, 1228, 1230: Coupling components 264, 266: Grain conductivity contacts 301a: Standard Interconnection Section 301b: Advanced Interconnection Section 309a, 309a', 317a, 317a', 309b, 309b', 317b, 317b': RX circuit 311a,311a',319a,319a',311b,311b',319b,319b': TX circuit 359: Electrical contact structure 356a, 356b: C4 bump 500, 600, 700, 800, 900, 1000: Example layout 1100: Manufacturing Method 1102-1112: Operation 1200: Integrated Circuit Assembly 1202: Circuit Board 1204: Intermediary Layer 1208: Metal Interconnect 1210: Through hole 1220: Integrated circuit components 1234: Stacked structure 1236: Stacked structure 1300: Electrical Devices 1302: Processor Unit 1304: Memory 1306: Display device 1308: Audio output device 1310: Additional output devices 1312: Communication Component 1314: Battery / Power Supply Circuit 1318: GNSS device 1320: Additional input device 1322: Antenna 1324: Audio input device

Claims

1. A microelectronic device comprising: a substrate; a physical layer (PHY) circuitry on the substrate, including a plurality of receiver (RX) circuits and a plurality of transmitter (TX) circuits; electrical contact structures at a bottom surface of the device; signal routing paths extending, on one hand, between the electrical contact structures and on the other hand, between at least some of the RX circuits or at least some of the TX circuits; and electrical pathways leading to the PHY circuitry and configured to satisfy at least one of the following conditions: an enable signal input to the device passes through at least some of the electrical pathways to enable a portion of the PHY circuitry; or a disable signal input to the device passes through at least some of the electrical pathways to disable a corresponding portion of the PHY circuitry, wherein the electrical pathways include at least one fuse or register for enabling or disabling at least one of the corresponding portion of the PHY circuitry.

2. The microelectronic device of claim 1, wherein the electrical paths leading to the PHY circuit are configured to satisfy at least one of the following conditions: an enable signal input to the device passes through at least some of the electrical paths to enable 1 / 2 of the RX circuits and 1 / 2 of the TX circuits; or an disable signal input to the device passes through at least some of the electrical paths to disable the remaining 1 / 2 of the RX circuits and 1 / 2 of the TX circuits.

3. The microelectronic device of claim 1, wherein the electrical paths leading to the PHY circuit are configured to satisfy at least one of the following conditions: an enable signal input to the device passes through at least some of the electrical paths to enable 1 / 4 of the RX circuits and 1 / 4 of the TX circuits; or an disable signal input to the device passes through at least some of the electrical paths to disable the remaining 3 / 4 of the RX circuits and 3 / 4 of the TX circuits.

4. The microelectronic device of claim 1, wherein some of the signal routing paths extend between the corresponding electrical contact structures and all of the RX circuits, and some of the signal routing paths extend between the corresponding electrical contact structures and all of the TX circuits.

5. The microelectronic device of claim 1, wherein some of the signal routing paths extend between corresponding electrical contact structures and portions of the RX circuits, and some of the signal routing paths extend between corresponding electrical contact structures and portions of the TX circuits.

6. The microelectronic device as claimed in claim 5, wherein: The RX circuits of this part include 1 / 2 of the RX circuits and the TX circuits of this part include or 1 / 2 of the TX circuits; or the RX circuits of this part include 1 / 4 of the RX circuits and the TX circuits of this part include or 1 / 4 of the TX circuits.

7. The microelectronic device of claim 1, wherein the isoelectric contact structure includes bumps.

8. The microelectronic device of claim 1, wherein the spacing between the equipotential contact structures is between approximately 110 micrometers and approximately 130 micrometers.

9. A microelectronic device as claimed in any of claims 1 to 8, wherein the spacing between the equielectric contact structures is between approximately 36 micrometers and approximately 55 micrometers.

10. A semiconductor package comprising: a package substrate; two pairs of dies, wherein the package substrate includes a first pair of dies and a second pair of dies, the first pair of dies including a first die and a second die, and the second pair of dies including a third die and a fourth die, wherein: Individual chips of the aforementioned chips include: a chip substrate; a physical layer (PHY) circuitry on the chip substrate, including a plurality of receive (RX) circuits and a plurality of transmit (TX) circuits; electrical contact structures at the bottom surface of the chip; individual chips of the first and second chips include signal routing paths extending, on one hand, between their respective electrical contact structures, and on the other hand, between all their respective RX circuits and all their respective TX circuits; individual chips of the third and fourth chips include signal routing paths extending, on one hand, between their respective electrical contact structures, and on the other hand, between a portion of their respective RX circuits and a portion of their respective TX circuits; wherein the package substrate includes a first package signal routing path and a second package signal routing path, the first package signal routing path extending between the first and second chips to provide device-to-device (D2D) signal interconnection between them, and the second package signal routing path extending between the third and fourth chips to provide device-to-device (D2D) signal interconnection between them.

11. The semiconductor package of claim 10, wherein the RX circuitry of that portion comprises 1 / 2 of the RX circuitry, and the TX circuitry of that portion comprises 1 / 2 of the TX circuitry.

12. The semiconductor package of claim 10, wherein the RX circuitry of that portion comprises 1 / 4 of the RX circuitry, and the TX circuitry of that portion comprises 1 / 4 of the TX circuitry.

13. The semiconductor package as described in claim 10, wherein, For each of these individual chips, the RX circuits are located in a first region of the chip, and the TX circuits are located in a second region of the chip that is different from the first region.

14. The semiconductor package as described in claim 10, wherein, For each individual of these grains, the signal routing path includes the conductive traces and vias of that grain.

15. The semiconductor package as described in claim 10, wherein, For each individual grain of these grains, the isoelectric contact structure includes bumps.

16. The semiconductor package as described in claim 15, wherein, For each individual grain of these grains, the isoelectric contact structure includes controlled chipping wafer collection bumps.

17. A semiconductor package as described in any of claims 10 to 16, wherein, For each individual grain of the first and second grains, the spacing between the isoelectric contact structures is between approximately 110 micrometers and approximately 130 micrometers, and for each individual grain of the third and fourth grains, the spacing between the isoelectric contact structures is between approximately 36 micrometers and approximately 55 micrometers.

18. The semiconductor package of claim 10, wherein at least one of the first package signal routing paths and the second package signal routing paths extends through and contacts a material layer of the package substrate.

19. An integrated circuit (IC) device assembly comprising: a printed circuit board; and a plurality of integrated circuit components coupled to the printed circuit board, wherein individual integrated circuit components include one or more semiconductor packages, and individual semiconductor packages include: Packaging substrate; A plurality of dies are disposed on the packaging substrate, each die comprising: a die substrate; a physical layer (PHY) circuitry on the die substrate, including a plurality of receiver (RX) circuits and a plurality of transmit (TX) circuits; electrical contact structures on the bottom surface of the die; signal routing paths extending, on one hand, between the electrical contact structures, and on the other hand, between at least some of the RX circuits or at least some of the TX circuits; and electrical paths leading to the PHY circuitry and configured to satisfy at least one of the following conditions: an enable signal input to the die passes through at least some of the electrical paths, and is used for... This enables a portion of the PHY circuit; or a deactivation signal input to the die deactivates a corresponding portion of the PHY circuit via at least some of the equivalent electrical paths; and wherein the package substrate includes a package signal routing path extending between a first die and a second die of the plurality of dies to provide device-to-device (D2D) signal interconnection between them, and wherein, for each individual die of the plurality of dies, the equivalent electrical path includes at least one fuse or register to enable or deactivate at least one of the corresponding portion of the PHY circuit.

20. The IC device assembly as described in claim 19, wherein, For each individual die, the electrical paths leading to the PHY circuit are configured to satisfy at least one of the following conditions: the enable signal input to the die passes through at least some of the electrical paths to enable 1 / 2 of the RX circuits and 1 / 2 of the TX circuits; or the disable signal input to the die passes through at least some of the electrical paths to disable the remaining 1 / 2 of the RX circuits and 1 / 2 of the TX circuits.

21. The IC device assembly as described in claim 19, wherein, For each individual die, the electrical paths leading to the PHY circuit are configured to satisfy at least one of the following conditions: the enable signal input to the die passes through at least some of the electrical paths to enable 1 / 4 of the RX circuits and 1 / 4 of the TX circuits; or the disable signal input to the die passes through at least some of the electrical paths to disable the remaining 3 / 4 of the RX circuits and 3 / 4 of the TX circuits.

22. A method of manufacturing a microelectronic device, comprising: providing a substrate; providing a physical layer (PHY) circuit on the substrate, the physical layer (PHY) circuit including a plurality of receiver (RX) circuits and a plurality of transmitter (TX) circuits; providing electrical contact structures at the bottom surface of the device; providing signal routing paths extending, on the one hand, between the electrical contact structures, and on the other hand, between at least some of the RX circuits or at least some of the TX circuits; and providing electrical pathways to the PHY circuit, wherein the electrical pathways include at least one fuse or register; and at least one of the following: providing an enable signal into the device to enable a portion of the PHY circuit through at least some of the electrical pathways; or providing a disable signal into the device to disable a corresponding portion of the PHY circuit through at least some of the electrical pathways.

23. The method of claim 22, wherein the electrical paths leading to the PHY circuit are configured to satisfy at least one of the following conditions: an enable signal input to the device passes through at least some of the electrical paths to enable 1 / 2 of the RX circuits and 1 / 2 of the TX circuits; or an disable signal input to the device passes through at least some of the electrical paths to disable the remaining 1 / 2 of the RX circuits and 1 / 2 of the TX circuits.

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