Semiconductor device and method of forming selective EMI shielding with slotted substrate

Abstract

The present invention provides a semiconductor device having a substrate and a trench formed in the substrate. A first electronic component is disposed above the substrate adjacent to the trench. An encapsulation is deposited above the first electronic component, wherein the surface of the encapsulation is coplanar with the surface of the substrate within the trench. A shielding layer is formed above the encapsulation and substantially contacts the surface of the substrate within the trench. After forming the shielding layer, the substrate is monolithically processed to form a semiconductor package having the first electronic component.

Description

Technical Field

[0001] This invention relates generally to a semiconductor device, and more specifically to a semiconductor device and a method for selective electromagnetic interference (EMI) shielding with a slotted substrate. Prior Technology

[0002] Semiconductor devices are commonly found in modern electronic products. They perform a wide range of functions, such as signal processing, high-speed computing, transmitting and receiving electromagnetic signals, controlling electronic devices, converting sunlight into electricity, and generating visual images for television displays. Semiconductor devices are found in communications, power conversion, networking, computers, entertainment, and consumer products. They are also found in military applications, aerospace, automotive, industrial controllers, and office equipment.

[0003] Semiconductor devices are typically manufactured using two complex processes: front-end fabrication and back-end fabrication. Front-end fabrication involves forming a plurality of dies on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electronic components that are electrically connected to form a functional circuit. Active electronic components, such as transistors and diodes, have the ability to control the flow of current. Passive electronic components, such as capacitors, inductors, and resistors, establish a relationship between the voltage and current required to perform the circuit function.

[0004] Back-end manufacturing refers to the process of dicing or monolithizing finished wafers into individual semiconductor dies and packaging these dies for structural support, electrical interconnection, and environmental insulation. To monolithize semiconductor dies, the wafer is scribed and broken along non-functional areas known as scribe lines or kerfs. Laser dicing tools or saw blades are used to monolithize the wafer. After monolithization, the individual semiconductor dies are mounted onto a package substrate, which includes pins or contact pads for interconnection with other system components. Contact pads formed on top of the semiconductor dies are then connected to contact pads within the package. Electrical connections can be made with conductive layers, bumps, column bumps, conductive paste, bonding wires, or other suitable interconnect structures. Encapsulation or other molding compounds are deposited on top of the package to provide physical support and electrical insulation. The finished package is then inserted into an electrical system, enabling the semiconductor device to function in other system components.

[0005] Figure 1a shows a semiconductor wafer 100 having a substrate material 102, such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk semiconductor materials. A plurality of semiconductor dies or components 104 are formed on the wafer 100, separated by inactive inter-die regions or kerfs 106 as described above. The kerfs 106 provide dicing areas to monolithize the semiconductor wafer 100 into individual semiconductor dies 104. In one specific example, the semiconductor wafer 100 has a width or diameter of 100 to 450 millimeters (mm).

[0006] Figure 1b shows a cross-sectional view of a portion of a semiconductor wafer 100. Each semiconductor die 104 has a rear or non-active surface 108 and an active surface 110, which contain analog or digital circuitry implemented as active devices, passive devices, conductive layers, and dielectric layers. These active devices, passive devices, conductive layers, and dielectric layers are formed within or above the die and electrically interconnected according to the die's electrical design and function. For example, the circuitry may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuitry, such as digital signal processors (DSPs), ASICs, MEMS, memory, or other signal processing circuitry. The semiconductor die 104 may also contain integrated passive devices (IPDs) such as inductors, capacitors, and resistors for RF signal processing. The back surface 108 of the semiconductor wafer 100 can be subjected to a back grinding operation, whichever is appropriate, through mechanical grinding or etching processes to remove a portion of the substrate material 102 and reduce the thickness of the semiconductor wafer 100 and the semiconductor die 104.

[0007] The conductive layer 112 is formed on the active surface 110 using PVD, CVD, electrolytic plating, electroless plating, or other suitable metal deposition processes. The conductive layer 112 comprises one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. The conductive layer 112 functions as a contact pad for electrical connections to circuitry on the active surface 110.

[0008] The conductive layer 112 may be formed as contact pads arranged side-by-side with respect to the edge of the semiconductor die 104 at a first distance, as shown in FIG1b. Alternatively, the conductive layer 112 may be formed as contact pads offset in a plurality of columns such that a first column of contact pads is arranged at a first distance from the edge of the die, and a second column of contact pads is alternately arranged with the first column at a second distance from the edge of the die. The conductive layer 112 represents the final conductive layer formed above the semiconductor die 104 having contact pads for subsequent electrical interconnection to a larger system. However, one or more intermediate conductive and insulating layers may be present between the actual semiconductor device formed on the active surface 110 and the contact pads 112 for signal routing.

[0009] Conductive bump material is deposited on the conductive layer 112 using evaporation, electroplating, electroless plating, drop ball, or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), Cu, solder, or combinations thereof, with a flux solution selected as appropriate. For example, the bump material can be eutectic Sn / Pb, high-lead solder, or lead-free solder. The bump material is bonded to the conductive layer 112 using a suitable attachment or bonding process. In one specific example, the bump material is reflowed by heating the material above its melting point to form conductive balls or bumps 114. In one specific example, conductive bumps 114 are formed on top of an under-bump metallization (UBM) having a wetting layer, a barrier layer, and an adhesive layer. Conductive bumps 114 can also be compression bonded or thermocompressed to the conductive layer 112. Conductive bump 114 represents a type of interconnect structure that can be formed above conductive layer 112 for electrical connection to a substrate. The interconnect structure may also use bonding wires, conductive paste, column bumps, micro bumps, conductive pillars or other electrical interconnects.

[0010] In Figure 1c, semiconductor wafer 100 is single-divided into individual semiconductor dies 104 via saw blade or laser cutting tool 118 through sawing path 106. Individual semiconductor dies 104 can be detected and electrically tested for identification after KGD single-division.

[0011] A method for forming a semiconductor package having a semiconductor die 104 is shown in Figures 2a to 2g. One or more discrete components 152 may be disposed over a package substrate 150 having the semiconductor die 104 to provide additional functionality. The encapsulation 154 is deposited over the substrate 150, the semiconductor die 104, and the discrete components 152 in Figure 2b.

[0012] Semiconductor devices are often susceptible to electromagnetic interference (EMI), radio frequency interference (RFI), harmonic distortion, or interference between other devices (such as capacitive, inductive, or conductive coupling, also known as crosstalk). High-speed analog circuits, such as radio frequency (RF) filters, or digital circuits also generate interference.

[0013] A conductive layer is typically formed over a semiconductor package to shield the electronic components within the package from EMI and other interference. The conductive layer is sputtered onto the package 154 to form a shielding layer over and around the component. The shielding layer absorbs EMI before signals can affect the semiconductor die and discrete components within the package, which could otherwise lead to accidents without shielding. The shielding layer is also formed over packages containing components expected to generate EMI to protect nearby devices.

[0014] The conductive layer formed over the package typically needs to be formed along the side surface of substrate 150 to allow physical contact with the conductive layer of the substrate and thus electrical connection to ground. Therefore, the package is typically monolithized before the shielding layer is formed, as shown in FIG2c, where a laser cutting tool 160 monolithizes substrate 150. FIG2d shows a plan view in which a circular package is formed. Trench 162 is formed throughout the package to monolithize the package from the larger panel of substrate 150. Substrate 150 is divided into multiple parts by the monolithization process: portion 150A remains as part of a plurality of semiconductor packages, while portion 150B is the remaining panel removed after monolithization, leaving only the package.

[0015] Figures 2e and 2f show the shielding layer 170 formed above the encapsulation 154. One common problem encountered when handling monolithic units is that these units can move during processing after monolithization, causing manufacturing defects. Figure 2g shows only two of many different failure modes. Damage 172 can be caused by processing equipment attempting to handle a package that has moved and is not in its intended position. Misalignment of the discrete device 174 can cause an accident if attributed to movement of the substrate before placement of the discrete components and improper connection to the underlying contact pad.

[0016] Processing semiconductor packages at the unit level provides numerous opportunities for manufacturing defects. Therefore, there is a need for improved shielding layer manufacturing processes and apparatuses to reduce the amount of processing after unitization. Summary of the Invention

[0017] One aspect of the present invention is a method for manufacturing a semiconductor device, comprising: providing a substrate; forming a trench in the substrate; disposing a first electronic component adjacent to the trench above the substrate; depositing an encapsulation over the first electronic component, wherein the surface of the encapsulation is coplanar with the surface of the substrate in the trench; forming a shielding layer over the encapsulation and substantially contacting the surface of the substrate in the trench; and, after forming the shielding layer, monolithizing the substrate to form a semiconductor package having the first electronic component.

[0018] The method described above further includes monolithizing the substrate by cutting from a first end of the groove to a second end of the groove.

[0019] The method described above further includes: placing a mask above the substrate before forming the shielding layer; and removing the mask after forming the shielding layer.

[0020] In the method described above in this invention, the semiconductor package is circular.

[0021] The method described above further includes placing a second electronic component on the substrate after forming the shielding layer.

[0022] In the method described above in this invention, after the step of forming the shielding layer is completed, a plurality of semiconductor packages remain connected by the substrate.

[0023] Another aspect of the present invention is a method of manufacturing a semiconductor device, comprising: providing a substrate including a trench formed therein; forming a shielding layer above the substrate and in the trench; and monolithizing the substrate after forming the shielding layer to form a semiconductor package.

[0024] Another embodiment of the present invention further includes monolithizing the substrate by cutting from a first portion of the groove to a second portion of the groove.

[0025] Another embodiment of the present invention further includes placing electronic components on the substrate after forming the shielding layer.

[0026] In another embodiment of the present invention, after the step of forming the shielding layer is completed, a plurality of semiconductor packages remain connected by the substrate.

[0027] Another aspect of the present invention is a semiconductor device comprising: a substrate including a trench formed therein; an encapsulation deposited above the substrate; and a shielding layer formed above the encapsulation and in the trench.

[0028] In another embodiment of the semiconductor device, the surface of the encapsulant is coplanar with the surface of the substrate within the trench.

[0029] In another embodiment of the invention, the semiconductor device further includes a mask disposed below the shielding layer and above the substrate.

[0030] In another embodiment of the semiconductor device described in the invention, the groove is curved.

[0031] In another embodiment of the invention, the semiconductor device further includes a plurality of semiconductor packages connected to the substrate. Simple Explanation of the Diagram

[0032] [Figures 1a] to [Figures 1c] illustrate a semiconductor wafer having a plurality of semiconductor grains separated by saw marks; Figures 2a to 2g illustrate the formation of a shielded semiconductor package; [Figures 3a] to [Figures 3o] illustrate the process of forming a shielded semiconductor package by monolithization after the shielding layer is formed; [Figure 4a] and [Figure 4b] illustrate the substitution process flow; and [Figure 5a] and [Figure 5b] illustrate the integration of shielded semiconductor packages into electronic devices. Implementation

[0033] The invention is described in the following description with reference to the accompanying drawings, in which the same reference numerals denote the same or similar elements. Although the invention is described according to the best mode for achieving the objectives of the invention, it will be understood by those skilled in the art that it is intended to cover alternatives, modifications, and equivalents that may include, as defined by the appended claims and their equivalents supported by the following disclosure and drawings, within the spirit and scope of the invention. As used herein, the term "semiconductor die" refers to both the singular and plural forms of the word, and therefore may refer to both a single semiconductor device and multiple semiconductor devices.

[0034] Figures 3a to 3o illustrate the formation of shielded packages using slotted printed circuit boards or substrates to address problems existing in the prior art. Figures 3a and 3b show the initial steps of forming a semiconductor package 200 on a substrate 202. Figure 3a is a partial cross-section and Figure 3b shows a plan view. Although only two units are shown formed on a single substrate, hundreds or thousands of packages 200 are typically formed in a single substrate panel 202 using the same steps described herein but performed collectively.

[0035] The substrate 202 includes one or more insulating layers 204 interleaved with one or more conductive layers 206. In one specific example, the insulating layer 204 is a core insulating board, wherein the conductive layers 206 are patterned above, for example, the top and bottom surfaces of a copper-clad laminate substrate. The conductive layers 206 also include conductive vias vertically electrically coupled through the insulating layers 204. The substrate 202 may include any number of conductive and insulating layers interleaved above each other. A solder mask or passivation layer may be formed above either side of the substrate 202. In other specific examples, any suitable type of substrate or lead frame is used for the substrate 202.

[0036] Any component intended to implement the intended functionality of package 200 is mounted onto or above substrate 202 and electrically connected to conductive layer 206. Components can be mounted on the top and bottom surfaces of substrate 202 in any suitable configuration. In the specific example disclosed, components mounted to substrate 202 at this stage are limited to region 208, which will be encapsulated in subsequent manufacturing steps. Semiconductor die 104 and discrete component 152 are surface-mounted onto substrate 200 within region 208 of each package 200 using, for example, any suitable gripping method or device. Any suitable electronic components can be mounted within region 208 as needed.

[0037] A trench 210 is formed adjacent to and along the boundary of each encapsulation region 208 through the substrate 202. The trench 210 is formed along the region 208 such that, after encapsulation, a shielding layer formed above the region 208 can extend downward into the trench 210 and connect to a portion of the conductive layer 206 exposed within the trench. The trench 210 is formed opposite to the unencapsulated package region 212, such that the trench corresponds to an area of ​​the substrate 202 that will need to be cut for monolithization. In some specific embodiments, the trench 210 may extend partially between regions 208 and 212. Multiple trenches 210 may be used at various locations along the boundary of the region 208, rather than a single long trench. The trench 210 extends completely through the substrate 202, but may also be formed only partially through the substrate. The trench 210 exposes the conductive layer 206 from the region 208 on the side surface of the substrate 202, such that the subsequently formed shielding layer will physically and electrically contact the conductive layer.

[0038] The groove 210 is formed during the initial manufacturing of the substrate 202, which is typically performed by a different manufacturer than the manufacturer that forms the package 200 on the substrate. Forming the groove 210 before the manufacturing of the package 200 begins is simpler for the substrate manufacturer and reduces the requirements for semiconductor package manufacturing. In other specific instances, the manufacturer of the semiconductor package 200 may use lasers, nozzles, saws, routers, or other types of cutting or machining tools to form the groove 210.

[0039] In Figures 3c and 3d, encapsulant 214 is deposited over region 208 using paste printing, compression molding, transfer molding, liquid encapsulation molding, vacuum lamination, spin coating, or other suitable applicators. Encapsulant 214 is confined to region 208 by pressing the mold against the top surface of substrate 202 and injecting encapsulant 214 into the mold. In other specific examples, encapsulant 214 completely covers substrate 202 and is then removed outside region 208. In specific examples using transfer molding or injection molding, encapsulant 214 is deposited using a mold, wherein each chamber is connected to an adjacent chamber that allows the deposited molding compound to flow between packages 200. The regions of encapsulant 214 shown in Figure 3d will be interconnected after molding by paths or bridging between the encapsulants. Before completing package 200, the encapsulation paths connecting the illustrated regions of encapsulant 214 are removed.

[0040] Encapsulation 214 may be a polymer composite material, such as epoxy resin, epoxy acrylate, or polymer with or without fillers. Encapsulation 214 is non-conductive and environmentally friendly, protecting the semiconductor device from external components and contaminants. Encapsulation 214 also protects the semiconductor die 104 from degradation due to light exposure. The side surface 215 of encapsulation 214 is coplanar with the side surface 216 of trench 210. In other specific embodiments, side surface 215 is laterally offset from side surface 216.

[0041] Figures 3e and 3f show the use of a strip 220 to shield the substrate 202 outside the package 214 and the trench 210. The strip 220 completely covers the substrate 202 outside the area 208 and the trench 210. A conductive material is sputtered over the substrate 200 in Figures 3g and 3h to form a conductive shielding layer 224. The shielding layer 224 is formed using any suitable metal deposition technique, such as chemical vapor deposition, physical vapor deposition, other sputtering methods, spraying, or plating. The sputtering material can be copper, steel, aluminum, gold, titanium, combinations thereof, or any other suitable conductive material. In some specific examples, the shielding layer 224 can be formed by sputtering multiple layers of different materials, such as stainless steel-copper-stainless steel or titanium-copper. The shielding layer 224 reduces electromagnetic interference (EMI) between the components of the package 200 and other adjacent electronic devices.

[0042] A shielding layer 224 is formed along the side surface 215 of the package 214 and in a groove 210. In a particular embodiment where surfaces 215 and 216 are not optimally aligned, the shielding layer 224 extends horizontally across the substrate 202 between surfaces 215 and 216. The shielding layer 224 is grounded via a conductive layer 206 exposed at the side surface 216 of the substrate 202. The groove 210 allows the shielding layer 224 to contact the side surface 216 without completely monolithizing each package 200 prior to sputtering. Therefore, the subsequent processing steps described below are performed when the substrate 202 is retained as a device and not a monolithized package 200. The groove 210 can be formed in any arbitrary shape, thus easily adaptable to complex package shapes and designs. The package 200 can be any suitable geometry, such as ellipse, circle, square, octagon, etc. The package 200 can also be an irregular shape, meaning it is not easily defined by words or mathematical expressions.

[0043] In Figures 3i and 3j, the portion of the shielding layer 224 formed on the strip 220 is removed together. The removal of the strip 220 exposes region 212 of the package 200, connecting to a plurality of contact pads of the conductive layer 206 for mounting components on the exterior of the encapsulation 214. The shielding layer 224 remains above the encapsulation 214 in region 208.

[0044] External discrete component 228 is surface-mounted onto substrate 202 in Figures 3k and 3l. Component 228 is reliably aligned with the contact pads of conductive layer 206 because package 200 remains connected to each other by substrate 202 and cannot be easily displaced from its intended position. With package 200 completed, monolithization occurs in Figures 3m and 3n by cutting around the boundary of package 200 using a laser or other cutting tool 230. Laser 230 cuts around package 200 from one end of slot 210 to the other to fully monolithize the package. Since slot 210 already contains partially monolithized package 200, the final monolithization step takes less time than cutting the entire package boundary.

[0045] Figure 3o shows the complete package 200 with shielding layer 224. Package 200 is manufactured with a lower failure rate compared to prior art because the processing steps after forming shielding layer 224 are performed using a substrate 202 that connects the individual cells together as a strip. A unitization step is not required before forming shielding layer 224. Unitization is the final manufacturing step, therefore, cell displacement after unitization is unlikely to cause manufacturing defects. The risk of cell disposal is significantly reduced.

[0046] Figures 4a and 4b illustrate the alternative process flow. Continuing the process steps shown in Figures 3c and 3d, a mask 220A is formed over region 212 in Figure 4a. Mask 220A is similar to strip 220, except that it is formed only over region 212 and not entirely over substrate 202. In Figure 4b, shielding layer 224A is formed over substrate 202, package 200, and mask 220A. Mask 220A is removed to expose region 212, including contact pads of conductive layer 206. Figure 4b shows a process similar to that of Figure 3j, except that shielding layer 224A remains outside package 200 covering substrate 202. The additional remaining portion of shielding layer 224A compared to shielding layer 224 is removed by the monolithization steps shown in Figures 3m and 3n. The resulting end package 200 is not significantly different.

[0047] In some specific instances, the aforementioned package (e.g., package 200) is a fully functional, independent electrical system. Plastic molding or other methods are used to hold the substrate 202 in a suitable location within a product such as a wireless headset or smartwatch. Package 200 may include an integrated antenna for Bluetooth, WiFi, or other protocols, as well as piezoelectric or other speakers for generating noise, a screen for displaying the dial, and other necessary electronic components. Additional electrical devices can be connected via wires or cables within the same product context if needed. The substrate 202 is the motherboard of the terminal device. There are no other motherboards to which package 200 is connected.

[0048] Figures 5a and 5b illustrate another specific example of the integration of the aforementioned semiconductor package (e.g., package 200) into a larger electronic device 300. Figure 5a illustrates a partial cross-section of package 200, which is part of electronic device 300, mounted on a printed circuit board (PCB) or other substrate 302. Bumps 306 are formed on the bottom of substrate 202 during manufacturing, in a process similar to that of bumps 114 formed on die 104, and then soldered back to the conductive layer 304 of PCB 302 to attach and electrically connect package 200 to the PCB. In other specific examples, thermoforming or other suitable attachment and connection methods are used. In some specific examples, an adhesive or underfill layer is used between package 200 and PCB 302. Semiconductor die 104 is electrically coupled to conductive layer 304 via substrate 202.

[0049] Figure 5b illustrates an electronic device 300 including a PCB 302, wherein a plurality of semiconductor packages (including package 200) are mounted on the surface of the PCB. Depending on the application, the electronic device 300 may have one type or multiple types of semiconductor packages. The electronic device 300 may be a standalone system using semiconductor packages to perform one or more electrical functions. Alternatively, the electronic device 300 may be a sub-component of a larger system. For example, the electronic device 300 may be part of a tablet computer, a cell phone, a digital camera, a communication system, or other electronic device. The electronic device 300 may also be a graphics card, a network interface card, or another signal processing card inserted into a computer. Semiconductor packages may include microprocessors, memory, ASICs, logic circuits, analog circuits, RF circuits, discrete active or passive devices, or other semiconductor chips or electronic components.

[0050] In Figure 5b, PCB 302 provides a general-purpose substrate for structural support and electrical interconnection of semiconductor packages mounted on the PCB. Conductive signal traces 304 are formed on or within the surface of PCB 302 using evaporation, electroplating, electroless plating, screen printing, or other suitable metal deposition processes. Signal traces 304 provide electrical connectivity between the semiconductor package, mounted components, and other external systems or components. If necessary, traces 304 also provide power and ground connections to the semiconductor package.

[0051] In some specific examples, the semiconductor device has two package levels. The first-level package is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second-level package involves mechanically and electrically attaching the intermediate substrate to the PCB 302. In other specific examples, the semiconductor device may have only a first-level package, in which the die is mechanically and electrically directly mounted to the PCB 302.

[0052] For illustrative purposes, several types of first-level packages, including wire bond package 346 and flip chip 348, are shown on PCB 302. Additionally, several types of second-level packages, including ball grid array (BGA) 350, bump chip carrier (BCC) 352, land grid array (LGA) 356, multi-chip module (MCM) 358, quad flat non-leaded (QFN) package 360, quad flat package 362, and embedded wafer level ball grid array (eWLB) 364, are shown mounted on PCB 302 together with package 200. Conductive traces 304 electrically couple the various packages and components mounted on PCB 302 to package 200, thereby enabling components within package 200 to be used by other components on the PCB.

[0053] Depending on system requirements, any combination of semiconductor packages configured with first and second level package types and other electronic components can be connected to PCB 302. In some specific instances, electronic device 300 includes a single attached semiconductor package, while other specific instances require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate pre-fabricated components into electronic devices and systems. Because semiconductor packages include complex functionality, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting devices are less prone to failure and less expensive to manufacture, thereby reducing consumer costs.

[0054] Although one or more specific embodiments of the present invention have been described in detail, those skilled in the art will understand that modifications and adaptations can be made to these specific embodiments without departing from the scope of the invention as set forth in the following claims.

[0055] 100: Semiconductor wafers 102: Substrate Material 104: Semiconductor chips / modules 106: Sawing track 108: Back surface 110: Active Surface 112: Conductive layer / contact pad 114: Conductive ball / bump 118: Laser Cutting Tools 150: Packaging substrate 150A: Partial 150B: Partial 152: Discrete Components 154: Encapsulated Body 160: Laser cutting tools 162: Trench 170: Shielding layer 172: Damaged 174: Discrete Devices 200: Semiconductor Packaging 202:Substrate 204: Insulation layer 206: Conductive layer 208: District 210: slot 212: Non-encapsulated packaging area 214: Encapsulated body 215: Side surface 216: Side surface 220: with 220A: Mask 224: Conductive shielding layer 224A: Shielding layer 228: External Discrete Components 230: Cutting tools 300: Electronic devices 302:Substrate 304: Conductive layer / trace 306: Bump 346: Wire Bond Package 348: Flip Chip 350: Ball Grid Array 352: Bumped wafer carrier 356: Planar Grid Array 358: Multi-chip module 360: Quad Flat No-Lead Package 362: Quad Flat Package 364: Embedded Wafer-Level Ball Grid Array

Claims

1. A method of manufacturing a semiconductor device, comprising: providing a substrate including a plurality of conductive layers and a plurality of insulating layers interleaved between the plurality of conductive layers; forming a trench that extends completely through the substrate; disposing a first electronic component adjacent to the trench over the substrate, wherein the substrate includes the plurality of conductive layers and the plurality of insulating layers before the first electronic component is disposed over the substrate; after forming the trench, depositing an encapsulant over the first electronic component and the substrate, wherein the surface of the encapsulant is coplanar with a surface of the substrate within the trench, and wherein the trench remains free of the encapsulant; forming a shielding layer over the encapsulant and substantially contacting the surface of the substrate within the trench; and after forming the shielding layer, monolithizing the substrate to form a semiconductor package having the first electronic component.

2. The method of claim 1, further comprising monolithizing the substrate by cutting from a first end of the groove to a second end of the groove.

3. The method of request item 1, further comprising: Before forming the shielding layer, a mask is placed on top of the substrate; And remove the shield after the shielding layer is formed.

4. The method of claim 1, wherein the semiconductor package is circular.

5. The method of claim 1, further comprising placing a second electronic component on the substrate after the shielding layer is formed.

6. The method of claim 1, wherein after the step of forming the shielding layer is completed, the plurality of semiconductor packages remain connected by the substrate.

7. A method of manufacturing a semiconductor device, comprising: providing a substrate, including forming a trench that extends completely through the substrate; after forming the trench that extends completely through the substrate, depositing an encapsulant over the substrate, wherein the trench remains free of the encapsulant; forming a shielding layer over the substrate and in the trench; and monolithizing the substrate after forming the shielding layer to form a semiconductor package.

8. The method of claim 7, further comprising monolithizing the substrate by cutting from a first portion of the groove to a second portion of the groove.

9. The method of claim 7, further comprising placing electronic components on the substrate after the shielding layer is formed.

10. The method of claim 7, wherein after the step of forming the shielding layer is completed, the plurality of semiconductor packages remain connected by the substrate.

11. The method of claim 7, further comprising: Before forming the shielding layer, a mask is placed above the substrate; And after the shielding layer is formed, the mask is removed.

12. The method of claim 7, wherein the semiconductor package is circular.

13. A method of manufacturing a semiconductor device, comprising: providing a substrate including a conductive layer and an insulating layer; forming a trench that extends completely through the substrate; after the substrate has been formed to include the conductive layer and the insulating layer, disposing a first electronic component over the substrate; after the trench has been formed in the substrate, depositing an encapsulant over the substrate, wherein a surface of the encapsulant is adjacent to the trench, and the trench remains free of the encapsulant; A shielding layer is formed on the surface of the substrate above the encapsulation and within the groove; And after forming the shielding layer, the substrate is monolithized to form a semiconductor package.

14. The method of claim 13, further comprising monolithizing the substrate by cutting from a first end of the groove to a second end of the groove.

15. The method of claim 13, further comprising: Before forming the shielding layer, a mask is placed above the substrate; And after the shielding layer is formed, the mask is removed.

16. The method of claim 15, wherein the mask completely covers the substrate except for the area where the encapsulation is deposited.

17. The method of claim 13, wherein the semiconductor package is circular or irregular in shape.

18. The method of claim 13, further comprising placing a second electrical component on the substrate after forming the shielding layer and before monolithizing the substrate.

19. The method of claim 13, wherein after the step of forming the shielding layer is completed, the plurality of semiconductor packages remain connected via the substrate.

20. A method of manufacturing a semiconductor device, comprising: providing a substrate including a trench formed in the substrate; depositing an encapsulation over the substrate after the trench has been formed through the substrate, wherein the trench remains free of the encapsulation; and forming a shielding layer over the encapsulation and within the trench.

21. The method of claim 20, further comprising depositing the encapsulation such that the surface of the encapsulation is coplanar with the surface of the substrate within the trench.

22. The method of claim 20, further comprising: The mask is placed above the substrate; And the shielding layer is formed above the shield.

23. The method of claim 20, wherein the groove is curved.

24. The method of claim 20, further comprising placing an electrical component above the substrate outside the encapsulation.

25. The method of claim 20, further comprising forming a plurality of semiconductor packages on the substrate.

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