Monolithic complementary field-effect transistors having carbon-doped release layers

Abstract

Embodiments of this disclosure advantageously provide semiconductor devices CFETs, and in particular, methods for manufacturing such devices having a fully strained superlattice structure having a substantially defect-free channel layer and a release layer having a reduced selective removal rate. The CFETs described herein comprise vertically stacked superlattice structures on a substrate, the vertically stacked superlattice structures comprising: a first hGAA structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in the range of greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprises alternating layers of silicon (Si)-containing nanosheet channel layers and nanosheet release layers containing doped silicon germanium (SiGe).

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of electronic component manufacturing, and more particularly, to transistors. More specifically, embodiments of the present disclosure are directed to complementary field-effect transistors (CFETs). Prior Art

[0002] Transistors are key components in most integrated circuits. Because a transistor's drive current and speed are proportional to its gate width, faster transistors typically require larger gate widths. Consequently, a trade-off exists between transistor size and speed, and "fin" field-effect transistors (finFETs) have been developed to address the conflicting goals of maximizing transistor drive current and minimizing transistor size. FinFETs are characterized by a fin-shaped channel region, which significantly increases transistor size without significantly increasing the transistor's footprint. FinFETs are now used in many integrated circuits. However, finFETs have their own drawbacks.

[0003] As transistor feature sizes continue to shrink to achieve greater circuit density and higher performance, improvements in transistor structure are needed to improve electrostatic coupling and reduce negative effects such as parasitic capacitance and off-state leakage. Examples of transistor structures include planar, fin field-effect transistor (FinFET), and gate-all-around (GAA) structures. The GAA device structure consists of several lattice-matched trenches suspended in a stacked configuration and connected by source / drain regions. The GAA structure provides excellent electrostatic control and is widely adopted in complementary metal-oxide-semiconductor (CMOS) wafer manufacturing.

[0004] An example of gate-all-around (GAA) technology is the complementary field-effect transistor (CFET), in which nFET and pFET nanowires / nanosheets are stacked vertically on top of each other. Compared to GAA transistors, CFETs increase on-chip device density and reduce area consumption. When stacking nFETs and pFETs in a monolithic fashion, the n and p superlattices are deposited sequentially, with the middle sacrificial layer selectively removed during processing and replaced with an intermediate dielectric isolation layer. The intermediate dielectric isolation layer serves to electrically isolate the lower-level GAA from the upper-level GAA.

[0005] Each n- or p-type superlattice in a CFET consists of alternating layers of channel and release layers. The release layer typically comprises silicon germanium (SiGe) with a low concentration of germanium (Ge). The middle sacrificial layer, with its high Ge concentration, contrasts with the etching of the channel and release layers. However, due to the high Ge concentration in the middle sacrificial layer, the superlattice relaxes, and strain and mobility are reduced, resulting in poor transistor performance due to reduced drive current.

[0006] Therefore, there is a need for semiconductor devices, particularly CFETs, and methods for fabricating such devices having a fully strained superlattice structure with a defect-free or substantially defect-free channel layer and a release layer with a reduced selective removal rate. Summary of the Invention

[0007] One or more embodiments of the present disclosure relate to semiconductor devices. In one or more embodiments, a semiconductor device includes a vertically stacked superlattice structure on a substrate, the vertically stacked superlattice structure comprising: a first horizontal gate-all-around (hGAA) structure on the substrate; a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of greater than 0% to 50% on an atomic basis; and a second hGAA structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprises alternating layers of a nanosheet channel layer and a nanosheet release layer. The nanosheet channel layer comprises silicon (Si), and the nanosheet release layer comprises doped silicon germanium (SiGe).

[0008] Additional embodiments of the present disclosure relate to methods for forming semiconductor devices. In one or more embodiments, a method for forming a semiconductor device includes forming a vertically stacked superlattice structure on a substrate by: forming a first horizontal gate-all-around (hGAA) structure on the substrate; forming a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in a range of greater than 0% to 50% atomically; and forming a second horizontal gate-all-around (hGAA) structure on a top surface of the sacrificial layer. Each of the first hGAA and the second hGAA comprises alternating layers of a nanosheet channel layer and a nanosheet release layer. The nanosheet channel layer comprises silicon (Si), and the nanosheet release layer comprises doped silicon germanium (SiGe). Simple diagram description

[0009] The features of the present disclosure have been briefly summarized above and discussed in more detail below. These features can be understood by reference to the embodiments of the present disclosure illustrated in the accompanying drawings. However, it should be noted that the accompanying drawings illustrate only typical embodiments of the present disclosure and, therefore, should not be considered limiting of its scope, as the disclosure may admit to other equally effective embodiments. The embodiments described herein are illustrated by way of example and not limitation in the accompanying drawings, where like reference numerals represent similar elements.

[0010] Figure 1 illustrates a process flow diagram of a method for forming a semiconductor device according to one or more embodiments;

[0011] Figure 2 illustrates a semiconductor structure according to one or more embodiments;

[0012] FIG3 illustrates a semiconductor structure according to one or more embodiments; and

[0013] FIG. 4 illustrates a vertically stacked superlattice structure according to one or more embodiments. Implementation Method

[0014] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or processing steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0015] As used herein, the term "about" means approximately or close to, and in the context of a listed numerical value or range, refers to a variation of ±15% or less of the numerical value. For example, values ​​that differ by ±14%, ±10%, ±5%, ±2%, or ±1% would meet the definition of about.

[0016] As used in this specification and the appended patent applications, the term "substrate" or "wafer" refers to a surface or portion of a surface on which a process is performed. Those skilled in the art will also understand that, unless the context clearly indicates otherwise, reference to a substrate may refer to only a portion of a substrate. Additionally, reference to deposition on a substrate may refer to both a bare substrate and a substrate having one or more films or features deposited or formed thereon.

[0017] As used herein, "substrate" refers to any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, substrate surfaces on which processing is performed include materials such as silicon, silicon oxide, strained silicon, silicon-on-insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, and any other materials (e.g., metals, metal nitrides, metal alloys, and other conductive materials), depending on the application. Substrates include, but are not limited to, semiconductor wafers. Substrates can be exposed to pretreatment processes to polish, etch, reduce, oxidize, hydroxylate, anneal, and / or bake the substrate surface. In addition to direct film processing directly on the substrate surface itself, any of the film processing steps disclosed in this disclosure may also be performed on an underlayer formed on the substrate, as described in more detail below, and the term "substrate surface" is intended to include such underlayers as the context dictates. Thus, for example, where a film / layer or portion of a film / layer is already deposited on a substrate surface, the exposed surface of the newly deposited film / layer becomes the substrate surface.

[0018] The term "on" indicates that there is direct contact between elements. The term "directly on" indicates that there is direct contact between elements without intervening elements.

[0019] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactant gas," etc. are used interchangeably to refer to any gaseous substance that can react with the substrate surface.

[0020] Epitaxy is a process by which a deposited film is forced into a high degree of crystalline alignment with the substrate. Epitaxy growth is broadly defined as the condensation of a gaseous precursor to form a film on a substrate. Liquid precursors can also be used. Vapor precursors can be obtained by chemical vapor deposition (CVD) and laser ablation. Several epitaxy techniques are currently available, such as molecular beam epitaxy (MBE), epitaxial CVD, and atomic layer epitaxy (ALE).

[0021] A transistor is a circuit component or element often formed on a semiconductor device. Depending on the circuit design, a transistor may be formed on a semiconductor device in addition to capacitors, inductors, resistors, diodes, wires, or other components. Generally, a transistor includes a gate formed between a source region and a drain region. In one or more embodiments, the source and drain regions comprise doped regions of the substrate and exhibit a doping profile suitable for a particular application. The gate is located above the channel region and includes a gate dielectric interposed between a gate electrode in the substrate and the channel region.

[0022] As used herein, the term "field-effect transistor" or "FET" refers to a transistor that uses an electric field to control its electrical behavior. A field-effect transistor is a voltage-controlled device whose current-carrying capacity is varied by applying an electric field. Field-effect transistors typically exhibit very high input impedance at low temperatures. The conductivity between the drain and source terminals is controlled by the electric field in the device, generated by the voltage difference between the bulk and gate of the device. The three terminals of a FET are the source (S), through which carriers enter the channel; the drain (D), through which carriers leave the channel; and the gate (G), which modulates the channel conductivity. Typically, the current entering the channel at the source (S) is denoted as IS, and the current entering the channel at the drain (D) is denoted as ID. The drain-to-source voltage is denoted as VDS. The current entering the channel at the drain (i.e., ID) can be controlled by applying a voltage to the gate (G).

[0023] A metal-oxide-semiconductor field-effect transistor (MOSFET) is a type of field-effect transistor (FET) used in integrated circuits and high-speed switching applications. A MOSFET has an insulated gate whose voltage determines the device's conductivity. This ability to change conductivity with applied voltage is used to amplify or switch electronic signals. The MOSFET is based on modulating charge concentration across a metal-oxide-semiconductor (MOS) capacitor between a body electrode and a gate electrode. The gate electrode sits above the body and is insulated from all other device regions by a gate dielectric layer. Compared to a MOS capacitor, a MOSFET includes two additional terminals (source and drain), each connected to a separate highly doped region separated by a body region. These regions can be either p-type or n-type, but are either the same type as the body region or the opposite type. The source and drain (unlike the body) are highly doped, as indicated by the "+" sign after the doping type.

[0024] If the MOSFET has an n-type channel, or an nMOS FET, the source and drain are the n+ regions, and the bulk is the p-type substrate region. If the MOSFET has a p-type channel, or a pMOS FET, the source and drain are the p+ regions, and the bulk is the n-type substrate region. The source is so named because it is the source of charge carriers flowing through the channel (electrons for an n-type channel, holes for a p-type channel); similarly, the drain is where the charge carriers leave the channel.

[0025] An nMOS FET consists of n-type source and drain electrodes and a p-type substrate. When a voltage is applied to the gate, holes in the bulk (p-type substrate) are driven away from the gate. This allows an n-type channel to form between the source and drain, and current is carried by electrons from the source through the induced n-type channel to the drain. Logic gates and other digital devices implemented using NMOS are said to have NMOS logic. NMOS has three operating modes: cutoff, triode, and saturation. Circuits with NMOS logic gates consume static power when the circuit is idle because DC current flows through the logic gate when the output is low.

[0026] A pMOS FET consists of p-type source and drain electrodes and an n-type substrate. When a positive voltage is applied between the source and gate (negative voltage between the gate and source), a p-type channel of opposite polarity is formed between the source and drain electrodes. Current is carried by holes from the source through the induced p-type channel to the drain. A high voltage on the gate causes the PMOS transistor to conduct, while a low voltage on the gate causes it to conduct. Logic gates and other digital devices implemented using PMOS are said to have PMOS logic. PMOS technology offers low cost and excellent noise immunity.

[0027] In NMOS, the carriers are electrons, while in PMOS, the carriers are holes. When a high voltage is applied to the gate, NMOS conducts, while PMOS does not. Furthermore, when a low voltage is applied to the gate, NMOS does not conduct, while PMOS conducts. NMOS is considered faster than PMOS because the carriers in NMOS (electrons) move twice as fast as the holes (PMOS). However, PMOS devices are more resistant to noise than NMOS devices. Furthermore, NMOS ICs are smaller than PMOS ICs (with the same functionality) because NMOS offers half the impedance of PMOS (with the same geometry and operating conditions).

[0028] As used herein, the term "FinFET" refers to a MOSFET transistor built on a substrate, in which the gate is located on two, three, or four sides of the channel, or surrounds the channel, forming a dual-gate structure. FinFET devices have been given the generic name FinFET because the source / drain regions form a "fin" on the substrate. FinFET devices feature fast switching times and high current density.

[0029] As used herein, the term "gate all-around" (GAA) refers to an electronic device, such as a transistor, in which the gate material surrounds the channel region on all sides. The channel region of a GAA transistor may include nanowires, nanoslabs, nanosheets, strip-shaped channels, or other suitable channel configurations known to those skilled in the art. In one or more embodiments, the channel region of a GAA device comprises multiple vertically spaced horizontal nanowires or strips, making the GAA transistor a stacked horizontal gate-all-around (hGAA) transistor.

[0030] As used herein, the term "complementary field-effect transistor (CFET)" refers to a transistor including an NMOS FET element and a PMOS FET element stacked on top of each other. Each of the NMOS FET element and the PMOS FET element forming the CFET is a GAA transistor or an hGAA transistor.

[0031] As used herein, the term "nanowire" refers to a nanostructure with a diameter on the order of nanometers (10⁻⁹ meters). A nanowire can also be defined as having an aspect ratio greater than 1000. Alternatively, a nanowire can be defined as a structure with a thickness or diameter limited to tens of nanometers or less and an unlimited length. Nanowires are used in transistors and some laser applications and, in one or more embodiments, are made of semiconductor, metallic, insulating, superconducting, or molecular materials. In one or more embodiments, nanowires are used in transistors for logic CPUs, GPUs, MPUs, and volatile (e.g., DRAM) and non-volatile (e.g., NAND) devices. As used herein, the term "nanosheet" refers to a two-dimensional nanostructure having a thickness ranging from approximately 0.1 nm to approximately 1000 nm, or from 0.5 nm to 500 nm, or from 0.5 nm to 100 nm, or from 1 nm to 500 nm, or from 1 nm to 100 nm, or from 1 nm to 50 nm.

[0032] Without wishing to be bound by theory, it is believed that relaxation within a vertically stacked superlattice structure comprising one or more hGAAs leads to defects in the nanosheet channel layer within the structure. Embodiments of the present disclosure advantageously provide semiconductor devices comprising a fully strained vertically stacked superlattice structure having a defect-free or substantially defect-free nanosheet channel layer. In some embodiments, the presence of defects in the nanosheet channel layer is determined using reciprocal space mapping (RSM). Without wishing to be bound by theory, RSM is an x-ray diffraction method that collects diffraction data of a vertically stacked superlattice structure in which defects are observable. As used herein, the term "substantially free" refers to a nanosheet channel layer that is substantially defect-free as determined by reciprocal space mapping (RSM).

[0033] To remove the sacrificial layer within a CFET superlattice without etching the nanosheet release layer, a three-color selectivity of >10:1 is required. In typical patterned wafers, the selectivity of SiGe to Si is very high, meeting the >10:1 requirement. However, the selectivity for SiGe with a high germanium content (i.e., greater than 30 atomic%) is much lower than for SiGe with a low germanium content (i.e., 15-20 atomic%) and does not meet the >10:1 requirement. Without intending to be bound by any particular theory of operation, it is believed that doping the SiGe release layer with a dopant (e.g., carbon (C)) slows the SiGe etch rate, thereby increasing the differential etch rate compared to the undoped SiGe of the sacrificial layer. Therefore, one or more embodiments of the present disclosure advantageously provide differentiation during etching of SiGe layers (i.e., the sacrificial layer and the nanosheet release layer) relative to each other and to the channel layer.

[0034] In one or more embodiments, the release layer is advantageously doped with carbon (C) to improve strain and mobility by reducing relaxation. Furthermore, doping the release layer with carbon (C) reduces the etch rate of the release layer compared to the etch rate of the sacrificial layer. In other words, doping the release layer with carbon (C) advantageously increases the etch rate of the intermediate sacrificial layer, facilitating easier removal without damaging the release layer or the channel layer.

[0035] Embodiments of the present disclosure are described with reference to the accompanying drawings, which illustrate components (e.g., transistors) and processes for forming the transistors according to one or more embodiments of the present disclosure. The illustrated processes are merely illustrative of possible uses of the disclosed processes, and those skilled in the art will recognize that the disclosed processes are not limited to the illustrated applications.

[0036] FIG1 illustrates a process flow diagram of a method 100 for fabricating a monolithic CFET device according to one or more embodiments of the present disclosure. More specifically, FIG1 illustrates a process flow diagram of a method 100 for fabricating an engineered substrate for an epitaxially grown superlattice composed of alternating silicon (Si) and silicon germanium (SiGe) layers for producing a monolithic CFET device. In one or more embodiments, the superlattice is strained and free of lattice defects, allowing for differential selective removal of two or more SiGe layers of varying composition. Referring to FIG1 , method 100 begins with operation 102 , where a vertically stacked superlattice structure is formed on a substrate. The vertically stacked superlattice structure is formed on the substrate by the following steps: At operation 104 , a first horizontal gate-all-around (hGAA) structure is formed on the substrate. At operation 106 , a sacrificial layer is formed on a top surface of the first hGAA structure. At operation 108 , a second horizontal gate-all-around (hGAA) structure is formed on a top surface of the sacrificial layer. At operation 110 , method 100 optionally includes the step of selectively removing the sacrificial layer so that an intermediate isolation layer can be formed during subsequent processing.

[0037] 2-4 illustrate cross-sectional views of a vertically stacked superlattice structure of a CFET device 200. The CFET device 200 shown in FIG2-4 can be manufactured by the method 100 shown in FIG1.

[0038] In one or more embodiments, the CFET element 200 includes a substrate 210 having a top surface 212. The substrate 210 can be any suitable substrate material known to those skilled in the art. In one or more embodiments, the substrate 210 includes a semiconductor material such as silicon (Si), carbon (C), germanium (Ge), silicon germanium (SiGe), gallium arsenide (GaAs), indium phosphate (InP), indium gallium arsenide (InGaAs), indium aluminum arsenide (InAlAs), germanium (Ge), silicon germanium (SiGe), other semiconductor materials, or any combination thereof. In one or more embodiments, the substrate 210 includes one or more of the following: silicon (Si), germanium (Ge), gallium (Ga), arsenic (As), indium (In), phosphorus (P), or selenium (Se). Although several examples of materials from which substrate 210 may be formed are described herein, any material that may serve as a foundation upon which passive and active electronic components (such as transistors, memory, capacitors, inductors, resistors, switches, integrated circuits, amplifiers, optoelectronic components, or any other electronic component) may be constructed falls within the spirit and scope of the present disclosure.

[0039] In one or more embodiments, substrate 210 is a p-type or n-type substrate. As used herein, the term "n-type" refers to a semiconductor created by doping an intrinsic semiconductor with an electron donor element during fabrication. The term n-type comes from the negative charge of electrons. In an n-type semiconductor, electrons are the majority carriers, while holes are the minority carriers. As used herein, the term "p-type" refers to the positive charge of the well (or hole). In contrast to n-type semiconductors, p-type semiconductors have a greater concentration of holes than electrons. In a p-type semiconductor, holes are the majority carriers, while electrons are the minority carriers.

[0040] In one or more embodiments, the vertically stacked superlattice structure 260 includes one or more horizontal gate-around-all-around (hGAA) structures on the substrate 210. In some embodiments, the vertically stacked superlattice structure 260 includes a first or lower horizontal gate-around-all-around (hGAA) structure 215 on the substrate 210. In some embodiments, at operation 104 of method 100, the vertically stacked superlattice structure 260 includes a first or lower horizontal gate-around-all-around (hGAA) structure 215 on the top surface 212 of the substrate 210. In some embodiments, the vertically stacked superlattice structure 260 includes a second or upper horizontal gate-around-all-around (hGAA) structure 255. Without intending to be limited to any particular theory of operation, the first or lower hGAA 215 and the second or upper hGAA 255 may independently include identical structures having identical layers. In the embodiment shown in Figures 3 and 4, the vertically stacked superlattice structure 260 includes a first hGAA structure 215 on the top surface 212 of the substrate 210, a sacrificial layer 240 on the top surface 225 of the first hGAA structure 215 (formed in operation 106 of the method 100), and a second hGAA structure 255 on the top surface 245 of the sacrificial layer 240 (formed in operation 108 of the method 100).

[0041] 2-4 , in some embodiments, each of the first hGAA 215 and the second hGAA 255 includes alternating layers of nanosheet channel layers 230 and nanosheet release layers 220. In some embodiments, the plurality of nanosheet release layers 220 and the plurality of nanosheet channel layers 230 may include any number of lattice-matched material pairs suitable for forming a vertically stacked superlattice structure 260. In some embodiments, each of the first hGAA 215 and the second hGAA 255 has alternating layers of nanosheet channel layers 230 and nanosheet release layers 220 in a range of 1 to 5 pairs.

[0042] Nanosheet release layer 220 can have any suitable thickness. In one or more embodiments, each nanosheet release layer 220 has a thickness in the range of 5 nm to 15 nm. Nanosheet channel layer 230 can have any suitable thickness. In one or more embodiments, each nanosheet channel layer 230 has a thickness in the range of 5 nm to 15 nm.

[0043] In some embodiments, each nanosheet channel layer 230 independently comprises silicon (Si). In some embodiments, each nanosheet release layer 220 independently comprises silicon germanium (SiGe) doped with a dopant. In one or more embodiments, the nanosheet release layer 220 comprises silicon germanium (SiGe) having a germanium content in the range of greater than approximately 0% to 30% atomically. In a specific embodiment, the nanosheet release layer 220 comprises silicon germanium (SiGe) having a germanium content in the range of approximately 10% to 25% atomically.

[0044] The silicon germanium (SiGe) of the nanosheet release layer 220 can be doped with any suitable dopant, including an element having an atomic weight less than that of silicon (Si). In some embodiments, the silicon germanium (SiGe) of the nanosheet release layer 220 is doped with a dopant including one or more of carbon (C) and boron (B). In one or more specific embodiments, the silicon germanium (SiGe) of the nanosheet release layer 220 is doped with carbon (C).

[0045] In one or more embodiments, the dopant of the nanosheet release layer 220 can have any suitable concentration. In some embodiments, the dopant has a concentration ranging from greater than 0% to less than or equal to 2% dopant by atom. In some embodiments, the dopant has a concentration less than or equal to 2% dopant by atom, including a dopant in the range of 0.1% to 1.99% by atom. In some embodiments, the dopant concentration is in the range of 0.1% to 1.99%, including a dopant in the range of 0.1% to 1.95%, 0.1% to 1.9%, 0.2% to 1.8%, 0.3% to 1.7%, 0.4% to 1.6%, 0.5% to 1.5%, 0.6% to 1.4%, 0.7% to 1.3%, 0.8% to 1.2%, and 0.9% to 1.1%.

[0046] In a specific embodiment, the dopant is carbon (C), and the carbon concentration is in a range of greater than 0% to less than or equal to 2% carbon (C) by atom. In some embodiments, the nanosheet release layer 220 is doped with carbon (C), and the carbon (C) concentration in the nanosheet release layer 220 is in a range of greater than 0% to less than or equal to 2% by atom. In some embodiments, the carbon concentration in the nanosheet release layer 220 is less than or equal to 2% carbon by atom, including in a range from 0.1% to 1.99% carbon by atom. In some embodiments, the carbon concentration in the nanosheet release layer 220 is in the range of 0.1% to 1.99%, including carbon in the range of 0.1% to 1.95%, in the range of 0.1% to 1.9%, in the range of 0.2% to 1.8%, in the range of 0.3% to 1.7%, in the range of 0.4% to 1.6%, in the range of 0.5% to 1.5%, in the range of 0.6% to 1.4%, in the range of 0.7% to 1.3%, in the range of 0.8% to 1.2%, and in the range of 0.9% to 1.1% by atom.

[0047] In other embodiments, the nanosheet release layer 220 dopant is boron (B) and the dopant has a concentration ranging from greater than 0% to less than or equal to 2% boron (B) on an atomic basis.

[0048] In one or more embodiments, the nanosheet release layer 220 may include a dopant containing one or more of carbon (C) and boron (B), and the total combined dopant concentration may be in a range from greater than 0% to less than or equal to 2%. Therefore, in some embodiments, the nanosheet release layer 220 is doped with carbon (C) and boron (B).

[0049] In one or more embodiments, it has been advantageously discovered that doping the silicon germanium (SiGe) of the nanosheet release layer 220 allows for control of the strain of the vertically stacked superlattice structure 260. Embodiments of the present disclosure advantageously provide a fully strained vertically stacked superlattice structure 260, wherein each of the nanosheet release layers 220 independently comprises doped silicon germanium (SiGe). More specifically, embodiments of the present disclosure advantageously provide a fully strained vertically stacked superlattice structure 260, wherein each of the nanosheet release layers 220 independently comprises silicon germanium (SiGe) doped with carbon (C).

[0050] In one or more embodiments, it has been surprisingly discovered that doping the silicon germanium (SiGe) of the nanosheet release layer 220 with carbon (C) reduces strain in the vertically stacked superlattice structure 260 and allows for higher growth temperatures, thereby resulting in an increased growth rate for forming the vertically stacked superlattice structure 260. As used herein, "increased growth rate" refers to reducing the amount of time it takes to form the layers of the vertically stacked superlattice structure 260. In other words, doping the silicon germanium (SiGe) of the nanosheet release layer 220 with carbon (C) at a temperature of approximately 600°C increases the growth rate by at least a factor of two or at least a factor of three compared to the growth rate at a temperature of approximately 560°C. Embodiments of the present disclosure advantageously provide a fully strained vertically stacked superlattice structure 260 in which each of the nanosheet release layers 220 independently comprises silicon germanium (SiGe) doped with carbon (C).

[0051] In one or more embodiments, a sacrificial layer 240 is formed between the first or lower hGAA and the second or upper hGAA. In one or more embodiments, the middle sacrificial layer 240 is selectively removed during subsequent processing and replaced with an intervening dielectric isolation layer. The intervening dielectric isolation layer serves to electrically isolate the source / drain regions of the lower GAA 215 from the source / drain regions of the upper GAA 255. In one or more embodiments, the sacrificial layer 240 comprises silicon germanium (SiGe) having a germanium content in the range of greater than 15% to 50% atomically. In a specific embodiment, the nanosheet release layer 220 comprises silicon germanium (SiGe) having a germanium content in the range of approximately 10% to 30% atomically, and the sacrificial layer 240 comprises silicon germanium (SiGe) having a germanium content in the range of 20% to 40% atomically. In a particular embodiment, the sacrificial layer 240 includes silicon germanium (SiGe) having a germanium content in the range of approximately 20% to 50% on an atomic basis, including 20%, 21%, 22%, 23%, 24%, 25%, 26%, 27%, 28%, 29%, 30%, 31%, 32%, 33%, 34%, 35%, 36%, 37%, 38%, 39%, 40%, 41%, 42%, 43%, 44%, 45%, 46%, 47%, 48%, 49% and 50%.

[0052] In one or more embodiments, the sacrificial layer 240 can have any suitable thickness. In some embodiments, the thickness of the sacrificial layer 240 is in a range of 15 nm to 90 nm, including 15 nm to 80 nm, 20 nm to 75 nm, 15 nm to 60 nm, 15 nm to 50 nm, 15 nm to 75 nm, and 20 nm to 50 nm. In some embodiments, increasing the thickness of the sacrificial layer 240 to greater than 40 nm increases the etch selectivity between the sacrificial layer 240 and the nanosheet release layer 220.

[0053] As known to those skilled in the art, sacrificial layer 240 can be removed during subsequent processing and replaced with an intermediate isolation layer. Therefore, at operation 110, method 100 optionally includes selectively removing sacrificial layer 240. The sacrificial layer 240 can be selectively removed by any suitable means known to those skilled in the art. In some embodiments, selectively removing sacrificial layer 240 includes an etching process that removes sacrificial layer 240 but does not remove nanosheet release layer 220. In some embodiments, the etching process includes one or more of a wet etching process or a dry etching process. In some embodiments, the etching process is a directional etching process.

[0054] Each of the nanosheet release layer 220, nanosheet channel layer 230, and sacrificial layer 240 within the vertically stacked superlattice structure 260 has its own selective removal rate. Without being bound by theory, it is believed that the high germanium content of the sacrificial layer 240 (e.g., greater than 30 atomic percent germanium) increases the selective removal rate within the vertically stacked superlattice structure, and that doping the SiGe of the nanosheet release layer 220 with carbon reduces the etch rate of the nanosheet release layer, resulting in a selectivity greater than 10:1 between the sacrificial layer 240 and the nanosheet release layer 220. In one or more embodiments, increasing the thickness of the sacrificial layer 240 to a thickness greater than 40 nm results in an increased selectivity greater than 15:1 between the sacrificial layer 240 and the nanosheet release layer 220.

[0055] In one or more embodiments, it has been advantageously discovered that doping the silicon germanium (SiGe) of the nanosheet release layer 220 with a dopant, such as carbon (C), with a dopant concentration ranging from greater than 0% to less than or equal to 2% atomically allows for differentiation of the nanosheet release layer 220, nanosheet channel layer 230, and sacrificial layer 240 within the vertically stacked superlattice structure 260. In other words, doping the silicon germanium (SiGe) of the nanosheet release layer 220 with carbon (C) advantageously reduces the selective removal rate of each nanosheet release layer within the vertically stacked superlattice structure 260. Embodiments of the present disclosure advantageously provide methods for selectively removing sacrificial layers while reducing their selective removal rate without damaging the nanosheet release layer and nanosheet channel layer within one or more of the first hGAA 215 or the second hGAA 255.

[0056] In one or more embodiments, it has been advantageously found that the carbon (C)-doped nanosheet release layer 220 has a reduced etch rate compared to a nanosheet release layer not doped with carbon (C). In some embodiments, the etch rate is reduced by a factor of at least 2.

[0057] Spatially relative terms such as "below," "beneath," "beneath," "above," and "above" may be used throughout this specification to describe one element or feature in relationship to other elements or features illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Thus, the exemplary term "below" would encompass both orientations of "above" and "beneath." The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative terms used herein interpreted accordingly.

[0058] The use of the terms "a," "an," and "the," and similar references in the context of describing the materials and methods discussed in this specification (especially in the context of the following claims) should be understood to include both the singular and the plural, unless otherwise indicated herein or clearly contradicted by context. The recitation of ranges of values ​​herein is merely intended as a shorthand method of representing the individual values ​​falling within the range, unless otherwise indicated herein, and each individual value is incorporated into the specification as if individually recited herein. All methods described herein can be performed in any suitable order, unless otherwise indicated herein or clearly contradicted by context. The use of any and all examples, or exemplary language (e.g., "for example") provided herein, is intended merely to better illustrate the materials and methods and does not limit the same unless otherwise claimed. No language in the specification should be construed as indicating any non-claimed element as essential to the practice of the disclosed materials and methods.

[0059] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" refer to a particular feature, structure, material, or characteristic described in connection with at least one embodiment of the present disclosure. Thus, the appearances of phrases such as "in one or more embodiments," "certain embodiments," "in one embodiment," or "in an embodiment" throughout this specification are not necessarily referring to the same embodiment of the present disclosure. In one or more embodiments, the particular features, structures, materials, or characteristics may be combined in any suitable manner.

[0060] Although the present disclosure has been described with reference to specific embodiments, it should be understood that these embodiments are merely illustrative of the principles and applications of the present disclosure. It will be apparent to those skilled in the art that various modifications and variations can be made to the methods and apparatus of the present disclosure without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure is intended to include such modifications and variations as come within the scope of the appended claims and their equivalents.

[0061] 100: Method 102: Operation 104: Operation 106: Operation 108: Operation 110: Operation 200:CFET components 210:Substrate 212: Top surface 215: First horizontal gate-around (hGAA) structure 220:Nanosheet release layer 225: Top surface 230:Nanosheet channel layer 240: Sacrificial layer 245: Top surface 255: Second hGAA 260: Vertically stacked superlattice structure

[0062] Domestic storage information (please note the order of storage institution, date, and number) none Overseas deposit information (please note the order of deposit country, institution, date, and number) none

Claims

1. A method of forming a semiconductor device, the method comprising the steps of: forming a vertically stacked superlattice structure on a substrate by means of the following steps: forming a first horizontal all-around gate (hGAA) structure on the substrate; forming a sacrificial layer on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content on an atomic basis in the range of greater than 0% to 50%; and forming a second horizontal all-around gate (hGAA) structure on a top surface of the sacrificial layer, wherein each of the first hGAA structure and the second hGAA structure comprises alternating layers of nanosheet channel layers and nanosheet release layers, each nanosheet channel layer independently comprising silicon (Si) and each nanosheet release layer independently comprising silicon germanium (SiGe) doped with a dopant, and wherein each nanosheet release layer has a reduced etch rate compared to the sacrificial layer.

2. The method as described in claim 1, wherein the sacrificial layer comprises silicon germanium (SiGe) having a germanium content in the range of 20% to 50% on an atomic basis.

3. The method as described in claim 2, wherein each nanosheet release layer comprises silicon germanium (SiGe) having a germanium content in the range of 10% to 30% on an atomic basis.

4. The method as described in claim 1, wherein the sacrificial layer has a thickness in the range of 15 nm to 90 nm.

5. The method as described in claim 1, wherein each of the first hGAA structure and the second hGAA structure has alternating layers of nanosheet channel layers and nanosheet release layers in the range of 1 to 5 pairs.

6. The method as described in claim 1, wherein the dopant comprises one or more of carbon (C) and boron (B).

7. The method as described in claim 6, wherein the silicon-germanium (SiGe) doped carbon (C) of each nanosheet release layer.

8. The method as described in claim 6, wherein the dopant has a concentration ranging from greater than 0% to less than or equal to 2% on an atomic basis.

9. The method as described in claim 1, wherein the etching rate is reduced by at least 2.

10. The method as described in claim 7, wherein the silicon-germanium (SiGe) of each nanosheet release layer is doped with carbon (C) to reduce strain in the vertically stacked superlattice structure and allow for higher growth temperatures and increased growth rates.

11. The method as described in claim 1, wherein the vertically stacked superlattice structure is fully strained and each nanosheet channel layer is substantially defect-free.

12. The method of claim 3, wherein the sacrificial layer comprises silicon germanium (SiGe) having a germanium content in the range of greater than 30% to 50% on an atomic basis, and wherein the nanosheet release layer comprises silicon germanium (SiGe) having a carbon concentration in the range of greater than 15% to 20% on an atomic basis and doped with carbon in the range of greater than 0% to less than or equal to 2% on an atomic basis.

13. The method as described in claim 1 further includes the step of selectively removing the sacrificial layer.

14. A semiconductor element, comprising: A vertically stacked superlattice structure is disposed on a substrate, the vertically stacked superlattice structure comprising: a first horizontal all-around gate (hGAA) structure disposed on the substrate; a sacrificial layer disposed on a top surface of the first hGAA structure, the sacrificial layer comprising silicon germanium (SiGe) having a germanium content in the range of greater than 0% to 50% on an atomic basis; and a second horizontal all-around gate (hGAA) structure disposed on a top surface of the sacrificial layer, wherein each of the first hGAA structure and the second hGAA structure comprises alternating layers of nanosheet channel layers and nanosheet release layers, the nanosheet channel layers comprising silicon (Si) and the nanosheet release layers comprising silicon germanium (SiGe) doped with dopants, and wherein each nanosheet release layer has a reduced etch rate compared to the sacrificial layer.

15. The semiconductor device as claimed in claim 14, wherein the dopant comprises one or more of carbon (C) and boron (B).

16. The semiconductor device as claimed in claim 15, wherein the silicon-germanium (SiGe) release layer of the nanosheet is doped with carbon (C).

17. The semiconductor device as claimed in claim 15, wherein the dopant has a concentration ranging from greater than 0% to less than or equal to 2% on an atomic basis.

18. The semiconductor device as claimed in claim 14, wherein the sacrificial layer comprises silicon germanium (SiGe) having a germanium content in the range of 20% to 50% on an atomic basis, and wherein the nanosheet release layer comprises silicon germanium (SiGe) having a carbon concentration in the range of 10% to 30% on an atomic basis and doped with a carbon concentration in the range of greater than 0% to less than or equal to 2% on an atomic basis.

19. The semiconductor device as claimed in claim 16, wherein the silicon-germanium (SiGe) of the nanosheet release layer is doped with carbon (C) to reduce strain in the vertically stacked superlattice structure and allow for higher growth temperatures and increased growth rates.

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