Wafer defect inspection system

Abstract

This invention discloses a wafer defect detection system, comprising a linear light source, a camera, and a processor. According to the design of this invention, the processor is coupled to the camera and the linear light source, thereby controlling the linear light source to provide detection light incident on the edge surface of a wafer. After incident on the wafer, the detection light travels inside the wafer according to the principle of total internal reflection, and when encountering a crack, a portion of the detection light passes through the crack and exits from the surface of the wafer. Furthermore, the processor controls the camera to acquire a wafer image containing at least one defect feature, and after processing the wafer image into a detection wafer image, compares the wafer image with a reference wafer image to confirm the at least one defect feature.

Description

Wafer Defect Detection System The present invention relates to the technical field of automated optical inspection (AOI), and particularly to a wafer defect detection system. Engineers familiar with the manufacturing of semiconductor integrated circuits (ICs) must be aware that dedicated IC foundries have four main manufacturing processes, namely etching, photolithography, diffusion, and thin film. In other words, during the process of manufacturing multiple IC chips on a wafer, these four manufacturing processes are repeatedly used until an electronic circuit containing multiple active components (i.e., transistors) and multiple passive components is realized in each IC chip. It is worth noting that after any one of the processes of etching, photolithography, diffusion, or thin film is completed, before the wafer is transferred to the next process, it must undergo defect inspection by an automated optical inspection (AOI) device. For example, Taiwan Patent No. I713130 discloses a system for on-line inspection of semiconductor wafers, which includes a conveyor, a camera, and a processor. The conveyor is used to transport a wafer from a processing station to an inspection station, so that the camera faces the wafer to capture at least one wafer image. The processor is used to process the wafer image to determine whether the wafer has surface defects. Such defects include, for example, line width not meeting the standard and / or particles that can be regarded as killer defects. Unfortunately, the conventional AOI still shows deficiencies in detecting wafer scratches. In view of this, the inventors of this case have made great efforts in research and creation, and finally developed a wafer defect detection system of a lead-free metal halide memristor according to the present invention. The first object of the present invention is to provide a wafer defect detection system for realizing the detection of scratches on a wafer by using the total reflection principle. To achieve the first object of the present invention described above, a first embodiment of the wafer defect detection system is proposed, which includes: a line light source disposed above the wafer; a camera disposed above the wafer and facing the wafer; and an electronic device coupled to the camera and the line light source; wherein the electronic device is configured to perform the following plurality of functions: controlling the line light source to provide a detection light to be incident on the surface of a wafer edge of a wafer, wherein an included angle θ between the detection light and the surface of the wafer ranges from 45° to 90°, such that the detection light travels inside the wafer according to the principle of total internal reflection after being incident on the wafer; wherein, in the case of encountering a crack, part of the detection light passes through the crack and exits from the surface of the wafer 2; controlling the camera to capture the wafer, so as to obtain a wafer image including at least one defect feature; wherein the detection light exits from a defect position on the surface of the wafer, and the defect feature corresponds to the defect position in the wafer image; and comparing the wafer image with a reference wafer image to identify the at least one defect feature. In one embodiment, the defect feature is a Wafer Scratch. In one embodiment, the wafer defect detection system of the present invention includes a Rod lens disposed between the line light source and the wafer and on an optical path of the detection light. In one embodiment, the camera is a Line scan camera. In one embodiment, the wafer defect detection system of the present invention further includes: a first adjustment mechanism connected to the camera and coupled to the electronic device; and a second adjustment mechanism pivotally connected to the line light source and coupled to the electronic device. In one embodiment, the wafer defect detection system of the present invention further includes: an optical device disposed between the line light source and the wafer and on the optical path of the detection light for guiding the detection light such that an included angle θ between the detection light and the surface of the wafer is formed; wherein the optical device is any one selected from the group consisting of a reflecting mirror and a polarizing mirror. In one embodiment, the wafer defect detection system of the present invention further includes: an optical device disposed between the line light source and the Rod lens and on the optical path of the detection light for guiding the detection light such that the detection light is perpendicularly incident on the Rod lens; wherein the optical device is any one selected from the group consisting of a reflecting mirror and a polarizing mirror. In one embodiment, the wafer is any one selected from the group consisting of a silicon wafer, a germanium wafer, a gallium arsenide wafer, and a gallium nitride wafer, and the wafer has a wafer size selected from the group consisting of 3 inches, 4 inches, 6 inches, 8 inches, 12 inches, and 18 inches. In one embodiment, the electronic device includes a processor and a memory storing an application program, enabling the processor to execute the application program by accessing the memory, thereby enabling the plurality of functions. In one embodiment, the application program includes: an image processing program, wherein the processor executes the image processing program and is configured to perform an image processing on the wafer image; a defect recognition program, wherein the processor executes the defect recognition program and is configured to compare the wafer image with the reference wafer image to identify the at least one defect feature; and a control program, wherein the processor executes the control program to control the first adjustment mechanism to adjust a horizontal position and a vertical position of the camera, and control the second adjustment mechanism to pivot the linear light source to adjust the included angle. The second object of the present invention is to provide a wafer defect detection system for detecting impurity particles and / or etching residues on the surface of a wafer by using the total reflection principle. To achieve the second object of the present invention, a second embodiment of the wafer defect detection system is proposed, which includes: a linear light source disposed above the wafer; a camera disposed above the wafer and facing the wafer; and an electronic device coupled to the camera and the linear light source; wherein the electronic device is configured to perform the following plurality of functions: controlling the linear light source to provide a detection light incident on the surface of an edge of the wafer, wherein the detection light has an included angle ranging from 45° to 90° with the surface of the wafer, so that the detection light travels inside the wafer according to the total reflection principle after being incident on the wafer, and a part of the detection light exits from the surface of the wafer; wherein, in the case where impurity particles and / or etching residues exist on the surface of the wafer, the detection light exiting from the surface of the wafer is blocked by the impurity particles and / or the etching residues; controlling the camera to capture the wafer to obtain a wafer image including at least one defect feature; wherein the detection light is blocked at a defect position on the surface of the wafer, and the defect feature corresponds to the defect position in the wafer image; comparing the wafer image with a reference wafer image to identify the at least one defect feature. In order to be able to more clearly describe a wafer defect detection system proposed by the present invention, the preferred embodiments of the present invention will be described in detail below in conjunction with the drawings. First Embodiment 1A, 1B and 1C show the first, second and third stereograms of a wafer defect detection system proposed by the present invention. 1A, 1B and 1C, a wafer transfer device 10 transfers a wafer 2 from a first process site to a second process site, and the wafer defect detection system 1 of the present invention is then disposed on a wafer transferring path located between the first process site and the second process site to achieve scratch detection using total reflection 2. In practical applications, the wafer 2 may be a silicon wafer, a zinc wafer, a gallium arsenide wafer, or a gallium nitride wafer. Further, the dimensions of the wafer 2 may be 3 inches, 4 inches, 6 inches, 8 inches, 12 inches, or 18 inches. In other words, the wafer defect detection system of the present invention can be applied to Scratch detection of any kind of wafer. It should be understood that the component symbol 3a refers to the wafer output device at the first process site, and the component symbol 3b is the wafer input device at the second process site. In more detail, the wafer defect detection system 1 of the present invention mainly includes: a line of light source 11 , a camera 12 , an electronic device 13 coupling the camera 12 and the line light source 11 , a first adjusting mechanism 15 , and a second adjusting mechanism 16 , wherein the camera 12 is a line scan camera (Line scan camera) and is provided above the line scan camera 12 . Furthermore, the camera 12 is also disposed above and facing the wafer 2 . In one embodiment, the electronic device 13 may be, but is not limited to, a desktop computer, a notebook computer, an industrial computer, a cloud computer, an all-in-one computer, a tablet, or a smartphone. Continuing to refer to FIGS. 1A, 1B, and 1C, and also referring to FIG. 2, which is a block diagram of the electronic device 13 in FIG. 1A. According to the design of the present invention, the electronic device includes a processor 13P and a memory 13M, where the memory 13M stores an application program, and the processor 13P executes the application program by accessing the memory 13M. When the application program is executed, the processor 13P is configured to perform a plurality of functions. The first function is: controlling the line light source 11 to provide a detection light incident on the surface of the edge of a wafer 2. It should be noted that the second function is: controlling the first adjustment mechanism 15 to adjust a horizontal position and a vertical position of the camera 12, and controlling the second adjustment mechanism 16 to pivot the line light source 11 so that an included angle θ between the detection light and the surface of the wafer 2 is between 45° and 90°. With such a setting, after the detection light is incident on the wafer 2, it travels inside the wafer 2 according to the total reflection principle. And, in the case of encountering a crack, part of the detection light exits from the surface of the wafer 2 through the crack. More specifically, if there is a Wafer Scratch on the wafer 2, then when the detection light traveling inside the wafer 2 according to the total reflection principle encounters a crack formed by the Wafer Scratch, part of the detection light will pass through the crack and exit from the surface of the wafer 2. FIG. 3 is a first side cross-sectional view of the wafer in FIG. 1A. As shown in FIGS. 2 and 3, the third of the plurality of functions is: controlling the camera 12 to capture the wafer 2, thereby obtaining a wafer image including at least one defect feature; wherein, the detection light exits from a defect position on the surface of the wafer 2, and the defect feature in the wafer image corresponds to the defect position. As shown in FIG. 1A, the first adjustment mechanism 15 is connected to the camera 12 and coupled to the processor 13, so that the camera 12 controls the first adjustment mechanism 15 to adjust a horizontal position and a vertical position of the camera 12, thereby obtaining a wafer image including at least one defect feature of the wafer at an optimal imaging position. In other words, the processor 13 can perform an analysis of the light intensity distribution of the wafer image to confirm whether the wafer image contains at least one defect feature. The fourth of the plurality of functions is: comparing the wafer image with a reference wafer image to identify the at least one defect feature. After completing the analysis of the light intensity distribution of the wafer image, a detected wafer image marked with the position of the defect feature can be generated. It should be understood that by comparing the detected wafer image with a reference wafer image, it is possible to identify and determine whether there is a Wafer Scratch on the wafer 2. As shown in FIG. 2, in one embodiment, the application program includes: an image processing program 13M1, a defect identification program 13M2, and a control program 13M3. Among them, the processor 13P executes the image processing program 13M1, and is thus configured to perform an image processing on the wafer image to obtain the detected wafer image. And, the processor 13P executes the defect identification program 13M2, and is thus configured to compare the detected wafer image with the reference wafer image to identify the at least one defect feature (i.e., wafer scratch). On the other hand, the processor 13P executes the control program 13M3 to control the first adjustment mechanism 15, the second adjustment mechanism 16, and / or the camera 12. FIG. 4 shows a second side cross-sectional view of the wafer 2 in FIG. 1A. As shown in FIGS. 1A and 4, when actually applying the wafer defect detection system 1 of the present invention, a rod lens 14 can be further disposed between the line light source 11 and the wafer 2 and located on an optical path of the detection light. With this setting, if the illuminance of the detection light emitted by the line light source 11 on the surface of the wafer 2 is 40 lux, after being focused by the rod lens 14, the illuminance of the detection light on the surface of the wafer 2 can be increased to 400 lux. FIG. 5 shows a third side cross-sectional view of the wafer 2 in FIG. 1A. As shown in FIGS. 1A and 4, when actually applying the wafer defect detection system 1 of the present invention, an optical device 17 can also be further disposed between the line light source 11 and the wafer 2 and located on an optical path of the detection light. With this setting, the optical device 17 can be used to guide the detection light to ensure that the included angle θ (i.e., 45° to 90°) exists between the detection light and the surface of the wafer 2. In a feasible embodiment, the optical device can be a reflecting mirror or a polarizing mirror. FIG. 6 shows a fourth side cross-sectional view of the wafer 2 in FIG. 1A. As shown in FIGS. 1A and 6, when actually applying the wafer defect detection system 1 of the present invention, an optical device 17 can also be further disposed between the line light source 11 and the wafer 2, a rod lens 14 can be disposed between the optical device 17 and the wafer 2, and both the rod lens 14 and the optical device 17 are located on an optical path of the detection light. With this setting, the optical device 17 can be used to guide the detection light to ensure that the included angle θ (i.e., 45° to 90°) exists between the detection light and the surface of the wafer 2. At the same time, the rod lens 14 can also be used to focus the detection light to the surface of the edge (wafer edge) of the wafer 2. Second Embodiment Please refer repeatedly to FIGS. 1A, 1B, 1C, and 2, and also refer to FIG. 7, which shows a fifth side sectional view of the wafer 2 in FIG. 1A. In the second embodiment, the wafer defect detection system 1 of the present invention is disposed on a wafer transferring path between a first process station and a second process station, and is used to detect impurity particles and / or etching residues on the surface of a wafer 2 by using the total reflection principle. Therefore, the second embodiment of the wafer defect detection system 1 of the present invention also includes: a linear light source 11, a camera 12, a processor 13 coupled to the camera 12 and the linear light source 11, a first adjustment mechanism 15, and a second adjustment mechanism 16. As shown in FIGS. 1A and 7, the processor 13 controls the linear light source 11 to provide a detection light to be incident on the surface of an edge of a wafer 2, such that an included angle θ between the detection light and the surface of the wafer 2 is in a range between 45° and 90°. After being incident on the wafer 2, the detection light travels inside the wafer 2 according to the total reflection principle. After being incident on the wafer 2, the detection light travels inside the wafer 2 according to the total reflection principle, and during the traveling process, a part of the detection light will exit from the surface of the wafer 2. It should be noted that if there are impurity particles and / or etching residues on the surface of the wafer 2, then the light exiting from the surface of the wafer 2 will surely be blocked by these substances. In other words, the camera 12 and the processor 13 can determine that there are impurity particles and / or etching residues on the surface of the wafer 2 by analyzing the intensity distribution of the exiting light. Therefore, as shown in FIGS. 1A and 7, the processor 13 controls the camera 12 to obtain a wafer image including at least one defect feature, and after processing the wafer image into a detection wafer image, compares the wafer image with a reference wafer image, so as to determine the at least one defect feature (i.e., impurity particles and / or etching residues). Thus, the above has completely and clearly described a wafer defect detection system of the present invention. It must be emphasized that the above detailed description is a specific description of the feasible embodiments of the present invention, but the embodiments are not used to limit the patent scope of the present invention. Any equivalent implementation or modification without departing from the technical spirit of the present invention should be included in the patent scope of this case. 1: Wafer defect detection system 10: Wafer transfer device 11: Linear light source 12: Camera 13: Electronic device 13P: Processor 13M: Memory 13M1: Image processing program 13M2: Defect recognition program 13M3: Control program 14: Cylindrical lens 15: First adjustment mechanism 16: Second adjustment mechanism 17: Optical device 2: Wafer FIG. 1A is a first perspective view of a wafer defect detection system of the present invention; FIG. 1B is a second perspective view of a wafer defect detection system of the present invention; FIG. 1C is a third perspective view of a wafer defect detection system of the present invention; FIG. 2 is a block diagram of the electronic device in FIG. 1A; FIG. 3 is a first side cross-sectional view of the wafer in FIG. 1A; FIG. 4 is a second side cross-sectional view of the wafer in FIG. 1A; FIG. 5 is a third side cross-sectional view of the wafer in FIG. 1A; FIG. 6 is a fourth side cross-sectional view of the wafer in FIG. 1A; and FIG. 7 is a fifth side cross-sectional view of the wafer in FIG. 1A. 11: Line light source 12: Camera 13: Electronic device 13P: Processor 13M: Memory 13M1: Image processing program 13M2: Defect recognition program 13M3: Control program 15: First adjustment mechanism 16: Second adjustment mechanism

Claims

1. A wafer defect detection system, comprising: A light source adjustment mechanism; A single light source, pivotally mounted on the light source adjustment mechanism, is used to provide a detection light; A camera is positioned above and facing a wafer; a cylindrical lens is positioned between the line light source and the wafer and is located in one of the optical paths of the detection light to enhance the illumination intensity of the detection light; an optical device is positioned between the line light source and the cylindrical lens and is configured to guide the detection light so that the detection light enters the cylindrical lens perpendicularly. The system also includes an electronic device coupled to the camera and the line light source, and further coupled to the light source adjustment mechanism; wherein the optical device is selected from a group consisting of a mirror and a polarizer; wherein the electronic device is configured to perform the following plurality of functions: controlling the line light source to provide detection light incident on an edge surface of the wafer; controlling the light source adjustment mechanism to pivot the line light source, thereby causing the detection light to travel inside the wafer according to the principle of total internal reflection; wherein when the detection light encounters a crack in the wafer, a portion of the detection light passes through the crack and exits from a surface of the wafer; controlling the camera to acquire a wafer image containing at least one defect feature; wherein the detection light exits from a defect location on the surface of the wafer, and the defect feature in the wafer image corresponds to the defect location; and comparing the wafer image with a reference wafer image to identify the at least one defect feature.

2. The wafer defect detection system as described in claim 1, wherein, The defect is characterized as a wafer scratch.

3. The wafer defect detection system as described in claim 1, wherein, This camera is a line scan camera.

4. The wafer defect detection system as described in claim 1 further includes: A camera adjustment mechanism is connected to the camera and coupled to the electronic device.

5. The wafer defect detection system as described in claim 1, wherein, The wafer is selected from any of the group consisting of silicon wafers, germanium wafers, gallium arsenide wafers, and gallium nitride wafers, and the wafer has any wafer size selected from the group consisting of 3 inches, 4 inches, 6 inches, 8 inches, 12 inches, and 18 inches.

6. The wafer defect detection system as described in claim 4, wherein, The electronic device includes a processor and a memory storing an application program, such that the processor executes the application program by accessing the memory, thereby enabling the plurality of functions.

7. The wafer defect detection system as described in claim 6, wherein, The application includes: an image processing program, wherein the processor executes the image processing program and is configured to perform image processing on the wafer image; a defect detection program, wherein the processor executes the defect detection program and is configured to compare the wafer image with the reference wafer image to identify the at least one defect feature; and a control program, wherein the processor executes the control program to control the camera adjustment mechanism to adjust a horizontal position and a vertical position of the camera, and to control the light source adjustment mechanism to pivot the line light source so that the detection light is incident on the surface of the wafer edge.

8. A wafer defect detection system, comprising: A light source adjustment mechanism; A single light source, pivotally mounted on the light source adjustment mechanism, is used to provide a detection light; A camera is positioned above and facing a wafer; a cylindrical lens is positioned between the line light source and the wafer and is located in one of the optical paths of the detection light to enhance the illumination intensity of the detection light; an optical device is positioned between the line light source and the cylindrical lens and is configured to guide the detection light so that the detection light enters the cylindrical lens perpendicularly. The device includes an electronic unit coupled to the camera and the line light source, and also coupled to the light source adjustment mechanism; wherein the optical unit is selected from a group consisting of a mirror and a polarizer; wherein the electronic unit is configured to perform the following plurality of functions: controlling the line light source to provide the detection light incident on one edge surface of the wafer; controlling the light source adjustment mechanism to pivot the line light source, thereby causing the detection light to travel inside the wafer according to the principle of total internal reflection, and a portion of the detection light to exit from one surface of the wafer; wherein, in the presence of impurity particles and / or etching residues on the surface of the wafer, the detection light exiting from the surface of the wafer will be blocked by the impurity particles and / or the etching residues; The camera is controlled to acquire a wafer image containing at least one defect feature from the wafer; wherein the detection light emitted from a defect location on the surface of the wafer is blocked, and the defect feature in the wafer image corresponds to the defect location; and the wafer image is compared with a reference wafer image to identify the at least one defect feature.

9. The wafer defect detection system as described in claim 8, wherein, This camera is a line scan camera.

10. The wafer defect detection system as described in claim 8 further includes: A camera adjustment mechanism is connected to the camera and coupled to the electronic device.

11. The wafer defect detection system as described in claim 8, wherein, The wafer is selected from any of the group consisting of silicon wafers, germanium wafers, gallium arsenide wafers, and gallium nitride wafers, and the wafer has any wafer size selected from the group consisting of 3 inches, 4 inches, 6 inches, 8 inches, 12 inches, and 18 inches.

12. The wafer defect detection system as described in claim 10, wherein, The electronic device includes a processor and a memory storing an application program, such that the processor executes the application program by accessing the memory, thereby enabling the plurality of functions.

13. The wafer defect detection system as described in claim 12, wherein, The application includes: an image processing program, wherein the processor executes the image processing program and is configured to perform image processing on the wafer image; a defect detection program, wherein the processor executes the defect detection program and is configured to compare the wafer image with the reference wafer image to identify the at least one defect feature; and a control program, wherein the processor executes the control program to control the camera adjustment mechanism to adjust a horizontal position and a vertical position of the camera, and to control the light source adjustment mechanism to pivot the line light source so that the detection light is incident on the surface of the wafer edge.

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