Semiconductor package and manufacturing method thereof

Abstract

The semiconductor package of the present invention includes: a first wafer having a top surface and a bottom surface opposite to each other; a plurality of first conductive blocks disposed on the top surface of the first wafer, the first conductive blocks being electrically connected to the first wafer; a molding layer covering the top surface of the first wafer and exposing the first conductive blocks; and a redistribution layer disposed on the molding layer and electrically connected to the first conductive blocks. The present invention further provides a method for manufacturing the above-described semiconductor package.

Description

Semiconductor Package and Method of Manufacturing the Same The present invention relates to a semiconductor package and a method of manufacturing the same, and more particularly to a semiconductor package including a redistribution layer and a method of manufacturing the same. In the conventional semiconductor package structure formed by flip chip technology, its thickness usually cannot meet the requirements of thinning, and for power components with fewer contact points, its manufacturing cost is relatively high. In view of this, the present invention provides a semiconductor package and a method of manufacturing the same, which use a wire bonding process to replace the ball mounting process to reduce costs, and use a redistribution process to reduce the overall thickness of the package. To achieve the above object, the semiconductor package of the present invention includes: a first chip having a top surface and a bottom surface opposite to each other; a plurality of first bonding pads disposed on the top surface of the first chip; a plurality of first conductive blocks respectively disposed on the first bonding pads, and the first conductive blocks are electrically connected to the first chip; a molding layer covering the top surface of the first chip and exposing the first conductive blocks; and a redistribution layer disposed on the molding layer and electrically connected to the first conductive blocks. The method of manufacturing the semiconductor package of the present invention includes: disposing a first chip on a carrier, wherein the first chip has a top surface and a bottom surface opposite to each other; forming a plurality of first conductive blocks on the top surface of the first chip by a wire bonding process, and the first conductive blocks are electrically connected to the first chip; forming a molding layer to cover the first conductive blocks and the first chip; grinding the molding layer to expose the first conductive blocks; forming a redistribution layer on the molding layer to be electrically connected to the first conductive blocks; and removing the carrier. According to the semiconductor package of the present invention, a wire bonding process is used to replace the ball mounting process to reduce costs, and a redistribution process is used to reduce the overall thickness of the package to less than 0.15 mm. In order to make the above and other objects, features, and advantages of the present invention more obvious, the embodiments of the present invention are hereinafter specifically described in detail in conjunction with the accompanying drawings. The following disclosure provides many different embodiments or examples for implementing different features of the present disclosure. Specific examples of components and configurations are described below to simplify the present disclosure. Of course, these components and configurations are only examples and are not intended to be restrictive. For example, in the following description, the formation of a first component above or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component such that the first component and the second component are not in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in various examples. This repetition is for the purpose of simplicity and clarity and does not itself indicate the relationship between the various embodiments and / or configurations discussed. In addition, for ease of description, spatial relative terms such as "underlying", "below", "lower", "overlying", "upper", and the like may be used herein to describe the relationship of one element or component to another or other elements or components as illustrated in the figures. Except for the orientation depicted in the figures, the spatial relative terms are intended to encompass different orientations of the device during use or operation. The device may be oriented otherwise (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly. Referring to FIG. 1, the semiconductor package of the present invention includes one or more wafers, for example, including a first wafer 110 and a second wafer 120, wherein the first wafer 110 and the second wafer 120 are arranged in parallel. The first wafer 110 has a first surface 111, a second surface 112, and a plurality of third surfaces 113 that are opposite to each other, wherein the first surface 111 is the active surface. The first surface 111 and the second surface 112 are located in different planes, and the third surfaces 113 connect the first surface 111 and the second surface 112. A plurality of first bonding pads 114 are formed on the first surface 111. In one embodiment, the first surface 111 is the top surface, the second surface 112 is the bottom surface, and the third surfaces 113 are the side surfaces, but the present invention is not limited thereto. The second wafer 120 has a first surface 121, a second surface 122, and a plurality of third surfaces 123 that are opposite to each other, wherein the first surface 121 is the active surface. The first surface 121 and the second surface 122 are located in different planes, and the third surfaces 123 connect the first surface 121 and the second surface 122. A plurality of second bonding pads 124 are formed on the first surface 121. In one embodiment, the first surface 121 is the top surface, the second surface 122 is the bottom surface, and the third surfaces 123 are the side surfaces, but the present invention is not limited thereto. A plurality of first conductive blocks 131 are respectively disposed on the first bonding pads 114 of the first surface 111 of the first wafer 110, and they are electrically connected to the first wafer 110 through the first bonding pads 114; a plurality of second conductive blocks 132 are respectively disposed on the second bonding pads 124 of the first surface 121 of the second wafer 120, and they are electrically connected to the second wafer 120 through the second bonding pads 124. The first conductive blocks 131 and the second conductive blocks 132 are made of a conductive material, for example, can be made of gold, copper, or an alloy. In the present invention, the first conductive blocks 131 and the second conductive blocks 132 can be bonded and formed on the first bonding pads 114 of the first wafer 110 and the second bonding pads 124 of the second wafer 120 by means of a wire bonding process using gold wires, copper wires, alloy wires, or other conductive wires. The semiconductor package of the present invention further includes a molding layer 170, which is made of a potting material, such as composed of an epoxy resin material, but not limited thereto. The molding layer 170 has a first surface 171 and a second surface 172 that are opposite to each other, and the first surface 171 and the second surface 172 are located in different planes. For example, the first surface 171 is the top surface and the second surface 172 is the bottom surface. The molding layer 170 is formed on the first surface 111 of the first wafer 110 and the first surface 121 of the second wafer 120, and covers the third surfaces 113 of the first wafer 110 and the third surfaces 123 of the second wafer 120. The molding layer 170 is not formed on the second surface 112 of the first wafer 110 and the second surface 122 of the second wafer 120, and does not completely cover the first conductive blocks 131 and the second conductive blocks 132. Each of the first conductive blocks 131 and the second conductive blocks 132 has a part exposed from the molding layer 170. Therefore, the first surface 171 of the molding layer 170 is located above the first surface 111 of the first wafer 110 and the first surface 121 of the second wafer 120, and the second surface 172 of the molding layer 170 is flush with the second surface 112 of the first wafer 110 and the second surface 122 of the second wafer 120. A redistribution layer (RDL) 140 is formed on the first surface 171 of the molding layer 170, and conductive circuits are disposed therein. The redistribution layer 140 extends from above the first surface 111 of the first wafer 110 to above the first surface 121 of the second wafer 120, and contacts the first conductive blocks 131 and the second conductive blocks 132 for electrical connection. The first wafer 110 is electrically connected to the second wafer 120 through the redistribution layer 140. A plurality of solder balls 150 are provided on the redistribution layer 140, and the solder balls 150 are electrically connected to the redistribution layer 140. The first wafer 110 and the second wafer 120 can be electrically connected to an external circuit through the redistribution layer 140 using the solder balls 150. Please refer to FIGS. 2 to 10, which show the manufacturing method of the semiconductor package shown in FIG. 1. As shown in FIG. 2, a carrier 190 is prepared, which can be composed of a silicon wafer, glass, metal, or other high-temperature resistant materials. As shown in FIG. 3, then a demolding material layer 180 is formed on the carrier 190 by coating or adhesion. The demolding material layer 180 is viscous and can be demolded. As shown in FIG. 4, then one or more wafers, such as a first wafer 110 and a second wafer 120, are adhered to the carrier 190 using the demolding material layer 180, wherein the first wafer 110 and the second wafer 120 are arranged in parallel. The first chip 110 has a relative first surface 111, a second surface 112 and a plurality of third surfaces 113, wherein the first surface 111 is the active surface, and the second surface 112 is adhered to the carrier 190. The first surface 111 and the second surface 112 are located in different planes, and the third surfaces 113 connect the first surface 111 and the second surface 112. A plurality of first bonding pads 114 are formed on the first surface 111. In an embodiment, the first surface 111 is the top surface, the second surface 112 is the bottom surface, and the third surfaces 113 are the side surfaces, but the present invention is not limited thereto. The second chip 120 has a relative first surface 121, a second surface 122 and a plurality of third surfaces 123, wherein the first surface 121 is the active surface, and the second surface 122 is adhered to the carrier 190. The first surface 121 and the second surface 122 are located in different planes, and the third surfaces 123 connect the first surface 121 and the second surface 122. A plurality of second bonding pads 124 are formed on the first surface 121. In an embodiment, the first surface 121 is the top surface, the second surface 122 is the bottom surface, and the third surfaces 123 are the side surfaces, but the present invention is not limited thereto. As shown in FIG. 5, a plurality of first conductive blocks 131 are then disposed on the first bonding pads 114 of the first surface 111 of the first chip 110; a plurality of second conductive blocks 132 are disposed on the second bonding pads 124 of the first surface 121 of the second chip 120. The first conductive blocks 131 are electrically connected to the first chip 110 through the first bonding pads 114; the second conductive blocks 132 are electrically connected to the second chip 120 through the second bonding pads 124. The first conductive blocks 131 and the second conductive blocks 132 are made of a conductive material, for example, can be made of gold, copper or an alloy. In the present invention, the first conductive blocks 131 and the second conductive blocks 132 can be bonded and formed on the first bonding pads 114 of the first chip 110 and the second bonding pads 124 of the second chip 120 by using gold wires, copper wires, alloy wires or other wire materials that can conduct electricity through a wire bonding process. As shown in FIG. 6, a molding layer 170 covering the first conductive blocks 131 and the second conductive blocks 132 is then formed on the carrier 190 using an encapsulant material, such as an epoxy resin material. The molding layer 170 has a first surface 171 and a second surface 172 opposite to each other, and the first surface 171 and the second surface 172 are located in different planes. For example, the first surface 171 is the top surface and the second surface 172 is the bottom surface. The molding layer 170 also covers the first surface 111 of the first wafer 110 and the first surface 121 of the second wafer 120, and covers the third surfaces 113 of the first wafer 110 and the third surfaces 123 of the second wafer 120. Due to being shielded by the carrier 190, the molding layer 170 is not formed on the second surface 112 of the first wafer 110 and the second surface 122 of the second wafer 120, and the second surface 172 of the molding layer 170 is flush with the second surface 112 of the first wafer 110 and the second surface 122 of the second wafer 120. As shown in FIG. 7, the first surface 171 of the molding layer 170 is then polished to reduce the thickness of the molding layer 170, exposing the tops of the first conductive blocks 131 and the second conductive blocks 132. As shown in FIG. 8, a redistribution line layer 140 is then formed on the first surface 171 of the molding layer 170 through a redistribution process. Conductive lines are arranged in the redistribution line layer 140, which extend from above the first surface 111 of the first wafer 110 to above the first surface 121 of the second wafer 120 and are in contact with the first conductive blocks 131 and the second conductive blocks 132 for electrical connection. The first wafer 110 is electrically connected to the second wafer 120 through the redistribution line layer 140. As shown in FIG. 9, the first conductive blocks 131 and the second conductive blocks 132 then generate pin contacts for electrical connection with the outside through a redistribution process, and then the carrier 190 is removed. As shown in FIG. 10, the molding layer 170 is then divided, and a plurality of solder balls 150 electrically connected to the redistribution line layer 140 are provided on the redistribution line layer 140 to form a plurality of semiconductor packages as shown in FIG. 1. For the semiconductor package according to the present invention, a wire bonding process is used to replace the ball mounting process to reduce costs, and a redistribution process is used to reduce the thickness of the overall package to less than 0.15 mm. Although the present invention has been disclosed in the foregoing embodiments, it is not intended to limit the present invention. Any person with ordinary knowledge in the technical field to which the present invention pertains can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the appended patent application. 110: First chip 111: First surface 112: Second surface 113: Third surface 114: First pad 120: Second chip 121: First surface 122: Second surface 123: Third surface 124: Second pad 131: First conductive block 132: Second conductive block 140: Redistribution layer 150: Solder ball 170: Molding layer 171: First surface 172: Second surface 180: Demolding material layer 190: Carrier board As will be best understood when read in conjunction with the accompanying drawings, aspects of the present disclosure are best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, various components are not drawn to scale. In fact, for clarity of discussion, the dimensions of various components may be arbitrarily increased or decreased. FIG. 1 is a schematic diagram of a semiconductor package of the present invention. FIGS. 2 to 10 show the manufacturing method of the semiconductor package shown in FIG. 1. 110: First chip 111: First surface 112: Second surface 113: Third surface 114: First pad 120: Second chip 121: First surface 122: Second surface 123: Third surface 124: Second pad 131: First conductive block 132: Second conductive block 140: Redistribution layer 150: Solder ball 170: Molding layer 171: First surface 172: Second surface

Claims

1. A method for manufacturing a semiconductor package, comprising: disposing a first wafer on a carrier substrate, wherein the first wafer has a top surface and a bottom surface opposite to each other; forming a plurality of first conductive blocks on the top surface of the first wafer by a wire bonding process, wherein the first conductive blocks are spherical and electrically connected to the first wafer; forming a molding layer to cover the first conductive blocks and the first wafer; grinding the molding layer to expose the first conductive blocks; forming a redistribution layer on the molding layer to electrically connect to the first conductive blocks; and removing the carrier substrate.

2. The method for manufacturing a semiconductor package as claimed in claim 1 further includes: disposing a second wafer on the carrier; forming a plurality of second conductive blocks on the second wafer by a wire bonding process, wherein the second conductive blocks are electrically connected to the second wafer; covering the second conductive blocks and the second wafer with a molding layer; exposing the second conductive blocks from the molding layer; and electrically connecting the redistribution layer to the second conductive blocks.

3. The method for manufacturing a semiconductor package as described in claim 1 or 2, wherein, These first conductive blocks are formed from one of gold wire, copper wire, and alloy wire.

4. The method for manufacturing a semiconductor package as described in claim 1 or 2, wherein, The molding layer has a bottom surface that is flush with the bottom surface of the first wafer.

5. The method of manufacturing a semiconductor package as claimed in claim 1 or 2 further includes: after the redistribution layer is formed, a plurality of solder balls electrically connected thereto are disposed on the redistribution layer.

6. The method for manufacturing the semiconductor package as described in claim 2, wherein, The first chip and the second chip are arranged side by side.

7. A semiconductor package made by any one of claims 1 to 6.

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