Semiconductor devices and methods of manufacture

Abstract

This paper presents a semiconductor device and a method for manufacturing the same. The method includes bonding a first semiconductor die to a first side of a first semiconductor device, the first semiconductor device including a first region having an active circuit system and a second region having an active circuit system, the second region having an active circuit system being electrically isolated from the first region having an active circuit system; bonding a second semiconductor die to the first side of the first semiconductor device and adjacent to the first semiconductor die; bonding a local interconnect die to the first side of the first semiconductor device and between the first and second semiconductor dies; wherein the local interconnect die electrically connects the first region having an active circuit system to the second region having an active circuit system; and forming a redistribution circuit structure on a second side of the first semiconductor device opposite to the first side of the first semiconductor device, wherein forming the redistribution circuit structure includes forming a plurality of dielectric layers on the second side of the first semiconductor device opposite to the first side, and forming a plurality of metallization layers within the plurality of dielectric layers.

Description

Prior Art

[0001] The semiconductor industry has experienced rapid growth due to continuous improvements in the integration density of various electronic components (such as transistors, diodes, resistors, and capacitors). This improvement in integration density is largely due to the repeated reduction in minimum feature size (for example, shrinking semiconductor process nodes to nodes below 20nm), which allows more components to be integrated into a given area. With the recent growing demand for miniaturization, higher speeds and bandwidth, as well as lower power consumption and latency, the demand for smaller and more innovative semiconductor chip packaging technologies has also continued to grow.

[0002] With further advancements in semiconductor technology, stacked and bonded semiconductor devices have become an effective alternative for further reducing the physical size of semiconductor devices. In stacked semiconductor devices, active circuitry such as logic, memory, and processor circuits is at least partially fabricated on separate substrates and then physically and electrically bonded together to form a functional component. This bonding process utilizes complex techniques and is in need of improvement. Simple diagram description

[0003] The various aspects of the present disclosure will be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with standard industry practice, various features are not drawn to scale. In fact, the dimensions of various features may be arbitrarily increased or reduced for clarity of discussion. 1 to 8 illustrate a semiconductor wafer according to some embodiments, wherein semiconductor devices are attached to the semiconductor wafer to form a first semiconductor package. FIG. 9 illustrates a top-down cross-sectional view of a first semiconductor package in accordance with some embodiments. 10 to 18 illustrate forming a second semiconductor package using a first local interconnect process according to some embodiments. FIG. 19 illustrates a top-down cross-sectional view of a second semiconductor package in accordance with some embodiments. 20 to 30 illustrate forming a third semiconductor package using a second local interconnect process according to some embodiments. FIG. 31 illustrates a top-down cross-sectional view of a third semiconductor package in accordance with some embodiments. FIG. 32A illustrates a first semiconductor package having a through substrate via guard ring and a deep trench capacitor in accordance with some embodiments. 32B illustrates a top-down cross-sectional view of a through substrate via guard ring surrounding a through substrate via, in accordance with some embodiments. Implementation Method

[0004] The following disclosure provides numerous different embodiments or examples for implementing various features of the present invention. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature being formed over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature may be formed between the first and second features, thereby eliminating direct contact between the first and second features. Furthermore, the present disclosure may reuse reference numbers and / or letters in various examples. This repetition is for the sake of brevity and clarity and does not inherently indicate a relationship between the various embodiments and / or configurations discussed.

[0005] Furthermore, for ease of description, spatially relative terms, such as "beneath," "below," "lower," "above," "upper," and similar terms, may be used herein to describe the relationship of one element or feature to another element or feature as illustrated in the figures. These spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0006] Embodiments for bonding various device wafers or semiconductor devices using a front-side to front-side orientation (sometimes referred to as face-to-face bonding) are described below. This front-side to front-side orientation allows for the formation of backside redistribution structures in conjunction with local interconnect structures, providing additional connection paths between active circuitry. This sequence of steps and the resulting structural arrangement provide improved processes and structures that help reduce or eliminate the potential for dielectric delamination.

[0007] Referring now to FIG. 1 , a semiconductor wafer 100 is shown, wherein a plurality of first semiconductor device regions 101 are formed and located on the semiconductor wafer 100. In a particular embodiment, the first semiconductor device regions 101 may be memory devices, such as wide I / O dynamic random access memory (DRAM) devices having a large number of I / O interfaces, for example, greater than 256 interfaces, thereby enabling large data bandwidth even at low clock speeds. However, the first semiconductor device regions 101 may also be any other suitable type of memory device with a high data transfer rate (such as an LPDDRn memory device or the like), or any other suitable device (such as a logic die, a central processing unit (CPU) die, an input / output (I / O) die, or a combination thereof). Furthermore, the semiconductor wafer 100 may be received by the manufacturer from a third-party manufacturer or may be manufactured in-house.

[0008] In one embodiment, the first semiconductor device region 101 may include a first substrate 103, a plurality of first active devices 107, and a plurality of first metallization layers 105. The first substrate 103 may include a doped or undoped bulk silicon material or an active layer of a silicon-on-insulator (SOI) substrate. Generally, an SOI substrate includes a layer of semiconductor material, such as silicon, germanium, silicon germanium, SOI, silicon germanium on insulator (SGOI), or a combination thereof. Other substrates that may be used include multi-layered substrates, gradient substrates, or hybrid orientation substrates.

[0009] The first active device 107 includes a variety of active and passive devices, such as capacitors, resistors, inductors, and the like, which can be used to produce the desired structural and functional requirements of the design of the first semiconductor device region 101. The first active device 107 can be formed on or within the first substrate 103 using any suitable method.

[0010] A first metallization layer 105 is formed over the first substrate 103 and the first active device 107 to connect the active devices to form a functional circuit system. In one embodiment, the first metallization layer 105 is formed from a plurality of first alternating layers of a dielectric material 153 (e.g., a low-k dielectric material, an extremely low-k dielectric material, an ultra-low-k dielectric material, combinations thereof, or the like) and a plurality of first conductive structures 155 (e.g., a plurality of conductive lines and a plurality of vias). In one embodiment, the first metallization layer 105 can be formed by any suitable process (e.g., deposition, damascene, dual damascene, etc.). In one embodiment, there can be at least four metallization layers separated from the first substrate 103 by at least one interlayer dielectric layer (ILD), although the exact number of first metallization layers 105 depends on the design of the first semiconductor device region 101.

[0011] A plurality of through substrate vias (TSVs) 111 can be formed in the first substrate 103 and, if desired, in one or more of the first metallization layers 105 to provide electrical connectivity from the front side of the first substrate 103 to the back side of the first substrate 103. In one embodiment, the first substrate vias 111 can be formed by initially forming a plurality of through-silicon via (TSV) openings in the first substrate 103 and, if desired, any overlying first metallization layer 105 (e.g., after the desired first metallization layer 105 has been formed but before forming the next overlying first metallization layer 105). The TSV openings can be formed by applying and developing an appropriate photoresist and removing a portion of the exposed underlying material to a desired depth. The TSV openings can be formed to extend into the first substrate 103 to a depth greater than the final desired height of the first substrate 103. Thus, while the depth depends on the overall design, it may be between about 20 μm and about 200 μm, for example a depth of about 50 μm.

[0012] After the TSV openings have been formed in the first substrate 103 and / or any first metallization layer 105, the TSV openings can be lined with a liner. The liner can be, for example, an oxide or silicon nitride formed from tetraethylorthosilicate (TEOS), although any suitable dielectric material can be used. The liner can be formed using a plasma enhanced chemical vapor deposition (PECVD) process, although other suitable processes, such as physical vapor deposition (PVD) or thermal processes, can also be used. Furthermore, the liner can be formed to a thickness between approximately 0.1 μm and approximately 5 μm, for example, approximately 1 μm.

[0013] After forming a liner along the sidewalls and bottom of the TSV opening, a barrier layer can be formed, and the remaining portion of the TSV opening can be filled with a first conductive material. The first conductive material can include copper, but other suitable materials such as aluminum alloys, doped polysilicon, combinations thereof, and the like can also be used. The first conductive material can be formed by electroplating copper onto the seed layer, filling and overfilling the TSV opening. After the TSV opening has been filled, excess liner, barrier layer, seed layer, and first conductive material outside the TSV opening can be removed by a planarization process such as chemical mechanical polishing (CMP), but any suitable removal process can be used.

[0014] In some embodiments, one or more seal rings 175 are located around the perimeter of each of the first semiconductor device regions 101. Each seal ring 175 may be a loop (see, for example, FIG. 9 ) that surrounds the functional metallization pattern (e.g., circuitry) in each first semiconductor device region 101. In one embodiment, the seal ring 175 may further serve as a boundary region, so that the semiconductor wafer 100 may not include any functional circuitry outside of the seal ring 175. For example, the functional circuitry in each first semiconductor device region 101 may be electrically isolated from one another.

[0015] Additionally, multiple intermediate regions 102 are disposed between adjacent first semiconductor device regions 101, such as between adjacent seal rings 175. In one embodiment, the intermediate regions 102 may not contain active circuitry, although some structures (such as test structures) may be formed within the intermediate regions 102. In some embodiments, some of the intermediate regions 102 may serve as scribe lines and subsequently undergo a singulation process, while other intermediate regions 102, other than those serving as scribe lines, remain intact in the singulated die. Furthermore, in one embodiment, the intermediate regions 102 may be defined by forming multiple seal rings 175. In one embodiment, the multiple seal rings 175 are formed within multiple first semiconductor device regions 101.

[0016] A plurality of first metallization layer via openings 151 may be formed on the front side of the first metallization layer 105 in preparation for fabricating a plurality of first metallization layer vias 201 (not shown in FIG. 1 , but shown in FIG. 2 ). In one embodiment, the first metallization layer via openings 151 may be formed by first applying and patterning a photoresist on the front side of the first metallization layer 105. The photoresist is then used to etch the dielectric material 153 in the first alternating layers to form the first metallization layer via openings 151. The dielectric material 153 in the first alternating layers may be etched using dry etching (e.g., reactive ion etching (RIE) or neutral beam etching (NBE)), wet etching, or the like. According to some embodiments of the present disclosure, the etching stops on the first conductive structure 155 of the first metallization layer 105, such that the first conductive structure 155 of the first metallization layer 105 is exposed through the first metallization layer via openings 151 in the first metallization layer 105.

[0017] Referring now to FIG. 2 , the first metallization layer via openings 151 may be filled to form a plurality of first metallization layer vias 201, and a first wafer bonding layer 209 may be formed over the first metallization layer 105 on the first substrate 103. In some embodiments, after exposing the first conductive structures 155 of the first metallization layer 105, the first metallization layer vias 201 may be formed to physically and electrically contact the first conductive structures 155 in the first metallization layer 105. In some embodiments, the first metallization layer vias 201 may include a barrier layer, a seed layer, a fill metal, or a combination thereof (not separately shown). For example, the barrier layer may be a blanket layer deposited over the first metallization layer 105. The barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The seed layer can be a conductive material (e.g., copper) and, depending on the desired material, can be a blanket layer deposited over the barrier layer using processes such as sputtering, evaporation, plasma-enhanced chemical vapor deposition (PECVD), or the like. The filler metal can be a conductor such as copper or a copper alloy and can be deposited over the seed layer using a plating process such as electrical plating or electroless plating to fill or overfill the opening. After the filler metal has been deposited, excess material in the filler metal, seed layer, and barrier layer can be removed from the outside of the opening using a planarization process such as chemical mechanical polishing.

[0018] In one embodiment, the first wafer bonding layer 209 can be used for hybrid bonding (also known as dielectric-to-dielectric and metal-to-metal bonding) or fusion bonding (also known as oxide-to-oxide bonding). According to some embodiments, the first wafer bonding layer 209 is formed of a dielectric material containing silicon, such as silicon oxide, silicon nitride, or the like. The first wafer bonding layer 209 can be deposited to a thickness between approximately 1 nm and approximately 1000 nm (e.g., approximately 5 nm) using any suitable method, such as atomic layer deposition (ALD), CVD, high-density plasma chemical vapor deposition (HDP-CVD), PVD, or the like. However, any suitable material, process, and thickness may be utilized.

[0019] After forming the first wafer bonding layer 209, a plurality of bond openings for preparing the first conductive bond pads 207 can be formed within the first wafer bonding layer 209. In one embodiment, the bond openings can be formed by first applying and patterning a photoresist on the top surface of the first wafer bonding layer 209. The photoresist is then used to etch the first wafer bonding layer 209 to form the bond openings. The first wafer bonding layer 209 can be etched using dry etching (e.g., reactive ion etching (RIE) or neutral beam etching (NBE)), wet etching, or the like. According to some embodiments of the present disclosure, the etching stops above the first metallization layer vias 201 in the first metallization layer 105, exposing the first metallization layer 105 through the bond openings in the first wafer bonding layer 209.

[0020] After the first metallization layer via 201 is exposed, a first conductive bonding pad 207 can be formed to physically and electrically contact the first metallization layer via 201. In one embodiment, the first conductive bonding pad 207 can include an optional barrier layer, an optional seed layer, a filler metal, or a combination thereof (not separately shown). For example, the optional barrier layer can be a blanket layer deposited over the first metallization layer 105. The optional barrier layer can include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The optional seed layer can be a conductive material such as copper and can be a blanket layer deposited over the optional barrier layer using a process such as sputtering, evaporation, plasma-enhanced chemical vapor deposition (PECVD), or the like, depending on the desired material. The filler metal can be a conductor such as copper or a copper alloy and can be deposited over the optional seed layer to fill or overfill the bonding opening via a plating process such as electroplating or electroless plating. After the filler metal has been deposited, excess material of the filler metal, optional seed layer, and optional barrier layer can be removed from the exterior of the bond opening by a planarization process (e.g., chemical mechanical polishing). Although a single damascene process has been described for forming the first conductive bond pad 207 and the first metallization layer through-hole 201, any suitable method, such as a dual damascene process, may be used.

[0021] However, the above-described embodiment (in which the first wafer bonding layer 209 is formed and patterned, and the first conductive bonding pads 207 are electroplated within the bonding openings prior to planarization) is intended to be illustrative and not limiting. Rather, the first wafer bonding layer 209 and the first conductive bonding pads 207 may be formed using any suitable method. In other embodiments, the first conductive bonding pads 207 may be formed using, for example, a photolithographic patterning and plating process, followed by gap-filling the area surrounding the first conductive bonding pads 207 with a dielectric material, and then planarizing the area using a planarization process. Any such manufacturing process is fully intended to be within the scope of the embodiments.

[0022] 3 , a first semiconductor die 313, a second semiconductor die 315, and a first local interconnect die 350 are bonded to the first conductive bond pad 207 and the first wafer bonding layer 209. In one embodiment, each of the first semiconductor die 313 and the second semiconductor die 315 can be a system-on-a-chip device, such as a logic device, designed to operate in conjunction with the first semiconductor device region 101 (e.g., a wide I / O DRAM device). However, the first semiconductor die 313 and the second semiconductor die 315 can utilize any suitable functionality, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination thereof, or the like.

[0023] In one embodiment, the first semiconductor die 313 and the second semiconductor die 315 can each include a second substrate 317, a second active device 301, a second metallization layer 319, a plurality of second metallization layer vias 307, a second wafer bonding layer 321, and a plurality of second conductive bonding pads 323. In one embodiment, the second metallization layer 319 includes a plurality of second conductive structures 305 and a plurality of second alternating layers of dielectric 303. In one embodiment, the second substrate 317, the second active device 301, the second metallization layer 319, the second metallization layer vias 307, the second wafer bonding layer 321, and the second conductive bonding pads 323 can be similar to the first substrate 103, the first active device 107, the first metallization layer 105, the first metallization layer vias 201, the first wafer bonding layer 209, and the first conductive bonding pads 207 described above, respectively. However, in other embodiments, these structures can be formed using different processes and different materials.

[0024] After preparing the first semiconductor die 313 and the second semiconductor die 315, they are bonded to the first semiconductor device region 101 using, for example, metal-to-metal and oxide-to-oxide bonding. In one embodiment, the surface of the first semiconductor device region 101 (e.g., the first wafer bonding layer 209 and the first conductive bonding pad 207) and the surfaces of the first semiconductor die 313 and the second semiconductor die 315 (e.g., the second wafer bonding layer 321 and the second conductive bonding pad 323) may be activated. By way of example, activation of the top surfaces of the first semiconductor device region 101, the first semiconductor die 313, and the second semiconductor die 315 may include dry processing, wet processing, plasma processing, exposure to an inert gas plasma, exposure to H₂, exposure to N₂, exposure to O₂, or a combination thereof. In embodiments using wet processing, for example, RCA cleaning may be used. In other embodiments, the activation process may include other types of processing. The activation process assists hybrid bonding of the first semiconductor device region 101 , the first semiconductor die 313 , and the second semiconductor die 315 .

[0025] After the activation process, the first semiconductor die 313 and the second semiconductor die 315 can be placed together in contact with the first semiconductor device region 101. In certain embodiments utilizing metal-to-metal and oxide-to-oxide bonding, the first conductive bonding pad 207 and the second conductive bonding pad 323 are placed in physical contact, while the first wafer bonding layer 209 and the second wafer bonding layer 321 are placed in physical contact. As the activation process chemically modifies the surfaces, the bonding process between the materials begins with physical contact.

[0026] After the physical contact initiates the bonding process, the bond can be strengthened by thermally treating the components. In one embodiment, the first semiconductor device region 101, the first semiconductor die 313, and the second semiconductor die 315 can be subjected to a temperature between approximately 200°C and approximately 400°C to strengthen the bond between the first wafer bonding layer 209 and the second wafer bonding layer 321. The first semiconductor device region 101, the first semiconductor die 313, and the second semiconductor die 315 can then be subjected to a temperature at or above the eutectic point of the materials of the first conductive bonding pad 207 and the second conductive bonding pad 323. In this manner, the first semiconductor device region 101, the first semiconductor die 313, and the second semiconductor die 315 fuse to form a hybrid-bonded device.

[0027] Additionally, while specific processes have been described to initiate and strengthen metal-to-metal and oxide-to-oxide bonding between the first semiconductor device region 101, the first semiconductor die 313, and the second semiconductor die 315, these descriptions are intended to be illustrative and not limiting of the embodiments. Rather, baking, annealing, pressing, or other bonding processes, or any suitable bonding processes or combinations thereof, may be utilized. All such processes are fully intended to be within the scope of the embodiments.

[0028] Additionally, while metal-to-metal and oxide-to-oxide bonding have been described as one method of bonding the first semiconductor device region 101 to the first semiconductor die 313 and the second semiconductor die 315, this is for illustrative purposes only and is not intended to limit the embodiments. Rather, any suitable bonding method, such as solder bonding using a ball grid array, may be utilized. Any suitable method of bonding the first semiconductor device region 101 to the first semiconductor die 313 and the second semiconductor die 315 may be utilized.

[0029] Furthermore, in one embodiment, the first local interconnect die 350 (sometimes referred to as a local silicon interconnect (LSI) or silicon bridge) includes a first interconnect substrate 351 supporting a first interconnect structure 353. The first interconnect structure 353 includes a plurality of first interconnect metallization patterns 355 (e.g., conductive lines, vias, and conductive pads) disposed within one or more first interconnect dielectric layers 357. The first interconnect metallization patterns 355 and the first interconnect dielectric layers 357 can be formed in a manner and from similar materials as discussed with respect to the first conductive structures 155 and the dielectric material 153 in the first alternating layers of the first metallization layer 105, respectively. In one embodiment, the first interconnect substrate 351 can be formed of silicon, such as bulk silicon. In one embodiment, the first interconnect substrate 351 can be formed in a similar manner and made of a similar material as the first substrate 103 .

[0030] In one embodiment, multiple first interconnect conductive pads 375 in the first interconnect metallization pattern 355 together with one of the first interconnect dielectric layers 357 can be used to bond the first local interconnect die 350 to the first wafer bonding layer 209 in a manner similar to the above-described bonding of the second wafer bonding layer 321 and the second conductive bonding pad 323 to the first wafer bonding layer 209 and the first conductive bonding pad 207, respectively.

[0031] In one embodiment, the first local interconnect die 350 electrically couples functional metallization patterns between respective first semiconductor device regions 101. Furthermore, in one embodiment, the first semiconductor die 313 is electrically coupled to the functional metallization patterns of one of the plurality of first semiconductor device regions 101, and the second semiconductor die 315 is electrically coupled to the functional metallization patterns of another of the plurality of first semiconductor device regions 101. In one embodiment, the first semiconductor die 313 can be electrically coupled to the second semiconductor die 315 by electrically coupling the first semiconductor device regions 101 electrically coupled to the first semiconductor die 313 and the second semiconductor die 315, respectively, via the first local interconnect die 350.

[0032] Referring to FIG. 4 , the first semiconductor die 313, the second semiconductor die 315, the first local interconnect die 350, and the first semiconductor device region 101 may be encapsulated by a first encapsulant 401. In one embodiment, the encapsulation may be performed in a molding device that may include a top molding portion and a bottom molding portion that is separable from the top molding portion. When the top molding portion is lowered to adjacent the bottom molding portion, a molding cavity is formed for the first semiconductor device region 101, the first semiconductor die 313, the second semiconductor die 315, and the first local interconnect die 350.

[0033] During the encapsulation process, the top molding portion can be placed adjacent to the bottom molding portion, thereby enclosing the first semiconductor device region 101, the first semiconductor die 313, the second semiconductor die 315, and the first local interconnect die 350 within the molding cavity. After encapsulation, the top and bottom molding portions can form a hermetic seal to control the flow of gas into and out of the molding cavity. After encapsulation, the first encapsulant 401 can be placed within the molding cavity.

[0034] The first encapsulant 401 can be made of epoxy or molding compound resin, such as polyimide, polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polyethersulfone (PES), heat-resistant crystal resin, or combinations thereof. The first encapsulant 401 can be placed within the molding cavity before the top and bottom molding parts are aligned, or can be injected into the molding cavity through an injection port using compression molding, transfer molding, or the like.

[0035] After placing the first encapsulant 401 into the mold cavity so that it encapsulates the first semiconductor device region 101, the first semiconductor die 313, the second semiconductor die 315, and the first local interconnect die 350, the first encapsulant 401 can be cured to harden the first encapsulant 401 for optimal protection. While the exact curing process depends at least in part on the specific material selected for the first encapsulant 401, in embodiments where a molding compound is selected as the first encapsulant 401, the curing process can be performed by, for example, heating the first encapsulant 401 to a temperature between approximately 100° C. and approximately 200° C., such as approximately 125° C., for a duration of approximately 60 seconds to approximately 3000 seconds (e.g., approximately 600 seconds). Additionally, an initiator and / or catalyst can be included within the first encapsulant 401 to better control the curing process.

[0036] However, as one of ordinary skill in the art will appreciate, the above-described curing process is merely exemplary and is not intended to limit the present embodiment. Other curing processes may also be used, such as irradiation or even allowing the first encapsulant 401 to cure at ambient temperature. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.

[0037] FIG4 further illustrates the thinning of the first encapsulant 401 to expose the first semiconductor die 313, the second semiconductor die 315, and the first local interconnect die 350 for further processing. Thinning can be performed, for example, using mechanical grinding, chemical methods, or a chemical mechanical polishing (CMP) process. A chemical etchant and an abrasive react and remove the first encapsulant 401, exposing the first semiconductor die 313, the second semiconductor die 315, and the first local interconnect die 350. The first encapsulant 401 has a thickness between approximately 100 μm and approximately 150 μm. Consequently, the first semiconductor die 313, the second semiconductor die 315, and the first local interconnect die 350 can have flat surfaces that are coplanar with the first encapsulant 401. In another embodiment, grinding can be omitted. For example, if the first semiconductor die 313 and the second semiconductor die 315 are already exposed after encapsulation, grinding can be omitted.

[0038] Furthermore, while the chemical mechanical polishing process described above is presented as an illustrative embodiment, it is not intended to limit the embodiments. Any other suitable removal process may be used to thin the first encapsulant 401. For example, a series of chemical etches may be used. The described process and any other suitable process may be used to planarize the first encapsulant 401, and all such processes are fully intended to be included within the scope of the embodiments.

[0039] 5 , the placement of a first carrier substrate 500 is illustrated. In one embodiment, the first carrier substrate 500 comprises, for example, a silicon-based material such as silicon or glass. In one embodiment, the first carrier substrate 500 is flat to accommodate the attachment of the first semiconductor die 313 and the second semiconductor die 315 , which can be attached via a bonding process or using an adhesive layer (not separately shown).

[0040] In one embodiment, the first carrier substrate 500 is bonded to the first semiconductor die 313 and the second semiconductor die 315. In this embodiment, a first bonding layer 501 can be formed on the planar surfaces of the first semiconductor die 313 and the second semiconductor die 315. In one embodiment, the first bonding layer 501 can include an oxide, such as silicon oxide, silicon oxynitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., deposition of CVD-based materials in a remote plasma system and post-curing to convert them to oxides), ALD, physical vapor deposition (PVD), or the like, or a combination thereof. Other oxide materials formed by any acceptable process can also be used to form the first bonding layer 501.

[0041] After forming the first bonding layer 501, the first carrier substrate 500 can be bonded to the first bonding layer 501 via the second bonding layer 503 of the first carrier substrate 500. In one embodiment, the second bonding layer 503 is formed on the first carrier substrate 500 in a similar manner and from a similar material as the first bonding layer 501. According to some embodiments, the first carrier substrate 500 includes silicon, etc. In one embodiment, the second bonding layer 503 is bonded to the first bonding layer 501 via a dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding) to form a dielectric-to-dielectric bond (e.g., oxide-to-oxide bonding). In one embodiment, the dielectric-to-dielectric bonding process may include applying a surface treatment to one or more of the first bonding layer 501 and the second bonding layer 503. The surface treatment may include a plasma treatment, which may be applied to the exposed surfaces of the respective bonding layers. The plasma treatment may be performed in a vacuum environment. After the plasma treatment, the surface treatment may also include a cleaning process (e.g., rinsing with deionized water or the like), which may be applied to one or more of the first bonding layer 501 and the second bonding layer 503. Next, the first carrier substrate 500 is aligned with the first bonding layer 501 and pressed against each other to initiate pre-bonding of the first carrier substrate 500 to the first bonding layer 501 on the first semiconductor die 313 and the second semiconductor die 315. This pre-bonding may be performed at room temperature (e.g., between approximately 21°C and approximately 25°C). Following pre-bonding, an annealing process may be performed, such as heating the first bonding layer 501 and the second bonding layer 503 to a temperature in the range of 150°C to 500°C. This annealing process increases the bonding strength and triggers the formation of covalent bonds between the first bonding layer 501 and the second bonding layer 503. Other bonding processes, such as ambient bonding, vacuum bonding, or the like, may also be used in other embodiments.

[0042] Referring to FIG. 6 , after attaching the first carrier substrate 500, the second side of the first substrate 103 can be thinned to expose the first through-substrate vias 111. In one embodiment, thinning the second side of the first substrate 103 can expose the first through-substrate vias 111. Thinning the second side of the first substrate 103 can be performed using a planarization process such as chemical mechanical polishing (CMP) or etching. However, any suitable method can be used to thin the second side of the first substrate 103. In one embodiment, the etching process is a time-controlled anisotropic plasma etching process that forms a plurality of recesses 601, from which the first through-substrate vias 111 protrude. In one embodiment, the recesses 601 can be formed to have a sufficient depth to facilitate the thickness of a subsequently formed first passivation layer 701 (not shown in FIG. 6 , but shown in FIG. 7 ).

[0043] 7 , the formation of a first passivation film 701 over the second side of the first substrate 103 is illustrated. In one embodiment, the first passivation film 701 may include silicon oxide, silicon oxynitride, silicon nitride, or the like. In one embodiment, the first passivation film 701 may be deposited using CVD, ALD, PVD, or the like. Following the deposition of the first passivation film 701, a planarization process may be performed to expose the top surface of the first through-substrate via 111.

[0044] Referring to Figure 8, a first backside redistribution structure 800 is formed. The first backside redistribution structure 800 may include one or more redistribution dielectric layers 803 and one or more corresponding redistribution metallization layers 801 in the redistribution dielectric layers 803. The redistribution dielectric layer 803 may be, for example, a low-k dielectric layer. The redistribution metallization layer 801 may include a plurality of vias (e.g., a plurality of redistribution conductive elements 805) formed between the redistribution metallization layers 801. The redistribution metallization layer 801 may be formed of a conductive material (e.g., a metal, such as copper, cobalt, aluminum, gold, a combination thereof, etc.). The redistribution metallization layer 801 of the first backside redistribution structure 800 may be formed by a damascene process, such as a single damascene process, a dual damascene process, etc.

[0045] In one embodiment, a first metallization contact pad 807 is formed on the topmost dielectric layer of the first backside redistribution wiring structure 800. The first metallization contact pad 807 can be formed in a manner similar to the redistribution metallization layer 801. In one embodiment, the first metallization contact pad 807 can be formed to a different thickness than the redistribution metallization layer 801. In one embodiment, a first redistribution passivation layer 809 can be formed above the topmost dielectric layer and above the first metallization contact pad 807. The first redistribution passivation layer 809 can be a material such as a nitride, an oxide, a polyimide, a low-temp polyimide, a solder resist, a combination thereof, or the like. Once formed, the first redistribution passivation layer 809 can be patterned (e.g., using appropriate lithography and etching processes) to expose a portion of the first metallization contact pad 807.

[0046] In one embodiment, a plurality of under bump metallizations (UBMs) 811 are formed for external connection to the first backside redistribution wiring structure 800. The first UBM 811 includes a bump portion located above the first redistribution passivation layer 809 and extending along the main surface of the first redistribution passivation layer 809, and includes a via portion extending through the first redistribution passivation layer 809 to physically and electrically couple to the first metallization contact pad 807. The first UBM 811 can be formed of the same material as the redistribution metallization layer 801.

[0047] In one embodiment, a plurality of first conductive connectors 818 are formed on the first underbump metallurgy 811. The first conductive connectors 818 can be ball grid array (BGA) connectors, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, microbumps, bumps formed using electroless nickel-electroless palladium-immersion gold (ENEPIG) technology, and the like. The first conductive connectors 818 can comprise conductive materials such as solder, copper, aluminum, gold, nickel, silver, palladium, titanium nitride, the like, or combinations thereof. In some embodiments, the first conductive connectors 818 can be formed by first forming a solder layer through evaporation, electroplating, printing, solder transfer, ball planting, or the like. After the solder layer is formed on the structure, reflow can be performed to shape the material into the desired bump shape. In another embodiment, the first conductive connectors 818 comprise metal pillars (e.g., copper pillars) formed through sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal pillars may be free of solder and have substantially vertical sidewalls. In some embodiments, a metal cap layer is formed over the tops of the metal pillars. The metal cap layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, the like, or combinations thereof, and may be formed by a plating process. The resulting structure shown in FIG. 8 may be referred to as a first semiconductor package 850.

[0048] Subsequently, in some embodiments, the first carrier substrate 500 may be removed, and a singulation process may be performed around the perimeter of the package region as shown. However, the singulation process may not be performed on certain regions within the middle region 102 , such as the region between the two first semiconductor device regions 101 as shown.

[0049] 9 , a top-down cross-sectional view of a first semiconductor package 850 is shown. In one embodiment, a plurality of seal rings 175 surround the active circuitry of the plurality of first semiconductor device regions 101 and also completely cover the first semiconductor die 313 and the second semiconductor die 315 , respectively. In one embodiment, the first local interconnect die 350 overlaps the seal ring 175 defining one of the first semiconductor device regions 101 , completely overlaps the intermediate region 102 , and overlaps the seal ring 175 defining another of the first semiconductor device regions 101 .

[0050] Figures 1 through 9 illustrate a particular package architecture, but other architectures are possible. For example, Figures 10 through 19 illustrate various intermediate steps in fabricating a semiconductor package according to some other embodiments. Referring to Figure 10 , a third semiconductor die 1001, a fourth semiconductor die 1003, and a second local interconnect die 1005 (sometimes referred to as a local silicon interconnect (LSI) or silicon bridge) are attached to a second carrier substrate 1000. In one embodiment, each of the third semiconductor die 1001 and the fourth semiconductor die 1003 can be a system-on-a-chip device, such as a logic device. However, the third semiconductor die 1001 and the fourth semiconductor die 1003 can utilize any suitable functionality, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination thereof, or the like.

[0051] In one embodiment, the third semiconductor die 1001 and the fourth semiconductor die 1003 can each include a third substrate 1077, a third active device 1071, and a third metallization layer 1079. The third metallization layer 1079 includes a plurality of third alternating layers of a third conductive structure 1081 and a dielectric 1083. In one embodiment, the third substrate 1077, the third active device 1071, and the third metallization layer 1079 can be formed similarly to the first substrate 103, the first active device 107, and the first metallization layer 105, respectively, as described above. However, in other embodiments, these structures can be formed using different processes and different materials.

[0052] In one embodiment, the front sides of the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005 are bonded to the second carrier substrate 1000. In this embodiment, a third bonding layer 1051 can be formed on the second carrier substrate 1000. In one embodiment, the third bonding layer 1051 can include an oxide, such as silicon oxide, silicon oxynitride, or a combination thereof, and can be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., deposition of CVD-based materials in a remote plasma system and post-curing to convert them to oxides), ALD, physical vapor deposition (PVD), or the like, or a combination thereof. Other oxide materials formed by any acceptable process can also be used to form the third bonding layer 1051.

[0053] In one embodiment, the alternating dielectric layers of the third metallization layer 1079 are bonded to the third bonding layer 1051 via a dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding) to form a dielectric-to-dielectric bond (e.g., oxide-to-oxide bonding). The dielectric-to-dielectric bonding process can be performed in a manner similar to that discussed above.

[0054] Furthermore, in one embodiment, the second local interconnect die 1005 includes a second interconnect substrate 1021 supporting a second interconnect structure 1023, which includes a plurality of second interconnect metallization patterns 1025 (e.g., conductive lines, vias, and conductive pads) disposed within one or more second interconnect dielectric layers 1027. The second interconnect metallization patterns 1025 and the second interconnect dielectric layers 1027 can be formed in a manner and from similar materials as discussed with respect to the first conductive structures 155 and the dielectric material 153 in the first alternating layers of the first metallization layer 105, respectively. In one embodiment, the second interconnect substrate 1021 can be formed from silicon, such as bulk silicon. In one embodiment, the second interconnect substrate 1021 can be formed in a manner and from similar materials as the first substrate 103. In one embodiment, the second interconnect dielectric layer 1027 is used to form a dielectric-to-dielectric bond with the third bonding layer 1051 to bond the second local interconnect die 1005 to the second carrier substrate 1000 .

[0055] Referring to FIG. 11 , the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005 may be encapsulated with a second encapsulant 1101. In one embodiment, the encapsulation may be performed in a molding apparatus that may include a top molding portion and a bottom molding portion that is separable from the top molding portion. When the top molding portion is lowered to a position adjacent to the bottom molding portion, molding cavities for the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005 may be formed.

[0056] During the encapsulation process, the top mold portion can be placed adjacent to the bottom mold portion, thereby enclosing the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005 within the mold cavity. After encapsulation, the top and bottom mold portions form a hermetic seal to control the flow of gas into and out of the mold cavity. After sealing, the second encapsulant 1101 can be placed within the mold cavity.

[0057] The second encapsulant 1101 may be an epoxy or molding compound resin, such as polyimide, polyphenylene sulfide (PPS), polyetheretherketone (PEEK), polyethersulfone (PES), a heat-resistant crystalline resin, or a combination thereof. The second encapsulant 1101 may be placed within the molding cavity prior to alignment of the top and bottom molding portions, or may be injected into the molding cavity through an injection port using compression molding, transfer molding, or the like.

[0058] After placing the second encapsulant 1101 into the mold cavity, such that the second encapsulant 1101 encapsulates the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005, the second encapsulant 1101 can be cured to harden the second encapsulant 1101 for optimal protection. While the exact curing process depends at least in part on the specific material selected for the second encapsulant 1101, in embodiments where a molding compound is selected as the second encapsulant 1101, the curing process can be performed by, for example, heating the second encapsulant 1101 to a temperature between approximately 100°C and approximately 200°C, such as approximately 125°C, for a duration of approximately 60 seconds to approximately 3000 seconds (e.g., approximately 600 seconds). Additionally, an initiator and / or catalyst can be included within the second encapsulant 1101 to better control the curing process.

[0059] However, as one of ordinary skill in the art will appreciate, the above-described curing process is merely exemplary and is not intended to limit the present embodiment. Other curing processes may also be used, such as irradiation or even allowing the second encapsulant 1101 to cure at ambient temperature. Any suitable curing process may be used, and all such processes are fully intended to be included within the scope of the embodiments discussed herein.

[0060] FIG11 further illustrates the thinning of the second encapsulant 1101 to expose the backsides of the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005 for further processing. Thinning can be performed, for example, using mechanical polishing, chemical methods, or a chemical mechanical polishing (CMP) process, wherein a chemical etchant and abrasive react and remove the second encapsulant 1101, exposing the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005. The second encapsulant 1101 has a thickness between approximately 100 μm and approximately 150 μm. Consequently, the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005 can have planar surfaces that are coplanar with the second encapsulant 1101.

[0061] Furthermore, while the chemical mechanical polishing process described above is presented as an illustrative embodiment, it is not intended to limit the embodiments. Any other suitable removal process may be used to thin the second encapsulation body 1101. For example, a series of chemical etches may be used. The described process and any other suitable process may be used to planarize the second encapsulation body 1101, and all such processes are fully intended to be included within the scope of the embodiments.

[0062] 12 , the placement of a third carrier substrate 1200 is illustrated. In one embodiment, the third carrier substrate 1200 comprises a silicon-based material, such as silicon, glass, etc. In one embodiment, the third carrier substrate 1200 is flat to accommodate the attachment of the third semiconductor die 1001 and the fourth semiconductor die 1003, which can be attached via a bonding process or using an adhesive layer (not separately shown).

[0063] In one embodiment, third carrier substrate 1200 is bonded to the backside of third semiconductor die 1001, the backside of fourth semiconductor die 1003, and the backside of second local interconnect die 1005. In this embodiment, fourth bonding layer 1201 may be formed on the planar surfaces of third semiconductor die 1001, fourth semiconductor die 1003, second local interconnect die 1005, and second encapsulation body 1101. In one embodiment, fourth bonding layer 1201 may include an oxide, such as silicon oxide, silicon oxynitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., deposition of CVD-based materials in a remote plasma system and post-curing to convert them to oxides), ALD, physical vapor deposition (PVD), or the like, or a combination thereof. Other oxide materials formed by any acceptable process may also be used to form fourth bonding layer 1201.

[0064] In one embodiment, the third carrier substrate 1200 can be bonded to the fourth bonding layer 1201 via the fifth bonding layer 1203 of the third carrier substrate 1200. In one embodiment, the fifth bonding layer 1203 is formed on the third carrier substrate 1200 in a manner similar to, and made of a material similar to, the fourth bonding layer 1201. In some embodiments, the third carrier substrate 1200 includes silicon, for example. In one embodiment, the fifth bonding layer 1203 is bonded to the fourth bonding layer 1201 via a dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding), forming a dielectric-to-dielectric bond (e.g., oxide-to-oxide bonding). The dielectric-to-dielectric bonding process can be performed in a manner similar to that discussed above.

[0065] Referring to FIG. 13 , the intermediate device shown in FIG. 12 is flipped over, and illustrates a first carrier removal process 1300 of the second carrier substrate 1000. In one embodiment, the first carrier removal process 1300 can be a mechanical process (e.g., a grinding process), a chemical process (e.g., etching), a chemical mechanical polishing (CMP) process, or the like. However, any suitable removal process may be utilized. In one embodiment, the first carrier removal process 1300 exposes the front side of the third semiconductor die 1001, the front side of the fourth semiconductor die 1003, and the front side of the second local interconnect die 1005.

[0066] 14 , a plurality of third metallization layer vias 1401 may be formed in the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005. Furthermore, FIG14 illustrates a third wafer bonding layer 1409 and a plurality of third conductive bonding pads 1411 formed on the front sides of the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005.

[0067] In one embodiment, the third metallization layer via 1401 can be formed in a similar manner and from similar materials as described above with respect to the first metallization layer via 201. The third metallization layer via 1401 can be formed to physically and electrically contact the first conductive structure 155 of the first metallization layer 105.

[0068] In one embodiment, the third wafer bonding layer 1409 can be formed in a manner and made of similar materials as described above with respect to the first wafer bonding layer 209. However, any suitable process and materials can be used to form the third metallization layer via 1401 and the third wafer bonding layer 1409.

[0069] Referring to FIG. 15 , a first semiconductor device 1501 and a second semiconductor device 1503 are bonded to a third wafer bonding layer 1409. In one embodiment, the first semiconductor device 1501 and the second semiconductor device 1503 can each be a system-on-a-chip device, such as a logic element. However, the first semiconductor device 1501 and the second semiconductor device 1503 can utilize any suitable functionality, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination thereof, or the like.

[0070] In one embodiment, the first semiconductor device 1501 and the second semiconductor device 1503 can each include a first device substrate 1553, a fourth active device 1557, a first device metallization layer 1555, a plurality of first device metallization layer vias 1559, a plurality of first device substrate vias 1561, a first device bonding layer 1563, and a first device conductive bonding material 1565. In one embodiment, the first device substrate 1553 can be formed from a material similar to the first substrate 103. The fourth active device 1557 can be formed in a manner similar to the first active device 107. The first device metallization layer 1555 can be formed in a manner similar to the first metallization layer 105 and from a material similar to the first metallization layer 105. The first device metallization layer via 1559 can be formed in a manner similar to the first metallization layer via 201 and from a material similar to the first metallization layer via 201. The first device substrate via 1561 can be formed in a manner similar to the first substrate via 111 and from a similar material. The first device bonding layer 1563 can be formed of a material similar to the first wafer bonding layer 209 and can be formed by a process similar to the first wafer bonding layer 209, and the first device conductive bonding material 1565 can be formed of a material similar to the first conductive bonding pad 207 and can be formed by a process similar to the first conductive bonding pad 207. However, any suitable materials and processes can be used to form the structures of the first semiconductor device 1501 and the second semiconductor device 1503.

[0071] In one embodiment, the first semiconductor device 1501 and the second semiconductor device can be formed as part of a wafer, similar to the formation of the semiconductor wafer 100 described in FIG1 . The first semiconductor device 1501 and the second semiconductor device 1503 can then be separated into individual semiconductor devices along scribe lines (not shown) defined by seal rings (not shown) (as shown).

[0072] In one embodiment, the front sides of the first semiconductor device 1501 and the second semiconductor device 1503 can be attached to the front sides of the third semiconductor die 1001, the fourth semiconductor die 1003, and the second local interconnect die 1005. In one embodiment, the first semiconductor device 1501 and the second semiconductor device 1503 can be attached via a bonding process or using an adhesive layer (not separately shown).

[0073] In one embodiment, the first semiconductor device 1501 can be bonded to the third semiconductor die 1001 and the second local interconnect die 1005 by bonding the first device bonding layer 1563 and the first device conductive bonding material 1565 of the first semiconductor device 1501 to the third wafer bonding layer 1409 and the third conductive bonding pad 1411, respectively. In one embodiment, the first device bonding layer 1563 and the first device conductive bonding material 1565 can be bonded to the third wafer bonding layer 1409 and the third conductive bonding pad 1411 in a manner similar to that described above regarding the bonding of the second wafer bonding layer 321 and the second conductive bonding pad 323 to the first wafer bonding layer 209 and the first conductive bonding pad 207, respectively. However, any suitable bonding process can be used to bond the first semiconductor device 1501 to the third wafer bonding layer 1409.

[0074] In one embodiment, the second semiconductor device 1503 can be attached to the fourth semiconductor die 1003 and the second local interconnect die 1005 by bonding the first device bonding layer 1563 and the first device conductive bonding material 1565 of the second semiconductor device 1503 to the third wafer bonding layer 1409 and the third conductive bonding pad 1411, respectively. In one embodiment, the first device bonding layer 1563 and the first device conductive bonding material 1565 can be bonded to the third wafer bonding layer 1409 and the third conductive bonding pad 1411 in a manner similar to that described above regarding the bonding of the second wafer bonding layer 321 and the second conductive bonding pad 323 to the first wafer bonding layer 209 and the first conductive bonding pad 207, respectively. However, any suitable bonding process can be used to bond the second semiconductor device 1503 to the third wafer bonding layer 1409.

[0075] In one embodiment, the second local interconnect die 1005 electrically couples the first semiconductor device 1501 to the second semiconductor device 1503. Furthermore, in one embodiment, the third semiconductor die 1001 is electrically coupled to the first semiconductor device 1501, and the fourth semiconductor die 1003 is electrically coupled to the second semiconductor device 1503. In one embodiment, the third semiconductor die 1001 can be electrically coupled to the fourth semiconductor die 1003 via the second local interconnect die 1005 electrically coupled between the first semiconductor device 1501 electrically coupled to the third semiconductor die 1001 and the second semiconductor device 1503 electrically coupled to the fourth semiconductor die 1003.

[0076] 16 , the first semiconductor device 1501 and the second semiconductor device 1503 may be encapsulated by a third encapsulant 1601. In one embodiment, the third encapsulant 1601 may be formed using a process similar to that of the second encapsulant 1101. However, any suitable process and materials may be used for the third encapsulant 1601.

[0077] Furthermore, after encapsulating the first semiconductor device 1501 and the second semiconductor device 1503 with the third encapsulant 1601, the third encapsulant 1601, the backside of the first semiconductor device 1501, and the backside of the second semiconductor device 1503 may be thinned to expose the top surface of the first through-substrate via 1561 of the first semiconductor device 1501 and the top surface of the first through-substrate via 1561 of the second semiconductor device 1503. This thinning may be performed, for example, using mechanical polishing, chemical methods, or a chemical mechanical polishing (CMP) process, wherein a chemical etchant and abrasive react and abrade the third encapsulant 1601, removing portions of the first device substrate 1553 of both the first semiconductor device 1501 and the second semiconductor device 1503. Consequently, the backside of the first semiconductor device 1501, the backside of the second semiconductor device 1503, and the third encapsulant 1601 may have flat surfaces.

[0078] Furthermore, while the chemical mechanical polishing process described above is presented as an illustrative embodiment, it is not intended to limit the embodiments. Any other suitable removal process may be used to thin the third encapsulant 1601 and the first device substrate 1553. For example, a series of chemical etches may be used. The described process and any other suitable process may be used to planarize the third encapsulant 1601 and the first device substrate 1553, and all such processes are fully intended to be included within the scope of the embodiments.

[0079] Referring to FIG. 17 , the formation of a second passivation film 1701 on the backside of the first semiconductor device 1501 and the backside of the second semiconductor device 1503 is illustrated. In one embodiment, an etch-back process is performed on the first device substrate 1553 of the first semiconductor device 1501 and the first device substrate 1553 of the second semiconductor device 1503, respectively. The etch-back process may be a time-controlled anisotropic plasma etching process, which forms a plurality of recesses (not separately shown) within the first device substrate 1553 of the first semiconductor device 1501 and the first device substrate 1553 of the second semiconductor device 1503, such that the first device substrate through-holes 1561 protrude from the first device substrate 1553. In one embodiment, the recesses may be formed to have a sufficient depth to reduce the thickness of the second passivation film 1701.

[0080] In one embodiment, the second passivation film 1701 may include silicon oxide, silicon oxynitride, silicon nitride, etc. In one embodiment, the second passivation film 1701 may be deposited by CVD, ALD, PVD, etc. After the deposition of the second passivation film 1701, a planarization process may be performed to expose the top surface of the first device substrate through hole 1561.

[0081] Referring to FIG. 18 , a first backside redistribution wiring structure 800 is formed over the backside of first semiconductor device 1501 and the backside of second semiconductor device 1503. In one embodiment, first backside redistribution wiring structure 800 is formed in a similar manner and from similar materials as described above, but is formed over first semiconductor device 1501 and second semiconductor device 1503. Furthermore, in one embodiment, first metallized contact pads 807, a first redistribution passivation layer 809, a plurality of first under-bump metallurgy (UBM) layers 811, and a plurality of first conductive connectors 818 are formed over first backside redistribution wiring structure 800 in a similar manner and from similar materials as described above. The resulting structure shown in FIG. 18 may be referred to as a second semiconductor package 1850.

[0082] Referring to FIG. 19 , a top-down cross-sectional view of a second semiconductor package 1850 is shown. In one embodiment, the third encapsulant 1601 in the top-down cross-sectional view defines the periphery of the second semiconductor package 1850. In one embodiment, the first semiconductor device 1501 completely covers the third semiconductor die 1001 and covers a first portion of the second local interconnect die 1005. In one embodiment, the second semiconductor device 1503 completely covers the fourth semiconductor die 1003 and covers a second portion of the second local interconnect die 1005.

[0083] Figures 10 through 19 illustrate a particular package architecture, but other architectures are possible. For example, Figures 20 through 31 illustrate various intermediate steps in fabricating a semiconductor package according to some other embodiments. Referring to Figure 20 , a third semiconductor device 2001 and a fourth semiconductor device 2003 are bonded to a fourth carrier substrate 2000. In one embodiment, the third semiconductor device 2001 and the fourth semiconductor device 2003 can each be a system-on-a-chip device, such as a logic element. However, the third semiconductor device 2001 and the fourth semiconductor device 2003 can utilize any suitable functionality, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination thereof, or the like.

[0084] In one embodiment, the third semiconductor device 2001 and the fourth semiconductor device 2003 may each include a second device substrate 2053, a fourth active device 2057, a second device metallization layer 2055, and a plurality of second device substrate through-vias 2061. In one embodiment, the second device substrate 2053 may be formed of a material similar to the first substrate 103. The fourth active device 2057 may be formed in a manner similar to the first active device 107. The second device metallization layer 2055 may be formed in a manner similar to the first metallization layer 105 and from a material similar to the first metallization layer 105. The second device substrate through-vias 2061 may be formed in a manner similar to the first substrate through-vias 111 and from a similar material. However, any suitable materials and processes may be used to form the structures of the third semiconductor device 2001 and the fourth semiconductor device 2003.

[0085] In one embodiment, the third semiconductor device 2001 and the fourth semiconductor device 2003 can be formed as part of a wafer, similar to the formation of the semiconductor wafer 100 described in FIG1 . The third semiconductor device 2001 and the fourth semiconductor device 2003 can then be separated into individual semiconductor devices along scribe lines (not shown) defined by seal rings (not shown) (as shown).

[0086] In one embodiment, the fourth carrier substrate 2000 includes, for example, a silicon-based material, such as silicon, glass, etc. In one embodiment, the fourth carrier substrate 2000 is flat to accommodate the attachment of the third semiconductor device 2001 and the fourth semiconductor device 2003, which can be attached through a bonding process or by using an adhesive layer (not separately shown).

[0087] In one embodiment, the fourth carrier substrate 2000 is bonded to the front side of the third semiconductor device 2001 and the front side of the fourth semiconductor device 2003. In this embodiment, a sixth bonding layer 2071 may be formed on the second device metallization layer 2055 of the third semiconductor device 2001 and the second device metallization layer 2055 of the fourth semiconductor device 2003. In one embodiment, the sixth bonding layer 2071 may include an oxide, such as silicon oxide, silicon oxynitride, or the like, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., deposition of CVD-based materials in a remote plasma system and post-curing to convert them to oxides), ALD, physical vapor deposition (PVD), or the like, or a combination thereof. Other oxide materials formed by any acceptable process may also be used to form the sixth bonding layer 2071.

[0088] The fourth carrier substrate 2000 can be bonded to the sixth bonding layer 2071 of the third semiconductor device 2001 and the sixth bonding layer 2071 of the fourth semiconductor device 2003 via the seventh bonding layer 2073 of the fourth carrier substrate 2000. In one embodiment, the seventh bonding layer 2073 is formed on the fourth carrier substrate 2000 in a manner similar to, and made of a material similar to, the fourth bonding layer 1201. According to some embodiments, the fourth carrier substrate 2000 includes silicon, etc. In one embodiment, the seventh bonding layer 2073 is bonded to the sixth bonding layer 2071 through a dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding) to form a dielectric-to-dielectric bond (e.g., oxide-to-oxide bonding). The dielectric-to-dielectric bonding process can be performed in a manner similar to that discussed above.

[0089] 21 , the third semiconductor device 2001 and the fourth semiconductor device 2003 may be encapsulated by a fourth encapsulant 2101. In one embodiment, the fourth encapsulant 2101 may be formed using a process similar to that of the third encapsulant 1601. However, any suitable process and materials may be used for the fourth encapsulant 2101.

[0090] Furthermore, after encapsulating the third semiconductor device 2001 and the fourth semiconductor device 2003 with the fourth encapsulant 2101, the fourth encapsulant 2101, the backside of the third semiconductor device 2001, and the backside of the fourth semiconductor device 2003 can be thinned to expose the top surface of the second through-substrate via 2061 of the third semiconductor device 2001 and the top surface of the second through-substrate via 2061 of the fourth semiconductor device 2003. This thinning can be performed, for example, using mechanical polishing, chemical methods, or a chemical mechanical polishing (CMP) process, in which a chemical etchant and abrasive react and abrade the fourth encapsulant 2101, removing portions of the second device substrate 2053 of both the third semiconductor device 2001 and the fourth semiconductor device 2003. Consequently, the backside of the third semiconductor device 2001, the backside of the fourth semiconductor device 2003, and the fourth encapsulant 2101 can have flat surfaces.

[0091] Furthermore, while the chemical mechanical polishing process described above is presented as an illustrative embodiment, it is not intended to limit the embodiments. Any other suitable removal process may be used to thin the fourth encapsulant 2101 and the second device substrate 2053. For example, a series of chemical etches may be used. The described process and any other suitable process may be used to planarize the fourth encapsulant 2101 and the second device substrate 2053, and all such processes are fully intended to be included within the scope of the embodiments.

[0092] Referring to FIG. 22 , a fifth carrier substrate 2200 is attached to the backside of the third semiconductor device 2001 and the backside of the fourth semiconductor device 2003. In one embodiment, the backsides of the third semiconductor device 2001 and the backsides of the fourth semiconductor device 2003 are bonded to the fifth carrier substrate 2200. In this embodiment, an eighth bonding layer 2251 may be formed on the fifth carrier substrate 2200. In one embodiment, the fifth carrier substrate 2200 comprises a silicon-based material, such as silicon, glass, or the like. In one embodiment, the eighth bonding layer 2251 may comprise an oxide, such as silicon oxide, silicon oxynitride, or the like, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., deposition of CVD-based materials in a remote plasma system followed by post-curing to convert them to oxides), ALD, physical vapor deposition (PVD), or the like, or a combination thereof. Other oxide materials formed by any acceptable process may also be used to form the eighth bonding layer 2251. Furthermore, a ninth bonding layer 2253 may be formed on the planar surfaces of the third semiconductor device 2001, the fourth semiconductor device 2003, and the fourth encapsulant 2101. In one embodiment, the ninth bonding layer 2253 may include an oxide, such as silicon oxide, silicon oxynitride, or the like, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., deposition of CVD-based materials in a remote plasma system and post-curing to convert them to oxides), ALD, physical vapor deposition (PVD), or the like, or a combination thereof. The ninth bonding layer 2253 may be formed using any other oxide material formed by any acceptable process.

[0093] In one embodiment, the eighth bonding layer 2251 is bonded to the ninth bonding layer 2253 via a dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding) to form a dielectric-to-dielectric bond (e.g., oxide-to-oxide bonding). The dielectric-to-dielectric bonding process can be performed in a manner similar to that discussed above.

[0094] Referring to FIG. 23 , the intermediate device shown in FIG. 22 is flipped over and a second carrier removal process 2300 is performed on the fourth carrier substrate 2000. In one embodiment, the second carrier removal process 2300 can be a mechanical process (e.g., a grinding process), a chemical process (e.g., etching), a chemical mechanical polishing (CMP) process, or the like. However, any suitable removal process may be utilized. In one embodiment, the second carrier removal process 2300 exposes the front side of the third semiconductor device 2001 and the front side of the fourth semiconductor device 2003.

[0095] 24 , a plurality of second device metallization layer vias 2401 may be formed in the third semiconductor device 2001 and the fourth semiconductor device 2003. Furthermore, FIG. 24 illustrates a fourth wafer bonding layer 2403 and fourth conductive bonding pads 2405 formed on the front side of the third semiconductor device 2001 and the front side of the fourth semiconductor device 2003.

[0096] In one embodiment, the second device metallization layer via 2401 can be formed in a similar manner and from similar materials as described above with respect to the first metallization layer via 201. The second device metallization layer via 2401 can be formed to physically and electrically contact the second device metallization layer 2055.

[0097] In one embodiment, the fourth wafer bonding layer 2403 can be formed in a manner and from similar materials as described above with respect to the first wafer bonding layer 209, and the fourth conductive bonding pad 2405 can be formed in a manner and from similar materials as described above with respect to the first conductive bonding pad 207. However, any suitable process and materials can be used to form the second device metallization layer through-hole 2401, the fourth wafer bonding layer 2403, and the fourth conductive bonding pad 2405.

[0098] Now, referring to FIG. 25 , a fifth semiconductor die 2513, a sixth semiconductor die 2515, and a third local interconnect die 2550 (sometimes referred to as a local silicon interconnect (LSI) or silicon bridge) are bonded to the fourth conductive bonding pad 2405 and the fourth wafer bonding layer 2403. In one embodiment, each of the fifth semiconductor die 2513 and the sixth semiconductor die 2515 can be a system-on-a-chip device, such as a logic device. However, the fifth semiconductor die 2513 and the sixth semiconductor die 2515 can utilize any suitable functionality, such as a logic die, a central processing unit (CPU) die, an input / output die, a combination thereof, or the like.

[0099] In one embodiment, the fifth semiconductor die 2513 and the sixth semiconductor die 2515 can each include a fourth substrate 2517, a fifth active device 2501, a fourth metallization layer 2519, a plurality of fourth metallization layer vias 2507, a fifth wafer bonding layer 2521, and a plurality of fifth conductive bonding pads 2523. In one embodiment, the fourth metallization layer 2519 includes a plurality of fourth alternating layers of dielectric 2503 and a plurality of fourth conductive structures 2505. In one embodiment, the fourth substrate 2517, the fifth active device 2501, the fourth metallization layer 2519, the fourth metallization layer vias 2507, the fifth wafer bonding layer 2521, and the fifth conductive bonding pads 2523 can be similar to the first substrate 103, the first active device 107, the first metallization layer 105, the first metallization layer vias 201, the first wafer bonding layer 209, and the first conductive bonding pads 207 described above, respectively. However, in other embodiments, these structures can be formed using different processes and different materials.

[0100] Furthermore, in one embodiment, the third local interconnect die 2550 includes a third interconnect substrate 2571 supporting a third interconnect structure 2573. The third interconnect substrate 2571 includes a plurality of third interconnect metallization patterns 2575 (e.g., conductive lines, vias, and conductive pads) disposed within one or more third interconnect dielectric layers 2557. The third interconnect metallization patterns 2575 and the third interconnect dielectric layers 2557 can be formed in a manner and from similar materials as discussed with respect to the first conductive structures 155 and the dielectric material 153 in the first alternating layers of the first metallization layer 105, respectively. In one embodiment, the third interconnect substrate 2571 can be formed from silicon, such as bulk silicon. In one embodiment, the third interconnect substrate 2571 can be formed in a manner similar to the first substrate 103 and from similar materials.

[0101] In one embodiment, a fifth semiconductor die 2513 is bonded onto the third semiconductor device 2001. The fifth semiconductor die 2513 can be bonded onto the third semiconductor device 2001 by bonding the fifth wafer bonding layer 2521 and the fifth conductive bonding pad 2523 of the fifth semiconductor die 2513 to the fourth wafer bonding layer 2403 and the fourth conductive bonding pad 2405, respectively, on the front side of the third semiconductor device 2001. In one embodiment, bonding the fifth wafer bonding layer 2521 and the fifth conductive bonding pad 2523 of the fifth semiconductor die 2513 to the fourth wafer bonding layer 2403 and the fourth conductive bonding pad 2405 can be performed in a manner similar to the bonding of the second wafer bonding layer 321 and the second conductive bonding pad 323 to the first wafer bonding layer 209 and the first conductive bonding pad 207, respectively, as described above. However, any suitable bonding process can be used to bond the fifth semiconductor die 2513 to the fourth wafer bonding layer 2403.

[0102] In one embodiment, the sixth semiconductor die 2515 is bonded onto the fourth semiconductor device 2003. The sixth semiconductor die 2515 can be bonded onto the fourth semiconductor device 2003 by bonding the fifth wafer bonding layer 2521 and the fifth conductive bonding pad 2523 of the sixth semiconductor die 2515 to the fourth wafer bonding layer 2403 and the fourth conductive bonding pad 2405, respectively, on the front side of the fourth semiconductor device 2003. In one embodiment, bonding the fifth wafer bonding layer 2521 and the fifth conductive bonding pad 2523 of the sixth semiconductor die 2515 to the fourth wafer bonding layer 2403 and the fourth conductive bonding pad 2405 can be performed in a manner similar to that described above regarding bonding the second wafer bonding layer 321 and the second conductive bonding pad 323 to the first wafer bonding layer 209 and the first conductive bonding pad 207, respectively. However, any suitable bonding process can be used to bond the sixth semiconductor die 2515 to the fourth wafer bonding layer 2403.

[0103] In addition, in one embodiment, multiple conductive pads in the third interconnect metallization pattern 2575 and one of the third interconnect dielectric layers 2557 can be used to bond the third local interconnect die 2550 to the fourth wafer bonding layer 2403 and the fourth conductive bonding pad 2405 in a manner similar to the above-mentioned bonding of the second wafer bonding layer 321 and the second conductive bonding pad 323 to the first wafer bonding layer 209 and the first conductive bonding pad 207, respectively.

[0104] In one embodiment, the third local interconnect die 2550 electrically couples the third semiconductor device 2001 to the fourth semiconductor device 2003. Furthermore, in one embodiment, the fifth semiconductor die 2513 is electrically coupled to the third semiconductor device 2001, and the sixth semiconductor die 2515 is electrically coupled to the fourth semiconductor device 2003. In one embodiment, the third semiconductor device 2001 can be electrically coupled to the fourth semiconductor device 2003 via the third local interconnect die 2550 electrically coupled between the third semiconductor device 2001 electrically coupled to the fifth semiconductor die 2513 and the fourth semiconductor device 2003 electrically coupled to the sixth semiconductor die 2515.

[0105] 26 , the fifth semiconductor die 2513, the sixth semiconductor die 2515, and the third local interconnect die 2550 may be encapsulated by a fifth encapsulant 2601. In one embodiment, the fifth encapsulant 2601 may be formed using a process similar to that of the third encapsulant 1601. However, any suitable process and materials may be used for the fifth encapsulant 2601.

[0106] Furthermore, after encapsulating the fifth semiconductor die 2513, the sixth semiconductor die 2515, and the third local interconnect die 2550 with the fifth encapsulant 2601, the fifth encapsulant 2601 may be thinned. In one embodiment, thinning the fifth encapsulant 2601 exposes the backsides of the fifth semiconductor die 2513, the sixth semiconductor die 2515, and the third local interconnect die 2550 for further processing. Thinning may be performed, for example, using mechanical polishing, chemical methods, or a chemical mechanical polishing (CMP) process, wherein a chemical etchant and abrasive react and grind away the fifth encapsulant 2601. This allows the fifth semiconductor die 2513, the sixth semiconductor die 2515, and the third local interconnect die 2550 to have flat surfaces that are also coplanar with the fifth encapsulant 2601.

[0107] Furthermore, while the chemical mechanical polishing process described above is presented as an illustrative embodiment, it is not intended to limit the embodiments. Any other suitable removal process may be used to thin the fifth encapsulant 2601. For example, a series of chemical etches may be used. The described process and any other suitable process may be used to planarize the fifth encapsulant 2601, and all such processes are fully intended to be within the scope of the embodiments.

[0108] Referring to FIG. 27 , a sixth carrier substrate 2700 is attached to the backsides of the fifth semiconductor die 2513, the sixth semiconductor die 2515, the third local interconnect die 2550, and the fifth encapsulant 2601. In one embodiment, the backsides of the fifth semiconductor die 2513, the sixth semiconductor die 2515, the third local interconnect die 2550, and the fifth encapsulant 2601 are bonded to the sixth carrier substrate 2700. In this embodiment, a tenth bonding layer 2751 may be formed over the sixth carrier substrate 2700. In one embodiment, the tenth bonding layer 2751 may include an oxide, such as silicon oxide, silicon oxynitride, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., deposition of CVD-based materials in a remote plasma system and post-curing to convert them to oxides), ALD, physical vapor deposition (PVD), the like, or a combination thereof. Other oxide materials formed by any acceptable process may also be used to form the tenth bonding layer 2751. Furthermore, the eleventh bonding layer 2753 may be formed on the planar surfaces of the fifth semiconductor die 2513, the sixth semiconductor die 2515, the third local interconnect die 2550, and the fifth package 2601. In one embodiment, the eleventh bonding layer 2753 may include an oxide, such as silicon oxide, silicon oxynitride, or the like, or a combination thereof, and may be formed by high-density plasma chemical vapor deposition (HDP-CVD), flowable CVD (FCVD) (e.g., deposition of CVD-based materials in a remote plasma system and post-curing to convert them to oxides), ALD, physical vapor deposition (PVD), the like, or a combination thereof. Other oxide materials formed by any acceptable process may also be used to form the eleventh bonding layer 2753.

[0109] In one embodiment, the tenth bonding layer 2751 is bonded to the eleventh bonding layer 2753 via a dielectric-to-dielectric bonding process (e.g., oxide-to-oxide bonding) to form a dielectric-to-dielectric bond (e.g., oxide-to-oxide bonding). The dielectric-to-dielectric bonding process can be performed in a manner similar to that discussed above.

[0110] Referring to FIG. 28 , the intermediate device shown in FIG. 27 is flipped over and a third carrier removal process 2800 is performed on the fifth carrier substrate 2200. In one embodiment, the third carrier removal process 2800 can be a mechanical process (e.g., a grinding process), a chemical process (e.g., etching), a chemical mechanical polishing (CMP) process, or the like. However, any suitable removal process may be utilized. In one embodiment, the third carrier removal process 2800 exposes the backside of the third semiconductor device 2001 and the backside of the fourth semiconductor device 2003.

[0111] Referring to FIG. 29 , a third passivation film 2901 is formed on the backside of the third semiconductor device 2001 and the backside of the fourth semiconductor device 2003. In one embodiment, an etch-back process is performed on the second device substrate 2053 of the third semiconductor device 2001 and the second device substrate 2053 of the fourth semiconductor device 2003. The etch-back process may be a time-controlled anisotropic plasma etching process, which forms a plurality of recesses (not separately shown) within the second device substrate 2053 of the third semiconductor device 2001 and the second device substrate 2053 of the fourth semiconductor device 2003, such that the second device substrate through-holes 2061 protrude from the second device substrate 2053. In one embodiment, the recesses may be formed to have a sufficient depth to reduce the thickness of the third passivation film 2901.

[0112] In one embodiment, the third passivation film 2901 may include silicon oxide, silicon oxynitride, silicon nitride, etc. In one embodiment, the third passivation film 2901 may be deposited by CVD, ALD, PVD, etc. After the deposition of the third passivation film 2901, a planarization process may be performed to expose the top surface of the second device substrate through-hole 2061.

[0113] Referring to FIG. 30 , a first backside redistribution wiring structure 800 is formed on the backside of the third semiconductor device 2001 and the backside of the fourth semiconductor device 2003. In one embodiment, the first backside redistribution wiring structure 800 is formed in a manner and from similar materials as described above, but is formed above the third semiconductor device 2001 and the fourth semiconductor device 2003. Furthermore, in one embodiment, a plurality of first metallization contact pads 807, a first redistribution passivation layer 809, a plurality of first under-bump metallurgy 811, and a plurality of first conductive connectors 818 are formed in a manner and from similar materials as described above above the first backside redistribution wiring structure 800. The resulting structure shown in FIG. 30 may be referred to as a third semiconductor package 3050.

[0114] 31 , a top-down cross-sectional view of a third semiconductor package 3050 is shown. In one embodiment, the fourth encapsulant 2101 in the top-down cross-sectional view defines the periphery of the third semiconductor package 3050. In one embodiment, the third semiconductor device 2001 completely covers the fifth semiconductor die 2513 and covers a first portion of the third local interconnect die 2550. In one embodiment, the fourth semiconductor device 2003 completely covers the sixth semiconductor die 2515 and covers a second portion of the third local interconnect die 2550.

[0115] Referring to FIG. 32A , a first semiconductor package 850 is shown having multiple TSV guard rings 3201 surrounding multiple first through-substrate vias 111, and a deep trench capacitor (DTC) 3203 may optionally be formed in the first local interconnect die 350. In one embodiment, the TSV guard rings 3201 may be formed using a damascene process. The TSV guard rings 3201 may be formed in the first metallization layer 105 and surround the first through-substrate vias 111 in the first metallization layer 105 in a top-down view (see, for example, FIG. 32B ). In one embodiment, the TSV guard rings 3201 do not extend into the first substrate 103. The TSV guard rings 3201 may comprise a metal, such as copper. However, the TSV guard rings 3201 may be formed using any suitable method and material.

[0116] In one embodiment, the TSV guard ring 3201 can reduce leakage current and provide electrical isolation between the first through substrate via 111 and other structures in the first metallization layer 105. Additionally, during the manufacture and operation of the first semiconductor package 850, the first through substrate via 111 can introduce mechanical stress, and the TSV guard ring 3201 can provide stress relief.

[0117] FIG32A also illustrates a plurality of passive devices, such as deep trench capacitors (DTCs) 3203, formed in the first local interconnect die 350 of the first semiconductor package 850. In some embodiments, the deep trench capacitors 3203 may be formed in the first interconnect substrate 351 of the first local interconnect die 350. In one embodiment, the deep trench capacitors 3203 may include a three-dimensional corrugated stack having multiple metal layers (not shown separately) separated by multiple insulating layers (not shown separately). In one embodiment, the deep trench capacitors 3203 may be single trench capacitors including multiple metal vias (not shown separately) within a single recess (not shown separately), or may be multi-trench capacitors including multiple metal vias within multiple recesses.

[0118] 32A illustrates a TSV protection ring 3201 and a deep trench capacitor 3203 in the first semiconductor package 850, this is for illustrative purposes only. The TSV protection ring 3201 can be formed using similar materials and processes to surround the first through-substrate via 1561 in the second semiconductor package 1850 and the second through-substrate via 2061 in the third semiconductor package 3050. Similarly, a DTC can be formed using similar processes and materials in the second local interconnect die 1005 of the second semiconductor package 1850 and the third local interconnect die 2550 of the third semiconductor package 3050.

[0119] Referring to FIG32B , a top-down section view of a TSV protection ring 3201 surrounding the first through-substrate via 111 is shown, taken along the section cut line AA in FIG32A . In one embodiment, the TSV protection ring 3201 may be rectangular (e.g., square) in a top view. However, any suitable shape may be used to surround the first through-substrate via 111.

[0120] Advantages can be realized by utilizing various carrier substrates (e.g., first carrier substrate 500, second carrier substrate 1000, third carrier substrate 1200, etc.) in combination with various local interconnect structures (e.g., first local interconnect die 350, second local interconnect die 1005, and third local interconnect die 2550) to bond various semiconductor devices or semiconductor wafers with active circuitry in a front-to-front orientation. The various carrier substrates allow the formation of various local interconnect structures at different steps in the manufacturing process, thereby increasing flexibility. Furthermore, the front-to-front orientation allows the formation of backside redistribution wiring structures (e.g., first backside redistribution wiring structure 800) to facilitate external connections. The combination of backside redistribution wiring structures and various local interconnect structures increases the interconnectivity between functional circuitry within various semiconductor packages (e.g., first semiconductor package 850, second semiconductor package 1850, and third semiconductor package 3050), improving the functionality, efficiency, and performance of these various semiconductor packages. The improved design flexibility allows for improved functionality in the manufacture of various semiconductor packages while reducing costs.

[0121] According to an embodiment, a method includes bonding a first semiconductor die to a first side of a first semiconductor device, the first semiconductor device including a first region of active circuitry and a second region of active circuitry electrically isolated from the first region of active circuitry; bonding a second semiconductor die to the first side of the first semiconductor device and adjacent to the first semiconductor die; bonding a local interconnect die to the first side of the first semiconductor device and between the first and second semiconductor dies, wherein the local interconnect die electrically connects the first region of active circuitry to the second region of active circuitry; and forming a redistribution structure on a second side of the first semiconductor device opposite the first side of the first semiconductor device, wherein forming the redistribution structure includes forming a plurality of dielectric layers above the second side of the first semiconductor device opposite the first side and forming a plurality of metallization layers within the plurality of dielectric layers. In one embodiment, the first region of active circuitry and the second region of active circuitry are disposed on the same semiconductor substrate. In one embodiment, before bonding the first semiconductor die to the first semiconductor device, the method further includes forming a first seal ring and a second seal ring within the first semiconductor device, wherein the first seal ring surrounds the first region of active circuitry and the second seal ring surrounds the second region of active circuitry. In one embodiment, after bonding the local interconnect die to the first semiconductor device, the local interconnect die directly covers the first seal ring, the second seal ring, and the intermediate region between the first and second seal rings. In one embodiment, after forming the first and second seal rings in the first semiconductor device, a backside thinning process is performed on the first semiconductor device to expose a plurality of through-substrate vias (TSVs) of the first semiconductor device, wherein the TSVs are electrically coupled to the interconnect structures of the first semiconductor device. In one embodiment, bonding the first semiconductor die to the first semiconductor device includes forming a plurality of metal-to-metal bonds and a plurality of dielectric-to-dielectric bonds between the first semiconductor device and the first semiconductor die. In one embodiment, before bonding the local interconnect die to the first side of the first semiconductor device, the method further includes bonding the local interconnect die to a carrier substrate. In one embodiment, after bonding the local interconnect die to the first side of the first semiconductor device, the method further includes bonding the local interconnect die to a carrier substrate.

[0122] According to an embodiment, a device includes a semiconductor device having a semiconductor substrate, a plurality of first through-substrate vias (TSVs) and a plurality of second TSVs extending through the semiconductor substrate, an interconnect structure above the semiconductor substrate, the interconnect structure including a plurality of first metallization patterns electrically coupled to the plurality of first TSVs and a plurality of second metallization patterns electrically coupled to the plurality of second TSVs, a first seal ring surrounding the plurality of first metallization patterns to define a first semiconductor region, and a second seal ring surrounding the plurality of second metallization patterns to define a second semiconductor region, a local interconnect structure bonded to both the first semiconductor region and the second semiconductor region, wherein the local interconnect structure directly covers the first seal ring and the second seal ring, and a first redistribution wiring structure disposed on the semiconductor device, the first redistribution wiring structure electrically connected to the first semiconductor region through the plurality of first TSVs and electrically connected to the second semiconductor region through the plurality of second TSVs. In one embodiment, the device further includes a first semiconductor die bonded to the first semiconductor region, and a second semiconductor die bonded to the second semiconductor region. In one embodiment, the first semiconductor die is electrically coupled to the second semiconductor die via the first redistribution wiring structure. In one embodiment, the first semiconductor region is electrically coupled to the second semiconductor region via the local interconnect structure, the first semiconductor die is electrically coupled to the first semiconductor region, and the second semiconductor die is electrically coupled to the second semiconductor region. In one embodiment, the first semiconductor die and the second semiconductor die are embedded in a molding compound. In one embodiment, the first semiconductor region and the second semiconductor region in the semiconductor device are electrically isolated.

[0123] According to an embodiment, a method includes bonding a first metallization structure of a first semiconductor die to a second metallization structure of a semiconductor device, wherein the second metallization structure is surrounded by a first seal ring, bonding a third metallization structure of a second semiconductor die to a fourth metallization structure of the semiconductor device, wherein the fourth metallization structure is surrounded by a second seal ring, bonding a fifth metallization structure of a local interconnect die to the second and fourth metallization structures of the semiconductor device, wherein the fifth metallization structure overlaps both the first and second seal rings, and forming a first redistribution structure on a side of the semiconductor device opposite to the first semiconductor die, the second semiconductor die, and the local interconnect die. In one embodiment, forming the first redistribution structure includes forming a sixth metallization structure in a plurality of dielectric layers using one or more damascene processes. In one embodiment, the method further includes forming a contact pad on the sixth metallization structure, forming a passivation layer on the contact pad, forming an underbump metallurgy (UBM) in direct physical contact with the contact pad, wherein a portion of the UBM is buried in the passivation layer, and forming a conductive connector in direct physical contact with the UBM, wherein the conductive connector and the contact pad are on opposite sides of the UBM. In one embodiment, the intermediate region is located between the first seal ring and the second seal ring and is free of active circuitry. In one embodiment, the method further includes, after bonding the first metallization structure of the first semiconductor die to the second metallization structure of the semiconductor device, bonding a carrier substrate to the semiconductor substrate of the semiconductor device opposite the first metallization structure. In one embodiment, the first seal ring surrounds the second metallization structure to electrically isolate the second metallization structure from the fourth metallization structure within the semiconductor device.

[0124] The foregoing summarizes the features of several embodiments so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations thereto without departing from the spirit and scope of the present disclosure.

[0125] 100:Semiconductor wafer 101: first semiconductor device region 102: Middle District 103: First base 105: first metallization layer 107: First active device 111: first substrate through hole 151: First metallization layer through hole opening 153: Dielectric materials 155: first conductive structure 175: Sealing ring 201: First metallization layer through hole 207: first conductive bonding pad 209: first wafer bonding layer 301: Second active device 303, 1083, 2503: dielectric 305: second conductive structure 307: Second metallization layer through hole 313: first semiconductor grain 315: second semiconductor grain 317: Second base 319: Second metallization layer 321: Second wafer bonding layer 323: second conductive bonding pad 350: First local interconnect die 351: First interconnect substrate 353: First internal connection structure 355: first interconnect metallization pattern 357: First interconnect dielectric layer 375: first internal connection conductive pad 401: first encapsulation 500: first carrier substrate 501: first bonding layer 503: Second bonding layer 601: Depression 701: first passivation film 800: First backside redistribution circuit structure 801: Redistribution of metallization layer 803: Redistribution of dielectric layer 805: Re-routing conductive elements 807: First metallized contact pad 809: First passivation layer 811: First under-bump metallurgy 818: first conductive connection 850: first semiconductor package 1000: second carrier substrate 1001: third semiconductor grain 1003: fourth semiconductor grain 1005: Second local interconnect die 1021: Second interconnect substrate 1023: Second internal connection structure 1025: Second interconnect metallization pattern 1027: Second interconnect dielectric layer 1051: third bonding layer 1071: Third Active Device 1077: Third Base 1079: Third metallization layer 1081: third conductive structure 1101: Second enclosure 1200: third carrier substrate 1201: Fourth bonding layer 1203: Fifth bonding layer 1300: First carrier removal process 1401:Third metallization layer through hole 1409: Third wafer bonding layer 1411: third conductive bonding pad 1501: First semiconductor device 1503: Second semiconductor device 1553: First device substrate 1555: First device metallization layer 1557, 2057: Fourth active device 1559: First device metallization layer through hole 1561: First device substrate through hole 1563: First device bonding layer 1565: First device conductive bonding material 1601: The third enclosure 1701: Second passivation film 1850: Second semiconductor package 2000: The fourth carrier base 2001: Third Semiconductor Device 2003: Fourth Semiconductor Device 2050: Third local interconnect structure 2053: Second device substrate 2055: Second device metallization layer 2061: Second device substrate through hole 2071: Sixth bonding layer 2073: Seventh bonding layer 2101: Fourth enclosure 2200: fifth carrier substrate 2251: Eighth bonding layer 2253: Ninth bonding layer 2300: Second carrier removal process 2401: Second device metallization layer through hole 2403: Fourth wafer bonding layer 2405: fourth conductive bonding pad 2501: Fifth Active Device 2505: fourth conductive structure 2507: Fourth metallization layer through hole 2513: Fifth semiconductor grain 2515: Sixth semiconductor grain 2517: Fourth Base 2519: Fourth metallization layer 2521: Fifth wafer bonding layer 2523: fifth conductive bonding pad 2550: Third local interconnect die 2557: Third interconnect dielectric layer 2571:Third interconnect base 2573: Third internal connection structure 2575: Third interconnect metallization pattern 2601: Fifth enclosure 2700: Sixth carrier substrate 2751: Tenth bonding layer 2753: Eleventh bonding layer 2800: Third carrier removal process 2901: Third passivation film 3050: Third semiconductor package 3201:TSV guard ring 3203: Deep Trench Capacitor AA: Segment cutting line

Claims

1. A method for manufacturing a semiconductor device, comprising: A first semiconductor die is bonded to a first side of a first semiconductor device, the first semiconductor device including a first region of an active circuit system and a second region of an active circuit system, the second region of the active circuit system being electrically isolated from the first region of the active circuit system; a second semiconductor die is bonded to the first side of the first semiconductor device and adjacent to the first semiconductor die; a partial interconnect die is bonded to the first side of the first semiconductor device and between the first semiconductor die and the second semiconductor die, wherein the partial interconnect die is electrically connected from the first region of the active circuit system to the second region of the active circuit system. And forming a redistribution circuit structure on a second side of the first semiconductor device opposite to the first side, wherein forming the redistribution circuit structure includes: forming a plurality of dielectric layers on the second side of the first semiconductor device, the second side being opposite to the first side; And a plurality of metallization layers are formed within the plurality of dielectric layers.

2. The method of claim 1, wherein the first region of the active circuit system and the second region of the active circuit system are disposed on the same semiconductor substrate.

3. The method of claim 2, further comprising forming a first sealing ring and a second sealing ring within the first semiconductor device before bonding the first semiconductor die to the first semiconductor device, wherein the first sealing ring surrounds a first region of the active circuit system and the second sealing ring surrounds a second region of the active circuit system.

4. The method of claim 3, wherein after the local interconnect die is attached to the first semiconductor device, the local interconnect die directly covers the first sealing ring, the second sealing ring, and the intermediate region disposed between the first sealing ring and the second sealing ring.

5. A semiconductor device, comprising: A semiconductor device includes: a semiconductor substrate; a plurality of first substrate vias and a plurality of second substrate vias extending through the semiconductor substrate; an interconnect structure disposed above the semiconductor substrate, the interconnect structure including a plurality of first metallization patterns electrically coupled to the plurality of first substrate vias and a plurality of second metallization patterns electrically coupled to the plurality of second substrate vias; a first sealing ring surrounding the plurality of first metallization patterns and defining a first semiconductor region; and a second sealing ring surrounding the plurality of second metallization patterns and defining a second semiconductor region; a partial interconnect structure joining both the first semiconductor region and the second semiconductor region, wherein the partial interconnect structure directly covers the first sealing ring and the second sealing ring, wherein in a plan view along the stacking direction of the semiconductor device and the partial interconnect structure, the partial interconnect structure extends from the first semiconductor region to the second semiconductor region; and a first redistributed wiring structure disposed on the semiconductor device, the first redistributed wiring structure being electrically connected to the first semiconductor region through the plurality of first substrate vias and electrically connected to the second semiconductor region through the plurality of second substrate vias.

6. The semiconductor device as claimed in claim 5, further comprising: The first semiconductor die is bonded to the first semiconductor region; And a second semiconductor die, which is bonded to the second semiconductor region.

7. The semiconductor device of claim 6, wherein the first semiconductor region is electrically coupled to the second semiconductor region through the local interconnect structure, the first semiconductor die is electrically coupled to the first semiconductor region, and the second semiconductor die is electrically coupled to the second semiconductor region.

8. The semiconductor device of claim 6, wherein the first semiconductor die and the second semiconductor die are embedded in a molding compound.

9. The semiconductor device of claim 5, wherein the first semiconductor region within the semiconductor element is electrically isolated from the second semiconductor region.

10. A method of manufacturing a semiconductor device, comprising: A first metallization structure is bonded to a second metallization structure of a semiconductor device, wherein the second metallization structure is surrounded by a first sealing ring; A third metallization structure of a second semiconductor die is bonded to a fourth metallization structure of the semiconductor device, wherein the fourth metallization structure is surrounded by a second sealing ring; a fifth metallization structure of a local interconnect die is bonded to both the second and fourth metallization structures of the semiconductor device, wherein the fifth metallization structure overlaps both the first and second sealing rings, wherein in a plan view along the stacking direction of the semiconductor device and the local interconnect die, the local interconnect die extends from the second metallization structure to the fourth metallization structure; and a first redistribution circuit structure is formed on the side of the semiconductor device opposite to the side where the first semiconductor die, the second semiconductor die, and the local interconnect die are disposed.

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