Display device and driving method

Abstract

This disclosure relates to a display device capable of stably driving a threshold voltage of a transistor and a driving method for such a display device. The display device may include a display area and a bezel area. First and second switches may be disposed in the bezel area. The first switch may be connected between a first voltage line and a first sub-pixel, and the second switch may be connected between a second voltage line and the first sub-pixel. During an initialization cycle, the first switch may be turned on to provide a first voltage to the first sub-pixel; during an emission cycle, the second switch may be turned on to provide a second voltage to the first sub-pixel.

Description

Display Device and Driving Method The present disclosure generally relates to an electronic device with a display, and more particularly, but not limited to, a display device and a method for driving such a display device. With the development of the information society, various demands for display devices used to display images have also increased. Recently, various types of display devices such as liquid crystal display (LCD) devices and organic light emitting diode (OLED) display devices have been developed and widely used. In order to increase the pixels per inch (PPI), that is, the number of pixels within one inch, it is preferable to further increase the circuit integration degree of the display panel. The display panel may include driving transistors for driving light-emitting elements. When driving the driving transistor, a body voltage may be provided to the body of the driving transistor. In this case, a body effect may occur depending on the body voltage. Just because it is mentioned in or related to this section does not mean that the foregoing content is prior art. The foregoing content may include information on one or more aspects of the subject technology, and the description in this section does not constitute a limitation to this case. The inventors of the present disclosure have also recognized the problems and deficiencies in the prior art and have conducted extensive research and experiments. Therefore, the inventors of the present disclosure have invented a new display device and a new method for driving such a display device, which largely avoid one or more problems caused by the limitations and deficiencies of the related technology. In one or more aspects, in order to increase the circuit integration degree of the display panel, it is desirable to reduce the number of components on the display panel. In addition, when the body voltage is provided to the driving transistor, the threshold voltage of the driving transistor may change due to the body effect. To solve these problems, one or more aspects of the present disclosure may provide a display device capable of stably controlling the threshold voltage of the driving transistor, and a driving method for such a display device. One or more aspects of the present disclosure may provide a display device and a driving method for such a display device, which can configure the circuit provided in the display panel with an improved integration degree. One or more aspects of the present disclosure may provide a display device and a driving method for such a display device, so as to configure the circuit in the display panel with an improved integration degree, thereby enabling the display device to be driven with low power consumption. According to one or more aspects of the present disclosure, a display device can be provided. The display device includes: a display area in which a plurality of sub-pixels including a first sub-pixel are placed; a border area different from the display area; a plurality of voltage lines arranged in the border area and including at least one driving voltage line and at least one reference base voltage line; and a first switch and a second switch provided in the border area. The first switch is electrically connected between the base voltage line and the first sub-pixel, and the second switch is electrically connected between the first voltage line among the plurality of voltage lines and the first sub-pixel. According to one or more aspects of the present disclosure, a driving method of the display device may include: providing an initialization period in which the first switch provided in the border area is turned on and a first voltage is provided to the first sub-pixel provided in the display area; and providing a light-emitting period in which the second switch provided in the border area is turned on, a second voltage is provided to the first sub-pixel, and the first sub-pixel emits light. According to one or more aspects of the present disclosure, a display device and a driving method thereof can be provided, and the display device can stably control the threshold voltage of a driving transistor. According to one or more aspects of the present disclosure, a display device and a driving method of the display device can be provided to configure the circuit provided in the display panel with improved integration. According to one or more aspects of the present disclosure, a display device and a driving method of the display device can be provided to configure the circuit provided in the display panel with improved integration, and further configure the circuit in the display panel with the improved integration, so as to be able to drive the display device with low power consumption. Other features, advantages, and aspects of the present disclosure will be partially explained hereinafter and partially become apparent from the present disclosure, or can be learned through practicing the inventive concept provided herein. Other features, advantages, and aspects of the present disclosure can be realized and achieved through the description provided in the present disclosure, or the description derived therefrom, the scope of the invention patent application of the present disclosure, and the drawings. All these features, advantages, and aspects are included in this specification, belong to the scope of the present disclosure, and are protected by the following invention patent application scope. Any content in this section should not be regarded as a limitation to these invention patent application scopes. More aspects and advantages will be discussed in combination with the embodiments of the present disclosure hereinafter. It should be understood that the descriptions before and after the content of the present disclosure are all examples, aiming to further explain the present disclosure claimed. Now, the embodiments of the present disclosure will be described in detail, and examples thereof can be seen in the drawings. In the following description, when a detailed description of well-known methods, functions, structures or configurations may unnecessarily make various aspects of the present disclosure difficult to understand, such detailed description may be omitted for the sake of brevity. In addition, for the sake of brevity, repeated descriptions may be omitted. The progress of the described processing steps and / or operations is a non-limiting example. The order of steps and / or operations is not limited to the order illustrated herein and may be different from the order illustrated herein, except in cases where the steps and / or operations must be performed in a specific order. In one or more instances, depending on the functions or operations involved, two consecutive operations may be performed substantially simultaneously, or these two steps may be executed in the reverse or different order. Unless otherwise specified, even if shown in different drawings, similar element symbols indicate similar elements. Unless otherwise specified, throughout the specification and drawings, the same element symbols may indicate the same or substantially the same elements. Unless otherwise specified, in one or more aspects, the same elements (or elements with the same name) in different drawings may have the same or substantially the same functions and characteristics. The names of the various elements used in the following description are selected for convenience only and may therefore be different from the names of the elements used in actual products. The advantages and features of the present disclosure and the implementation methods of the present disclosure are clarified by describing the embodiments with reference to the drawings. However, the present disclosure can be embodied in different forms and should not be construed as limited to the embodiments described herein. On the contrary, these embodiments are examples and are provided to make the content of the present disclosure comprehensive and complete to help those with ordinary knowledge in the art understand the concept of the present invention, and these embodiments do not limit the protection scope of the present disclosure. The shapes, dimensions (such as size, length, width, height, thickness, position, radius, diameter and area), proportions, ratios, angles, numbers, the number of elements, etc. shown in the drawings disclosed herein are only examples, and therefore, the present disclosure is not limited to the details illustrated. However, it should be noted that the relative dimensions of the elements shown in the drawings are part of the present disclosure. When terms such as "comprising", "having", "including", "containing", "constituting", "made of", "formed from", "composed of" or similar terms are used with respect to one or more elements (e.g., layer, film, region, component, part, element, component, region, area, part, step, operation, and / or similar terms), one or more additional elements may be added unless terms such as "only" or similar terms are used. The terms used in this disclosure are only for describing specific exemplary embodiments and are not intended to limit the scope of this disclosure. Unless the context clearly indicates otherwise, terms in the singular form may include the plural form. The term "exemplary" is used to refer to an example or illustration. An embodiment is an exemplary embodiment. An aspect is an exemplary aspect. "Embodiment", "example", "aspect", etc. should not be understood as being a preferred implementation or superior to other implementations. Unless otherwise stated, an embodiment, an example, an exemplary embodiment, an aspect, etc. may refer to one or more embodiments, one or more examples, one or more exemplary embodiments, one or more aspects, etc. In addition, the term "may" includes all meanings of the term "can". In one or more aspects, unless otherwise clearly stated, an element, feature or corresponding information (such as a level, range, dimension, size or similar information) shall be construed as including an error or tolerance range, even if such error or tolerance range is not explicitly stated. The error or tolerance range may be caused by various factors (such as, process factors, internal or external influences, noise and other factors). When interpreting a numerical value, unless otherwise clearly stated, the numerical value shall be construed as including an error range. When describing the positional relationship between two elements (e.g., layer, film, region, component, part, element, component, region, area, component) using any one of the terms that indicate a position or a specific area, such as "above", "above the top", "on the upper surface", "top", "above", "below", "on top", "upper part", "lower part", "underneath", "near", "close to", "adjacent to", "beside", "next to", "located on or at one side", etc., one or more other elements may be located between these two elements, unless more restrictive terms such as "immediately", "directly", or "right next to" are used. For example, when describing one element in relation to other elements using any of the aforementioned terms, such a description should be interpreted as including the situation where the two elements are in direct contact with each other and the situation where one or more other elements are placed or inserted between the two elements. In addition, spatial relationship terms, such as the aforementioned terms and other terms such as "front", "back", "rear", "left", "right", "top", "bottom", "downward", "upward", "above", "below", "column", "row", "vertical", "horizontal", "diagonal", etc., all refer to an arbitrary reference system. For example, these terms can be used to understand examples of the relative relationship between elements, including any relevant relationships as shown in the diagrams. However, the embodiments of the present disclosure are not limited to this. Spatial relative terms should be understood to include different orientations of the elements during use or operation, in addition to the orientations depicted in the figures or described in the text. For example, when a lower element or an element located below another element is flipped, that element can be referred to as an upper element or an element located above another element. Thus, for example, the term "below" or "beneath" can include the meaning of the term "above" or "over". For example, the exemplary term "under the surface" or a similar term can include all directions, which include "below", "above", and diagonal directions. Similarly, the exemplary terms "on the upper surface", "above", or similar terms can include all directions, which include "above", "over", "below", and diagonal directions. When describing a time relationship, when describing the time sequence using terms such as "after", "subsequently", "next", "before", "previously", "prior to this", or similar terms, it may include non - consecutive situations or non - sequential situations, and thus one or more other events may occur between the two, unless more restrictive words such as "just", "immediately", or "directly" are used. It will be understood that although terms such as "first", "second", etc. may be used herein to describe various elements (layers, films, regions, components, parts, elements, components, regions, parts, steps, operations, and / or similar elements), these elements should not be limited by these terms. For example, they should not be limited by a specific order, sequence, or number of elements. These terms are only used to distinguish one element from other elements. For example, a first element may be labeled as a second element, and similarly, a second element may be labeled as a first element, without departing from the scope of the present disclosure. In addition, the first element, the second element, etc. may be arbitrarily named for the convenience of those of ordinary skill in the art, without departing from the scope of the present disclosure. For clarity, the functions or structures of these elements (such as the first element, the second element, etc.) are not limited by the serial number or the name in front of the element. In addition, the first element may include one or more first elements. Similarly, the second element or a similar element may include one or more second elements or similar elements. In the process of describing the elements of the present disclosure, terms such as "first", "second", "A", "B", "(a)", "(b)", or similar terms may be used. These terms are intended to identify the corresponding elements from other elements, rather than to define the nature, basis, order, or number of the elements. For the description of an element (such as a layer, film, region, component, part, element, component, region, part, step, operation, and / or similar element) being "connected", "coupled", "attached", "adhered", or otherwise combined to another element, unless otherwise specified, the element can not only be directly connected, coupled, attached, adhered, or otherwise combined to the other element, but also be indirectly connected, coupled, attached, adhered, or otherwise combined to the other element with one or more intermediate elements placed or inserted therebetween. For the representation of an element (such as a layer, film, region, component, part, element, component, region, part, step, operation, and / or similar element) being "in contact", "overlapping", or otherwise combined to another element, unless otherwise specified, this element can not only be directly in contact, overlapping, or otherwise combined with the other element, but also be indirectly in contact, overlapping, or otherwise combined with the other element with one or more intermediate elements placed or inserted therebetween. For example, the phrase that one element (e.g., a layer, a film, a region, a component, a part, an element, a member, a region, a portion, etc.) is "disposed", "placed", "connected", "coupled" or the like in, on, or to another element can be interpreted as at least a part of the element being disposed in, placed in, connected to, or coupled to at least a part of the other element. For example, the phrase "through" can be understood as partially through or entirely through. For example, when an element (e.g., a layer, a film, a region, a component, a part, an element, a member, a region, a portion, etc.) is described with terms such as "contact", "cover", or the like with another element, it should be interpreted that at least a part of this element contacts, covers, or is combined with at least a part of the other element in a similar manner. Terms such as "line" or "direction" should not be interpreted only based on the geometric relationships where the respective lines or directions are parallel, perpendicular, diagonal, or inclined to each other, and can be understood to have a broader directivity within the range where the components in the present disclosure can perform functional operations. The term "at least one" should be interpreted as any combination or all combinations of one or more of the relevant listed items. For example, each of the phrases "at least one of the first item, the second item, or the third item" and "at least one of the first item, the second item, and the third item" can represent (i) a combination of items provided by two or more of the first item, the second item, and the third item, or (ii) only one of the first item, the second item, or the third item. The expression of the first element, the second element "and / or" the third element should be understood as one of the first element, the second element, and the third element, or any or all combinations of the first element, the second element, and the third element. For example, A, B, and / or C can refer to only A; only B; only C; any one of A, B, and C (e.g., A, B, or C); a certain combination of A, B, and C (e.g., A and B; A and C; or B and C); or all of A, B, and C. In addition, the expression "A / B" can be understood as A and / or B. For example, the expression "A / B" can refer to only A; only B; A or B; or A and B. In one or more aspects, unless otherwise specified, for convenience, the terms "between" and "among" can be used interchangeably. For example, the expression "between a plurality of elements" can be understood as among a plurality of elements. In another example, "among a plurality of elements" can be understood as between a plurality of elements. In one or more instances, the number of elements can be two. In one or more instances, the number of elements can be more than two. In addition, when an element (e.g., a layer, a film, a region, a component, a part, an element, a member, a region, a portion, etc.) is said to be located "between" at least two elements, the element can be the only element between the at least two elements, or can be one or more intermediate elements. In one or more aspects, for convenience, unless otherwise specified, the two phrases "each other" and "one another" can be used interchangeably. For example, the expression "different from each other" can be understood as being different from each other. In another example, "different from each other" can be understood as being different from another. In one or more instances, the number of elements involved in the foregoing expression can be two. In one or more instances, the number of elements involved in the foregoing expression can be more than two. In one or more aspects, unless otherwise specified, the two phrases "one or more of" and "one or more among" can be used interchangeably, solely for convenience. In one or more aspects, unless otherwise specified, the term "n-th" can refer to "n-nd" (e.g., the second means n is 2) or "n-rd" (e.g., the third means n is 3), and n can be a natural number. The term "or" refers to "inclusive or", rather than "exclusive or". That is to say, unless otherwise specified or clearly apparent from the context, the expression "x uses a or b" refers to any natural inclusive arrangement. For example, "a or b" can refer to "a", "b", or "a and b". For example, "a, b, or c" can refer to "a", "b", "c", "a and b", "b and c", "a and c", or "a, b, and c". The features of the various embodiments of the present disclosure can be partially or wholly coupled or combined with each other, can be technically interrelated, and can be operated, linked, or driven together in various ways. The embodiments of the present disclosure can be implemented or executed independently of each other, or can be implemented or executed together in a co-dependent relationship or a related relationship. In one or more aspects, each device and component of the various embodiments according to the present disclosure is operably coupled and configured. Unless otherwise defined, the terms used herein (including technical terms and scientific terms) have the same meaning as commonly understood by those of ordinary skill in the technical field to which the example embodiments belong. It should also be understood that terms (such as terms defined in a common dictionary) should be interpreted as having a meaning consistent with, for example, the meaning in the relevant technical background, and should not be given an idealized interpretation or an overly formal interpretation, unless otherwise clearly defined herein. The terms used herein are common terms in the relevant technical field, but there may be other terms according to the development and / or changes of the technology, conventions, preferences of those of ordinary skill, etc. Therefore, the terms used herein should not be understood as a limitation on the technical concept, but should be understood as examples of terms used to describe exemplary embodiments. In addition, in specific situations, the applicant can arbitrarily select terms, and in such situations, the detailed meaning of the terms is explained herein. Therefore, the terms used herein should be understood not only according to the name of the terms, but also according to the meaning and content of the terms. In the following description, various embodiments of the present disclosure are described with reference to the drawings. Regarding the reference symbols of the elements in the drawings, since the same elements may be shown in other drawings, unless otherwise specified, similar reference symbols may indicate similar elements. Even if shown in different drawings, the same or similar elements may be labeled with the same reference symbol. In addition, for ease of description, the proportions, dimensions, sizes, and thicknesses of the elements shown in the drawings may be different from the actual proportions, dimensions, sizes, and thicknesses. Therefore, the embodiments of the present disclosure are not limited to the proportions, dimensions, sizes, and thicknesses shown in the drawings. FIG. 1 shows an exemplary system structure of a display device 100 according to various aspects of the present disclosure. Referring to FIG. 1, the display device 100 may include a display panel 110 and at least one driving circuit for driving the display panel 110. For example, the display panel 110 may include a silicon material. In an example where the display panel 110 includes a silicon material and organic light emitting elements such as organic light emitting diodes (OLEDs), this display panel 110 may be referred to as an OLED-on-silicon (OLEDoS) panel. The display panel 110 may also include glass. The display panel 110 may include a plurality of signal lines, such as a plurality of data lines DL and a plurality of gate lines GL, and the display panel includes a plurality of sub-pixels SP. The display panel 110 may include a display area AA for displaying an image; and a border area BA for not displaying an image. The plurality of sub-pixels SP for displaying an image may be disposed in the display area AA of the display panel 110. The driving circuits (data driving circuit 120, gate driving circuit 130, and controller 140) may be electrically connected to or mounted on the border area BA of the display panel 110. In addition, a pad portion connected to at least one integrated circuit or at least one printed circuit board may be provided in the border area BA of the display panel 110. At least one driving circuit may include a data driving circuit 120, a gate driving circuit 130, etc., and further includes a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130. The data driving circuit 120 may be a circuit for driving a plurality of data lines DL and may provide data signals to these data lines DL. The gate driving circuit 130 may be a circuit for driving a plurality of gate lines GL and may provide gate signals to these gate lines GL. The gate driving circuit 130 can provide a gate signal with a conduction-level voltage or a gate signal with a cut-off level voltage according to the control of the controller 140. The gate driving circuit 130 can drive these gate lines GL in sequence by sequentially providing a gate signal with a conduction-level voltage to a plurality of gate lines GL. The controller 140 can provide a data control signal DCS to the data driving circuit 120 to control the operation timing of the data driving circuit 120. The controller 140 can provide a gate control signal GCS to the gate driving circuit 130 to control the operation timing of the gate driving circuit 130. The controller 140 can start scanning pixels according to the respective timings set in each frame, convert the image data input from an external device or an external image source (such as a host system) into a data signal form readable by the data driving circuit 120, then provide the converted image data Data to the data driving circuit 120, and load the image data to at least one pixel when at least one corresponding light-emitting element of at least one pixel needs to emit light according to the scanning of at least one pixel (or at least one pixel array) in the pixel. To control the data driving circuit 120 and the gate driving circuit 130, the controller 140 can receive timing signals such as a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, a clock signal CLK, etc., generate various control signals (data control signal DCS, gate control signal GCS, and / or similar signals), and output the generated signals to the data driving circuit 120 and the gate driving circuit 130. The controller 140 can be implemented as a component separate from the data driving circuit 120 or integrated into the data driving circuit 120, so that the controller 140 and the data driving circuit 120 can be implemented in an integrated circuit. The data driving circuit 120 can drive these data lines DL by providing the data voltage corresponding to the image data Data received from the controller 140 to a plurality of data lines DL. The data driving circuit 120 can also be referred to as a source driving integrated circuit. For example, the data driving circuit 120 can include one or more source driver integrated circuits (SDICs). Each source driver integrated circuit SDIC can include: a shift register, a latch circuit, a digital-to-analog converter DAC, an output buffer, etc. In one or more exemplary embodiments, each source driver integrated circuit SDIC can also include an analog-to-digital converter ADC. In one or more exemplary embodiments, each source driver integrated circuit (SDIC) may be connected to the display panel 110 using tape-automated-bonding (TAB) technology, connected to a conductive pad (e.g., a bonding pad of the display panel 110) using Chip On Glass (COG) technology or chip-on-panel (COP) technology, or implemented in the display panel 110 using Chip On Film (COF) technology. In one or more example embodiments, the gate driver circuit 130 may be connected to the display panel 110 using TAB technology, connected to a conductive pad (such as a bonding pad of the display panel 110) using COG technology or COP technology, or implemented in the display panel 110 using COF technology. In one or more exemplary embodiments, the gate driver circuit 130 may be formed in the border area BA of the display panel 110 using gate-in-panel (GIP) technology. When a specific gate line is selected and driven by the gate driver circuit 130, the data driver circuit 120 may convert the image data Data received from the controller 140 into a data voltage in analog form and supply the converted data voltage to a plurality of data lines DL. The data driver circuit 120 may be located only on and / or electrically connected to one side or a part (e.g., the upper edge or the lower edge) of the display panel 110, but this does not limit the present disclosure. In one or more exemplary embodiments, depending on the driving scheme, the panel design scheme, or other factors, the data driver circuit 120 may be located on and / or electrically connected to two sides or two parts (e.g., the upper edge and the lower edge) of the display panel 110 or at least two sides or at least two parts of the four sides or four parts (e.g., the upper edge, the lower edge, the left edge, and the right edge) of the display panel 110, but this does not limit the present disclosure. The gate driver circuit 130 may be located only on and / or electrically connected to one side or a part (e.g., the left edge or the right edge) of the display panel 110, but this does not limit the present disclosure. In one or more exemplary embodiments, depending on the driving scheme, the panel design scheme, or other factors, the gate driver circuit 130 may be located on and / or electrically connected to two sides or two parts (e.g., the upper edge and the lower edge) of the display panel 110 or at least two sides or at least two parts of the four sides or four parts (e.g., the upper edge, the lower edge, the left edge, and the right edge) of the display panel 110, but this does not limit the present disclosure. The controller 140 may be a timing controller used in typical display technologies, or may be a control device / apparatus capable of additionally performing other control functions in addition to the timing controller. In one or more exemplary embodiments, the controller 140 may be one or more other control circuits different from the timing controller, or the controller 140 may be a circuit or component in the control device / apparatus. The controller 140 may be implemented using various circuits or electronic components, such as integrated circuits (ICs), field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), processors, and / or similar devices. The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or a similar device, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, or a similar device. The controller 140 may transmit signals to the data driving circuit 120 through one or more predetermined interfaces and receive signals from the data driving circuit 120. For example, such an interface may include a low voltage differential signaling (LVDS) interface, an embedded clock point-point interface (EPI), a serial peripheral interface (SPI), etc. The controller 140 may include a storage medium or one or more storage locations, such as one or more registers. In one or more aspects, the display device 100 may be a self-emitting display with or without a backlight unit, such as an organic light emitting diode (OLED) display, a quantum dot (QD) display, a micro light emitting diode (M-LED) display, etc. FIG. 2 shows a schematic equivalent circuit of the sub-pixel SP included in the display device 100 according to various aspects of the present disclosure. Referring to FIG. 2, the display panel 110 may include a plurality of sub-pixels SP disposed on the substrate SUB. The display panel 110 may include a silicon material or a glass substrate. Referring to FIG. 2, in one or more exemplary embodiments, each sub-pixel SP among the multiple sub-pixels SP disposed in the display panel 110 of the display device 100 may include: a light-emitting element ED, a driving transistor DRT, a scanning transistor SCT, a sensing transistor SENT, a storage capacitor Cst, etc. Such a circuit structure in which one sub-pixel SP is configured with three transistors (i.e., "3T" means: a driving transistor DRT, a scanning transistor SCT, and a sensing transistor SENT) and one capacitor (i.e., "1C" means: a storage capacitor Cst) can thus be referred to as a "3T1C structure". The light-emitting element ED may include: a pixel electrode PE, a common electrode CE, and a light-emitting layer EL disposed between the pixel electrode PE and the common electrode CE. For example, the pixel electrode PE may be disposed in each sub-pixel SP, and the common electrode CE may generally be disposed in all of the multiple sub-pixels SP or in two or more sub-pixels SP. For example, the pixel electrode PE may be an anode electrode, and the common electrode CE may be a cathode electrode. In another example, the pixel electrode PE may be a cathode electrode, and the common electrode CE may be an anode electrode. In one or more exemplary embodiments, the light-emitting element ED may be an organic light-emitting diode (OLED), a light-emitting element configured with quantum dots, a micro light-emitting diode (µ-LED), a light-emitting diode (LED) based on inorganic materials, etc. In the example where the light-emitting element ED is an organic light-emitting diode (OLED), the display panel 110 may be a silicon-based OLED (OLEDoS) panel. The driving transistor DRT may be a transistor for driving the light-emitting element ED and may include a first node N1, a second node N2, a third node N3, etc. The first node N1 of the driving transistor DRT may be the gate node of the driving transistor DRT and may be electrically connected to the source node or drain node of the scanning transistor SCT. The second node N2 of the driving transistor DRT may be the source node or drain node of the driving transistor DRT. The second node N2 may be electrically connected to the source node or drain node of the sensing transistor SENT, and the second node N2 may also be connected to the pixel electrode PE of the light-emitting element ED. The third node N3 of the driving transistor DRT may be electrically connected to the driving voltage line DVL for transmitting a driving voltage EVDD. The scanning transistor SCT may be controlled by a scanning signal SCAN and may be connected between the first node N1 of the driving transistor DRT and the data line DL. The scanning transistor SCT may be turned on or off through the scanning signal SCAN transmitted as a scanning signal line SCL of a gate line GL and controls the electrical connection between the data line DL and the first node N1 of the driving transistor DRT. The scanning transistor SCT can be turned on by a scanning signal SCAN having a conduction-level voltage, and cause a data voltage Vdata transmitted through a data line DL to pass through a first node of a driving transistor DRT. The conduction-level voltage of the scanning signal SCAN for turning on the scanning transistor SCT can be a high-level voltage or a low-level voltage. The turn-off level voltage of the scanning signal SCAN for turning off the scanning transistor SCT can be a low-level voltage or a high-level voltage. In an example where the scanning transistor SCT is an n-type transistor, the conduction-level voltage can be a high-level voltage, and the turn-off level voltage can be a low-level voltage. In another example where the scanning transistor SCT is a p-type transistor, the conduction-level voltage can be a low-level voltage, and the turn-off level voltage can be a high-level voltage. The sensing transistor SENT can be controlled by a sensing signal SENSE and can be connected between a second node N2 of the driving transistor DRT and a reference voltage line RVL. The sensing transistor SENT can be turned on or off by a sensing signal SENSE transmitted through a sensing signal line SENL (another type of gate line GL), and control the electrical connection between the second node N2 of the driving transistor DRT and the reference voltage line RVL. The sensing transistor SENT can be turned on by a sensing signal SENSE having a conduction-level voltage, and transmit a reference voltage Vref to the second node N2 of the driving transistor DRT through the reference voltage line RVL. The conduction-level voltage of the sensing signal SENSE for turning on the sensing transistor SENT can be a high-level voltage or a low-level voltage. The turn-off level voltage of the sensing signal SENSE for turning off the sensing transistor SENT can be a low-level voltage or a high-level voltage. In an example where the sensing transistor SENT is an n-type transistor, the conduction-level voltage can be a high-level voltage, and the turn-off level voltage can be a low-level voltage. In another example where the sensing transistor SENT is a p-type transistor, the conduction-level voltage can be a low-level voltage, and the turn-off level voltage can be a high-level voltage. In one or more exemplary embodiments, the display device 100 may further include a line capacitor Crvl formed between the reference voltage line RVL and a ground terminal GND, a sampling switch SAM for controlling the connection between the reference voltage line RVL and an analog-to-digital converter ADC, and a power switch SPRE for controlling the connection between the reference voltage line RVL and a reference voltage power node Nref. The reference voltage Vref output from a power supply can be provided to the reference voltage power node Nref, and then applied to the reference voltage line RVL through the power switch SPRE. In addition, the sensing transistor SENT can be turned on by the sensing signal SENSE having a conduction-level voltage, so that the voltage on the second node N2 of the driving transistor DRT is transmitted to the reference voltage line RVL. Therefore, the line capacitor Crvl formed between the reference voltage line RVL and the ground terminal GND can be charged. Here, the characteristic value of the sub-pixel SP can be the characteristic value of the driving transistor DRT or the light-emitting element ED. The characteristic value of the driving transistor DRT can include the threshold voltage and / or mobility of the driving transistor DRT. The characteristic value of the light-emitting element ED can include the threshold voltage of the light-emitting element ED. Each of the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT can be an n-type transistor or a p-type transistor. Here, for ease of description, an example in which the driving transistor DRT, the scanning transistor SCT, and the sensing transistor SENT are all based on n-type transistors will be discussed. The storage capacitor Cst can be connected between the first node N1 and the second node N2 of the driving transistor DRT. The storage capacitor Cst can store the charge amount corresponding to the voltage difference between both ends and maintain the voltage difference between both ends within a predetermined frame time. Therefore, the corresponding sub-pixel SP can emit light within a predetermined frame time. The storage capacitor Cst can be an external capacitor intentionally designed to be located outside the driving transistor DRT, rather than an internal capacitor that can be formed between the gate node and the source node (or drain node) of the driving transistor DRT, such as a parasitic capacitance. In one embodiment, the scanning signal line SCL and the sensing signal line SENL can be different gate lines GL. In this embodiment, the scanning signal SCAN transmitted through the scanning signal line SCL and the sensing signal SENSE transmitted through the sensing signal line SENL can be independent gate signals, and the conduction timing and / or the turn-off timing of the scanning transistor SCT and the sensing transistor SENT in one sub-pixel SP can be independent of each other. For example, the conduction timing and / or the turn-off timing of the scanning transistor SCT and the conduction timing and / or the turn-off timing of the sensing transistor SENT in one sub-pixel SP can be the same or different according to design requirements. In another embodiment, the scan signal line SCL and the sense signal line SENL can be the same gate line GL. For example, the gate nodes of the scan transistor SCT and the sense transistor SENT in a sub-pixel SP can be connected to a gate line GL. In this embodiment, the scan signal SCAN transmitted through the scan signal line SCL and the sense signal SENSE transmitted through the sense signal line SENL can be the same gate signal, and the respective turn-on timings and / or turn-off timings of the scan transistor SCT and the sense transistor SENT in a sub-pixel SP can be the same. In one embodiment, the reference voltage line RVL can be provided in each row of sub-pixels SP. In another embodiment, the reference voltage line RVL can be provided in each row of two or more rows of sub-pixels SP. In the embodiment where the reference voltage line RVL is provided in each row of two or more rows of sub-pixels SP, multiple sub-pixels SP can receive the reference voltage Vref through one reference voltage line RVL. Each driving transistor DRT included in the multiple sub-pixels SP provided in the display panel 110 of the display device 100 can have one or more unique characteristic values. For example, the characteristic values of the driving transistor DRT can include: threshold voltage, mobility, etc. The characteristic values of each driving transistor DRT in each sub-pixel SP included in the multiple sub-pixels SP may change over time of driving. The driving times of the sub-pixels SP may be different from each other. For example, the driving times of some sub-pixels SP among the multiple sub-pixels SP may be different from those of one or more other sub-pixels SP or other sub-pixels SP. Therefore, the characteristic values of the corresponding one or more driving transistors DRT of one or more sub-pixels SP among the multiple sub-pixels SP may be different from the characteristic values of the corresponding one or more driving transistors DRT of one or more other sub-pixels SP. Since the characteristic values among the multiple driving transistors DRT provided on the display panel 110 are not the same, there may be a brightness difference among the multiple sub-pixels SP provided on the display panel 110. Therefore, the display panel 110 may exhibit uneven brightness. To solve this problem, in one or more exemplary embodiments, the display device 100 can provide a compensation function, that is, perform sense driving on the sub-pixels SP of the display panel 110, detect the respective characteristic values of the driving transistors DRT, and perform an operation for reducing the difference in characteristic values among the driving transistors DRT. FIG. 3 shows an exemplary equivalent circuit of a sub-pixel SP in the display device 100 according to various aspects of the present disclosure and an exemplary structure of a driving transistor DRT included in the sub-pixel SP. FIG. 4 is an exemplary graph of the threshold voltage according to the body voltage change in the display device 100 according to various aspects of the present disclosure. Referring to FIG. 3, in one or more exemplary embodiments, the sub-pixel SP disposed in the display panel 110 of the display device 100 may include: a light-emitting element ED, a driving transistor DRT, a scanning transistor SCT, a sensing transistor SENT, a storage capacitor Cst, etc. The sub-pixel SP shown in FIG. 3 is substantially the same as the sub-pixel SP shown in FIG. 2. However, the scanning transistor SCT and the sensing transistor SENT in FIG. 2 may be controlled by different signals from each other, which may be referred to as double-scanning driving. On the contrary, the scanning transistor SCT and the sensing transistor SENT in FIG. 3 may be controlled by the same signal, which may be referred to as single-scanning driving. For example, as shown in FIG. 3, the gate node of the scanning transistor SCT and the gate node of the sensing transistor SENT may be electrically connected to the scanning signal line SCL. FIG. 3 is a cross-sectional schematic view of the corresponding driving transistor DRT disposed in a partial region A3 of the sub-pixel SP. The driving transistor DRT may include: a body 310, a drain layer 320, a source layer 330, an active layer 340, a gate insulating layer 350, and a gate layer 360. The drain layer 320, the source layer 330, and the active layer 340 may be disposed on the body 310. As shown in FIG. 3, the drain layer 320 may be electrically connected to the d node d. The source layer 330 may be electrically connected to the s node s. The gate insulating layer 350 may be electrically connected to the g node g. The body 310 may be electrically connected to the b node b. The active layer 340 may be disposed between the drain layer 320 and the source layer 330. The gate insulating layer 350 may be disposed on the active layer 340. The gate layer 360 may be disposed on the gate insulating layer 350. The source layer 330 may be a source node, that is, the third node N3 shown in FIG. 2. The drain layer 320 may be a drain node, and this drain node may be the second node N2 shown in FIG. 2. The driving voltage EVDD may be provided to the drain layer 320. The data voltage Vdata may be provided to the gate layer 360. The reference voltage Vref may be provided to the source layer 330. The driving current may flow from the drain layer 320 to the source layer 330 through the voltage charged in the storage capacitor Cst. Therefore, the driving current may flow along the active layer 340. The driving transistor DRT can have one or more unique features. The unique features of the driving transistor DRT may include the threshold voltage Vth. The threshold voltage Vth of the driving transistor DRT can have an initial threshold voltage value Vt0. The value of the threshold voltage Vth of the driving transistor DRT can change based on external factors. In addition, a body voltage can be provided to the body 310. When the body voltage is provided to the body 310, a body effect may occur. "Body effect" may refer to the phenomenon that the threshold voltage of a transistor changes when a body voltage is provided to the body of the transistor. Figure 4 shows a graph of the change in the threshold voltage with respect to the body voltage. The threshold voltage Vth can be expressed by the following formula: "Threshold voltage (Vth) = Initial threshold voltage (Vt0) + Body effect coefficient (a) × Source-body voltage (Vsb)". The source-body voltage Vsb can be the voltage value obtained by subtracting the voltage of the body 310 from the voltage of the source layer 330. The body effect coefficient (a) can be a coefficient obtained through experiments. When the source-body voltage Vsb is small, the corresponding threshold voltage Vth can be the initial threshold voltage Vt0. However, the corresponding threshold voltage Vth increases as the source-body voltage Vsb increases. When the threshold voltage Vth increases, the image quality may deteriorate due to the increased threshold voltage Vth. Therefore, in order to compensate for the increased threshold voltage Vth, the display device 100 may need to unnecessarily increase the corresponding data voltage Vdata. In particular, when the display panel 110 is an OLEDoS panel, the display device 100 may need to provide a body voltage to the body 310 to ensure stable driving of the corresponding driving transistor DRT. That is to say, in an example where the OLEDoS panel is used as the display panel 110 in the display device 100, the threshold voltage change caused by the body effect may affect the stable driving of the corresponding driving transistor DRT. In addition, in an example of using an OLEDoS panel, in order to achieve ultra-high resolution, each sub-pixel included in the display device 100 may need to be as small as the micron level. And in order to reduce the size of the sub-pixel, it is best to minimize the components included in the sub-pixel. To solve these problems, various aspects of the present disclosure can provide a display device 100 capable of stably controlling the threshold voltage of a driving transistor and a driving method of the display device 100. Various aspects of the present disclosure can provide a display device 100 and its driving method capable of configuring the circuit disposed in the display panel 110 with improved integration. Aspects of the present disclosure can provide a display device 100 and a driving method thereof that can be driven with low power consumption by configuring circuits provided in the display panel 110 with improved integration. FIGS. 5 and 6 illustrate exemplary configurations of a display panel 110 including at least one initialization transistor and at least one light-emitting transistor in a display device 100 according to various aspects of the present disclosure. Referring to FIG. 5, the display panel 110 may include a display area AA and a border area BA. The display area AA may be an area where an image can be displayed, and the border area BA may be an area where no image is displayed. A plurality of sub-pixels SP may be provided in the display area AA. At least one driving circuit, at least one voltage line, at least one signal line, etc. for driving the plurality of sub-pixels SP may be provided in the border area BA. FIG. 5 shows a partial area A5 of the display panel 110. The area A5 of the display panel 110 may include a part of the display area AA and a part of the border area BA. FIG. 5 shows six sub-pixels SP provided in the display area AA. A plurality of initialization transistors (e.g., a first initialization transistor 511 and a second initialization transistor 521) and a plurality of light-emitting transistors (e.g., a first light-emitting transistor 512 and a second light-emitting transistor 522) may be provided in the border area BA. A plurality of voltage lines for electrically connecting the plurality of initialization transistors to the sub-pixels SP may be provided in the border area BA and the display area AA. A plurality of voltage lines for electrically connecting the plurality of light-emitting transistors and the sub-pixels SP may be provided in the border area BA and the display area AA. A plurality of gate lines GL may be provided in the border area BA and the display area AA. The first gate line GL1 may be electrically connected to the first sub-pixel SPa, the second sub-pixel SPb, and the third sub-pixel SPc. The plurality of sub-pixels SP connected to the first gate line GL1 may be referred to as a first row of sub-pixel groups. The first voltage line VL1 may be electrically connected to the first sub-pixel SPa, the second sub-pixel SPb, and the third sub-pixel SPc. The first voltage line VL1 may be electrically connected to the first initialization transistor 511 and the first light-emitting transistor 512. The first initialization transistor 511 may obtain a first initialization signal Init1 through its gate node. The first initialization transistor 511 may be controlled by the first initialization signal Init1. The first initialization transistor 511 may be supplied with a first voltage V1. The first light-emitting transistor 512 can be provided with a first light-emitting signal Em1 through its gate node. The first light-emitting transistor 512 can be controlled by the first light-emitting signal Em1. The first light-emitting transistor 512 can be supplied with a second voltage V2. The first voltage V1 or the second voltage V2 can be provided to the first sub-pixel SPa, the second sub-pixel SPb, and the third sub-pixel SPc under the control of the first initialization signal Init1 and the first light-emitting signal Em1. Since the first voltage V1 or the second voltage V2 can be provided to the sub-pixel SP, the threshold voltage of the driving transistor DRT included in the sub-pixel SP can be stably controlled. The second gate line GL2 can be electrically connected to the fourth sub-pixel SPd, the fifth sub-pixel SPe, and the sixth sub-pixel SPf. The sub-pixels SP connected to the second gate line GL2 can be referred to as the second row sub-pixel group. In the description of FIG. 7 and hereinafter, descriptions of the first column sub-pixel group, the second column sub-pixel group, and the third column sub-pixel group are mentioned. And in the description of the corresponding part, this can be expressed as "the first row sub-pixel group includes the first sub-pixel SP1". In addition, this can also be expressed as "the second row sub-pixel group includes the second sub-pixel SP2, and the third row sub-pixel group includes the third sub-pixel SP3". The second voltage line VL2 can be electrically connected to the fourth sub-pixel SPd, the fifth sub-pixel SPe, and the sixth sub-pixel SPf. The second voltage line VL2 can be electrically connected to the second initialization transistor 521 and the second light-emitting transistor 522. The second initialization transistor 521 can be provided with a second initialization signal Init2 through its gate node. The second initialization transistor 521 can be controlled by the second initialization signal Init2. The second initialization transistor 521 can be provided with the first voltage V1. The second light-emitting transistor 522 can be provided with a second light-emitting signal Em2 through its gate node. The second light-emitting transistor 522 can be controlled by the second light-emitting signal Em2. The second light-emitting transistor 522 can be provided with the second voltage V2. The first voltage V1 or the second voltage V2 can be provided to the fourth sub-pixel SPd, the fifth sub-pixel SPe, and the sixth sub-pixel SPf under the control of the second initialization signal Init2 and the second light-emitting signal Em2. Since the first voltage V1 or the second voltage V2 can be provided to the sub-pixel SP, the threshold voltage of the driving transistor DRT included in the sub-pixel SP can be stably controlled. After the first initialization transistor 511 and the first light-emitting transistor 512 are controlled during the first period, the second initialization transistor 521 and the second light-emitting transistor 522 can be controlled during the second period. The first row of sub-pixel groups can be controlled in a first period, and the second row of sub-pixel groups can be controlled in a second period. During the first period, the driving transistors in the first row of sub-pixel groups can be stably controlled, and the storage capacitors in the first row of sub-pixel groups can be charged with corresponding voltages during the first period to emit light. During the second period, the driving transistors in the second row of sub-pixel groups can be stably controlled, and the storage capacitors in the second row of sub-pixel groups can be charged with multiple voltages during the second period to emit light. A structure in which a sub-pixel includes a light-emitting element and three transistors can be referred to as a "3T1C structure". A structure in which a sub-pixel includes a light-emitting element and two transistors can be referred to as a "2T1C structure". Each of the plurality of sub-pixels SP shown in FIG. 5 can include: a driving transistor, a scanning transistor, a storage capacitor, a light-emitting element, etc. Therefore, each sub-pixel SP shown in FIG. 5 can have a "2T1C structure" or a "3T1C structure". Referring to FIG. 5, the initialization transistor and the light-emitting transistor can be disposed in a part of the border area BA adjacent to any one of the upper edge, lower edge, left edge, and right edge of the display area AA. For example, the initialization transistor and the light-emitting transistor can be disposed in a part of the border area BA. In another example, the initialization transistor and the light-emitting transistor can be disposed in two or more parts of the border area BA. Referring to FIG. 6, the display panel 110 can include a display area AA, a first border area BA1, and a second border area BA2. The first border area BA1 and the second border area BA2 can be located above or in the middle of both sides of the display area AA. Referring to FIGS. 5 and 6, the first initialization transistor 511, the first light-emitting transistor 512, the second initialization transistor 521, and the second light-emitting transistor 522 can be disposed in the first border area BA1. Referring to FIG. 6, the third initialization transistor 531, the third light-emitting transistor 532, the fourth initialization transistor 541, and the fourth light-emitting transistor 542 can be disposed in the second border area BA2. The third initialization signal Init3 can be provided to the gate node of the third initialization transistor 531. The third light-emitting signal Em3 can be provided to the gate node of the third light-emitting transistor 532. The fourth initialization signal Init4 can be provided to the gate node of the fourth initialization transistor 541. The fourth light-emitting signal Em4 can be provided to the gate node of the fourth light-emitting transistor 542. FIG. 7 shows an exemplary configuration of a display panel 110 including the initialization transistor and the light-emitting transistor in the first embodiment in a display device 100 according to various aspects of the present disclosure. FIG. 7 shows that under the control of the first initialization signal Init1 and the first emission signal Em1, a driving voltage EVDD or a basic voltage EVSS can be provided for the first sub-pixel SP1. During the initialization period T_Init, the basic voltage EVSS can be provided for the first sub-pixel SP1, and during the emission period T_Em, the driving voltage EVDD can be provided for the first sub-pixel SP1. Through this operation, the threshold voltage of the driving transistor DRT included in the first sub-pixel SP1 can be stably controlled. The first sub-pixel SP1 shown in FIG. 7 can be the same as the first sub-pixel SPa shown in FIG. 5. A plurality of sub-pixels SP can be provided in the display area AA, and driving circuits, voltage lines, signal lines, etc. for driving the sub-pixels SP can be provided in the border area BA. FIG. 7 shows a sub-pixel SP provided in the display area AA. FIG. 7 shows an initialization transistor 711, an emission transistor 712, a main basic voltage line 750, and a main driving voltage line 760 provided in the border area BA. Referring to FIG. 7, in one or more exemplary embodiments, the sub-pixel SP may include: a light-emitting element ED, a driving transistor DRT, a scanning transistor SCT, a storage capacitor Cst, etc. The driving transistor DRT can be a transistor for driving the light-emitting element ED. The driving transistor DRT can be electrically connected between the second node N2 and the third node N3. The gate node of the driving transistor DRT can be electrically connected to or correspond to the first node N1. The scanning transistor SCT can be electrically connected between the data line DL and the first node N1. The gate node of the scanning transistor SCT can be electrically connected to the first gate line GL1. Through the control of the scanning transistor SCT, a corresponding data voltage Vdata can be provided to the gate node of the driving transistor DRT. The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2. The storage capacitor Cst can be charged with a voltage having a certain level, and the sub-pixel SP can emit light with an expected brightness based on the voltage stored in the storage capacitor Cst. The light-emitting element ED can be electrically connected between the second node N2 and the basic voltage node N_EVSS. The basic voltage node can be a node that provides the basic voltage EVSS. When the light-emitting element ED is driven, an image can be displayed on the display panel 110. The first initialization transistor 711 can be electrically connected between the main basic voltage line 750 and the auxiliary driving voltage line 770. The first initialization transistor 711 can be controlled by the first initialization signal Init1. The main basic voltage line 750 can be located in the border area BA. The main basic voltage line 750 can be a line that provides the basic voltage EVSS to the sub-pixel SP. The first light-emitting transistor 712 can be electrically connected between the main drive voltage line 760 and the auxiliary drive voltage line 770. The first light-emitting transistor 712 can be controlled by the first light-emitting signal Em1. The main drive voltage line 760 can be disposed in the border area BA. The main drive voltage line 760 can be a line for providing the drive voltage EVDD to the sub-pixel SP. The sub-pixel SP shown in FIG. 7 can be driven through the driving timings shown in FIGS. 8 to 15. The driving of the sub-pixel SP shown in FIG. 7 will be described below with reference to FIGS. 8 to 15. FIGS. 8 to 15 illustrate examples of driving timings of the initialization transistor and the light-emitting transistor in the embodiment 1 shown in FIG. 7 in the display panel 110 according to various aspects of the present disclosure. The driving period of the sub-pixel SP may include an initialization period and a light-emitting period. Referring to FIG. 8, the driving period of the sub-pixel SP may include: a first initialization period T_Init1 and a first light-emitting period T_Em1. The first initialization period T_Init1 may be a period for preparing the period for the sub-pixel SP to emit light. The first light-emitting period T_Em1 may be a period during which the sub-pixel SP emits light. The driving period of the sub-pixel SP may include a first period T1, a second period T2, a third period T3, a fourth period T4, a fifth period T5, and a sixth period T6. The nth period Tn may be a period from the (n - 1)th time to the nth time. Here, n is a natural number of 1 or more. For example, referring to FIG. 8, the second period T2 may be a period from the first time t1 to the second time t2. The third period T3 may be a period from the second time t2 to the third time t3. The fourth period T4 may be a period from the third time t3 to the fourth time t4. The fifth period T5 may be a period from the fourth time t4 to the fifth time t5. The first period T1 may be a light-emitting period before the first initialization period T_Init1. The second period T2 to the fifth period T5 may be included in the first initialization period T_Init1. The sixth period T6 may be the first light-emitting period T_Em1. During the first period T1 and the sixth period T6, the first light-emitting signal Em1 may have a high level. During the second period T2 to the fifth period T5, the first light-emitting signal Em1 may be at a low level. During the first period T1, the second period T2, the fifth period T5, and the sixth period T6, the first initialization signal Init1 may be at a low level. During the third period T3 and the fourth period T4, the first initialization signal Init1 may be at a high level. During the first period T1, second period T2, fourth period T4, fifth period T5, and sixth period T6, the first scan signal Scan1 may have a low level. During the third period T3, the first scan signal Scan1 may have a high level. During the second period T2 to the fifth period T5, a data voltage Vdata may be provided to the data line DL electrically connected to the first sub-pixel. Referring to FIG. 9, the first period T1 may be a light-emitting period before the first initialization period T_Init1. During the first period T1, the scan transistor SCT may be turned off, the initialization transistor 711 may be turned off, and the light-emitting transistor 712 may be turned on. Since the light-emitting transistor 712 is in the on state, the driving voltage EVDD may be provided to the drain node of the driving transistor DRT. Therefore, during the first period T1, the light-emitting transistor 712 may be turned on, and the driving voltage EVDD may be provided to the driving transistor DRT. Referring to FIG. 10, the second period T2 may be a period in which the supply of the driving voltage EVDD is interrupted and the storage capacitor Cst charged with a certain voltage is discharged. During the second period T2, the scan transistor SCT, the initialization transistor 711, and the light-emitting transistor 712 may all be turned off. Since the initialization transistor 711 and the light-emitting transistor 712 are both in the off state during the second period T2, a short circuit caused by the simultaneous power supply of the driving voltage EVDD and the base voltage EVSS can be prevented. Referring to FIG. 11, the third period T3 may be a period in which the base voltage EVSS is provided to the driving transistor DRT. During the third period T3, the scan transistor SCT and the initialization transistor 711 may be turned on. During the third period T3, the light-emitting transistor 712 may be turned off. During the third period T3, the base voltage EVSS may be supplied to the drain node of the driving transistor DRT. Since the voltage of the drain node is lower than the voltage of the source node, the voltage of the source node can be initialized with the base voltage EVSS. During the third period T3, the source node of the driving transistor DRT may be initialized to the base voltage EVSS, and at the same time, the data voltage Vdata is provided to the gate node of the driving transistor DRT. When the data voltage Vdata is provided to the gate node of the driving transistor DRT, a capacitor Cst can be charged with a voltage to emit light. Referring to FIG. 12, the fourth period T4 can be a period during which the storage capacitor Cst is stably charged to a certain voltage level. During the fourth period T4, the scanning transistor SCT and the light-emitting transistor 712 can be turned off. During the fourth period T4, the initialization transistor 711 can be turned on. The scanning transistor SCT can be turned off before the initialization transistor 711 is turned off. If the scanning transistor SCT is turned off after the initialization transistor 711 is turned off, the source node of the driving transistor DRT may be affected by the diode threshold voltage (Diode Vth) and the thin-film transistor threshold voltage (TFT Vth). Since the scanning transistor SCT is turned off before the initialization transistor 711 is turned off, the voltage of the source node of the driving transistor DRT can be stably maintained. Referring to FIG. 13, the fifth period T5 can be a period during which the supply of the driving voltage EVDD is interrupted and the storage capacitor Cst charged to a certain voltage is discharged. During the fifth period T5, the scanning transistor SCT, the initialization transistor 711, and the light-emitting transistor 712 can all be turned off. Since the initialization transistor 711 and the light-emitting transistor 712 are all turned off during the fifth period T5, a short circuit caused by the simultaneous supply of the driving voltage EVDD and the base voltage EVSS can be prevented. Referring to FIG. 14, the sixth period T6 can be a period during which the sub-pixel SP emits light. During the sixth period T6, the scanning transistor SCT can be turned off, the initialization transistor 711 can be turned off, and the light-emitting transistor 712 can be turned on. Since the light-emitting transistor 712 is in the on state, the driving voltage EVDD can be supplied to the drain node of the driving transistor DRT. Therefore, during the sixth period T6, the light-emitting transistor 712 can be turned on, and the driving voltage EVDD can be supplied to the driving transistor DRT. As described above, the operation of the sub-pixel SP included in the first row of sub-pixel groups has been described with reference to FIGS. 8 to 14. After controlling the operation of the first row of sub-pixel groups, the second row of sub-pixel groups can be controlled. A part of the period of operation of the first row of sub-pixel groups and a part of the period of operation of the second row of sub-pixel groups can overlap each other. Regarding the discussion of the timing diagram in FIG. 15, the first sub-pixel SP1 can be a sub-pixel included in the first row sub-pixel group (e.g., the first row sub-pixel group discussed in FIG. 5), the second sub-pixel SP2 can be a sub-pixel included in the second row sub-pixel group (e.g., the second row sub-pixel group discussed in FIG. 5), and the third sub-pixel SP3 can be a sub-pixel included in the third row sub-pixel group. The first sub-pixel SP1 can be connected to the first gate line, the second sub-pixel SP2 can be connected to the second gate line, and the third sub-pixel SP3 can be connected to the third gate line. The first sub-pixel SP1 shown in FIG. 15 can be the same as the first sub-pixel SPa shown in FIG. 5. The second sub-pixel SP2 shown in FIG. 15 can be the same as the second sub-pixel SPb shown in FIG. 5. The first emission signal Em1 shown in FIG. 15 can be the same as the first emission signal Em1 shown in FIG. 8. The first initialization period T_Init1 shown in FIG. 15 can be the same as the first initialization period T_Init1 shown in FIG. 8. The first scan signal Scan1 shown in FIG. 15 can be the same as the first scan signal Scan1 shown in FIG. 8. The characteristics among the second emission signal Em2, the second initialization signal T_Init2, and the second scan signal Scan2 can be the same as the characteristics among the first emission signal Em1, the first initialization signal T_Init1, and the first scan signal Scan1. Referring to FIG. 15, the driving period of the first row sub-pixel group can include the first initialization period T_Init1 and the first emission period T_Em1. Referring to FIG. 15, the driving period of the second row sub-pixel group can include the second initialization period T_Init2 and the second emission period T_Em2. During the first initialization period T_Init1, the data voltage Vdata can be the first data voltage provided to the first sub-pixel SP1 in the first row sub-pixel group. During the first emission period T_Em1, the first sub-pixel SP1 can emit light with a brightness corresponding to the first data voltage. Referring to FIG. 15, when the first emission period T_Em1 is enabled, the second initialization period T_Init2 can also be enabled. During the second initialization period T_Init2, the data voltage Vdata can be the second data voltage provided to the second sub-pixel SP2 included in the second row sub-pixel group. During the second emission period T_Em2, the second sub-pixel SP2 can emit light with a brightness corresponding to the second data voltage. Referring to FIG. 15, when the second emission period T_Em2 is enabled, the third initialization period can also be enabled. During the third initialization period, the data voltage Vdata can be the third data voltage provided to the third sub-pixel SP3 in the third row of sub-pixels. During the third emission period, the third sub-pixel SP3 can emit light with a brightness corresponding to the third data voltage. FIGS. 16 and 17 illustrate exemplary configurations of initialization transistors and emission transistors in a display panel in Example 2 according to various aspects of the present disclosure. FIG. 16 shows that a reference voltage Vref or a ground voltage EVSS can be provided to the first sub-pixel SP1 by controlling the first initialization signal Init1 and the first emission signal Em1. During the initialization period T_Init, the reference voltage Vref can be provided to the first sub-pixel SP1; while during the emission period T_Em, the ground voltage EVSS can be provided to the first sub-pixel SP1. Through this operation, the threshold voltage of the driving transistor DRT included in the first sub-pixel SP1 can be stably controlled. Multiple sub-pixels SP can be disposed in the display area AA, and driving circuits, voltage lines, signal lines, etc. for driving the sub-pixels SP can be disposed in the border area BA. FIG. 16 shows one sub-pixel SP disposed in the display area AA. FIG. 16 shows the initialization transistor, emission transistor, main reference voltage line 1650, and main ground voltage line 1660 disposed in the border area BA. Referring to FIG. 16, in one or more exemplary embodiments, the sub-pixel SP may include a light-emitting element ED, a driving transistor DRT, a scanning transistor SCT, a storage capacitor Cst, etc. The driving transistor DRT can be a transistor for driving the light-emitting element ED. The driving transistor DRT can be electrically connected between the second node N2 and the third node N3. The gate node of the driving transistor DRT can be electrically connected to the first node N1 or correspond to the first node N1. The scanning transistor SCT can be electrically connected between the data line DL and the first node N1. The gate node of the scanning transistor SCT can be electrically connected to the first gate line GL1. By controlling the scanning transistor SCT, a data voltage Vdata can be provided to the gate node of the driving transistor DRT. The storage capacitor Cst can be electrically connected between the first node N1 and the second node N2. The storage capacitor Cst can be charged with a certain level of voltage, and the sub-pixel SP can emit light with an expected brightness according to the voltage stored in the storage capacitor Cst. The light-emitting element ED can be electrically connected between the third node N3 and the driving voltage node N_EVDD. The driving voltage node N_EVDD can be a node for providing the driving voltage EVDD. When the light-emitting element ED is driven, an image can be displayed on the display panel 110. The first initialization transistor 1611 can be electrically connected between the main reference voltage line 1650 and the auxiliary base voltage line 1670. The first initialization transistor 1611 can be controlled by the first initialization signal Init1. The main reference voltage line 1650 can be located in the border area BA. The main reference voltage line 1650 can be a line that provides the reference voltage Vref to the sub-pixel SP. The first light-emitting transistor 1612 can be electrically connected between the main base voltage line 1660 and the auxiliary base voltage line 1670. The first light-emitting transistor 1612 can be controlled by the first light-emitting signal Em1. The main base voltage line 1660 can be located in the border area BA. The main base voltage line 1660 can be a line that provides the base voltage EVSS to the sub-pixel SP. The sub-pixel SP shown in FIG. 16 can be driven through the driving timings shown in FIGS. 18 to 24. The driving of the sub-pixel SP shown in FIG. 16 will be described below. FIGS. 18 to 24 show exemplary driving timings of the initialization transistor 1611 and the light-emitting transistor 1612 in the display panel 110 in the second embodiment shown in FIG. 16 according to various aspects of the present disclosure. The period during which the sub-pixel SP is driven can include an initialization period and a light-emitting period. Referring to FIG. 18, the driving period of the sub-pixel SP can include a first initialization period T_Init1 and a first light-emitting period T_Em1. The first initialization period T_Init1 can be a period for preparing the sub-pixel SP to be able to emit light. The first light-emitting period T_Em1 can be a period during which the sub-pixel SP emits light. The driving period of the sub-pixel SP can include: a first period T1, a second period T2, a third period T3, a fourth period T4, a fifth period T5, and a sixth period T6. The nth period Tn can be a period from the (n - 1)th time to the nth time. Here, n is a natural number of 1 or more. For example, referring to FIG. 8, the second period T2 can be a period from the first time t1 to the second time t2. The fifth period T5 can be a period from the fourth time t4 to the fifth time t5. The first period T1 can be a light-emitting period before the first initialization period T_Init1. The second period T2 to the fifth period T5 can be included in the first initialization period T_Init1. The sixth period T6 can be the first light-emitting period T_Em1. In the first period T1 and the sixth period T6, the first light-emitting signal Em1 can have a high level. During the second period T2 to the fifth period T5, the first light-emitting signal Em1 can be at a low level. During the first period T1, second period T2, fifth period T5, and sixth period T6, the first initialization signal Init1 can be at a low level. During the third period T3 and fourth period T4, the first initialization signal Init1 can be at a high level. During the first period T1, second period T2, fourth period T4, fifth period T5, and sixth period T6, the first scan signal Scan1 may have a low level. During the third period T3, the first scan signal Scan1 may have a high level. During the second period T2 to fifth period T5, a data voltage Vdata can be provided to the data line DL electrically connected to the first sub-pixel. Referring to FIG. 19, the first period T1 can be a light-emitting period before the first initialization period T_Init1. During the first period T1, the scan transistor SCT can be turned off, the initialization transistor 1611 can be turned off, and the light-emitting transistor 1612 can be turned on. Since the light-emitting transistor 1612 is in the on state, the base voltage EVSS can be provided to the source node of the driving transistor DRT. Therefore, during the first period T1, the light-emitting transistor 1612 can be turned on, and the base voltage EVSS can be provided to the driving transistor DRT. Referring to FIG. 20, the second period T2 can be a period in which the provision of the base voltage EVSS is interrupted and the storage capacitor Cst charged to a certain voltage level is discharged. During the second period T2, the scan transistor SCT, the initialization transistor 1611, and the light-emitting transistor 1612 can all be turned off. Since both the initialization transistor 1611 and the light-emitting transistor 1612 are in the off state during the second period T2, a short circuit caused by the simultaneous supply of the base voltage EVSS and the reference voltage Vref can be prevented. Referring to FIG. 21, the third period T3 can be a period in which the reference voltage Vref is provided to the driving transistor DRT. During the third period T3, the scan transistor SCT and the initialization transistor 1611 can be turned on. In the third period T3, the light-emitting transistor 1612 can be turned off. During the third period T3, the reference voltage Vref can be provided to the source node of the driving transistor DRT, and at the same time, the data voltage Vdata can be provided to the gate node of the driving transistor DRT. When the data voltage Vdata is provided to the gate node of the driving transistor DRT, a capacitor can be charged with a voltage to emit light. A voltage corresponding to the voltage difference between the data voltage Vdata and the reference voltage Vref can be stored in the storage capacitor Cst. Referring to FIG. 22, the fourth period T4 can be a period in which the storage capacitor Cst is stably charged with a certain level of voltage. During the fourth period T4, the scan transistor SCT and the light-emitting transistor 1612 can be turned off. In the fourth period T4, the initialization transistor 1611 can be turned on. The scan transistor SCT can be turned off before the initialization transistor 1611 is turned off. In a situation where the data voltage Vdata is provided to one end of the storage capacitor Cst and the reference voltage Vref is provided to the other end of the storage capacitor Cst, the supply of the data voltage Vdata can be interrupted first. Referring to FIG. 23, the fifth period T5 can be a period in which the supply of the reference voltage Vref is interrupted and the storage capacitor Cst charged with a certain level of voltage is discharged. During the fifth period T5, the scan transistor SCT, the initialization transistor 1611, and the light-emitting transistor 1612 can all be turned off. Since both the initialization transistor 1611 and the light-emitting transistor 1612 are in the off state during the fifth period T5, a short circuit caused by the simultaneous supply of the base voltage EVSS and the reference voltage Vref can be prevented. Referring to FIG. 24, the sixth period T6 can be a period in which the sub-pixel SP emits light. During the sixth period T6, the scan transistor SCT can be turned off, the initialization transistor 1611 can also be turned off, and the light-emitting transistor 1612 can be turned on. Since the light-emitting transistor 1612 is in the on state, the base voltage EVSS can be provided to the source node of the driving transistor DRT. Therefore, during the sixth period T6, the light-emitting transistor 1612 can be turned on and the base voltage EVSS can be supplied to the driving transistor DRT. Different from the configuration of FIG. 16, referring to FIG. 17, the gate node of the scan transistor SCT and the gate node of the first initialization transistor 1611 can be simultaneously controlled through a gate line. In this embodiment, since the number of lines is reduced, the circuit integration degree in the display panel 110 can be improved. For example, the sub-pixel SP shown in FIG. 17 can be driven according to the timing diagram shown in FIG. 25. Referring to FIGS. 18 and 25, FIG. 25 shows that the first scan signal Scan1 is used but the first initialization signal Init1 is not used. For example, as shown in FIG. 17, the gate node of the scan transistor SCT and the gate node of the first initialization transistor 1611 can be electrically connected to the first gate line GL1. In this example, the scan transistor SCT and the first initialization transistor 1611 can be simultaneously controlled by the first scan signal Scan1 provided through the first gate line GL1. The foregoing feature also applies to the gate node of the initialization transistor 711 and the gate node of the scan transistor SCT shown in FIG. 7. In other words, the gate node of the initialization transistor 711 and the gate node of the scan transistor SCT shown in FIG. 7 can be electrically connected to the same gate line. As described above, the operation of the sub-pixels SP (i.e., the first sub-pixel SP1) included in the first row of sub-pixel groups (e.g., the first row of sub-pixel groups discussed in FIG. 5) has been described with reference to FIGS. 18 to 24. After controlling the operation of the first row of sub-pixel groups, the second row of sub-pixel groups (e.g., the second row of sub-pixel groups discussed in FIG. 5) can be controlled. A part of the period of the operation of the first row of sub-pixel groups and a part of the period of the operation of the second row of sub-pixel groups can overlap with each other. Regarding the discussion of the timing diagram in FIG. 26, the first sub-pixel SP1 can be a sub-pixel included in the first row of sub-pixel groups, the second sub-pixel SP2 can be a sub-pixel included in the second row of sub-pixel groups, and the third sub-pixel SP3 can be a sub-pixel included in the third row of sub-pixel groups. The first sub-pixel SP1 can be connected to the first gate line, the second sub-pixel SP2 can be connected to the second gate line, and the third sub-pixel SP3 can be connected to the third gate line. Referring to FIG. 26, the driving period of the first row of sub-pixel groups may include a first initialization period T_Init1 and a first emission period T_Em1. Referring to FIG. 26, the driving period of the second row of sub-pixel groups may include a second initialization period T_Init2 and a second emission period T_Em2. During the first initialization period T_Init1, the data voltage Vdata can be the first data voltage provided to the first sub-pixel SP1 in the first row of sub-pixel groups. During the first emission period T_Em1, the first sub-pixel SP1 can emit light with a brightness corresponding to the first data voltage. Referring to FIG. 26, when the first emission period T_Em1 is enabled, the second initialization period T_Init2 can also be enabled. During the second initialization period T_Init2, the data voltage Vdata can be the second data voltage provided to the second sub-pixel SP2 included in the second row of sub-pixel groups. During the second emission period T_Em2, the second sub-pixel SP2 can emit light with a brightness corresponding to the second data voltage. Referring to FIG. 26, when the second emission period T_Em2 is enabled, the third initialization period can also be enabled. During the third initialization period, the data voltage Vdata can be the third data voltage provided to the third sub-pixel SP3 in the third row of sub-pixel groups. During the third emission period Em3, the third sub-pixel SP3 can emit light with a brightness corresponding to the third data voltage. FIG. 27 is an exemplary flowchart of a driving method of the display device 100 according to various aspects of the present disclosure. The driving method of the display device 100 may include an initialization step S2710 and an emission step S2720. The initialization step S2710 may be a stage of preparing for the sub-pixel SP to emit light. In the initialization step S2710, a first voltage may be provided to the driving transistor DRT included in the sub-pixel SP. The light-emitting step S2720 may be a stage where the sub-pixel SP emits light. In the light-emitting step S2720 after the initialization step S2710, a second voltage may be provided to the driving transistor DRT included in the sub-pixel SP. In the initialization step S2710, a first voltage may be provided to the driving transistor DRT, and in the light-emitting step S2720, a second voltage may be provided to the driving transistor DRT. Therefore, the threshold voltage of the driving transistor DRT can be stably controlled, thereby improving the quality of the image displayed on the display panel 110. Various examples and aspects of the present disclosure are described below. These are only examples and do not limit the scope of the present disclosure. According to one or more aspects of the present disclosure, a display device can be provided, which includes: a display area in which a plurality of sub-pixels including a first sub-pixel are placed; a border area different from the display area; a plurality of voltage lines provided in the border area and including at least one driving voltage line and at least one basic voltage line; and a first switch and a second switch provided in the border area, the first switch being electrically connected between the basic voltage line and the first sub-pixel, and the second switch being electrically connected between a first voltage line among the plurality of voltage lines and the first sub-pixel. The first sub-pixel may include: a driving transistor for driving a light-emitting element; a scanning transistor electrically connected between a first node and a data line, where the first node is the gate node of the driving transistor or corresponds to the gate node of the driving transistor; and a storage capacitor electrically connected between a second node of the driving transistor and the first node. The first switch and the second switch may be electrically connected to the driving transistor. Each of the first switch and the second switch may include or may be a transistor. Each of the first switch and the second switch may include an initialization transistor or a light-emitting transistor, or each of the first switch and the second switch may be an initialization transistor or a light-emitting transistor. The first voltage line may be a driving voltage line. The first switch and the second switch may be electrically connected to the drain node of the driving transistor. The light-emitting element may be electrically connected between the second node and the basic voltage node. The first voltage line may be a reference voltage line provided with a reference voltage. The first switch and the second switch may be electrically connected to the source node of the driving transistor. The light-emitting element may be electrically connected between the third node of the driving transistor and the driving voltage node. The gate line electrically connected to the gate node of the scanning transistor can be electrically connected to the gate node of the initialization transistor serving as the second switch. The driving period of the sub-pixel may include: a light-emitting period during which the light-emitting element emits light, and an initialization period during which the storage capacitor is charged with a data voltage. During the initialization period, the source node of the driving transistor may be initialized to a base voltage. When the first switch is turned on, the second switch may be turned off; when the second switch is turned on, the first switch may be turned off. During the light-emitting period when the first sub-pixel emits light, the light-emitting transistor serving as the second switch may be turned on, and during the initialization period before the light-emitting period, the initialization transistor serving as the first switch may be turned on. During the initialization period, a base voltage may be provided to the first sub-pixel; during the light-emitting period, a driving voltage may be provided to the first sub-pixel. During the light-emitting period when the first sub-pixel emits light, the light-emitting transistor serving as the first switch may be turned on, and during the initialization period before the light-emitting period, the initialization transistor serving as the second switch may be turned on. During the initialization period, a reference voltage may be provided to the first sub-pixel through the first voltage line; during the light-emitting period, a base voltage may be provided to the first sub-pixel. The first switch and the second switch may be disposed in the first border area, and the third switch and the fourth switch different from the first switch and the second switch may be disposed in the second border area different from the first border area. A plurality of sub-pixels may be disposed on the silicon substrate. According to one or more aspects of the present disclosure, a driving method of a display device may include: providing an initialization period during which the first switch disposed in the border area is turned on and a first voltage is provided to the first sub-pixel disposed in the display area; and providing a light-emitting period during which the second switch disposed in the border area is turned on, a second voltage is provided to the first sub-pixel, and the first sub-pixel emits light. During the initialization period, a base voltage may be provided through the first switch; during the light-emitting period, a driving voltage may be provided through the second switch. During the initialization period, a reference voltage may be provided through the first switch; during the light-emitting period, a base voltage may be provided through the second switch. According to one or more aspects of the present disclosure, a display device can be provided, which includes: a display area; a border area different from the display area; a plurality of sub-pixels disposed in the display area and including a first sub-pixel; a plurality of voltage lines disposed in the border area and including a driving voltage line and a basic voltage line; and a first switch and a second switch disposed in the border area. In a first period, the first switch can supply a first voltage to the first sub-pixel. In a second period, the second switch can supply a second voltage to the first sub-pixel. The first voltage can be supplied through a first voltage line among the plurality of voltage lines. The second voltage can be supplied through a second voltage line among the plurality of voltage lines. The first period and the second period can be an initialization period and a light-emitting period, respectively. The first switch and the second switch can be connected to each other. The first switch and the second switch can be directly connected. The first voltage can be a basic voltage, and the second voltage can be a driving voltage. The first voltage can be a reference voltage, and the second voltage can be a basic voltage. The first switch can include an initialization transistor, and the second switch can include a light-emitting transistor. The first voltage can be supplied to the drain node of the driving transistor. The second voltage can be supplied to the drain node of the driving transistor. The above description is provided to enable any person of ordinary skill in the art to make, use, and practice the technical features of this case, and is provided as an example in the context of a specific application and its requirements. It will be obvious to those of ordinary skill in the art to make various modifications, additions, and substitutions to the described embodiments. The principles described herein can be applied to other embodiments and applications without departing from the scope of the present invention. The above description and drawings provide examples of the technical features of the present invention for reference only. That is to say, the disclosed embodiments are intended to illustrate the scope of the technical features of the present invention. 100: Display device 110: Display panel 120: Data driving circuit 130: Gate driving circuit 140: Controller 310: Body 320: Drain layer 330: Source layer 340: Active layer 350: Gate insulating layer 360: Gate layer 511: First initialization transistor 512: First light-emitting transistor 521: Second initialization transistor 522: Second light-emitting transistor 531: Third initialization transistor 532: Third light-emitting transistor 541: Fourth initialization transistor 542: Fourth light-emitting transistor 711: Initialization transistor 712: Light-emitting transistor 750: Main base voltage line 760: Main driving voltage line 770: Auxiliary driving voltage line 1611: First initialization transistor 1612: First light-emitting transistor 1650: Main reference voltage line 1660: Main base voltage line 1670: Auxiliary base voltage line AA: Display area BA: Border area BA1: First border area BA2: Second border area ADC: Analog-to-digital converter DL: Data line GL: Gate line GL1: First gate line GL2: Second gate line DCS: Data control signal GCS: Gate control signal Data: Image data SUB: Substrate DRT: Driving transistor PE: Pixel electrode CE: Common electrode EL: Light-emitting layer ED: Light-emitting element DRT: Driving transistor SCT: Scanning transistor Crvl: Line capacitor SENT: Sensing transistor Cst: Storage capacitor SENSE: Sensing signal RVL: Reference voltage line DVL: Driving voltage line SENL: Sensing signal line Nref: Reference voltage power supply node GND: Ground terminal SPRE: Power switch SCAN: Scanning signal SAM: Sampling switch SCL: Scanning signal line SP: Sub-pixel A5: Partial area SP1,SPa: First sub-pixel SP2,SPb: Second sub-pixel SP3,SPc: Third sub-pixel SP4,SPd: Fourth sub-pixel SP5,SPe: Fifth sub-pixel SP6,SPf: Sixth sub-pixel T1: First period T2: Second period T3: Third period T4: Fourth period T5: Fifth period T6: Sixth period t1: First time t2: Second time t3: Third time t4: Fourth time t5: Fifth time N1: First node N2: Second node N3: Third node Vth: Threshold voltage Vt0: Initial threshold voltage value Vref: Reference voltage a: Body effect coefficient Vsb: Source-body voltage Vdata: Data voltage V1: First voltage V2: Second voltage VL1: First voltage line VL2: Second voltage line Scan1: First scan signal Scan2: Second scan signal Init1: First initialization signal Init2: Second initialization signal Init3: Third initialization signal Init4: Fourth initialization signal Em1: First emission signal Em2: Second emission signal Em3: Third emission signal Em4: Fourth emission signal T_Init1: First initialization period T_Em1: First emission period T_Init2: Second initialization period T_Em2: Second emission period EVDD: Driving voltage N_EVDD: Driving voltage node EVSS: Ground voltage N_EVSS: Ground voltage node S2710: Initialization step S2720: Emission step d: d node s: s node g: g node b: b node, The drawings included in this disclosure to provide a further understanding of the disclosure are incorporated into and form a part of this disclosure. The drawings illustrate various aspects and embodiments of the disclosure and, together with the description, are used to explain the principles and embodiments of the disclosure. In the drawings: FIG. 1 shows an exemplary system configuration of a display device according to the present disclosure; FIG. 2 shows an exemplary equivalent circuit of a sub-pixel included in a display device according to various aspects of the present disclosure; FIG. 3 shows an exemplary equivalent circuit of a sub-pixel in a display device according to various aspects of the present disclosure and an exemplary structure of a driving transistor included in the sub-pixel; FIG. 4 is an exemplary graph for explaining the variation of the threshold voltage with the body voltage in a display device according to various aspects of the present disclosure; FIGS. 5 and 6 show exemplary configurations of a display panel including at least one initialization transistor and at least one emission transistor in a display device according to various aspects of the present disclosure; FIG. 7 shows an exemplary configuration of a display panel including the initialization transistor and the emission transistor in Embodiment 1 in a display device according to various aspects of the present disclosure; Figures 8 to 15 show exemplary driving timings of initialization transistors and light-emitting transistors in a display panel in Embodiment 1 according to various aspects of the present disclosure; Figures 16 and 17 show exemplary configurations of initialization transistors and light-emitting transistors in a display panel in Embodiment 2 according to various aspects of the present disclosure; Figures 18 to 26 show exemplary driving timings of initialization transistors and light-emitting transistors in a display panel in Embodiment 2 according to various aspects of the present disclosure; and Figure 27 is an exemplary flowchart of a method for driving a display device according to various aspects of the present disclosure. Throughout the drawings and the detailed description, unless otherwise specified, the same reference numerals in the drawings should be understood to refer to the same or similar elements, features, and structures. For clarity, illustration, and / or convenience, the dimensions, lengths, and thicknesses of layers, regions, and elements, as well as the descriptions thereof, may be exaggerated. 100: Display device 110: Display panel 120: Data driving circuit 130: Gate driving circuit 140: Controller AA: Display area BA: Border area DL: Data line GL: Gate line DCS: Data control signal GCS: Gate control signal Data: Image data

Claims

1. A display device, comprising: a display area, wherein a plurality of subpixels, each including a first subpixel, are disposed thereon; a border area, different from the display area; a plurality of voltage lines disposed in the border area and including a driving voltage line and a base voltage line; and a first switch and a second switch disposed in the border area, wherein: The first switch is electrically connected between the base voltage line and the first sub-pixel; and the second switch is electrically connected between a first voltage line of the voltage lines and the first sub-pixel. The first sub-pixel includes a driving transistor for driving a light-emitting element. A driving cycle of the first sub-pixel includes an initialization cycle preceding the light-emitting cycle. During the light-emitting cycle, the light-emitting element emits light. During at least a portion of the initialization cycle, when a data voltage is applied to the gate node of the driving transistor, one of the first switch and the second switch is turned on. During at least a second portion of the initialization cycle, the data voltage is not applied to the gate node of the driving transistor; the at least a second portion of the initialization cycle is after the at least a portion of the initialization cycle and before the emission cycle; during at least a third portion of the initialization cycle, the data voltage is not applied to the gate node of the driving transistor, and both the first switch and the second switch are turned off; and the at least a third portion of the initialization cycle is after a previous emission cycle and before the at least a portion of the initialization cycle.

2. The display device as described in claim 1, wherein, The first sub-pixel further includes: a scanning transistor electrically connected between a first node and a data line, wherein the first node serves as or corresponds to the gate node of the driving transistor; and a storage capacitor electrically connected between a second node of the driving transistor and the first node, wherein the first switch and the second switch are electrically connected to the driving transistor.

3. The display device as claimed in claim 2, wherein the first voltage line is the driving voltage line.

4. The display device as claimed in claim 3, wherein the first switch and the second switch are electrically connected to one of the drain nodes of the driving transistor.

5. The display device as claimed in claim 4, wherein the light-emitting element is electrically connected between the second node and a base voltage node.

6. The display device as claimed in claim 2, wherein the first voltage line is configured to provide a reference voltage line having a reference voltage.

7. The display device as claimed in claim 6, wherein the first switch and the second switch are electrically connected to one of the source nodes of the driving transistor.

8. The display device as claimed in claim 7, wherein the light-emitting element is electrically connected between a third node of the driving transistor and a driving voltage node.

9. The display device as claimed in claim 2, wherein a gate line electrically connected to a gate node of the scanning transistor is electrically connected to a gate node of an initialization transistor, wherein the initialization transistor is the second switch.

10. The display device as claimed in claim 2, wherein a driving cycle of the first sub-pixel includes: a light-emitting cycle and an initialization cycle, wherein the light-emitting element is configured to emit light during the light-emitting cycle, and the storage capacitor is configured to be charged with a data voltage during the initialization cycle, and wherein, During this initialization cycle, one of the source nodes of the driving transistor is configured to be initialized to a base voltage.

11. The display device as claimed in claim 1, wherein during the light emission cycle in which the first sub-pixel is configured to emit light, a light-emitting transistor serving as the second switch is configured to be turned on, and during at least a portion of the initialization cycle preceding the light emission cycle, an initialization transistor serving as the first switch is configured to be turned on.

12. The display device as claimed in claim 11, wherein during at least a portion of the initialization cycle, a base voltage is provided to the first sub-pixel, and during the emission cycle, a driving voltage is provided to the first sub-pixel.

13. The display device as claimed in claim 1, wherein during the light emission period in which the first sub-pixel is configured to emit light, a light-emitting transistor serving as the first switch is configured to be turned on, and during at least a portion of the initialization period preceding the light emission period, an initialization transistor serving as the second switch is configured to be turned on.

14. The display device as claimed in claim 13, wherein during at least a portion of the initialization cycle, a reference voltage is provided to the first sub-pixel through the first voltage line, and during the emission cycle, a base voltage is provided to the first sub-pixel.

15. A driving method for a display device, the driving method comprising: providing an initialization cycle, wherein during the initialization cycle, a first switch disposed in a border region is turned on, and a first voltage is provided to a first sub-pixel disposed in a display region; and providing a light emission cycle, wherein during the light emission cycle, a second switch disposed in the border region is turned on, a second voltage is provided to the first sub-pixel, and the first sub-pixel emits light, wherein: The first sub-pixel includes a driving transistor coupled to a light-emitting element for emitting light; during at least a portion of the initialization period, a data voltage is applied to the gate node of the driving transistor, and the first switch is turned on. During at least a second portion of the initialization cycle, the data voltage is not applied to the gate node of the driving transistor; the at least a second portion of the initialization cycle is after the at least a portion of the initialization cycle and before the emission cycle; during at least a third portion of the initialization cycle, the data voltage is not applied to the gate node of the driving transistor, and both the first switch and the second switch are turned off; and the at least a third portion of the initialization cycle is after a previous emission cycle and before the at least a portion of the initialization cycle.

16. The driving method as claimed in claim 15, wherein a base voltage is provided through the first switch during at least a portion of the initialization cycle, and a driving voltage is provided through the second switch during the light emission cycle.

17. The driving method as claimed in claim 15, wherein a reference voltage is provided through the first switch during at least a portion of the initialization cycle, and a base voltage is provided through the second switch during the emission cycle.

18. A display device comprising: a display area; a border area different from the display area; a plurality of sub-pixels disposed in the display area and including a first sub-pixel; a plurality of voltage lines disposed in the border area and including a driving voltage line and a base voltage line; and a first switch and a second switch disposed in the border area, wherein: During a first cycle, the first switch is configured to provide a first voltage to the first sub-pixel using a first voltage line among the voltage lines; during a second cycle, the second switch is configured to provide a second voltage to the first sub-pixel using a second voltage line among the voltage lines, the first sub-pixel including a driving transistor for driving a light-emitting element; during the first cycle, during at least a portion of an initialization cycle, the first switch is turned on when a data voltage is applied to the gate node of the driving transistor, the at least a portion of the initialization cycle being the first cycle; During at least a second portion of the initialization cycle, the data voltage is not applied to the gate node of the driving transistor; the at least a second portion of the first cycle is after the at least a portion of the first cycle and before the second cycle; during at least a third portion of the initialization cycle, the data voltage is not applied to the gate node of the driving transistor, and both the first switch and the second switch are turned off. And the at least third part of the initialization cycle preceding the at least part of the initialization cycle.

19. The display device as claimed in claim 18, wherein, The second cycle is a light-emitting cycle; wherein the first switch and the second switch are interconnected; and wherein: the first voltage is a base voltage and the second voltage is a driving voltage; or the first voltage is a reference voltage and the second voltage is the base voltage.

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