Semiconductor device structure and methods of forming the same

Abstract

The embodiments disclosed herein provide a semiconductor device structure and a method for forming the same. The structure includes a first source / drain region, a second source / drain region disposed adjacent to the first source / drain region along a first direction, a third source / drain region disposed adjacent to the first source / drain region along a second direction substantially perpendicular to the first direction, a first gate electrode layer disposed between the first and third source / drain regions, a second gate electrode layer disposed adjacent to the second source / drain region, and a first dielectric material disposed between the first and second gate electrode layers. The length of the first dielectric material is less than or equal to a first distance between the first and second source / drain regions.

Description

Technical Field

[0001] This disclosure relates to a semiconductor device structure and a method for forming the same. Prior Technology

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in several generations of ICs, each featuring smaller and more complex circuitry than the previous generation. In the evolution of ICs, functional density (i.e., the number of interconnect devices per wafer area) typically increases, while geometry (i.e., the smallest component (or line) that can be created using manufacturing processes) decreases. This shrinkage process generally provides benefits through increased production efficiency and reduced associated costs. However, this shrinkage also increases the complexity of processing and manufacturing ICs.

[0003] Therefore, improvements are needed in IC processing and manufacturing. Summary of the Invention

[0004] This disclosure relates to a semiconductor device structure, comprising: a first source / drain region; a second source / drain region disposed adjacent to the first source / drain region along a first direction; a third source / drain region disposed adjacent to the first source / drain region along a second direction substantially perpendicular to the first direction; a first gate electrode layer disposed between the first source / drain region and the third source / drain region; a second gate electrode layer disposed adjacent to the second source / drain region; and a first dielectric material disposed between the first gate electrode layer and the second gate electrode layer, wherein the length of the first dielectric material is less than or equal to a first distance between the first source / drain region and the second source / drain region.

[0005] This disclosure also relates to a semiconductor device structure, comprising: a first source / drain region; a second source / drain region disposed adjacent to the first source / drain region along a first direction; a third source / drain region disposed adjacent to the first source / drain region along a second direction substantially perpendicular to the first direction; a first gate spacer and a second gate spacer disposed between the first source / drain region and the third source / drain region; and a first dielectric material disposed between the first gate spacer and the second gate spacer, wherein the top surface of the first dielectric material has a cross shape.

[0006] This disclosure also relates to a method for forming a semiconductor device structure, comprising: forming a first gate spacer and a second gate spacer on a substrate; forming a first source / drain region and a second source / drain region on the substrate, wherein the first source / drain region and the second source / drain region are aligned along a first direction and adjacent to the first gate spacer; forming a gate electrode layer between the first gate spacer and the second gate spacer; forming an opening in the gate electrode layer, wherein the size of the opening along the first direction is less than or equal to the distance between the first source / drain region and the second source / drain region; and depositing a dielectric material in the opening. Simple Explanation of the Diagram

[0007] Various aspects of this disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, the various features are not drawn to scale. In fact, for clarity of discussion, the dimensions of the various features may be arbitrarily increased or decreased.

[0008] Figures 1 to 6 are perspective views of various stages of manufacturing a semiconductor device structure according to some embodiments.

[0009] Figures 7A to 10A are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line AA of Figure 6 according to some embodiments.

[0010] Figures 7B to 10B are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line BB of Figure 6 according to some embodiments.

[0011] Figures 7C to 10C are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line CC of Figure 6 according to some embodiments.

[0012] Figure 11 is a top view of a semiconductor device structure shown in Figures 10A, 10B, and 10C according to some embodiments.

[0013] Figures 12A to 16A are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line DD of Figure 11 according to some embodiments.

[0014] Figures 12B to 16B are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line EE of Figure 11 according to some embodiments.

[0015] Figure 17 is a top view of a semiconductor device structure shown in Figures 16A and 16B according to some embodiments.

[0016] Figures 18A, 18B, and 18C are views of one of the various stages of manufacturing a semiconductor device structure according to some embodiments.

[0017] Figure 19 is a top view of a semiconductor device structure shown in Figures 18A, 18B, and 18C according to some embodiments.

[0018] Figures 20A to 24A are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line FF of Figure 19 according to some embodiments.

[0019] Figures 20B to 24B are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line GG of Figure 19 according to some embodiments.

[0020] Figures 20C to 24C are cross-sectional side views of various stages of manufacturing a semiconductor device structure, taken along line HH of Figure 19 according to some embodiments.

[0021] Figure 22D is a top view of an opening in a semiconductor device structure according to some embodiments.

[0022] Figure 25 is a top view of a semiconductor device structure shown in Figures 24A, 24B and 24C according to some embodiments.

[0023] Figure 26 is a top view of a semiconductor device structure according to an alternative embodiment.

[0024] Figures 27A to 27C are top views of the dielectric material of the semiconductor device structure of Figure 26 according to some embodiments.

[0025] Figures 28A and 28B are cross-sectional side views of one of the various stages of manufacturing a semiconductor device structure, taken along line II of Figure 26 according to some embodiments. Implementation

[0026] The following disclosure provides numerous different embodiments or examples for implementing various features of the provided subject matter. Specific examples of elements and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature on or over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples throughout this disclosure. Such repetition is for the purpose of brevity and clarity and does not, in itself, indicate a relationship between the various embodiments and / or configurations discussed.

[0027] Furthermore, spatially related terms (e.g., "below," "below," "lower," "above," "above," "upper," "top," "higher," etc.) may be used herein to readily describe the relationship of one element or feature shown in the figure relative to another element(s) or feature(s). These spatially related terms are intended to cover different orientations of the device in use or operation other than those shown in the figure. The device may be oriented in other directions (rotated 90 degrees or in other orientations), and the spatially related descriptors used herein can be interpreted similarly accordingly.

[0028] Embodiments of this disclosure provide a semiconductor device structure having a first dielectric material and a second dielectric material, the first dielectric material separating portions of a gate electrode layer, and the second dielectric material is used to isolate the active device. In some embodiments, the first dielectric material has a first longitudinal axis, the second dielectric material has a second longitudinal axis, and the first longitudinal axis is substantially parallel to the second longitudinal axis. As a result, parasitic capacitance is reduced.

[0029] While embodiments of this disclosure are discussed with regard to nanostructured channel FETs (e.g., gate-all-around (GAA) FETs, such as horizontal gate-all-around (HGAA) FETs or vertical gate-all-around (VGAA) FETs), implementations of some aspects of this disclosure can be used in other processes and / or other devices (e.g., planar FETs, fin FETs, and other suitable devices). Those skilled in the art will readily understand that other modifications may be considered within the scope of this disclosure. In the case of employing a gate-all-around (GAA) transistor structure, the GAA transistor structure can be patterned by any suitable method. For example, these structures can be patterned using one or more photolithography processes (including dual-patterning or multi-patterning processes). Typically, dual-patterning or multi-patterning processes combine photolithography and self-alignment processes, thereby allowing the production of patterns, for example, with a pitch smaller than that achievable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the GAA structure.

[0030] Figures 1 through 25 illustrate exemplary processes for manufacturing a semiconductor device structure 100 according to embodiments of the present disclosure. It should be understood that additional operations may be provided before, during, and after the processes shown in Figures 1 through 25, and some operations described below may be replaced or eliminated for additional embodiments of the method. The order of operations / processes is not limiting and is interchangeable.

[0031] Figures 1 to 6 are perspective views of various stages of manufacturing a semiconductor device structure 100 according to some embodiments. As shown in Figure 1, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may contain crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for reinforcement. In one aspect, the insulating layer is an oxygen-containing layer.

[0032] The substrate 101 may include various regions that have been doped with impurities (e.g., dopants with p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for an n-type field-effect transistor (NFET) and boron for a p-type field-effect transistor (PFET).

[0033] Semiconductor layer stack 104 comprises alternating semiconductor layers made of different materials to facilitate the formation of nanostructure channels in multi-gate devices (e.g., nanostructure channel FETs). In some embodiments, semiconductor layer stack 104 comprises a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, semiconductor layer stack 104 comprises alternating first semiconductor layer 106 and second semiconductor layer 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, while the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, while the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of semiconductor layers 106, 108 may be or may comprise other materials, such as Ge, SiC, GaAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof.

[0034] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of each layer of the semiconductor layer stack 104 can be performed by a molecular beam epitaxy (MBE) process, a metal-organic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0035] The first semiconductor layer 106 or portions thereof may form one or more nanostructured channels of the semiconductor device structure 100 in subsequent manufacturing stages. The term nanostructure is used herein to refer to any portion of material having nanometer or even micrometer-scale dimensions and an elongated shape, regardless of the cross-sectional shape of that portion. Thus, the term refers to elongated material portions having circular or substantially circular cross-sections, as well as beam-shaped or strip-shaped material portions comprising, for example, cylindrical or substantially rectangular cross-sections. One or more nanostructured channels of the semiconductor device structure 100 may be surrounded by gate electrodes. The semiconductor device structure 100 may contain nanostructured transistors. Nanostructured transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having gate electrodes surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0036] Each first semiconductor layer 106 may have a thickness ranging from about 5 nm to about 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness ranging from about 2 nm to about 50 nm. As shown in FIG1, three first semiconductor layers 106 and three second semiconductor layers 108 are arranged alternately, this is for illustrative purposes only and is not intended to limit the scope specifically described in the claims. It will be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels in the semiconductor device structure 100.

[0037] In Figure 2, fin structures 112 are formed from semiconductor layer stack 104. Each fin structure 112 has an upper portion comprising semiconductor layers 106, 108 and a substrate portion 116 formed from substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on semiconductor layer stack 104 using a multi-patterning operation including photolithography and etching processes. The etching process can include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process can include forming a photoresist layer (not shown) on the hard mask layer, exposing the photoresist layer to the pattern, performing a post-exposure baking process, and developing the photoresist layer to form a masking element comprising the photoresist layer. In some embodiments, patterning the photoresist layer to form the masking element can be performed using an electron beam lithography process. The etching process forms trenches 114 in the unprotected area, which penetrate the hard mask layer, the semiconductor layer stack 104, and into the substrate 101, leaving a plurality of extended fin structures 112. The trenches 114 extend in the X direction. The trenches 114 can be etched using dry etching (e.g., RIE), wet etching, and / or combinations thereof. In some embodiments, each fin structure 112 has a longitudinal axis in the X direction.

[0038] In Figure 3, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation (e.g., chemical mechanical polishing (CMP) and / or etch-back) is performed to expose the top of the fin structure 112. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorine-doped silicate glass (FSG), low-k dielectric material, or any suitable dielectric material. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0039] In Figure 4, insulating material 118 is recessed to form isolation region 120. The recess in insulating material 118 exposes portions of fin structures 112, such as semiconductor layer stack 104. The recess in insulating material 118 exposes trenches 114 between adjacent fin structures 112. Isolation region 120 can be formed using suitable processes (e.g., dry etching, wet etching, or a combination thereof). The top surface of insulating material 118 may be flush with or below the surface of the second semiconductor layer 108 that contacts the substrate portion 116 formed from substrate 101.

[0040] In Figure 5, one or more sacrificial gate structures 130 (only one is shown) are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 may include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a masking layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136 can be formed by sequentially depositing uniform-thickness layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136, and then patterning these layers into the sacrificial gate structure 130. Gate spacers 138 are then formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 can be formed by conformally depositing one or more layers of the gate spacers 138 and anisotropically etching the one or more layers. In some embodiments, the gate spacers 138 are also formed on the sidewalls of the exposed portion of the fin structure 112. Although one sacrificial gate structure 130 is shown, in some embodiments two or more sacrificial gate structures 130 may be arranged along the X direction.

[0041] The sacrificial gate dielectric layer 132 may comprise one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may comprise silicon, such as polycrystalline silicon or amorphous silicon. The masking layer 136 may comprise more than one layer, such as an oxide layer and a nitride layer. The gate spacer 138 may be made of a dielectric material (e.g., silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof).

[0042] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as a channel region of the semiconductor device structure 100.

[0043] In Figure 6, the portion of fin structure 112 not covered by sacrificial gate structure 130 and gate spacer 138 is recessed to a level above, at, or below the top surface of isolation region 120. These recesses of fin structure 112 can be achieved through an etching process (isotropic or anisotropic etching process), and this etching process can be selective for one or more crystal planes of substrate 101. The etching process can be dry etching (e.g., RIE, NBE, etc.) or wet etching (e.g., using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant).

[0044] Figures 7A, 7B, and 7C are cross-sectional side views of the semiconductor device structure 100 taken along lines AA, BB, and CC of Figure 6, respectively.

[0045] Figures 8A, 8B, and 8C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various stages of manufacturing a semiconductor device structure 100. As shown in Figure 8A, edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are removed horizontally along the X direction. The removal of the edge portions of the second semiconductor layer 108 forms cavities. In some embodiments, these portions of the second semiconductor layer 108 are removed by a selective wet etching process. In cases where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant (e.g., but not limited to ammonium hydroxide (NH₄OH), tetramethylammonium hydroxide (TMAH), ethylenediamine catechol (EDP), or potassium hydroxide (KOH) solution).

[0046] After removing the edge portions of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 can be made of a low-k dielectric material (e.g., SiON, SiCN, SiOC, SiOCN, or SiN). The dielectric spacer 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., ALD), followed by removing the portion of the conformal dielectric layer other than the dielectric spacer 144 by anisotropic etching. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is capped between the dielectric spacers 144 along the X direction.

[0047] In some embodiments, instead of removing the edge portions of each second semiconductor layer 108, the second semiconductor layer 108 is removed and replaced with a dielectric material (e.g., high-density SiN or SiO). The edge portions of the dielectric material are removed, and dielectric spacers 144 are formed to cover the dielectric material.

[0048] Figures 9A, 9B, and 9C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various stages of fabricating a semiconductor device structure 100. As shown in Figures 9A and 9C, source / drain (S / D) regions 146 are formed from substrate portion 116. In some embodiments, S / D regions 146 may be grown vertically and horizontally to form facets that may correspond to crystal planes of the material used for substrate portion 116. In this disclosure, source regions and drain regions may be used interchangeably and have substantially the same structure. Furthermore, one or more source / drain regions may individually or collectively refer to a source or drain, depending on the context. S / D regions 146 may be made of one or more layers of Si, SiP, SiC, and SiCP for n-channel FETs or one or more layers of Si, SiGe, and Ge for p-channel FETs. For p-channel FETs, p-type dopants (e.g., boron (B)) may also be included in S / D regions 146. The S / D region 146 can be formed using epitaxial growth methods such as CVD, ALD, or MBE.

[0049] Figures 10A, 10B, and 10C are cross-sectional side views taken along lines AA, BB, and CC of Figure 6, respectively, according to some embodiments, of one of the various stages of manufacturing a semiconductor device structure 100. In Figures 10A, 10B, and 10C, a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. CESL 162 covers the sacrificial gate structure 130, the insulating material 118, and the sidewalls of the S / D region 146. CESL 162 may comprise oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbide, etc., or combinations thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 above the semiconductor device structure 100. The material of ILD layer 164 may comprise compounds containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. Organic materials (e.g., polymers) may also be used for ILD layer 164. ILD layer 164 may be deposited using a PECVD process or other suitable deposition techniques. In some embodiments, after ILD layer 164 is formed, the semiconductor device structure 100 may be heat-treated to cure ILD layer 164.

[0050] After the ILD layer 164 is formed, a planarization operation (e.g., CMP) is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as shown in Figures 10A and 10B. In some embodiments, after the planarization process, the ILD layer 164 is recessed, and a dielectric layer 163 is formed on the recessed ILD layer 164. The dielectric layer 163 may contain a nitride (e.g., silicon nitride) to protect the ILD layer 164 during subsequent processes. A second planarization process may be performed to remove portions of the dielectric layer 163 formed on the sacrificial gate electrode layer 134.

[0051] Figure 11 is a top view of a semiconductor device structure 100 shown in Figures 10A, 10B, and 10C according to some embodiments. For clarity, some elements of the semiconductor device structure 100, such as dielectric layer 163 and CESL 162, are omitted in Figure 11. Furthermore, the locations of the S / D region 146 and isolation region 120 are for illustrative purposes only and not precisely defined. As shown in Figure 11, the semiconductor device structure 100 includes an S / D region 146 formed on the opposite side of a sacrificial gate electrode layer 134. Each sacrificial gate electrode layer 134 has a longitudinal axis along the Y direction, while each fin structure 112 has a longitudinal axis along the X direction.

[0052] Figures 12A to 16A are cross-sectional side views of various stages of manufacturing a semiconductor device structure 100, taken along line DD of Figure 11 according to some embodiments. Figures 12B to 16B are cross-sectional side views of various stages of manufacturing a semiconductor device structure 100, taken along line EE of Figure 11 according to some embodiments. As shown in Figures 12A and 12B, a masking layer 150 is formed on a dielectric layer 163 and a sacrificial gate electrode layer 134. The masking layer 150 may comprise a dielectric layer (e.g., SiN) or a semiconductor material (e.g., amorphous Si).

[0053] In Figures 13A and 13B, an opening 160 is formed in the masking layer 150. In some embodiments, the opening 160 exposes a portion of the sacrificial gate electrode layer 134, and the exposed portion of the sacrificial gate electrode layer 134 extends across a plurality of fin structures 112. In some embodiments, the exposed portion of the sacrificial gate electrode layer 134 extends across four fin structures 112, as shown in Figure 13B. Therefore, the masking layer 150 is not shown in Figure 13B.

[0054] In Figures 14A and 14B, the exposed portion of the sacrificial gate electrode layer 134 is removed. This exposed portion of the sacrificial gate electrode layer 134 can be removed by an etching process (e.g., a selective etching process that substantially does not affect the mask layer 150 and the sacrificial gate dielectric layer 132). In Figures 15A and 15B, the exposed portion of the sacrificial gate dielectric layer 132 and some portions of the fin structure 112 located beneath it are removed. These portions of the fin structure 112 can be removed by one or more etching processes. In some embodiments, the one or more etching processes can be selective etching processes that substantially do not affect the dielectric material of the mask layer 150, the dielectric spacer 144, and the insulating material 118. In some embodiments, the one or more etching processes can be anisotropic etching processes, and the portion of the first semiconductor layer 106 located below the gate spacer 138 and the dielectric spacer 144 can be retained, as shown in Figure 15A. As shown in Figures 15A and 15B, the opening 160 extends into the substrate 101.

[0055] In some embodiments, the fin structure 112 comprises a dielectric material instead of the second semiconductor layer 108, and one or more etching processes for removing these portions of the fin structure 112 may also cause the insulating material 118 to be recessed.

[0056] In Figures 16A and 16B, dielectric material 166 is formed in opening 160. Dielectric material 166 can comprise any suitable dielectric material. In some embodiments, dielectric material 166 comprises SiN. Dielectric material 166 can also be formed on dielectric layer 163, and a planarization process (e.g., CMP process) can be performed to remove portions of dielectric material 166 formed on dielectric layer 163. The CMP process can also remove masking layer 150. In some embodiments, a liner (not shown) can first be deposited in opening 160, and dielectric material 166 is formed on the liner. The liner can be deposited via a conformal process (e.g., ALD). The liner and dielectric material 166 can comprise different dielectric materials.

[0057] Figure 17 is a top view of a semiconductor device structure 100 shown in Figures 16A and 16B according to some embodiments. For clarity, some elements of the semiconductor device structure 100, such as dielectric layer 163 and CESL 162, are omitted in Figure 17. As shown in Figure 17, a portion of the sacrificial gate electrode layer 134 is replaced by dielectric material 166. The process described in Figures 12A to 16B can be referred to as a continuous polysilicon diffusion (CPODE) process, which is used to divide the active region into multiple segments or to isolate the active device. As shown in Figure 17, in some embodiments, dielectric material 166 has a longitudinal axis along the Y direction.

[0058] Figures 18A, 18B, and 18C are views of various stages of fabricating a semiconductor device structure 100 according to some embodiments. As shown in Figures 18A and 18B, the sacrificial gate structure 130 and the second semiconductor layer 108 are replaced by a gate dielectric layer 170 and a gate electrode layer 172. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms openings between the gate spacers 138 and between the first semiconductor layer 106. The dielectric materials of the dielectric layer 163 and the dielectric material 166 are substantially unaffected by the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 can be removed first by any suitable process (e.g., dry etching, wet etching, or a combination thereof), followed by the removal of the sacrificial gate dielectric layer 132, which can also be performed by any suitable process (e.g., dry etching, wet etching, or a combination thereof). In some embodiments, a wet etchant (e.g., a tetramethylammonium hydroxide (TMAH) solution) can be used to selectively remove the sacrificial gate electrode layer 134 without removing the gate spacer 138, dielectric material 166, dielectric layer 163, and CESL 162.

[0059] The second semiconductor layer 108 can be removed using a selective wet etching process. In cases where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of Si, the chemicals used in the selective wet etching process remove the SiGe without substantially affecting the Si and the dielectric materials of the gate spacer 138, dielectric material 166, dielectric layer 163, and dielectric spacer 144. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant (e.g., but not limited to hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), phosphoric acid (H3PO4)), a dry etchant (e.g., a fluorine-based gas (e.g., F2) or a chlorine-based gas (e.g., Cl2)), or any suitable isotropic etchant.

[0060] After the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106) is formed, a gate dielectric layer 170 is formed around the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on the gate dielectric layer 170. The gate dielectric layer 170 and the gate electrode layer 172 may be collectively referred to as the gate structure 174. In some embodiments, an interface layer (IL) (not shown) is formed between the exposed surface of the first semiconductor layer 106 and the gate dielectric layer 170. In some embodiments, the gate dielectric layer 170 comprises one or more layers of dielectric material, such as silicon oxide, silicon nitride, or high-k dielectric material, other suitable dielectric materials, and / or combinations thereof. Examples of high-k dielectric materials include HfO₂, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, zirconium oxide, alumina, titanium oxide, hafnium dioxide-alumina (HfO₂-Al₂O₃) alloys, other suitable high-k dielectric materials, and / or combinations thereof. The gate dielectric layer 170 can be formed using CVD, ALD, or any suitable deposition technique. The gate electrode layer 172 can comprise one or more layers of conductive material, such as polycrystalline silicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, TiN, WN, TiAl, TiAlN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or any combination thereof. The gate electrode layer 172 can be formed using CVD, ALD, electroplating, or other suitable deposition techniques. The gate electrode layer 172 can also be deposited on top of the dielectric layer 163. The gate dielectric layer 170 and gate electrode layer 172 formed on the dielectric layer 163 are then removed by means of, for example, CMP, until the top surface of the dielectric layer 163 is exposed.

[0061] Figure 19 is a top view of a semiconductor device structure 100 shown in Figures 18A, 18B, and 18C according to some embodiments. For clarity, some elements of the semiconductor device structure 100, such as dielectric layer 163, gate dielectric layer 170, and CESL 162, are omitted in Figure 19. As shown in Figure 19, the sacrificial gate electrode layer 134 is replaced by the gate electrode layer 172.

[0062] Figures 20A to 24A are cross-sectional side views of various stages of manufacturing a semiconductor device structure 100, taken along line FF of Figure 19 according to some embodiments. Figures 20B to 24B are cross-sectional side views of various stages of manufacturing a semiconductor device structure 100, taken along line GG of Figure 19 according to some embodiments. Figures 20C to 24C are cross-sectional side views of various stages of manufacturing a semiconductor device structure 100, taken along line HH of Figure 19 according to some embodiments. In some embodiments, dielectric layer 163 is optional and is not formed on the recessed ILD layer 164. As shown in Figures 20A, 20B, and 20C, a masking layer 180 is formed on the gate electrode layer 172, the ILD layer 164, and the dielectric material 166. Masking layer 180 may contain the same material as masking layer 150.

[0063] As shown in Figures 21A, 21B, and 21C, a mask structure 152 is formed on a mask layer 180. In some embodiments, the mask structure 152 is a three-layer photoresist. For example, the mask structure 152 may include a base layer 154 and an intermediate layer 156 disposed on the base layer 154. The base layer 154 and the intermediate layer 156 are made of different materials, such that the optical properties and / or etch properties of the base layer 154 and the intermediate layer 156 are different from each other. In some embodiments, the base layer 154 may be a carbon layer, while the intermediate layer 156 may be a silicon-rich layer designed to provide etch selectivity between the intermediate layer 156 and the base layer 154. The mask structure 152 further includes a photoresist layer 158, which may be a chemically amplified photoresist layer and may be a positive or negative photoresist. The photoresist layer 158 may comprise a polymer, such as phenol formaldehyde resin, poly(norbornene)-co-malaic anhydride (COMA) polymer, poly(4-hydroxystyrene) (PHS) polymer, phenol-formaldehyde (bakelite) polymer, polyethylene (PE) polymer, polypropylene (PP) polymer, polycarbonate polymer, polyester polymer, or acrylate-based polymer (e.g., poly(methyl methacrylate) (PMMA) polymer or poly(methacrylic acid) (PMAA)). The photoresist layer 158 may be formed by spin coating. The photoresist layer 158 may be patterned to have openings 182 formed therein.

[0064] As shown in Figures 22A, 22B, and 22C, opening 182 extends into the intermediate layer 156, the bottom layer 154, and the masking layer 180. The masking structure 152 can be removed after opening 182 is extended into the masking layer 180. Portions of the gate electrode layer 172 and the gate dielectric layer 170 are exposed in opening 182. Next, by removing the exposed portions of the gate electrode layer 172 and the gate dielectric layer 170, opening 182 is extended through the gate electrode layer 172 and the gate dielectric layer 170. In some embodiments, opening 182 extends into the insulating material 118, as shown in Figures 22B and 22C. As shown in Figure 22C, in some embodiments, the gate spacer 138 is protected by the masking layer 180 and is not removed during the removal of portions of the gate electrode layer 172 and the gate dielectric layer 170.

[0065] Figure 22D is a top view of one of the openings 182 according to some embodiments. For clarity, the gate dielectric layer 170 is omitted in Figure 22D. As shown in Figure 22D, the opening 182 is formed between the gate spacers 138. In other words, the opening 182 does not extend through the gate spacers 138 in the X direction. In some embodiments, the opening 182 extends through the gate spacers 138 in the X direction. As a result, the opening 182 will be located between the S / D regions 146 (FIG. 19) above and below the opening 182. With the dielectric material subsequently formed in the opening 182, the parasitic capacitance will increase due to the dielectric material located between the two conductive materials, which has a higher k value than the ILD layer 164. Therefore, by confining the opening 182 between the gate spacers 138 in the X direction, the parasitic capacitance is reduced.

[0066] As shown in FIG22D, the opening 182 is defined along the Y direction by the remaining portion of the gate electrode layer 172. In some embodiments, if the opening 182 extends between two S / D regions 146 (FIG. 19) along the X direction, parasitic capacitance may increase due to the dielectric material subsequently formed in the opening 182 located between the two conductive materials. Therefore, the dimension of the opening 182 along the Y direction is less than or equal to the distance between two adjacent S / D regions 146 along the Y direction. However, if the opening 182 is too small, parasitic capacitance may also increase because the dielectric material subsequently formed in the opening 182 is between the two portions of the gate electrode layer 172. Therefore, in some embodiments, the dimension of the opening 182 along the Y direction is about 80% to about 100% of the distance between two adjacent S / D regions 146 along the Y direction.

[0067] As shown in Figures 23A, 23B, and 23C, dielectric material 184 is deposited in the opening 182. Dielectric material 184 can comprise any suitable dielectric material. In some embodiments, dielectric material 184 comprises SiN or SiO. Next, a planarization process (e.g., a CMP process) can be performed to remove portions of dielectric material 184 deposited on the masking layer 180 and to remove the masking layer 180, as shown in Figures 24A, 24B, and 24C. The process described in Figures 20A through 24C can be referred to as a cut metal gate (CMG) process. The CMG process divides the gate electrode layer 172 into two or more portions, and these two or more portions can be controlled independently.

[0068] Figure 25 is a top view of a semiconductor device structure 100 shown in Figures 24A, 24B, and 24C according to some embodiments. For clarity, some elements of the semiconductor device structure 100, such as dielectric layer 163, gate dielectric layer 170, and CESL 162, are omitted in Figure 25. As shown in Figure 25, dielectric material 184 has a length L1 along the Y direction, and the length L1 is less than or equal to the distance D1 between adjacent S / D regions 146 along the Y direction. In some embodiments, the length L1 is about 80% to about 100% of the distance D1 to minimize parasitic capacitance. Furthermore, dielectric material 184 is located between gate spacers 138 and does not extend in the X direction between two adjacent S / D regions 146 along the Y direction to further reduce parasitic capacitance. In some embodiments, dielectric material 184 has a longitudinal axis along the Y direction, and the longitudinal axis of dielectric material 184 is substantially parallel to the longitudinal axis of dielectric material 166, as shown in Figure 25. Dielectric material 184 does not intersect with dielectric material 166.

[0069] Figure 26 is a top view of a semiconductor device structure 100 according to an alternative embodiment. For clarity, some elements of the semiconductor device structure 100, such as dielectric layer 163, gate dielectric layer 170, and CESL 162, are omitted in Figure 26. In some embodiments, misalignment may occur during the formation of opening 182 (Figures 22B and 22C), and a portion of gate electrode layer 172 may remain in opening 182 (Figure 22D). In other words, masking layer 180 may cover a portion of gate electrode layer 172, and the gate electrode layer 172 may not be fully cut to separate it into two or more portions. In some embodiments, dielectric material 184 may have a cross shape, as shown in Figure 26, to ensure a complete cut in gate electrode layer 172. In other words, the top surface of dielectric material 184 has a cross shape. In some embodiments, dielectric material 184 includes a vertical portion 184v extending in the Y direction and a horizontal portion 184h extending in the X direction. The vertical portion 184v has a length L1, which is less than or equal to the distance D1 between adjacent S / D regions along the Y direction. The horizontal portion 184h has a width W1, which is less than or equal to the distance D2 between adjacent S / D regions 146 along the X direction. In some embodiments, the width W1 is about 80% to about 100% of the distance D2. In some embodiments, the S / D regions 146 are in contact with the gate spacers 138, and the distance D2 is the sum of the widths (along the X direction) of the two gate spacers 138, the two gate dielectric layers 170, and the gate electrode layer 172.

[0070] The width of the vertical portion 184v along the X direction is significantly smaller than the width W1, and the length of the horizontal portion 184h along the Y direction is significantly smaller than the length L1. Because the length L1 and width L2 of the dielectric material 184 do not extend between the conductive materials (i.e., adjacent S / D regions 146), parasitic capacitance is minimized. Furthermore, in the event of an overlay (OVL) shift due to misalignment during the formation of the opening 182, the opening of the horizontal portion 184h ensures that the gate electrode layer 172 is divided into two or more portions. The dielectric material 184 electrically isolates the two or more portions of the gate electrode layer 172. In some embodiments, the photoresist layer 158 (FIGs 21B and 21C) is patterned in a cross shape, and this pattern is transferred to the gate electrode layer 172.

[0071] Figures 27A to 27C are top views of the dielectric material 184 of the semiconductor device structure 100 of Figure 26 according to some embodiments. As shown in Figure 27A, in some embodiments, the dielectric material 184 includes a vertical portion 184v and a horizontal portion 184h. In some embodiments, a sharp corner is formed between the vertical portion 184v and the horizontal portion 184h, as shown in Figure 26. In some embodiments, as shown in Figure 27A, a connecting portion 184c with a curved surface connects the horizontal portion 184h and the vertical portion 184v. In some embodiments, the connecting portion 184c is concave.

[0072] In some embodiments, the horizontal portion 184h has a substantially constant length (along the Y direction), and the vertical portion 184v has a varying width (along the X direction). For example, the vertical portion 184v includes an upper portion above the horizontal portion 184h and a lower portion below the horizontal portion 184h. The upper portion of the vertical portion 184v has a width that increases in the direction toward the horizontal portion 184h, and the lower portion of the vertical portion 184v also has a width that increases in the direction toward the horizontal portion 184h. In some embodiments, the vertical portion 184v has a substantially constant width (along the X direction), and the horizontal portion 184h has a varying length (along the Y direction). For example, the horizontal portion 184h includes a left portion located on a first side of the vertical portion 184v and a right portion located on a second side opposite to the first side of the vertical portion 184v. The left portion of the horizontal portion 184h has a length that increases in the direction toward the vertical portion 184v, and the right portion of the horizontal portion 184h also has a length that increases in the direction toward the vertical portion 184v.

[0073] In some embodiments, the dielectric material 184 has different shapes. For example, near the edges where the pattern type and density of the functional circuit change drastically, the etching process used to form the openings of the dielectric material 184 can have very different behavior than other parts of the circuit with different pattern densities. As a result, the dielectric material 184 can have a "T" shape (as shown in FIG27B) or an "L" shape (as shown in FIG28C).

[0074] Figures 28A and 28B are cross-sectional side views taken along line II of Figure 26 according to some embodiments of a semiconductor device structure 100 at one of the various stages of its fabrication. In some embodiments, as shown in Figure 28A, when opening 182 is formed, gate electrode layer 172, gate dielectric layer 170, and gate spacer 138 are removed, and dielectric material 184 contacts CESL 162. The removal of gate electrode layer 172, gate dielectric layer 170, and gate spacer 138 can be performed via one or more etching processes with low etch selectivity, so that the material of gate electrode layer 172, gate dielectric layer 170, and gate spacer 138 is removed at substantially the same rate. Alternatively, in some embodiments, one or more etching processes have high etch selectivity. As a result, gate electrode layer 172 and gate dielectric layer 170 are removed, while gate spacer 138 is recessed, as shown in Figure 28B. As shown in Figure 28B, gate spacers 138 are recessed, and dielectric material 184 is formed between and over the gate spacers 138. The dielectric material 184 includes a top having a first width along the X direction and a bottom having a second width along the X direction. In some embodiments, the first width is significantly greater than the second width due to the presence of the recessed gate spacers 138.

[0075] As described above, in some embodiments, dielectric material 184 is formed via a CMG process, while dielectric material 166 is formed via a CPODE process. Alternatively, dielectric material 184 is formed via a cut poly (CPO) process, which forms openings 182 in the sacrificial gate electrode layer 134 to divide the sacrificial gate electrode layer 134 into multiple portions, forms dielectric material 184 in the openings 182, and replaces the divided portions of the sacrificial gate electrode layer 134 with gate electrode layers 172 and gate dielectric layers 170. In some embodiments, dielectric material 166 is formed via a continuous metal on-diffusion edge (CMODE) process, which forms openings 160 in the gate electrode layers 172 and gate dielectric layers 170. Dielectric material 166 may be formed before or after the formation of dielectric material 184. In some embodiments, dielectric material 166 and dielectric material 184 are formed simultaneously. For example, openings 160 and 182 can be formed simultaneously using a single mask, and openings 160 and 182 can be filled simultaneously by dielectric material 166 and dielectric material 184, respectively.

[0076] In some embodiments, the semiconductor device structure 100 includes a nanostructured transistor, as shown. In some embodiments, the semiconductor device structure 100 includes a nanostructured transistor having hybrid fins located between fin structures 112. The hybrid fins may include one or more dielectric materials and are used to isolate the S / D region 146 and / or the gate electrode layer 172. Dielectric material 184 may be disposed on and / or around the hybrid fins, and dielectric material 166 may be disposed around the hybrid fins. In some embodiments, the semiconductor device structure 100 includes a FinFET with or without hybrid fins.

[0077] Embodiments of this disclosure provide a semiconductor device structure and a method for forming the same. In some embodiments, the semiconductor device structure includes a dielectric material 184 separating portions of a gate electrode layer 172. The dielectric material 184 has a length L1 and a width W1, wherein the length L1 is less than or equal to the distance D1 between adjacent S / D regions 146 along the Y direction, and the width W1 is less than or equal to the distance D2 between S / D regions 146 along the X direction. Some embodiments can achieve various advantages. For example, parasitic capacitance is minimized by preventing the dielectric material 184 (which has a higher k value than the ILD layer 164) from extending between adjacent S / D regions 146 (which may be conductive).

[0078] One embodiment is a semiconductor device structure. The structure includes a first source / drain region, a second source / drain region disposed adjacent to the first source / drain region along a first direction, a third source / drain region disposed adjacent to the first source / drain region along a second direction substantially perpendicular to the first direction, a first gate electrode layer disposed between the first and third source / drain regions, a second gate electrode layer disposed adjacent to the second source / drain region, and a first dielectric material disposed between the first and second gate electrode layers. The length of the first dielectric material is less than or equal to a first distance between the first and second source / drain regions.

[0079] Another embodiment is a semiconductor device structure. This structure includes a first source / drain region, a second source / drain region disposed adjacent to the first source / drain region along a first direction, a third source / drain region disposed adjacent to the first source / drain region along a second direction substantially perpendicular to the first direction, a first gate spacer and a second gate spacer disposed between the first source / drain region and the third source / drain region, and a first dielectric material disposed between the first gate spacer and the second gate spacer. The top surface of the first dielectric material has a cross shape.

[0080] Another embodiment is a method for forming a semiconductor device structure. The method includes: forming a first gate spacer and a second gate spacer on a substrate, and forming a first source / drain region and a second source / drain region on the substrate. The first source / drain region and the second source / drain region are aligned along a first direction and adjacent to the first gate spacer. The method further includes: forming a gate electrode layer between the first gate spacer and the second gate spacer, and forming an opening in the gate electrode layer. The size of the opening along the first direction is less than or equal to the distance between the first source / drain region and the second source / drain region. The method further includes: depositing a dielectric material in the opening.

[0081] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to perform the same purposes and / or achieve the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made without departing from the spirit and scope of this disclosure.

[0082] 100: Semiconductor Device Structure 101:Substrate 104: Semiconductor layer stacking 106: First semiconductor layer / semiconductor layer 108: Second semiconductor layer / semiconductor layer 112: Fin Structure 114: Trench 116: Substrate portion 118: Insulating materials 120: Isolation Area 130: Sacrificial gate structure 132: Sacrificial gate dielectric layer 134: Sacrificial gate electrode layer 136: Masking layer 138: Gate spacer 144: Dielectric spacer 146: Source / Drain (S / D) Region 150: Mask layer 160: Opening 162: Contact Etching Stop Layer (CESL) 163: Dielectric layer 164: Interlayer Dielectric (ILD) Layer 166: Dielectric materials 170: Gate dielectric layer 172: Gate electrode layer 174: Gate Structure 180: Mask layer 182: Opening 184: Dielectric Materials 184h: Horizontal section 184v: Vertical section 184c: Connecting part AA, BB, CC, DD, EE, FF, GG, HH, II: line L1: Length W1: Width D1, D2: Distance

Claims

1. A semiconductor device structure, comprising: a first source / drain region; a second source / drain region disposed adjacent to the first source / drain region along a first direction; a third source / drain region disposed adjacent to the first source / drain region along a second direction perpendicular to the first direction; a first gate electrode layer disposed between the first source / drain region and the third source / drain region; a second gate electrode layer disposed adjacent to the second source / drain region; and a first dielectric material disposed between the first gate electrode layer and the second gate electrode layer, wherein a length of the first dielectric material is less than or equal to a first distance between the first source / drain region and the second source / drain region; wherein a width of the first dielectric material is less than or equal to a second distance between the first source / drain region and the third source / drain region.

2. The semiconductor device structure as claimed in claim 1 further includes a first gate spacer and a second gate spacer, wherein the first gate electrode layer and the second gate electrode layer are disposed between the first gate spacer and the second gate spacer.

3. The semiconductor device structure as claimed in claim 2, wherein the first gate spacer and the second gate spacer are disposed between the first source / drain region and the third source / drain region.

4. The semiconductor device structure as claimed in claim 2, wherein the first dielectric material is disposed between the first gate spacer and the second gate spacer.

5. The semiconductor device structure as claimed in claim 1 further includes a second dielectric material disposed adjacent to the third source / drain region, wherein the second dielectric material extends across a first fin structure and a second fin structure.

6. The semiconductor device structure as claimed in claim 5, wherein the first dielectric material is disposed between the first fin structure and the second fin structure.

7. The semiconductor device structure of claim 1, wherein the first dielectric material includes a horizontal portion and a vertical portion, wherein the first dielectric material further includes a connecting portion connecting the horizontal portion and the vertical portion, wherein the connecting portion has a curved surface.

8. A semiconductor device structure comprising: a first source / drain region; a second source / drain region disposed adjacent to the first source / drain region along a first direction; a third source / drain region disposed adjacent to the first source / drain region along a second direction perpendicular to the first direction; a first gate spacer and a second gate spacer disposed between the first source / drain region and the third source / drain region; and a first dielectric material disposed between the first gate spacer and the second gate spacer, wherein a top surface of the first dielectric material has a cross shape; wherein a width of the first dielectric material is less than or equal to a distance between the first source / drain region and the third source / drain region.

9. The semiconductor device structure as claimed in claim 8, wherein the first dielectric material extends into the first gate spacer and the second gate spacer.

10. A method for forming a semiconductor device structure, comprising: forming a first gate spacer and a second gate spacer on a substrate; forming a first source / drain region, a second source / drain region, and a third source / drain region on the substrate, wherein the first source / drain region and the second source / drain region are aligned along a first direction and adjacent to the first gate spacer, and the third source / drain region is disposed adjacent to the first source / drain region along a second direction perpendicular to the first direction; forming a gate electrode layer between the first gate spacer and the second gate spacer; forming an opening in the gate electrode layer, wherein a dimension of the opening along the first direction is less than or equal to a distance between the first source / drain region and the second source / drain region; and depositing a dielectric material in the opening; wherein a width of the dielectric material is less than or equal to another distance between the first source / drain region and the third source / drain region.

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