Semiconductor image sensor structure and method forming the same

Abstract

This disclosure relates to a semiconductor image sensor structure and a method for forming the structure. The structure includes image sensing pixels with a critical dimension (CD) and a plurality of image sensing pixels separated by deep trench isolation (DTI) with a high aspect ratio (AR). Multiple portions of the DTI between adjacent image sensing pixels have substantially uniform bottom surface profiles compared to the bottom surface profile at the intersection of the DTIs. The method includes performing an etching process and a coating process to mitigate loading effects. The etching and coating processes are alternately repeated until the bottom surface of the DTI is etched into a doped layer beneath the image sensing pixels to prevent leakage of photoexcited charge carriers between the image sensing pixels.

Description

Technical Field

[0001] none Prior Technology

[0002] Semiconductor image sensors are configured to sense radiation, such as light. Complementary metal-oxide-semiconductor (CMOS) image sensors and charge-coupled device (CCD) sensors are used in a variety of applications, such as digital cameras and mobile phone cameras. These devices utilize an array of pixels in a substrate (which may include photodiodes and transistors) to sense radiation projected toward the pixels and convert the sensed radiation into electrical signals. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The various embodiments disclosed herein can be best understood by reading in conjunction with the accompanying drawings through the following detailed description. It should be noted that, in accordance with industry standard practice, the various features are not drawn to scale. In fact, for the sake of clarity, the dimensions of the various features may be arbitrarily increased or decreased. Figures 1A and 1B are horizontal cross-sectional views of a semiconductor image sensor device according to some embodiments; Figures 2A and 2B are vertical cross-sectional views of a semiconductor image sensor device according to some embodiments; Figures 3A and 3B are flowcharts of a method for configuring a structure in forming a semiconductor image sensor device according to some embodiments; Figures 4A and 7A are top views of an intermediate structure during the manufacturing process of a semiconductor image sensor device according to some embodiments; and Figures 4B to 6 and 7B to 13 are vertical cross-sectional views of an intermediate structure during the manufacturing process of a semiconductor image sensor device according to some embodiments. Implementation

[0005] The following disclosure provides numerous different embodiments or examples for implementing various features of this disclosure. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these specific examples are merely illustrative and not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various examples in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed, nor is it intended to limit the relationship between the various embodiments and / or configurations described.

[0006] Additionally, for ease of description, spatial relative terms (e.g., "below," "under," "lower," "above," "upper," and similar terms) may be used herein to describe the relationship between one component or feature and another illustrated in the figures. Besides the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or positioned in other orientations), and therefore the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] The terms "approximately" and "substantially" can mean a given quantity that varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%). These values ​​are merely illustrative and are not intended to limit this disclosure. It should be understood that, according to this disclosure, the terms "approximately" and "substantially" can mean a percentage of a given quantity.

[0008] Semiconductor image sensing devices (such as complementary metal-oxide-semiconductor (CMOS)) may include an array of one or more image sensing pixels to generate an image. The image sensing pixels are separated by deep trench isolation (DTI), which is filled with a dielectric material. Each image sensing pixel may include a photodiode to generate charge carriers in response to incident light. These charge carriers can pass through a doped layer beneath the image sensing pixel and are then collected as an electrical signal for processing by electronic devices. The doped layer may form a depletion region to prevent charge carriers generated by the image sensing pixel from leaking into adjacent image sensing pixels, thereby enabling the resolution of the signal provided by the image sensing pixel.

[0009] With advancements in semiconductor manufacturing technology, the critical dimension (CD) of image sensing pixel arrays can be scaled down, thereby providing improved performance, such as higher resolution, for semiconductor image sensing devices. For instance, by reducing the width of image sensing pixels to the micrometer range and the width of the depth-to-width (DTI) array to the sub-micrometer range, more image sensing pixels can be packaged within the limited sensing area of ​​a semiconductor image sensing device. During the manufacturing process of forming DTIs with narrower and deeper features (corresponding to higher aspect ratios), the etching rate of the bottom surface of the DTI can vary significantly depending on the local geometric details of the DTI. This phenomenon is also known as the "loading effect." Specifically, the bottom surface at the intersection of DTIs can have a larger CD and can be etched deeper than the bottom surface of the portion of the DTI farther from the intersection. As the CD of image sensing pixels shrinks, the effect of the higher etching rate at the bottom surface of the DTI intersection can extend to the DTI portion between adjacent image sensing pixels, resulting in an uneven bottom surface of the DTI. Therefore, some portions of the bottom surface of the DTI may not be etched deep enough into the doped layer, and photoexcited charge carriers between adjacent image sensing pixels may leak in these portions, thereby impairing the resolution of the semiconductor image sensing device.

[0010] To overcome the aforementioned challenges, the embodiments disclosed herein relate to the structure of a semiconductor image sensor device and a method for forming the structure. In some embodiments, the structure may include image sensing pixels having a small CD and separated by a DTI having a high aspect ratio (AR). In some embodiments, portions of the DTI between adjacent image sensing pixels may have a substantially uniform bottom surface profile to prevent photoexcited charge carrier leakage between the image sensing pixels. In some embodiments, the method may include performing an etching process and a coating process to mitigate loading effects. In some embodiments, the etching process and the coating process may be repeated alternately until the bottom surface of the DTI is etched into a doped layer beneath the image sensing pixels.

[0011] Please refer to Figures 1A to 2B showing the image sensor device 100. Figure 1A illustrates a top view of the image sensor device 100 according to some embodiments. Figure 1A also illustrates a horizontal cross-sectional view of structure 105, which is an enlarged portion of the image sensor device 100. Figure 1B also illustrates another horizontal cross-sectional view of structure 105 according to some embodiments. Figure 2A illustrates a vertical cross-sectional view of structure 105 corresponding to line A-A' in Figures 1A and 1B according to some embodiments. Figure 2B illustrates a cross-sectional view of structure 105 corresponding to line B-B' in Figures 1A and 1B according to some embodiments. It should be noted that the horizontal cross-sectional view shown in Figure 1A corresponds to line C-C' in Figures 2A and 2B, and the horizontal cross-sectional view shown in Figure 1B corresponds to line D-D' in Figures 2A and 2B.

[0012] Referring to Figures 1A to 2B, structure 105 may include a doped layer 112 disposed on a substrate 104 and an array of a plurality of pixels 120, with the doped layer 112 surrounding a plurality of lower portions of the array of pixels 120. The substrate 104 may extend along a horizontal direction (e.g., the x and / or y axes) and have a top surface perpendicular to a vertical direction (e.g., the z-axis). The substrate 104 may include a semiconductor material, such as silicon (Si). In some embodiments, the substrate 104 may include a crystalline silicon substrate (e.g., a Si wafer). In some embodiments, substrate 104 may include (i) elemental semiconductors, such as silicon or germanium (Ge); (ii) compound semiconductors, including silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs), and / or indium antimonide (InSb); (iii) alloy semiconductors, including silicon germanium carbide (SiGeC), silicon germanium (SiGe), gallium arsenide phosphide (GaAsP), indium gallium phosphide (InGaP), indium gallium arsenide (InGaAs), indium gallium arsenide phosphide (InGaAsP), indium aluminum arsenide (InAlAs), and / or aluminum gallium arsenide (AlGaAs); (iv) or combinations thereof. Furthermore, substrate 104 may be doped according to design requirements (e.g., p-type substrate or n-type substrate). In some embodiments, substrate 104 may be undoped. In some embodiments, substrate 104 may be doped with a p-type dopant (e.g., boron (B), indium (In), aluminum (Al), or gallium (Ga)) or an n-type dopant (e.g., phosphorus (P), arsenic (As), or antimony (Sb)). In some embodiments, the crystal orientation of substrate 104 may be (100), (110), or (111). In some embodiments, substrate 104 may include a grain, a buffer layer on the grain, and an interlayer dielectric having conductive vias and / or wires embedded in the interlayer dielectric. In some embodiments, the conductive vias and / or wires may be coupled to external electrical components, such as transistors, resistors, capacitors, and inductors. In some embodiments, electrical components may be included in the interlayer dielectric of substrate 104. In some embodiments, a doped layer 112 may be disposed on the interlayer dielectric.

[0013] Referring to Figures 2A and 2B, substrate 104 may include a die 610, a buffer layer 608 disposed on the die 610, and an interlayer dielectric 502 disposed on the buffer layer 608. In some embodiments, the die 610 may be a semiconductor wafer bonded through the buffer layer and the interlayer dielectric 502. The buffer layer 608 provides mechanical bonding strength and electrical isolation between the interlayer dielectric 502 and the die 610, and may include a dielectric material, such as silicon oxide, silicon nitride, any other suitable dielectric material, and / or combinations thereof. The interlayer dielectric 502 may include silicon oxide, silicon nitride, any other suitable dielectric material, and / or combinations thereof. In some embodiments, the interlayer dielectric 502 may include a transistor 508 electrically coupled to pixel 120 to process charge signals generated by pixel 120 according to optical signals. Transistor 508 may include a metal-oxide-semiconductor field-effect transistor (MOS FET), a fin-FET, a gate-all-around field-effect transistor (GAA-FET), and / or combinations thereof. In some embodiments, transistor 508 may include p-type and / or n-type transistors. In some embodiments, transistor 508 includes a charge transport transistor, a transfer transistor, a reset transistor, an amplification transistor, a selection transistor, a source follower transistor, and / or a readout transistor. In some embodiments, interlayer dielectric 502 may include a plurality of interconnect layers coupling transistors 508 to each other and / or to external circuitry. The interconnect layers may include conductive vias 504 and wires 506. Conductive vias 504 and wires 506 may include conductive materials, such as copper, aluminum, tungsten, doped polysilicon, any other suitable conductive material, and / or combinations thereof. Other circuitry and devices for detecting and processing photo-excited charge carriers may also be embedded in interlayer dielectric 502 and are not shown for simplicity.

[0014] Referring to Figures 1A to 2B, the doped layer 112 may extend along the horizontal directions (x-axis and y-axis) between pixels 120 and surround the lower portion of pixels 120. For example, the doped layer 112 may include multiple portions 112x extending along the x-axis and multiple portions 112y extending along the y-axis. It is worth noting that, according to Figures 1A and 1B, since line A-A' in Figures 1A and 1B does not pass through portion 112y, portion 112y shown in Figure 2B is not part of a cross-section but is viewed against the background. The doped layer 112 may be doped with p-type or n-type dopants to form a depletion region beneath the array of pixels 120 to prevent photo-excited charge carriers from leaking between adjacent pixels 120. In some embodiments, the doped layer 112 may comprise the same elemental semiconductor or the same compound semiconductor as the substrate 104. In some embodiments, the doped layer 112 may comprise a semiconductor different from the semiconductor in the substrate 104. In some embodiments, the doped layer 112 may be doped with a p-type dopant (e.g., B, Al, Ga, and / or In) or an n-type dopant (e.g., P, As, and / or Sb). In some embodiments, the crystal orientation of the doped layer 112 may be (100), (110), or (111). In some embodiments, the doping concentration of the doped layer 112 may be between about 1 × 10¹⁷ cm⁻³ and about 5 × 10¹⁸ cm⁻³. In some embodiments, the thickness of the doped layer 112 may be between about 0.3 μm and about 5 μm. In some embodiments, the doped layer 112 may be formed by an ion implantation process. In some embodiments, the doped layer 112 may be formed by a diffusion process.

[0015] Referring to Figures 1A to 2B, the pixels 120 disposed on the substrate 104 are separated from each other by the doped layer 112 and the deep trench isolation (DTI) 142. In some embodiments, the array of pixels 120 may include multiple columns and multiple rows of pixels 120. For example, the array of pixels 120 may include 480 columns and 640 rows, such that the resolution of the image sensor device 100 is 480 × 640. It is worth noting that, according to Figures 1A and 1B, since the line A-A' in Figures 1A and 1B does not pass through the pixel 120, the pixel 120 depicted in Figure 2B is not part of a cross-section and is viewed through the background. In some embodiments, the pixels 120 may have the same shape, such as a rectangular shape with a width W1 and a length L1, as shown in Figures 1A and 1B. In some embodiments, the pixels 120 may have a square shape with a width W1 equal to a length L1. In some embodiments, the pixels 120 may have other shapes, such as circles, ellipses, triangles, polygons, or any other suitable shape. In some embodiments, the pixel 120 may have different shapes. In some embodiments, the width W1 may be between about 0.5 μm and about 10 μm. In some embodiments, the length L1 may be between about 0.5 μm and about 10 μm.

[0016] Pixel 120 includes a radiation sensing region capable of absorbing incident light and generating photoexcited charge carriers, which can be collected through substrate 104 and further converted into electrical signals and processed by transistor 508 in interlayer dielectric 502. In some embodiments, pixel 120 may include the same elemental semiconductor or the same compound semiconductor as doped layer 112. In some embodiments, each pixel 120 may be doped with both p-type and n-type dopants to form a photodiode structure, such as a PN junction or a PIN junction. In some embodiments, pixel 120 may include a pinned layer photodiode, a photogate, a reset transistor, a source follower transistor, a transfer transistor, other suitable structures, and / or combinations thereof. In some embodiments, pixel 120 may be doped using an ion implantation process. In some embodiments, pixel 120 may be doped using a diffusion process.

[0017] Referring to Figures 1A to 2B, DTI 142 extends along a horizontal direction (e.g., the x-axis and y-axis). For example, as shown in Figures 1A, 2A, and 2B, DTI 142 may include DTI 142x separating pixels 120 in different columns and DTI 142y separating pixels 120 in different rows. In some embodiments, DTI 142x / 142y may have a width W between about 0.03 μm and about 0.5 μm. In some embodiments, the ratio of width W1 to width W may be between about 2 and about 20. DTI 142 may include a plurality of intersections 142c, where DTI 142x and 142y intersect each other, as shown in Figure 1A. In some embodiments, DTI 142 may be formed by etching the material originally located between pixels 120, thereby isolating pixels 120.

[0018] In some embodiments, the intersection 142c and DTI 142x / 142y may have different critical dimensions (CD). For example, the CD of DTI 142x / 142y may be a width W, which is smaller than the CD of intersection 142c as measured by the width C of the recess in intersection 142c. In some embodiments, the ratio of width C to width W may be between about 1 and about 3. In some embodiments, because the CDs of intersection 142c and DTI 142x / 142y are different, and the etch rates of intersection 142c and DTI 142x / 142y may be different, the etchant may reach the bottom of intersection 142c more easily than it reaches the bottom of DTI 142x / 142y, resulting in a difference in depth between intersection 142c and DTI 142x / 142y. This is also known as the "loading effect". For example, as shown in Figure 2A, the depth Dt near the midpoint of a portion between two adjacent intersections 142c may differ from the depth Dc within the intersection 142c. In some embodiments, depths Dc and Dt may be between about 0.5 μm and about 5 μm. In some embodiments, depth Dc may be greater than depth Dt. For example, depth Dc may be about 0.1 μm to about 0.4 μm deeper than depth Dt. In some embodiments, the aforementioned loading effect becomes more pronounced for trenches with a higher aspect ratio (AR), which may be defined as the ratio of the trench depth to the trench's CD. In some embodiments, the aspect ratio of DTI 142 may be between about 5:1 and about 50:1. For example, the aspect ratio of DTI 142 may be about 5:1, 10:1, 20:1, 30:1, 40:1, and 50:1.

[0019] In some embodiments, the load effect may affect the profile of the bottom surface of the DTI 142. Figure 2A is a cross-sectional view of one of the DTI 142x of structure 105 drawn along line A-A' as shown in Figures 1A and 1B, according to some embodiments. Figure 2A illustrates the bottom surface 245x of the DTI 142x, the bottom surface 245y of the DTI 142y, and the bottom surface 245c of the intersection 142c. As shown in Figure 2A, the bottom surface 245c may have a recess. Each bottom surface 245x of the DTI 142x includes a center 245xc, which is the midpoint between two adjacent intersections 142c.

[0020] Forming a substantially uniform bottom surface profile of the DTI is challenging due to loading effects. In some embodiments, due to the uneven profile of the bottom surface of the DTI, some portions below the bottom surface of the DTI may lie above the doped layer 112. Since these portions may not be doped with the appropriate doping distribution as the doped layer 112, leakage channels for photoexcited charge carriers in adjacent pixels 120 can be formed through these portions below the bottom surface of the DTI, thereby impairing the performance of the array of pixels 120 and the image sensor device 100.

[0021] In some embodiments, as shown in Figure 2A, the loading effect can be mitigated by forming a substantially uniform profile of the bottom surface of the DTI 142 between adjacent pixels. In some embodiments, the bottom surface 245c is more susceptible to the higher etch rate at the intersection 142c due to the loading effect. However, by using the method 300 described in Figures 3A and 3B thereafter, the bottom surface 245c is controlled to extend only partially toward the center 245xc of the DTI 142x, such that the profile of the bottom surface 245x can remain substantially uniform. In some embodiments, the DTI 142x / 142y can extend vertically deep enough between pixels 120 that the bottom surfaces 245x, 245y, and 245c reach the doped layer 112, and no portion below the bottom surface of the DTI is above the doped layer 112, thus avoiding the aforementioned leakage problem.

[0022] In some embodiments, bottom surfaces 245x and 245c may be joined at peak 245xp, and the distance r1 between peak 245xp and center 245xc is greater than the distance r2 between peak 245xp and the nearest side surface 120s of pixel 120, as shown in Figure 2A. The position of peak 245xp can be considered as the boundary or edge between adjacent bottom surfaces 245x and 245c. In some embodiments, the ratio of distance r1 to distance r2 may be greater than 2:1. In some embodiments, peak 245xp is formed because the position of center 245xc is lower than the position of peak 245xp, resulting in bottom surface 245x having a concave curvature, and center 245xc may be the lowest point of bottom surface 245x, as shown in Figure 2A. In some embodiments, the vertical distance t1 between center 245xc and peak 245xp may be between about 0 nanometers (nm) and about 100 nm. In some embodiments, the distance t1 may be approximately 0 nm, such that peak 245xp is not prominent, or the bottom surface 245x is substantially flat. For example, the variation of the bottom surface 245x may be less than 50 nm. In some embodiments, the vertical distance t2 between the center 245xc and the minimum value of the bottom surface 245c may be between approximately 300 nm and approximately 700 nm. In some embodiments, the vertical distance t1+t2 between peak 245xp and center 245xc may be between approximately 300 nm and approximately 800 nm. In some embodiments, the maximum gradient of the bottom surface 245x quantized by angle α may be less than the maximum gradient of the bottom surface 245c quantized by angle β. In some embodiments, angle α may be between approximately 0° and approximately 30°. In some embodiments, angle β may be between approximately 50° and approximately 90°. Similarly, the profile of the bottom surface 245y may be the same as or similar to the profile of the bottom surface 245x.

[0023] Referring to Figures 1A to 2B, in some embodiments, structure 105 may further include a gap filler 162 located above the side surfaces 120s and top surfaces 120t of pixel 120 and filling DTI 142. In some embodiments, the gap filler 162 may extend to the bottom surfaces 245x / 245y of DTI 142x / 142y and the bottom surface 245c of the intersection 142c. In some embodiments, due to the recess of the bottom surface 245c, the gap filler 162 may include a portion that is recessed and protrudes into the doped layer 112. In some embodiments, the gap filler 162 may include a dielectric material, such as silicon oxide, silicon nitride, any other suitable dielectric material, and / or combinations thereof. Structure 105 may further include a buffer layer 264 located on the gap filler 162. The buffer layer 264 may include the same or different dielectric material as the gap filler 162. In some embodiments, structure 105 may further include filters 268 and microlenses 270 located on buffer layer 264. In some embodiments, each filter 268 and each microlens 270 may be vertically aligned above one of the pixels 120. In some embodiments, adjacent filters 268 may be separated by a plurality of mesh structures 266. In some embodiments, filter 268 may include a plurality of filters, such as filters configured for red, blue, and / or green light. In some embodiments, filter 268 may include filters configured for invisible light (e.g., infrared and / or ultraviolet light). In some embodiments, microlens 270 may be configured to focus incident light onto pixel 120.

[0024] According to some embodiments, Figures 3A and 3B illustrate flowcharts of a method 300 configured to form structure 105 as shown in Figures 1A to 2B. This disclosure is not limited to the description of the steps and additional steps may be performed. Other steps may be performed between the steps of method 300 and are omitted for clarity. Furthermore, not all steps need to perform the disclosure provided herein. Additionally, some steps may be performed simultaneously or in a different order than that shown in Figures 3A and 3B. In some embodiments, one or more other steps may be performed in addition to or in place of the steps currently described. For illustrative purposes, method 300 may also be described with reference to the intermediate structures shown in Figures 4A to 13. Unless otherwise stated, the annotations of the elements described in Figures 1A to 2B also apply to Figures 4A to 13.

[0025] Referring to Figure 3A, method 300 begins at step 310, where a doped layer is formed in a substrate, as shown in Figures 4A through 6. Figure 4A is a top view of the semi-finished structure 105. Figures 4B, 5, and 6 are cross-sectional views of the semi-finished structure 105 (along line A-A' in Figure 4A). Figure 4C is a cross-sectional view of the semi-finished structure 105 (along line B-B' in Figure 4A). The structure 105 at this stage of method 300 may include a substrate 420 having a first surface 420b and a second surface 420f opposite to each other, and a doped layer 412 disposed on the substrate 420. For example, as shown in Figures 4A to 4C, a patterned mask 440 can be formed on a first surface 420b of substrate 420, and a dopant 450 can be implanted into multiple portions of the first surface 420b exposed by the mask 440 during an ion implantation method to form a doped layer 412, such that a portion of the substrate 420 beneath the first surface 420b can be doped and transformed into the doped layer 412. It should be noted that, according to Figure 4A, the patterned mask 440 shown in Figure 4B is not a cross-section but is viewed against the background. In some embodiments, the dopant 450 may include a p-type dopant (e.g., B, Al, Ga, and / or In) or an n-type dopant (e.g., P, As, and / or Sb). For example, the dopant 450 may include B. In some embodiments, the implantation energy of the dopant 450 may be between about 40 keV and about 80 keV to control the thickness of the doped layer 412 to between about 0.3 μm and about 5 μm. In some embodiments, the implantation dose of dopant 450 may be between about 1 × 10 13 cm⁻² and about 2.5 × 10 15 cm⁻² to control the dopant concentration of the doped layer 412 between about 1 × 10 17 cm⁻³ and about 5 × 10 18 cm⁻³.

[0026] In some embodiments, step 310 may further include forming an interlayer dielectric 502 on the doped layer 412 and forming an interconnect layer in the interlayer dielectric 502, as shown in Figure 5. A dielectric material is deposited on the doped layer 412 to form the interlayer dielectric 502. In some embodiments, the interlayer dielectric 502 may include silicon oxide, silicon nitride, any other suitable dielectric material, and / or combinations thereof. In some embodiments, a plurality of transistors 508 may be formed in the interlayer dielectric 502 and on the doped layer 412. In some embodiments, a plurality of conductive vias 504 and a plurality of wires 506 may be formed in the interlayer dielectric 502 to electrically couple the transistors 508. The conductive vias 504 and wires 506 may be formed of conductive materials, such as copper, aluminum, tungsten, doped polycrystalline silicon, any other suitable conductive material, and / or combinations thereof. The interconnect layer may be electrically coupled to the pixel formed in the steps described later. Other circuits and devices configured for detecting and processing photoexcited charge carriers can also be embedded in the interlayer dielectric 502, and are not shown for simplicity.

[0027] In some embodiments, step 310 may further include forming a buffer layer 608 on the interlayer dielectric 502 and forming a grain 610 on the buffer layer 608, as shown in Figure 6. It should be noted that the structure 105 in Figure 6 has a second surface 420f along the z+ direction, and is flipped over from the structure 105 in Figure 5, which has a second surface 420f along the z- direction. The interlayer dielectric 502, the buffer layer 608, and the grain 610 together constitute the substrate 104, as shown in Figures 1A to 2B. The buffer layer 608 may be formed by depositing a dielectric material, such as silicon oxide, silicon nitride, any other suitable dielectric material, and / or combinations thereof. The buffer layer 608 can be formed by a suitable deposition method, such as chemical vapor deposition (CVD), plasma-enhanced CVD (PECVD), atomic layer deposition (ALD), physical vapor deposition (PVD), any other suitable process, and / or combinations thereof. The buffer layer 608 can be planarized to form a smooth surface by a planarization process (e.g., chemical mechanical polishing). In some embodiments, the buffer layer 608 provides electrical isolation between the interlayer dielectric 502 and the die 610. In some embodiments, the die 610 can be bonded to the interlayer dielectric 502 using a suitable wafer bonding method and through the buffer layer 608, such as fusion bonding, anodic bonding, direct bonding, any other suitable bonding process, and / or combinations thereof. The die 610 provides mechanical support to the semi-finished image sensor device, allowing multiple processes to be performed on the second surface 420f. In some embodiments, the die 610 can be formed using a material similar to the substrate 420. In some embodiments, the grain 610 may include a glass substrate.

[0028] Referring to Figure 3A, method 300 continues with step 320, forming a patterned mask layer with cross grooves on the substrate, as shown in Figures 7A to 7C. Figure 7A is a top view of the semi-finished structure 105. Figure 7B is a cross-sectional view of the semi-finished structure 105 (along line A-A' in Figure 7A). Figure 7C is a cross-sectional view of the semi-finished structure 105 (along line B-B' in Figure 7A). For example, a mask layer 740 can be formed on the second surface 420f of the substrate 420. The mask layer 740 can be patterned through multiple openings 742 to expose multiple portions of the second surface 420f, which are then etched in subsequent steps to form a DTI. Specifically, the mask layer 740 has the same pattern as the patterned mask 440 shown in Figures 4A to 4C, and as shown in Figure 7C, the opening 742 is aligned with the doped layer 412 so that the DTI formed in subsequent steps can be aligned with the doped layer 412. It should be noted that, according to Figure 7A, the patterned mask 440 shown in Figure 7B is not part of a cross-section but is viewed through the background. As shown in Figures 7A to 7C, the opening 742 includes a plurality of slots 742x extending along the x-axis and a plurality of slots 742y extending along the y-axis, the slots 742x and 742y defining the positions of DTIs 142x and 142y (as shown in Figures 1A to 2B). Similarly, the intersection 742c of the slots 742x and 742y defines an intersection 142c. Therefore, the remaining portion of the second surface 420f covered by the mask layer 740 defines the pixel 120.

[0029] Referring to Figure 3A, method 300 continues with step 330, and a process for forming a DTI in the substrate according to a patterned mask layer, as shown in Figures 8 to 12, where Figures 8 to 12 are cross-sectional views of the semi-finished structure 105 (corresponding to line A-A' in Figure 7A). In some embodiments, step 330 may form a DTI having a substantially uniform bottom surface profile, as shown in Figure 2A. Step 330 is further described in detail in Figure 3B.

[0030] Referring to Figure 3B, step 330 begins at step 332 and involves etching the substrate exposed through the cross-slots, as shown in Figure 8. For example, etchant 840 may be used to etch multiple portions of the substrate 420 exposed through slots 742x and 742y to form multiple DTIs 842 and multiple pixels 820. It should be noted that the pixels 820 depicted in Figure 8 (and subsequently Figures 9 through 13) according to Figure 7A are not part of a cross-section and are viewed through the background. In some embodiments, etchant 840 may comprise reactive plasma from a reactive ion etching process. In some embodiments, the etching may be anisotropic etching, wherein the etching rate along the vertical direction (e.g., z-axis) is greater than the etching rate along the horizontal direction (e.g., x-axis or y-axis), such that the etching process toward the bottom surface of the DTI 842 is faster than the etching process toward the side surfaces of the DTI 842. In some embodiments, an inter-voltage bias may be applied to the substrate during the etching process. For example, a voltage between about 100 V and about 400 V can be used to bias the substrate 420. In some embodiments, the etching power of the etchant can be between about 500 W and about 1500 W. In some embodiments, due to the loading effect, the bottom surface 845c corresponding to the intersection 742c can be etched at a higher etching rate than the bottom surface 845x / 845y corresponding to the groove 742x / 742y, and the etchant 840 is more likely to reach the bottom surface because the CD of the intersection 742c is larger. Therefore, the etchant 840 is more likely to reach the bottom surface 845c than to reach the bottom surface 845x / 845y. In some embodiments, due to the loading effect, the bottom surface 845c can have a concave curvature, and the bottom surface 845x / 845y can have a convex curvature. In some embodiments, the etching process of step 332 can be stopped before the convex curvature of the bottom surface 845x / 845y becomes significant. For example, the etching process in step 332 can be stopped when the depth D8 of the bottom surface 845x reaches a certain value. In some embodiments, the ratio of depth D8 to the distance D between the top surface of pixel 820 and the doped layer 412 can be between about 0.1 and about 0.5. For example, the ratio of depth D8 to distance D can be between about 0.1 and about 0.2, between about 0.2 and about 0.3, between about 0.3 and about 0.4, and between about 0.4 and about 0.5.

[0031] Referring to Figure 3B, step 330 continues to step 334, the process of coating DTI through the polymer layer, as shown in Figure 9. For example, a polymer layer 960 can be deposited on the bottom surfaces 845x / 845y and 845c and on the side surfaces of DTI 842. In some embodiments, depositing the polymer layer 960 may include a gas 950 for providing the polymer material. In some embodiments, the gas 950 may include fluorocarbons (CxFy), hydrofluorocarbons (CxHyFz), sulfur fluorides (SxFy), hydrogen bromide (HxBry), or combinations thereof. In some embodiments, the gas 950 may include C4F8 with a flow rate between about 10 sccm and about 100 sccm. In some embodiments, the gas 950 may include SF6 with a flow rate between about 100 sccm and about 600 sccm. Similar to the loading effect in step 332, because the CD of the bottom surface 845c is larger, the bottom surface 845c is more likely to contact the etchant 840 than the bottom surfaces 845x / 845y. The bottom surface 845c in step 334 is also more likely to contact the gas 950 than the bottom surface 845c, thus resulting in a greater thickness of the deposited polymer layer 960 on the bottom surface 845c than on the bottom surfaces 845x / 845y. For example, as shown in Figure 9, the thickness t1 of the polymer layer 960 at a first location at the midpoint of the portion of the bottom surface 845x between two adjacent DTIs extending along the y-axis can be less than the thickness t2 of the polymer layer 960 at a second location on the bottom surface 845c, and the thickness of the polymer layer 960 increases monotonically from the first location to the second location. In some embodiments, the uneven thickness of the polymer layer 960 on the bottom surface 845x can compensate for or balance the convex curvature of the bottom surface 845x, such that the surface 945x of the polymer layer 960 on the bottom surface 845x can have a smaller convex curvature. In some embodiments, the surface 945x can be substantially flat. In some embodiments, the surface 945x can have a concave curvature. The curvature conditions of the surface 945x can be controlled by controlling the deposition conditions of the polymer layer 960 (e.g., deposition rate and / or deposition time). In some embodiments, by using a larger deposition rate and a longer deposition time, the curvature of the surface 945x can be changed from a convex curvature to a substantially flat concave curvature. In some embodiments, the coating process of step 334 can be stopped when the curvature of the surface 945x reaches the condition of compensating for or balancing the convex curvature of the bottom surface 845x.

[0032] Referring to Figure 3B, step 330 continues to step 336, a process of etching the polymer layer and substrate to increase the depth of the DTI, as shown in Figure 10. For example, etchant 1040 can be applied to etch multiple portions of the polymer layer 960 and the substrate 420 to increase the depth of the DTI 842 and the height of the pixel 820. Unless otherwise stated, in some embodiments, etchant 1040 may be the same as or similar to etchant 840, and the description of the etching process in step 332 applies to step 334. During step 334, the bottom surfaces 1045x and 1045y of the DTI 842 are formed to extend along the x-axis and y-axis, respectively. A bottom surface 1045c is also formed at the intersection of bottom surfaces 1045x and 1045y. In some embodiments, due to the thickness distribution of the polymer layer 960 formed in step 334, the etchant 1040 in step 336 can etch the bottom surfaces 1045x and 1045y to form a more uniform profile compared to the profiles of the bottom surfaces 845x and 845y as shown in Figure 8. For example, despite the loading effect, the etchant 1040 can etch a greater thickness in the substrate 420 after etching a thinner polymer layer 960 around the midpoint 1045xc compared to a location farther from the midpoint 1045xc and covered with a thicker polymer layer 960. Overall, the etched bottom surfaces 1045x and 1045y can have a more uniform profile than the bottom surfaces 845x and 845y (as shown in Figure 8). For example, the convex curvature of the bottom surfaces 1045x and 1045y can be less than that of the bottom surfaces 845x and 845y. In another example, the bottom surfaces 1045x and 1045y can be substantially flat. In the third example, the bottom surfaces 1045x and 1045y may have concave curvature. In some embodiments, the etching process of step 336 may be stopped when the depth D10 of the bottom surface 1045x reaches a certain value. In some embodiments, the ratio between depth D10 and distance D may be between about 0.2 and about 0.7. For example, the ratio between depth D10 and distance D may be between about 0.2 and about 0.3, between about 0.3 and about 0.5, and between about 0.5 and about 0.7.

[0033] Referring to Figure 3B, step 330 proceeds to step 338, determining whether the depth of the DTI is sufficient for the bottom surface of the DTI to reach the doped layer. As described in Figures 1A through 2B, if the bottom surface of the DTI is not completely etched into the doped layer, photoexcited charge carriers between pixels may leak and impair the performance of the image sensor device 100. Therefore, if the answer to the question in step 338 is "no," step 330 proceeds to a process of coating the DTI with a polymer layer by repeating step 334, as shown in Figure 11. For example, a polymer layer 1160 can be deposited on the bottom surfaces 1045x / 1045y and 1045c and on the side surfaces of the DTI 842. In some embodiments, depositing the polymer layer 1160 may include a gas 1150 for providing the polymer material. The description of the deposited polymer layer 960 in Figure 9 applies to the deposition of the polymer layer 1160. Step 330 then proceeds to step 336, a process of etching the polymer layer and the substrate to increase the depth of the DTI, as shown in Figure 12. For example, etchant 1240 can be applied to etch multiple portions of polymer layer 1160 and substrate 420 to increase the depth of DTI 842 and the height of pixel 820. In some embodiments, etchant 1240 can be the same as etchant 1040. In some embodiments, the coating process in step 334 and the etching process in step 336 can be repeated alternately multiple times (e.g., 2 to 5 times) until the answer to the question in step 338 is "yes". If the answer is "yes", then the entire bottom surface 1245x / 1245y and 1245c of DTI 842 has been etched into doped layer 412, as shown in Figure 12 and step 340, and pixel 120 is formed to be unaffected by charge carrier leakage. Step 330 can then be completed by a removal process to remove mask layer 740.

[0034] Referring to Figure 3A, method 300 continues to step 350, a process of filling the DTI with dielectric material to form multiple filters and multiple microlenses, as shown in Figure 13. Figure 13 is a cross-sectional view of structure 105 according to some embodiments. In some embodiments, forming image sensing pixels may include forming gap filler 162, buffer layer 264, mesh structure 266, filter 268, and microlens 270.

[0035] After gap filler 162 is formed over pixel 120 by overlay deposition, a planarization process is performed. Gap filler 162 fills DTI 842. Gap filler 162 can be formed using any suitable dielectric material, such as silicon oxide, silicon nitride, any other suitable dielectric material, and / or combinations thereof. In some embodiments, a pad layer (not shown) is formed between pixel 120 and gap filler 162. The pad layer can be formed using a high-k dielectric material, such as hafnium oxide (HfO 2), tantalum pentoxide (Ta 2O 5), zirconium dioxide (ZrO 2), aluminum oxide (Al 2O 3), other high-k materials, and / or combinations thereof. The material disposed in the gap filler 162 can be deposited using any suitable deposition method, such as atomic layer deposition (ALD), molecular beam epitaxy (MBE), high-density plasma CVD (HDPCVD), metal-organic CVD (MOCVD), remote plasma CVD (RPCVD), plasma-enhanced CVD (PECVD), electroplating, any other suitable method, and / or combinations thereof. After depositing the gap filler material, a planarization process (e.g., chemical mechanical polishing) is performed on the deposited gap filler material to form a flat top surface of the gap filler 162. In some embodiments, the gap filler 162 is deposited in the DTI 842 to prevent crosstalk between pixels 120.

[0036] In some embodiments, a buffer layer 264 may be formed on the top surface of the gap filler 162. After overlay deposition of the buffer material, a planarization process is performed to form the buffer layer 264 and provide a flat top surface for one or more subsequent manufacturing processes. In some embodiments, the buffer layer 264 may be the same dielectric material as the gap filler 162. In some embodiments, the buffer layer 264 may be a different dielectric material from the gap filler 162.

[0037] Mesh structure 266 is formed on buffer layer 264. In some embodiments, mesh structure 266 may be formed by depositing a metal layer on buffer layer 264 and performing a patterning process. Mesh structure 266 can be used to reduce crosstalk between pixels (e.g., between adjacent pixels) and may include a metal mesh configured to reflect light toward corresponding pixel 120. In some embodiments, mesh structure 266 is formed using a metal, such as copper, tungsten, aluminum, any other suitable metal, and / or combinations thereof. In some embodiments, mesh structure 266 is formed using any material with high reflectivity. In some embodiments, mesh structure 266 may have a stacked structure, wherein a plurality of additional dielectric grating structures are formed on mesh structure 266. In some embodiments, each mesh structure 266 may have a height between about 200 nm and about 300 nm (e.g., 200 nm to 300 nm). For example, mesh structure 266 may have a height of about 250 nm.

[0038] Multiple filters 268 may be formed on the buffer layer 264 between the mesh structure 266. Microlenses 270 may be formed above the filters 268 and the mesh structure 266. Each microlens 270 and each filter 268 are formed to be perpendicularly aligned with one of the pixels 120.

[0039] Pixel 120 is configured to sense radiation (or radiated waves), such as incident light projected toward microlens 270. The incident light enters the image sensor device 100 through the back surface and can be detected by one or more pixels 120. In some embodiments, in addition to detecting visible light, the image sensor device 100 can also be configured to detect non-visible light due to the increased depth of the trench semiconductor material and reduced crosstalk between pixels.

[0040] The embodiments disclosed herein relate to the structure of a semiconductor image sensor device and a method of forming the structure. In some embodiments, the structure may include a plurality of image sensing pixels having a small critical dimension (CD) and separated by deep trench isolation (DTI) having a high aspect ratio (AR). In some embodiments, multiple portions of the DTI between adjacent image sensing pixels may have a uniform bottom surface profile to prevent photoexcited charge carrier leakage between the image sensing pixels. In some embodiments, the method may include performing an etching process and a coating process to mitigate loading effects. In some embodiments, the etching process and the coating process may be repeated alternately until the bottom surface of the DTI is etched into a doped layer beneath the image sensing pixels.

[0041] In some embodiments, the method includes forming a doped layer in a substrate and forming a mask on the substrate. The mask is patterned such that it forms first and second trenches having intersecting top surfaces of the substrate and exposing them. The method may further include forming first and second trenches in the substrate according to the mask. Forming the first and second trenches includes etching the substrate, depositing polymer layers in the first and second trenches, forming bottom surfaces of the first and second trenches below the top surfaces of the doped layer, and forming a recess at the intersection of the first and second trenches. The bottom surface of the recess is lower than the bottom surfaces of the first and second trenches. The edges of the recess are higher than the bottom surfaces of the first and second trenches.

[0042] In some embodiments, the method includes forming a doped layer in a substrate; etching the substrate to form a first trench and a second trench; depositing a polymer layer in the first trench and the second trench; increasing the depth of the first trench and the second trench by etching the polymer layer and a portion of the substrate in the first trench and the second trench until the depth is greater than the distance between the doped layer and the top surface of the substrate; and forming a recess at the intersection of the first trench and the second trench, while increasing the depth of the first trench and the second trench. The edge of the recess is located above the bottom surface of the first trench and the second trench.

[0043] In some embodiments, a structure includes a doped layer disposed on a substrate; a first radiation sensing region, a second radiation sensing region, a third radiation sensing region, and a fourth radiation sensing region disposed on the substrate, wherein the doped layer surrounds the lower portions of the first, second, third, and fourth radiation sensing regions; and a first trench and a second trench intersect and separate the first, second, third, and fourth radiation sensing regions. The first and second trenches extend vertically to the top surface of the doped layer. The structure may further include a recess located at the intersection of the first and second trenches. The bottom surface of the recess is located below the bottom surfaces of the first and second trenches. The edge of the recess is located above the bottom surfaces of the first and second trenches.

[0044] It should be understood that the implementation portion, rather than the abstract portion, is intended to be configured to interpret the scope of the claims. The abstract portion of this disclosure may illustrate one or more, but not all, possible embodiments of this disclosure as conceived by the inventors, and therefore is not intended to limit the scope of the appended claims in any way.

[0045] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the various embodiments disclosed herein. Those skilled in the art should understand that they can simply use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purpose and / or the same advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of this disclosure.

[0046] 100: Image sensor device 104,420:Substrate 105: Structure 112: Doped layer 112x, 112y: Partial 120,820: pixels 120s: Side surface 120t: Top surface 142, 142x, 142y, 842: DTI / Deep Trench Isolation 142c, 742c: Intersection 162: Gap filler 245c,245x,245y,845c,845x,845y,1045c,1045x,1045y,1245c,1245x,1245y: Bottom surface 245xc: Center 245xp: Peak 264,608: Buffer layer 266: Grid Structure 268: Filter 270: Microlens 300: Method 310,320,330,332,334,336,338,340,350: Steps 412: Doped layer 420b: First surface 420f: Second surface 440: Mask 450: Dopant 502: Interlayer dielectric 504: Conductive via 506: Wire 508: Transistor 610: Grain 740: Masking layer 742: Opening 742x, 742y: slots 840, 1040, 1240: Etching agent 945x: Surface 950, 1150: Gas 960, 1160: Polymer layer 1045xc: Midpoint A-A', B-B', C-C', D-D': Lines CW,W1: Width D,r1,r2,t1,t2: Distance Dc, Dt, D8, D10: Depth L1: Length x, y, z: axes z: Direction α, β: Angles

[0047] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for forming a semiconductor image sensor structure, comprising: A doped layer is formed in a substrate; A mask is formed on the substrate, wherein the mask includes a first groove and a second groove that intersect each other and expose a top surface of the substrate; And forming a first trench and a second trench in the substrate according to the mask, wherein forming the first trench and the second trench includes: etching the substrate; A polymer layer is deposited in the first trench and the second trench; a bottom surface of the first trench and a bottom surface of the second trench are formed below a top surface of the doped layer; and a recess is formed at an intersection of the first trench and the second trench, wherein a bottom surface of the recess is lower than the bottom surface of the first trench and the bottom surface of the second trench, and wherein an edge of the recess is higher than the bottom surface of the first trench and the bottom surface of the second trench.

2. The method as described in claim 1, wherein depositing the polymer layer comprises: A first portion of the polymer layer is deposited on the bottom surface of the first trench and the bottom surface of the second trench at a first deposition rate; And a second portion of the polymer layer is deposited in the depression at a second deposition rate greater than the first deposition rate.

3. The method as described in claim 1, wherein forming the first trench and the second trench includes forming the first trench and the second trench having an aspect ratio between about 5 and about 50.

4. The method as described in claim 1, wherein: Forming the depression includes forming the depression having a first width; and forming the first groove and the second groove includes forming the first groove and the second groove having a second width, wherein a ratio of the first width to the second width is between about 1 and about 3.

5. A method for forming a semiconductor image sensor structure, comprising: A doped layer is formed in a substrate; the substrate is etched to form a first trench and a second trench; A polymer layer is deposited in the first trench and the second trench; the depth of the first trench and the second trench is increased until the depth is greater than a distance between the doped layer and a top surface of the substrate, wherein increasing the depth includes etching the polymer layer and a portion of the substrate in the first trench and the second trench; and a recess is formed at an intersection of the first trench and the second trench while increasing the depth of the first trench and the second trench, wherein a bottom surface of the recess is located below a bottom surface of the first trench and a bottom surface of the second trench, and an edge of the recess is located above the bottom surface of the first trench and the bottom surface of the second trench.

6. The method as described in claim 5, further comprising forming a third trench that intersects the first trench and is parallel to the second trench, wherein a ratio of a distance between the second trench and the third trench to a width of the second trench is between about 2 and about 10.

7. The method as described in claim 6, further comprising forming another recess at an intersection of the first groove and the third groove, wherein a distance between the recess and the other recess is less than the distance between the second groove and the third groove.

8. The method of claim 5, wherein forming the recess includes forming a side surface of the recess, and wherein an angle between the side surface of the recess and the top surface of the substrate is between about 50° and about 90°.

9. A semiconductor image sensor structure, comprising: A doped layer is disposed on a substrate; A first radiation sensing region, a second radiation sensing region, a third radiation sensing region, and a fourth radiation sensing region are disposed on the substrate, wherein the doped layer surrounds a lower portion of the first radiation sensing region, a lower portion of the second radiation sensing region, a lower portion of the third radiation sensing region, and a lower portion of the fourth radiation sensing region; a first trench and a second trench intersect each other and separate the first radiation sensing region, the second radiation sensing region, the third radiation sensing region, and the fourth radiation sensing region, wherein the first trench and the second trench extend vertically to a top surface of the doped layer; a recess is located at an intersection of the first trench and the second trench and extends into the doped layer, wherein a bottom surface of the recess is lower than a bottom surface of the first trench and a bottom surface of the second trench, and an edge of the recess is higher than the bottom surface of the first trench and the bottom surface of the second trench; and a dielectric layer fills the first trench, the second trench, and the recess.

10. The semiconductor image sensor structure as described in claim 9, wherein a variation of the bottom surface of the first trench is less than about 50 nanometers.

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