Vias, semiconductor devices and method of forming thereof

Abstract

A conductive via, a semiconductor device having a conductive via, and a method for forming the semiconductor device are provided. The conductive via includes: a first end and a second end; a first portion adjacent to the first end; a second portion adjacent to the second end; and an intermediate portion located between the first portion and the second portion, wherein the conductive via is composed of metal particles, the metal particles in the first portion having a first particle size; the metal particles in the second portion having a second particle size; and the metal particles in the intermediate portion having a third particle size; the first particle size is larger than the third particle size; and the second particle size is larger than the third particle size.

Description

Technical Field

[0001] none Prior Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and using photolithography to pattern the various material layers to form circuit elements and components thereon.

[0003] The semiconductor industry continues to increase the integration density of various electronic components by continuously reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed.

[0004] In efforts to reduce the size of integrated circuits and minimize RC delay, three-dimensional integrated circuits (3DICs) and stacked chips are commonly used. Therefore, conductive through-substrate vias (TSVs) are used in 3DICs and stacked chips. For example, conductive TSVs are typically used to connect integrated circuits on a chip to the back side of the chip. Furthermore, conductive TSVs are also used to provide short ground paths for grounding integrated circuits through the back side of the chip, which can be covered by a grounding metal film. Summary of the Invention

[0005] none Simple Explanation of the Diagram

[0006] When read in conjunction with the accompanying drawings, the following detailed description is the best way to understand the nature of this disclosure. It should be noted that, in accordance with standard industry practice, the various features are not drawn to scale. In practice, for clarity of explanation, the dimensions of the various features may be arbitrarily increased or decreased. Figure 1 is a flowchart illustrating a method according to some embodiments. Figures 2 through 8 are cross-sectional views of intermediate stages in the fabrication of a wafer including conductive TSVs and deep conductive vias connected to the conductive TSVs, according to various embodiments. Figure 9 illustrates a wafer including conductive TSVs and deep conductive vias, wherein the metal lines connecting the conductive TSVs and deep conductive vias are formed in a process step separate from the process steps used to form the conductive TSVs and deep conductive vias. Figure 10 illustrates a wafer including conductive TSVs and deep conductive vias, wherein the conductive TSVs extend through a substrate that is substantially free of integrated circuit devices. Figures 11 to 22 are cross-sectional views of an intermediate stage in the fabrication of a wafer including conductive TSVs and deep conductive vias connected to the conductive TSVs, according to various embodiments. Figure 23 is a diagram illustrating the particle size distribution in the top, middle, and bottom portions of a conductive TSV according to various embodiments. Figure 24 is a cross-sectional view of a portion of a layer deposited on the trench sidewall, for example, in the intermediate stage of Figure 16. Figure 25 is a cross-sectional view of a portion of an alloy layer formed after an annealing process, such as that shown in Figure 20. Implementation

[0007] The following disclosure provides numerous different embodiments or instances for implementing various features of the subject matter. Specific examples of elements and configurations are described below to simplify this disclosure. Of course, these specific embodiments or instances are merely examples and are not intended to be limiting. For example, the formation of a first feature over or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not need to be in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances in this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0008] Additionally, for ease of description, spatial relative terms (such as "above," "overlapping," "on top," "upper part," "top," "below," "subordinate to," "below," "under," "below," "lower part," "bottom," "side," and the like) may be used herein to describe the relationship between one component or feature and another component or feature illustrated in the figures. Besides the orientation depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and therefore the spatial relative descriptive terms used herein may be interpreted accordingly.

[0009] In some embodiments herein, a "material structure" is a structure comprising at least 50 wt.% of the identified material (e.g., at least 60 wt.% of the identified material, at least 75 wt.% of the identified material, at least 90 wt.% of the identified material, at least 95 wt.% of the identified material, or at least 99 wt.% of the identified material); and a structure formed from the "material" comprises at least 50 wt.% of the identified material, such as at least 60 wt.% of the identified material, at least 75 wt.% of the identified material, at least 90 wt.% of the identified material, at least 95 wt.% of the identified material, or at least 99 wt.% of the identified material. For example, in some embodiments, each of the tungsten structure and the structure formed from tungsten is at least 50 wt.%, at least 60 wt.%, at least 75 wt.%, at least 90 wt.%, at least 95 wt.%, or at least 99 wt.% of tungsten.

[0010] For the sake of brevity, typical technologies associated with semiconductor device manufacturing are not described in detail herein. Furthermore, the various tasks and processes described herein can be incorporated into more comprehensive processes or procedures with additional functionality not described in detail herein. Specifically, various processes in semiconductor device manufacturing are well-known, and therefore, for the sake of brevity, many typical processes are simply mentioned or omitted entirely without providing well-known process details. As will be apparent to those skilled in the art upon fully reading this disclosure, the structures disclosed herein can employ various technologies and can be incorporated into various semiconductor devices and products. Additionally, it should be noted that semiconductor device structures contain varying numbers of elements, and a single element shown in the illustration may represent multiple elements.

[0011] This document presents embodiments of semiconductor devices and methods for manufacturing such devices having through-substrate vias (TSVs), which are sometimes also referred to as through-silicon vias (TSVs) when formed in a silicon substrate. The methods described herein can be readily integrated into current process flows.

[0012] Some embodiments described herein relate to three-dimensional integrated circuit (3DIC) applications constructed by vertically stacking different chips or wafers together into a single package. For example, in 3DIC applications, through-substrate vias (TSVs) can be applied to chip-to-chip stacks or chip-to-intercalator stacks for vertical electrical signal connections. Some embodiments described herein optimize the stress and void distribution within the TSVs to achieve 100% yield during manufacturing. For example, a selective metallization process for forming conductive TSVs can be used to achieve a large-small-large (LSL) particle distribution along the height or depth of the TSV, i.e., from top to bottom (or from bottom to top). Furthermore, this particle distribution can be symmetrical.

[0013] In some embodiments, a method is provided to obtain a large-small-large (LSL) particle distribution in a conductive structure, such as in a conductive via such as a conductive TSV. The method may utilize a metallization process to fill a trench, comprising forming an outer adhesive layer with a thickness gradient, forming an outer barrier layer with a constant thickness on the outer adhesive layer, forming an inner adhesive layer with a thickness gradient on the outer barrier layer, removing the inner adhesive layer from the bottom surface of the trench, and subsequently forming a seed layer and performing an annealing process to form an alloy with particles before filling the trench with a conductive filler.

[0014] In some embodiments, the annealing process used to form the TSV may cause small voids to diffuse to the middle or mid-layer height of the TSV, rather than to the bottom of the TSV. Specifically, voids move downwards from the top of the TSV to the mid-layer, while voids move upwards from the bottom of the TSV to the mid-layer.

[0015] Furthermore, the conductive TSV material forms relatively large particles at the top and bottom of the conductive TSV, and relatively small particles in the middle layer. Because voids migrate from high stress to low stress (i.e., from larger particles to smaller particles or to the top or bottom surface of the TSV), there is no void accumulation at the interface between the top of the conductive TSV and the top redistribution layer (RDL), nor at the interface between the bottom of the conductive TSV and the bottom redistribution layer (RDL). Instead, most voids diffuse towards the middle layer of the conductive TSV. Therefore, there is less void accumulation on the top or bottom surface of the TSV.

[0016] The embodiments described herein avoid or reduce the formation of large voids, sidewall delamination, conductive TSV end protrusions, and TSV / grain interface voids. The embodiments described herein improve the particle distribution of conductive materials (such as copper and / or titanium-copper alloys) to form conductive TSVs with high thermal stability.

[0017] The embodiments disclosed herein offer advantages over the prior art, although it should be understood that other embodiments may offer different advantages, but not all advantages are necessarily discussed herein, and no particular advantage is required in any of the embodiments.

[0018] For the purposes of the following discussion, Figure 1 provides a flowchart of a method 900 for manufacturing a semiconductor device during a semiconductor manufacturing process. The method 900 is described below in conjunction with Figures 2 to 10 and Figures 11 to 22, which illustrate semiconductor devices at various manufacturing stages according to the method 900.

[0019] Figures 2 through 8 are cross-sectional views of intermediate stages in the fabrication of a wafer including conductive TSVs and deep conductive vias connected to the conductive TSVs, according to various embodiments. Figure 9 illustrates a wafer including conductive TSVs and deep conductive vias, wherein metal lines connecting the conductive TSVs and deep conductive vias are formed in a process step separate from the process steps for forming the conductive TSVs and deep conductive vias. Figure 10 illustrates a wafer including conductive TSVs and deep conductive vias. Figures 11 through 22 are cross-sectional views of intermediate stages for forming conductive TSVs within trenches.

[0020] Referring to Figure 2, method 900 includes, in operation S902, providing a semiconductor device 20 comprising a substrate 22 and an integrated circuit 24 (represented by a transistor) therein. According to various embodiments, device 20 is a wafer comprising an active integrated circuit device 24, such as a transistor. Substrate 22 may be a semiconductor substrate, such as a bulk silicon substrate, although substrate 22 may be formed of other semiconductor materials, such as germanium silicon, gallium arsenide, and / or the like. A semiconductor device, such as a transistor (represented by transistor 24), may be formed on the front surface 22a of substrate 22. Interconnect structure 26 is formed on the front side of substrate 22. Interconnect structure 26 may include an interlayer dielectric (ILD) 28 (with electrodes of the transistor located therein) and contact plugs 30 in the ILD 28, wherein contact plugs 30 may be formed of tungsten or other metallic materials.

[0021] Furthermore, interconnect structure 26 includes an inter-metal dielectric (IMD) 34 and metal lines / pads 38 (including 38A and 38B) and vias 40 within the IMD 34. The IMD 34 may be formed of a low-k dielectric material with a low k value, such as below about 2.5 or even below about 2.0. Interconnect structure 26 may include a bottom metallization layer (typically referred to as M1) and a top metallization layer (typically referred to as Mtop), and a plurality of metallization layers in between, including a metallization layer (M2) directly above M1, a metallization layer (M3) directly above M2, and the like. Metal features in interconnect structure 26 may be electrically coupled to semiconductor device 24. The metal lines / pads 38 and vias 40 may be formed of copper or a copper alloy and may be formed using known damascene processes. The metal lines / pads 38 include metal lines 38A and metal pads 38B, wherein metal pads 38B are used to connect subsequently formed deep vias.

[0022] The interconnect structure 26 may further include one or more passivation layers 47 directly above the metallization layer Mtop. The passivation layer 47 may be a non-low-k dielectric layer and may be formed of silicon oxide, silicon nitride, undoped silicate glass, polyimide, or the like. In addition, additional metal lines / pads and vias (not shown) may be formed in the passivation layer 47.

[0023] In alternative embodiments, such as the example in Figure 10, device 20 is an insertion wafer and substantially free of integrated circuit devices, including active devices such as transistors and diodes formed therein. In these embodiments, substrate 22 may be formed of a semiconductor material or a dielectric material. The dielectric material may be silicon oxide, an organic material such as polyimide, a mixture of materials such as molding compounds, glass, or the like. Furthermore, insertion device 20 may include or exclude passive devices such as capacitors, resistors, inductors, varactor diodes, and / or the like.

[0024] Referring to Figure 3, after forming interconnect structure 26, interconnect structure 26 may or may not include layer 47. Method 900 may include, in operation S904, forming trenches, such as TSV trenches 44 and deep via trenches 46 (including 46A, 46B, 46C, 46D, and possibly more undetailed trenches). In this embodiment, photoresist 50 is formed and patterned. Subsequently, TSV trenches 44 and deep via trenches 46 are formed simultaneously by etching. TSV trenches 44 extend into substrate 22, while deep via trenches 46 stop at corresponding metal pads 38B, where metal pads 38B are exposed through deep via trenches 46. Furthermore, the formation of deep via trenches 46 may stop at metal pads 38B in any of the different metallization layers in any desired combination within the range of M1 to Mtop.

[0025] In this embodiment, a pattern loading effect is used to simultaneously form TSV trenches 44 and deep via trenches 46 with different depths. It has been observed that when forming certain via openings, via openings with larger horizontal dimensions may have greater depths than those with smaller dimensions, even if the via openings are formed using the same etching process. As a result of the pattern loading effect in the etching process, and also due to the size difference between the TSV trenches 44 and the deep via trenches 46, the resulting TSV trenches 44 and deep via trenches 46 will have different depths. By appropriately adjusting the horizontal dimensions W1 to W5, when the desired depth D1 of the TSV trench 44 is achieved, desired depths D2, D3, D4, D5, and similar depths are also achieved. This can reduce undesirable over-etching of the metal pads 38B, and therefore minimize undesirable damage to the metal pads 38B. Therefore, the horizontal size W1 of the TSV trench 44 (which can be either diameter or length / width, depending on the shape of the TSV trench 44) is greater than the horizontal sizes W2, W3, W4, and W5 of the deep via trench 46. In embodiments, the ratio of W1 / W2 (or W1 / W3, W1 / W4, etc.) can be greater than about 1.5, greater than about 5, or even greater than about 100. Furthermore, the depth D1 of the TSV trench 44 is greater than the depth D2 of the deep via trench 46. In embodiments, the ratio of D1 / D2 (or D1 / D3, D1 / D4, etc.) can be greater than about 5 or even greater than about 5000. Furthermore, in the illustrated embodiments, W2 can be greater than W3, where the ratio W2 / W3 is greater than about 1.2; W3 can be greater than W4, where the ratio W3 / W4 is greater than about 1.2; and W4 can be greater than W5, where the ratio W4 / W5 is greater than about 1.2.

[0026] Referring to Figure 4, method 900 can continue in operation S906 to form insulating layer 52. For example, insulating layer 52 can be deposited and patterned, and metal pads 38B can be exposed through openings in insulating layer 52.

[0027] Method 900 can continue in operation S950 to form an adhesion / barrier layer stack 54.

[0028] Method 900 can continue in operation S962 to form a thin seed layer (not shown in Figure 4). For example, the seed layer can be formed over the stack 54. The material of the seed layer can include copper or a copper alloy, and may also include metals such as silver, gold, aluminum, and combinations thereof. In an embodiment, the seed layer is formed by sputtering. In other embodiments, other commonly used methods, such as electroplating or electroless plating, can be used.

[0029] Referring to Figure 5, method 900 may include, in operation S968, patterning a photomask 56 on a previously formed structure. In an embodiment, for example, the photomask 56 includes photoresist. In an exemplary embodiment, the resulting conductive TSVs need to be connected to metal pads 38B. Therefore, openings 58 are formed in the photomask 56 to expose TSV trenches 44 and deep via trenches 46.

[0030] In Figure 6, method 900 includes, in operation S970, filling trenches 44, 46 and opening 58 with a metallic material and forming conductive vias 60, such as conductive TSVs 60 in TSV trenches 44, deep conductive vias 62 in deep via trenches 46, and metallic lines 66 in opening 58. In various embodiments, the filler material comprises copper or a copper alloy, but other metals, such as aluminum, silver, gold, and combinations thereof, may also be used. Formation methods may include printing, electroplating, electroless plating, and the like. In the same deposition process of filling TSV trenches 44 with metallic material, the same metallic material may also be filled in opening 58 to form metallic lines 66, also referred to as redistribution lines (RDLs).

[0031] Next, as shown in Figure 7, method 900 includes removing the photomask 56 in operation S972.

[0032] Method 900 can be included in performing the annealing process in S980.

[0033] Method 900 can continue in operation S982 to flatten the surface of the device.

[0034] In Figure 8, method 900 includes, in operation S994, forming a front-side interconnect structure, such as including a redistribution layer (RDL), a passivation layer 72, and under-bump metallurgy (UBM) 74 and metal bumps 76. The metal bumps 76 may be solder bumps, copper bumps, and may include other layers / materials, such as nickel, gold, solder, and / or the like.

[0035] In Figure 8, method 900 includes, in operation S996, polishing the back side of the apparatus 20 to expose the conductive TSV 60. Furthermore, method 900 includes, in operation S998, forming a back-side interconnect structure on the back side of the apparatus 20, which may include a UBM 78 and bonding pads / metal bumps 80. Additionally, a back-side interconnect structure (not shown) comprising a plurality of redistribution layers may be formed between the conductive TSV 60 and the metal bumps 80, electrically coupling the conductive TSV 60 and the metal bumps 80.

[0036] Figure 9 illustrates an alternative embodiment. This embodiment is essentially the same as the embodiment shown in Figure 8, except that the metal line 66 is not formed in the same process as forming the conductive TSV 60 and the via 62. In the embodiment of Figure 9, after forming the structure shown in Figure 4, the TSV trench 44 and the via trench 46 are filled, followed by a planarization process such as chemical mechanical polishing (CMP) to remove excess metal, thus forming the conductive TSV 60 and the via 62. After the CMP process, the conductive TSV 60 and the via 62 are electrically disconnected from each other. Next, the metal line 66 is formed to electrically couple the conductive TSV 60 to the via 62. In the resulting structure, a diffusion barrier layer 67 separates the conductive TSV 60 and the via 62 from the metal line 66. The diffusion barrier layer 67 may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. However, in the structure shown in Figure 8, no diffusion barrier layer is formed to separate the conductive TSV 60 and the deep via 62 from the metal line 66.

[0037] Although a device die containing semiconductor devices is used as an example in the illustrated figures, the teachings provided by the embodiments can be readily applied to interposers that do not include integrated circuitry, such as transistors, resistors, diodes, capacitors, and / or the like. Similarly, by using the embodiments, deep vias can be formed on the interconnect structures in either or both of the front and back interconnect structures, wherein the deep vias connect to TSVs in the interposer.

[0038] Figures 11 to 22 illustrate embodiments for forming a conductive interconnect structure 200, a conductive via 200, such as a conductive TSV 60 formed in the embodiments shown in Figures 2 to 10.

[0039] Figure 11 illustrates the device 120 after operation S904, where a trench 144 similar to the TSV trench 44 of the embodiments from Figures 2 through 10 has been formed. Specifically, the trench 144 is etched into the device layer, typically indicated by reference numerals (device layer 110). The device layer 110 may comprise various dielectric layers or substrates. In Figure 11, the trench 144 extends from the upper device surface 121 through the device layer and has opposing trench sidewalls 112 and a trench bottom surface 114. As shown, the trench 144 has an opening 111 at the upper device surface 121.

[0040] Figure 12 illustrates the device 120 after performing operation S906, where an insulating layer 152 is formed in the trench 144. For example, the insulating layer 152 may be silicon oxide or another suitable insulating material. In some embodiments, the insulating layer 152 is conformally deposited and formed along the upper device surface 121, the trench sidewall 112, and the trench bottom surface 114.

[0041] Figures 13 through 16 illustrate embodiments of the adhesion / barrier stack 54 for forming operation S950. Specifically, as shown in Figure 13, method 900 may continue in operation S954, as appropriate, to form an adhesion layer 154 over insulating layer 152. In some embodiments, adhesion layer 154 is titanium (Ti). In other embodiments, adhesion layer 154 may be selected from common materials such as titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof. In some embodiments, adhesion layer 154 is deposited using physical vapor deposition (PVD). As shown, adhesion layer 154 is formed over upper device surface 121, over trench sidewall 112, and over trench bottom surface 114. Due to the deposition process, adhesion layer 154 typically has a larger relative thickness above the horizontal surfaces (i.e., above upper device surface 121 and trench bottom surface 114) compared to the vertical surface of trench sidewall 112. Furthermore, due to the deposition process, the adhesive layer 154 is typically formed on the trench sidewall 112 with a thickness decreasing from the upper device surface 121, which has the largest self-adhesive layer thickness, to the trench bottom surface 114, which has the smallest adhesive layer sidewall thickness and can be zero.

[0042] For example, in one embodiment, the adhesive layer 154 has a maximum lateral or sidewall thickness on each trench sidewall 112 at the opening 111 of the trench 144, which is 25 to 60 times, such as 50 times, greater than the minimum lateral or sidewall thickness on each trench sidewall 112 adjacent to the trench bottom surface 114. For example, the maximum sidewall thickness of the adhesive layer 154 can be 250 nanometers (nm), and the minimum sidewall thickness of the adhesive layer 154 can be 5 to 10 nanometers (nm). In this example, the vertical thickness of the adhesive layer 154 above the trench bottom surface 114 can be 50 nanometers (nm).

[0043] In Figure 14, method 900 can continue in operation S956, forming a barrier layer 156 over the adhesive layer 154. In some embodiments, the barrier layer 156 is titanium nitride (TiN). In other embodiments, the barrier layer 156 can be selected from common materials such as titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof. In some embodiments, the barrier layer 156 is deposited using chemical vapor deposition (CVD). As shown, the barrier layer 156 is formed over the upper device surface 121, over the trench sidewall 112, and over the trench bottom surface 114. In some embodiments, the barrier layer 156 is conformally deposited over the upper device surface 121, the trench sidewall 112, and the trench bottom surface 114 with substantially the same thickness.

[0044] In Figure 15, method 900 can continue in operation S958, forming an adhesive layer 158 over the barrier layer 156. In some embodiments, the adhesive layer 158 is titanium (Ti). In other embodiments, the adhesive layer 158 can be selected from common materials such as titanium, titanium nitride, tantalum, tantalum nitride, and combinations thereof. In some embodiments, the adhesive layer 158 is deposited using physical vapor deposition (PVD). As shown, the adhesive layer 158 is formed over the upper device surface 121, over the trench sidewall 112, and over the trench bottom surface 114. Due to the deposition process, the adhesive layer 158 typically has a larger relative thickness above the horizontal surfaces (i.e., above the upper device surface 121 and the trench bottom surface 114) compared to the greater vertical surface area of ​​the trench sidewall 112. Furthermore, due to the deposition process, the adhesive layer 158 is typically formed on the trench sidewall 112 with a thickness decreasing from the upper device surface 121, which has the largest self-adhesive layer thickness, to the trench bottom surface 114, which has the smallest adhesive layer sidewall thickness and can be zero.

[0045] For example, in one embodiment, the adhesive layer 158 has a maximum lateral or sidewall thickness on each trench sidewall 112 at the opening 111 of the trench 144, which is 25 to 60 times, such as 50 times, greater than the minimum lateral or sidewall thickness on each trench sidewall 112 adjacent to the trench bottom surface 114. For example, the maximum sidewall thickness of the adhesive layer 158 can be 250 nanometers (nm), and the minimum sidewall thickness of the adhesive layer 158 can be 5 to 10 nanometers (nm). In this example, the vertical thickness of the adhesive layer 158 above the trench bottom surface 114 can be 50 nanometers (nm).

[0046] In Figure 16, method 900 can continue at operation S960, performing an etching process to remove the adhesive layer 158 from above the trench bottom surface 114. For example, a dry etching process such as plasma etching can be performed. In some embodiments, the etching process can use argon gas without reactive ions. In some embodiments, the etching process is a sputtering etching process. For example, ions such as argon ions can bombard the adhesive layer 158 above the trench bottom surface 114. The etching process can be highly oriented, such that it can be concentrated on the trench bottom surface 114.

[0047] As a result of the etching process, the adhesive layer 158 is removed from above the bottom surface 114 of the trench. Specifically, the barrier layer 156 is exposed at the bottom surface 114 of the trench. Furthermore, as indicated by arrow 159, the removed adhesive layer can form a gaseous material 160, which is subsequently deposited on the trench sidewall 112. Thus, the coverage of the adhesive layer material above the lower portion of the trench sidewall 112 can be increased. It should be noted that using an adhesive layer material (such as titanium) to enhance the coverage of the lower portion of the trench sidewall 112 can prevent copper delamination.

[0048] Figure 16 illustrates the formation of a metallized stack or structure comprising an adhesive layer 154, a barrier layer 156, and an adhesive layer 158, configured to provide a final conductive TSV with a desired particle distribution. As shown, layers 154, 156, and 158 are provided with different thicknesses at different locations in the trench 144. For example, layers 154, 156, and 158 may be provided with different thicknesses above the bottom surface 114 of the trench, at a bottom sidewall location 141 adjacent to the bottom surface 114 of the trench, at a top sidewall location 143 adjacent to the opening 111 of the trench, and at a middle or intermediate height sidewall location 142 located between the top sidewall location 143 and the bottom sidewall location 141. In some embodiments, the intermediate height sidewall location 142 may be equidistant from the top sidewall location 143 and the bottom sidewall location 141. In other embodiments, the intermediate height sidewall position may be located above the bottom surface 114 of the trench at a height equal to 20%, 30%, 40%, 50%, 60%, 70%, or 80% of the total height 108 of the trench 144.

[0049] In Figure 17, method 900 can continue in operation S962, forming a seed layer 162 above the upper device surface 121 and in the trench 144. The seed layer 162 may be copper. In some embodiments, the material of the seed layer may comprise copper or a copper alloy, and may also comprise metals such as silver, gold, aluminum, and combinations thereof.

[0050] In this embodiment, the seed layer 162 is formed using physical vapor deposition (PVD). Furthermore, compared to the material of the barrier layer 156 (i.e., titanium nitride), the seed layer 162 can be selectively deposited over the material of the adhesive layer 158 (e.g., titanium). Therefore, the seed layer can have its maximum thickness over the adhesive layer 158 at the horizontal device surface 121, its minimum thickness or zero thickness over the barrier layer 156 at the trench bottom surface 114, and a decreasing thickness over the adhesive layer 158 at the trench sidewall 112, from the upper device surface 121 where the seed layer thickness is greatest towards the trench bottom surface 114 where the seed layer sidewall thickness is smallest and can be zero.

[0051] At Figure 18, method 900 can continue in operation S970, depositing conductive material 164 to fill trench 144. In some embodiments, conductive material 164 is a metallic material, such as copper. In various embodiments, the filler material 164 comprises copper or a copper alloy, but other metals, such as aluminum, silver, gold, and combinations thereof, may also be used. Formation methods may include printing, electroplating, electroless plating, and the like. For example, conductive material 164 may be deposited using electrochemical deposition (ECD).

[0052] Typically, during the deposition process, the conductive material 164 is formed in small particles. As used herein, "small particles" have a maximum size of 0.5 micrometers (μm). In some embodiments, the small particles have a maximum size of 0.4 μm, 0.3 μm, 0.2 μm, or 0.1 μm. In some embodiments, at least 50 wt.%, at least 60 wt.%, at least 70 wt.%, at least 80 wt.%, at least 90 wt.%, at least 95 wt.%, or at least 99 wt.% of the conductive material 164 is formed from small particles.

[0053] Because the adhesive layer 158 has been previously removed from the bottom surface 114 of the trench, the conductive material 164 directly contacts the barrier layer 156, such as titanium nitride, at the bottom surface 114 of the trench. Along the trench sidewall 112, the conductive material and / or seed layer 162 directly contacts the adhesive layer 158, such as titanium.

[0054] At Figure 19, method 900 can continue in operation S980, performing an annealing process. The annealing process may relate to particle growth and stress release. Specifically, during the annealing process, a conductive material 164, such as copper, is heated above its recrystallization temperature to release internal stress and is subsequently allowed to cool under controlled conditions. Therefore, particles of the conductive material 164 may grow during the annealing process. Furthermore, voids may migrate from high-stress locations to low-stress locations, i.e., from large particles to small particles. Additionally, an alloy 166 may be formed in the region adjacent to the conductive material 164 and the adhesive layer 158. For example, a titanium-copper alloy 166 may be formed. It should be noted that a seed layer 162 is formed between the conductive material 164 and the adhesive layer 158 or barrier layer 156. For simplicity, the conductive material 164 is described below, and can be collectively referred to as the separately deposited seed layer 162 and the conductive material 164. Furthermore, in some embodiments, the seed layer 162 and the conductive material 164 are made of the same material.

[0055] As described above, prior to the annealing process, the conductive material 164 directly contacts the barrier layer 156 at the bottom surface 114 of the trench, and the conductive material and / or seed layer 162 directly contacts the adhesive layer 158 along the trench sidewall 112. Therefore, the formation of titanium-copper alloy along the trench sidewall 112 may be more extensive than that at the bottom surface 114 of the trench.

[0056] In the embodiments described herein, the conductive material 164 may form large particles in some areas and small particles in some areas, as described below with respect to Figure 22.

[0057] In Figure 20, method 900 can continue in operation S982, planarizing the upper device surface 121. Specifically, the material of layers 152, 154, 156, 158, 162, and 164 located above the upper device surface 121 can be removed, for example, by a chemical mechanical planarization (CMP) process. Therefore, the conductive via 200 is formed and defined within the trench 144.

[0058] In Figure 21, method 900 can continue in operation S994 to form a front interconnect structure, including a redistribution layer (RDL) 170 formed above the conductive via 200.

[0059] In Figure 22, method 900 can continue in operation S996, polishing the back of the apparatus and removing the apparatus layer 110 below the trench bottom surface 114, thereby opening the trench bottom surface 114. For example, a planarization process can be used to open the trench bottom surface 114. In addition, the bottom end of the conductive TSV 200 can be polished.

[0060] At Figure 22, method 900 can further continue in operation S998 by forming a back-side interconnect structure including a redistribution layer (RDL) 170 above the open bottom end of the conductive TSV 200.

[0061] As shown in Figure 22, the conductive TSV 200 has a top surface 201 and a bottom surface 202. The top surface 201 and the bottom surface are separated by a vertical height 208, for example, in the Z direction. The vertical height 208 can be from 5 micrometers to 200 micrometers (μm). Furthermore, the conductive TSV 200 has a lateral width or critical dimension in the X direction perpendicular to the Z direction. The lateral critical dimension 209 can be from 1 micrometer to 10 micrometers (μm). Therefore, the conductive TSV 200 can have an aspect ratio (height / critical dimension) of 5 to 20.

[0062] In addition, the conductive TSV 200 includes a top portion 210 adjacent to the top surface 201, a bottom portion 220 adjacent to the bottom surface 202, and an intermediate portion 230 or middle layer located between the top portion 210 and the bottom portion 220. Each portion 210, 220, and 230 may have a height equal to one-third of the total height 208.

[0063] Figure 22 further illustrates the particles 300 formed within the conductive TSV 200 during the annealing process of operation S980. As shown, relatively large particles 310 are formed at the top portion 210 and the bottom portion 220. Additionally, relatively small particles 330 are formed at the middle portion 230. In some embodiments, the metal particles 310 in the first portion 210 have a first particle size, the metal particles 320 in the second portion 220 have a second particle size, and the metal particles 330 in the middle portion 230 have a third particle size, wherein the first particle size is larger than both the second and third particle sizes, and wherein the second particle size is larger than the third particle size.

[0064] In some embodiments, the largest particle 310 in the first portion 210 defines the largest particle size. In some embodiments, the largest particle size is 200 nanometers to 1000 nanometers (nm).

[0065] In some embodiments, the average particle size of the particles 310 in the first portion 210 is greater than 0.5 times the maximum particle size. For example, the average particle size of the particles 310 in the first portion 210 may be greater than 0.51, 0.52, 0.53, 0.54, 0.55, 0.56, 0.57, 0.58, 0.59, 0.60, 0.61, or 0.62 times the maximum particle size. Furthermore, the average particle size of the particles 310 in the first portion 210 may be less than 0.8, 0.75, 0.74, 0.73, 0.72, 0.71, 0.70, 0.69 times the maximum particle size, or less than 0.68, 0.67, 0.66, 0.65, 0.64, 0.63, or 0.62 times the maximum particle size.

[0066] In some embodiments, the average particle size of the particles 320 in the second portion 220 is greater than 0.5 times the maximum particle size. For example, the average particle size of the particles 320 in the second portion 220 may be greater than 0.51, 0.52, 0.53, 0.54, or 0.55 times the maximum particle size. Furthermore, the average particle size of the particles 320 in the second portion 220 may be less than 0.8, 0.75, 0.7, 0.65, 0.64, 0.63, 0.62, 0.61, 0.60, 0.59, 0.58, 0.57, 0.56, or 0.55 times the maximum particle size.

[0067] In some embodiments, the average particle size of the particles 330 in the intermediate portion 230 is less than 0.5 times the maximum particle size. For example, the average particle size of the particles 330 in the intermediate portion 230 may be greater than 0.25, 0.28, 0.3, 0.31, 0.32, 0.33, 0.34, 0.35, 0.36, or 0.37 times the maximum particle size. Furthermore, the average particle size of the particles 330 in the intermediate portion 230 may be less than 0.5, 0.49, 0.48, 0.47, 0.46, 0.45, 0.44, 0.43, 0.42, 0.41, 0.40, 0.39, 0.38, or 0.37 times the maximum particle size.

[0068] Figure 23 provides a particle size distribution map. In the figure, the vertical axis represents the number of particles on a logarithmic scale, and the horizontal axis represents the ratio of particle size to the maximum particle size (Gmax). As shown, one particle 310 in the top portion 210 has the maximum particle size, and no particles 320 or 330 have the maximum particle size. More than one particle 310 and more than one particle 320 have a size of 0.8 times the maximum particle size. A further number of particles 330 have a minimum size of 0.2 times the maximum particle size.

[0069] Without theoretical constraints, it is believed that the free surface above the opening of the trench 144, i.e., the unconstrained surface, forms large particles 310 in the top portion 210 (as shown in Figure 19). In the case of the free surface, there is no constraint in at least one direction, allowing for the growth of larger particles.

[0070] Furthermore, without being bound by theory, it is believed that the large amount of titanium available for forming the titanium-copper alloy from the titanium adhesive layer 158 results in the formation of small particles 330 in the intermediate portion 230. For example, the alloying of copper and titanium occurs at temperatures above 300°C; therefore, in annealing processes performed at temperatures below 300°C (such as at 400°C), more titanium-copper alloys are formed. In some embodiments, an annealing process can be performed such that all of the titanium adhesive layer 158 is converted into a titanium-copper alloy. As the titanium-copper alloy formation increases, copper particle growth can be suppressed, resulting in smaller particles. Furthermore, the copper-contacting surface of the titanium adhesive layer 158 can promote small particle growth at selected annealing temperatures, such as in an annealing process performed at 400°C.

[0071] Furthermore, without being bound by theory, it is believed that the formation of large particles 310 in the bottom portion 220 is partly due to the absence or minimal formation of the titanium-copper alloy. The alloying of copper and titanium nitride occurs at temperatures above 450°C; therefore, in annealing processes performed at temperatures below 450°C, such as at 400°C, almost no titanium-copper alloy forms from the titanium nitride barrier layer 156. With almost no or no formation of the titanium-copper alloy, copper particle growth is not inhibited. Furthermore, the surface of the titanium nitride barrier layer 156 forming the trench bottom surface 114 in contact with copper can promote large particle growth in selected annealing temperatures, such as annealing processes performed at 400°C.

[0072] It should be noted that the growth rate of copper particles is typically highest at free, unconstrained surfaces, and decreases in the order of silicon oxide layer, tantalum nitride layer, titanium nitride layer, tantalum layer, and finally, at titanium layer, where the growth rate is lowest. Therefore, the formation of titanium surrounding the middle portion 230, titanium nitride at the bottom surface 114 of the trench in the bottom portion 220, and trench 144 with an open free surface connecting to the top portion 210 provides for the formation of a conductive TSV 200 with the large-small-large particle size distribution shown in Figure 22. More specifically, the top portion 210 may have the largest particle size, or the largest average or mean particle size; the bottom portion 220 may have the second largest particle size, or the second largest average or mean particle size; and the middle portion 230 may have the smallest particle size, or the smallest average or mean particle size.

[0073] As described above, prior to the annealing process, the conductive material 164 directly contacts the barrier layer 156 at the bottom surface 114 of the trench, and the conductive material and / or seed layer 162 directly contacts the adhesive layer 158 along the trench sidewall 112. Therefore, the formation of titanium-copper alloy along the trench sidewall 112 may be more extensive than that at the bottom surface 114 of the trench.

[0074] Figure 22 further illustrates the formation of small voids 399 in the middle portion 230. Specifically, after heat treatment, the small voids 399 diffuse into the middle portion 230. Therefore, unlike the formation of large voids that may occur in other manufacturing processes of the bottom portion 220 and lead to delamination, the voids 399 may have little or no impact on the device yield.

[0075] The embodiments described herein further provide good adhesion between the copper conductive material 164 and the titanium nitride barrier layer 156 at the bottom surface 114 of the trench. Furthermore, the embodiments described herein use a re-sputtering or ion etching process to utilize the titanium material from the adhesive layer 158 removed from the bottom surface 114 of the trench to increase the coverage of the trench sidewalls 112. The increased amount of titanium on the trench sidewalls 112 in the bottom portion 220 improves adhesion and reduces delamination. Additionally, the embodiments described herein avoid barrier layer failure by using CVD-deposited titanium nitride as the barrier layer 156.

[0076] Figure 24 is a schematic cross-sectional view focusing on the trench sidewall 112 and the layers formed thereon prior to the annealing process (as shown in Figure 16). Figure 24 is a focused view of the trench sidewall 112, such as at the top sidewall position 143, the intermediate height sidewall position 142, or the bottom sidewall position 141, as identified in Figure 16.

[0077] As shown in Figure 24, an insulating layer 152 is formed on the trench sidewall 112, an adhesive layer 154 is formed on the insulating layer 152 and has a thickness T1, a barrier layer 156 is formed on the adhesive layer 154 and has a thickness T2, and an adhesive layer 158 is formed on the barrier layer 156 and has a thickness T3.

[0078] Thicknesses T1, T2, and T3 can be measured after depositing layers 154, 156, and 158, and after etching layer 158 from the bottom surface of the trench, i.e., after performing operation S960.

[0079] In the embodiments described herein, the thicknesses T1, T2, and T3 may vary depending on the height of the measurement location relative to the bottom surface 114 of the trench (or the depth relative to the trench opening 111). It should be noted that at the bottom sidewall location 141, the thickness may be measured at a position 5 μm above the bottom surface 114 of the trench or at a position 10% of the trench height above the bottom surface 114 of the trench. Furthermore, at the top sidewall location 143 adjacent to the trench opening 111, the thickness may be measured at a position 1 μm from the trench opening 111 or at a position 2% of the trench height below the trench opening 111.

[0080] For example, at the bottom sidewall location 141 (and in the bottom portion 220 of the conductive via 200), the thickness T1 can be from 1 nm to 10 nm, such as 2 nm. At the bottom sidewall location 141, the thickness T1 can be at least 1 nm, at least 1.1 nm, at least 1.2 nm, at least 1.3 nm, at least 1.4 nm, at least 1.5 nm, at least 1.6 nm, at least 1.7 nm, at least 1.8 nm, at least 1.9 nm, or at least 2.0 nm. Furthermore, at position 141 on the bottom sidewall, the thickness T1 can be up to 10 nm, up to 9 nm, up to 8 nm, up to 7 nm, up to 6 nm, up to 5 nm, up to 4 nm, up to 3.5 nm, up to 3 nm, up to 2.9 nm, up to 2.8 nm, up to 2.7 nm, up to 2.6 nm, up to 2.5 nm, up to 2.4 nm, up to 2.3 nm, up to 2.2 nm, up to 2.1 nm, or up to 2 nm.

[0081] Furthermore, at the bottom sidewall location 141 (and in the bottom portion 220 of the conductive via 200), the thickness T2 can be from 15 nm to 40 nm, such as 25 nm. At the bottom sidewall location 141, the thickness T2 can be at least 15 nm, at least 20 nm, at least 21 nm, at least 22 nm, at least 23 nm, at least 24 nm, at least 25 nm, at least 26 nm, at least 27 nm, or at least 30 nm. At the bottom sidewall location 141, the thickness T2 can be at most 40 nm, at most 35 nm, at most 34 nm, at most 33 nm, at most 32 nm, at most 31 nm, at most 30 nm, at most 29 nm, at most 28 nm, at most 27 nm, at most 26 nm, or at most 25 nm.

[0082] Furthermore, at the bottom sidewall location 141 (and in the bottom portion 220 of the conductive via 200), the thickness T3 can be from 1 nm to 60 nm. In some embodiments, the thickness T3 at the bottom sidewall location 141 depends on the critical dimension of the trench 144. For example, the thickness T3 at the bottom sidewall location 141, measured in nanometers (nm), can be equal to or greater than 60,000 divided by the lateral critical dimension measured in nanometers (nm), or equal to or greater than 60 divided by the lateral critical dimension measured in micrometers (μm). Therefore, for a critical dimension of 1 micrometer to 10 micrometers (μm), the thickness T3 at the bottom sidewall location 141 can be from 1 nm to 60 nm. Therefore, for a critical dimension of 4 micrometers (μm), the thickness T3 at the bottom sidewall location 141 can be 15 nm.

[0083] In some embodiments, at the bottom sidewall location 141 (and in the bottom portion 220 of the conductive via 200), the thickness T3 can be at least 1 nm, at least 2 nm, at least 3 nm, at least 4 nm, at least 5 nm, at least 6 nm, at least 7 nm, at least 8 nm, at least 9 nm, at least 10 nm, at least 12 nm, at least 14 nm, at least 16 nm, at least 18 nm, at least 20 nm, at least 22 nm, at least 24 nm, at least 26 nm, at least 27 nm, at least 30 nm, at least 32 nm, at least 34 nm, at least 36 nm, at least 38 nm, at least 40 nm, at least 42 nm, at least 44 nm, at least 46 nm, at least 48 nm, at least 50 nm, at least 52 nm, at least 54 nm, at least 56 nm, at least 58 nm, or at least 60 nm. In some embodiments, at the bottom sidewall location 141 (and in the bottom portion 220 of the conductive via 200), the thickness T3 can be up to 80 nm, up to 70 nm, up to 65 nm, up to 60 nm, up to 58 nm, up to 56 nm, up to 54 nm, up to 52 nm, up to 50 nm, up to 48 nm, up to 46 nm, up to 44 nm, up to 42 nm, up to 40 nm, up to 38 nm, up to 36 nm, up to 34 nm, up to 32 nm, up to 30 nm, up to 28 nm, up to 26 nm, up to 24 nm, up to 22 nm, up to 20 nm, up to 18 nm, up to 16 nm, up to 14 nm, up to 12 nm, up to 10 nm, up to 9 nm, up to 8 nm, up to 7 nm, up to 6 nm, up to 5 nm, up to 4 nm, up to 3 nm, up to 2 nm or at most 1 nm.

[0084] The thicknesses T1, T2, and T3 at the middle layer or intermediate height sidewall position 142 of the trench 144 (such as in the middle portion 230 of the conductive via 200) are typically greater than the thickness at the bottom surface 114 of the trench.

[0085] For example, at the middle layer or intermediate height sidewall location 142 (such as in the middle portion 230 of the conductive via 200), the thickness T1 can be from 6 nm to 20 nm, such as 12 nm. At the middle layer or intermediate height sidewall location 142, the thickness T1 can be at least 6 nm, at least 8 nm, at least 9 nm, at least 10 nm, at least 11 nm, at least 12 nm, at least 13 nm, at least 14 nm, or at least 15 nm. Furthermore, at the middle layer or intermediate height sidewall location 142, the thickness T1 can be at most 20 nm, at most 18 nm, at most 16 nm, at most 15 nm, at most 14 nm, at most 13 nm, at most 12 nm, at most 11 nm, or at most 10 nm.

[0086] Furthermore, at the mid-layer or intermediate height sidewall location 142, the thickness T2 can be from 20 nm to 35 nm, such as 27 nm. At the mid-layer or intermediate height sidewall location 142, the thickness T2 can be at least 20 nm, at least 22 nm, at least 24 nm, at least 25 nm, at least 26 nm, or at least 27 nm. Furthermore, at the mid-layer or intermediate height sidewall location 142, the thickness T2 can be at most 35 nm, at most 30 nm, at most 29 nm, at most 28 nm, at most 27 nm, at most 26 nm, or at most 25 nm.

[0087] At the mid-layer or intermediate height sidewall location 142 (such as in the intermediate portion 230 of the conductive via 200), the thickness T3 can be from 40 nm to 80 nm, such as 60 nm. At the mid-layer or intermediate height sidewall location 142, the thickness T3 can be at least 40 nm, at least 45 nm, at least 50 nm, at least 55 nm, at least 56 nm, at least 57 nm, at least 58 nm, at least 59 nm, or at least 60 nm. Furthermore, at the mid-layer or intermediate height sidewall location 142, the thickness T3 can be at most 80 nm, at most 75 nm, at most 70 nm, at most 65 nm, at most 64 nm, at most 63 nm, at most 62 nm, at most 61 nm, or at most 60 nm.

[0088] The thicknesses T1, T2, and T3 at the top sidewall location 143 adjacent to the trench opening 111 (such as in the top portion 210 of the conductive via 200) are generally greater than the thickness at the middle layer or intermediate height.

[0089] For example, at the top sidewall location 143 (such as in the top portion 210 of the conductive via 200), the thickness T1 can be from 20 nm to 50 nm, such as 36 nm. At the top sidewall location 143, the thickness T1 can be at least 20 nm, at least 25 nm, at least 30 nm, at least 31 nm, at least 32 nm, at least 33 nm, at least 34 nm, at least 35 nm, or at least 36 nm. At the top sidewall location 143, the thickness T1 can be at most 50 nm, at most 45 nm, at most 40 nm, at most 39 nm, at most 38 nm, at most 37 nm, or at most 36 nm.

[0090] At position 143 on the top sidewall, the thickness T2 can be from 15 nm to 50 nm, such as 30 nm. At position 143 on the top sidewall, the thickness T2 can be at least 20 nm, at least 25 nm, at least 26 nm, at least 27 nm, at least 28 nm, at least 29 nm, or at least 30 nm. At position 143 on the top sidewall, the thickness T2 can be at most 50 nm, at most 45 nm, at most 40 nm, at most 35 nm, at most 34 nm, at most 33 nm, at most 32 nm, at most 31 nm, or at most 30 nm.

[0091] At position 143 on the top sidewall, the thickness T3 can be from 100 nm to 300 nm, such as 180 nm. At position 143 on the top sidewall, the thickness T3 can be at least 100 nm, at least 125 nm, at least 150 nm, at least 175 nm, at least 180 nm, at least 200 nm, or at least 250 nm. At position 143 on the top sidewall, the thickness T3 can be at most 300 nm, at most 250 nm, at most 225 nm, at most 200 nm, at most 190 nm, at most 180 nm, at most 160 nm, or at most 150 nm.

[0092] Figure 25 is a cross-sectional view focusing on a portion of the copper core 164, the adjacent adhesive layer 158, and the alloy 166 formed by performing an annealing process.

[0093] Specifically, Figure 25 illustrates the formation of alloy 166 at the interface between conductive material 164 and adhesive layer 158. For example, a titanium-copper alloy 166 can be formed between copper conductive material 164 and titanium adhesive layer 158. The amount of alloy 166 formed can be controlled by the temperature and duration of the annealing process. In some embodiments, the annealing process is performed at a temperature of 400°C for 30 minutes. In some embodiments, the annealing process is a hydrogen (H2) annealing process, i.e., performed using hydrogen gas.

[0094] As shown, the adhesive layer 158 has a lateral thickness T3 before the annealing process, which varies along the height or depth 208 of the trench 144 and between portions 210, 220, and 230. During the annealing process, an alloy 166 with a lateral thickness T4 is formed. Each lateral thickness T3 and T4 can vary along the height (or depth) 208 of the trench 144, as shown. As shown, the lateral thickness T3 before annealing is maximum near the opening 111 of the trench 144 and minimum at or near the bottom surface 114 of the trench. At each height or depth 208 of the trench 144, the thickness T3 before annealing is greater than or equal to the thickness T4. In other words, all or less of the adhesive layer 158 can be converted into alloy 166 at each height.

[0095] Although Figure 25 illustrates that a portion of the titanium adhesive layer 158 is retained after the annealing process, particularly in the top portion 210, it is conceivable that all of the titanium adhesive layer 158 could be converted into a titanium-copper alloy 166 such that T4 = T3 at all locations along the height 208 of the conductive TSV 200.

[0096] Referring interactively to Figures 22, 24, and 25, in this embodiment, the conductive TSV 200 may include an adhesive layer 154 having a bottom sidewall thickness of 2 nm, a middle sidewall thickness of 12 nm, and a top sidewall thickness of 36 nm. The conductive TSV 200 may include a barrier layer 156 having a bottom sidewall thickness of 25 nm, a middle sidewall thickness of 27 nm, and a top sidewall thickness of 30 nm. The conductive TSV 200 may initially have an adhesive layer 158 having a bottom sidewall thickness of 2 nm, a middle sidewall thickness of 12 nm, and a top sidewall thickness of 36 nm. The conductive TSV 200 may include an alloy layer 166 having a bottom sidewall thickness of 15 nanometers (nm), a middle sidewall thickness of 60 nanometers (nm), and a top sidewall thickness of 180 nanometers (nm). In other words, the adhesive layer 158 may be completely converted into alloy 166 at the bottom and middle height sidewall locations, and may be partially converted into alloy 166 at the top sidewall location, such that the adhesive layer 158 has a remaining top sidewall thickness of 60 nanometers (nm) in the conductive TSV 200.

[0097] While the above embodiments provide the use of suitable materials to form the conductive TSV 200, the embodiments select PVD-deposited titanium instead of PVD-deposited tantalum as each adhesive layer, and select CVD-deposited titanium nitride instead of CVD-deposited tantalum nitride or PVD-deposited tantalum nitride or PVD-deposited titanium nitride as the barrier layer.

[0098] It should be noted that each adhesive layer should have good adhesion, and the particle growth of the conductive material 164 (i.e., copper) should be suppressed by forming an alloy with the conductive material 164. Furthermore, the material of the adhesive layer should be easily etchable, such as using a process operating at S960. PVD-deposited titanium has a material density of 4.5 g / cm³ and a relatively fast Ar etching rate, while materials with high material densities (such as 10 g / cm³ or higher) have relatively slow Ar etching rates. Therefore, using an Ar etching process operating at 10 A / s with S960, PVD-deposited titanium exhibits a high etching rate.

[0099] Copper particle inhibition is related to the alloy formation temperature. For example, lower alloy formation temperatures are associated with more alloy formation and inhibit copper particle growth. PVD-deposited titanium forms titanium-copper alloys at relatively low temperatures above 300°C. Furthermore, after annealing at 400°C, titanium promotes the growth of small copper particles on the titanium.

[0100] Regarding adhesion to copper, metals are superior to metal nitrides. Furthermore, titanium is better than tantalum. Additionally, PVD-deposited titanium exhibits better adhesion to copper due to fewer interface defects and impurities compared to CVD-deposited titanium. Therefore, PVD-deposited titanium demonstrates good adhesion to copper.

[0101] Furthermore, PVD-deposited titanium provides 1% to 5% bottom step coverage on the sidewalls and 5% to 15% bottom step coverage. PVD-deposited titanium exhibits poor barrier properties.

[0102] It should be noted that, according to operation S960, the barrier layer should exhibit good barrier properties and good step coverage, and should be easily etched (or resputtered), such as using PVD processes employing argon. CVD-deposited titanium nitride has a relatively low material density of 4.5 (g / cm³) and a relatively fast argon etch rate (at 10 Å / s).

[0103] CVD-deposited titanium nitride forms a titanium-copper alloy at a relatively high temperature above 450°C. Furthermore, annealing the CVD-deposited titanium nitride at 400°C promotes the growth of large copper particles on the titanium nitride.

[0104] CVD-deposited titanium nitride exhibits poor copper adhesion.

[0105] CVD-deposited titanium nitride provides greater than 90% bottom step coverage on the sidewalls and also provides greater than 90% bottom step coverage. CVD-deposited titanium nitride exhibits good barrier properties.

[0106] In addition, in some embodiments, method 900 provides, as appropriate, the formation of a PVD-deposited titanium outer adhesive layer 154, the formation of a CVD-deposited metal nitride barrier layer 156, the formation of a PVD-deposited metal inner adhesive layer 158, and etching of the inner adhesive layer 158 from the bottom surface 114 of the trench using a PVD argon etching process.

[0107] Some embodiments are performed without a PVD-deposited titanium external adhesive layer 154, which may be selected as appropriate. In such embodiments, the method includes forming a CVD-deposited metal nitride barrier layer 156 on the trench sidewalls 112 and the trench bottom surface 114, forming a PVD-deposited metal internal adhesive layer 158, and etching the internal adhesive layer 158 from the trench bottom surface 114, such as using a PVD argon etching process.

[0108] In some embodiments, method 900 provides the formation of a PVD-deposited titanium outer adhesive layer 154, a CVD-deposited titanium nitride barrier layer 156, a PVD-deposited titanium inner adhesive layer 158, and etching of the inner adhesive layer 158 from the bottom surface 114 of a trench using a PVD argon etching process.

[0109] In one embodiment, the conductive via includes: a first end and a second end; a first portion adjacent to the first end; a second portion adjacent to the second end; and a middle portion located between the first portion and the second portion, wherein the conductive via includes metal particles, the metal particles in the first portion having a first particle size; the metal particles in the second portion having a second particle size; the metal particles in the middle portion having a third particle size; the first particle size is larger than the third particle size; and the second particle size is larger than the third particle size.

[0110] In some embodiments, the conductive via has a critical size of 1 micrometer to 10 micrometers (μm).

[0111] In some embodiments, the conductive via has an aspect ratio of 5 to 20.

[0112] In some embodiments, the size of the first particle is larger than the size of the second particle.

[0113] In some embodiments, the first particle size is the maximum particle size, and the maximum particle size is 200 nanometers to 1000 nanometers (nm).

[0114] In some embodiments, the first end and the second end are separated by a height; the first part, the second part and the middle part each have a sub-height equal to 1 / 3 of the height; the first part has an average particle size greater than 0.5 times the maximum particle size; the second part has an average particle size greater than 0.5 times the maximum particle size; and the middle part has an average particle size less than 0.5 times the maximum particle size.

[0115] In some embodiments, the first portion has an average particle size that is 0.6 times larger than the maximum particle size; the second portion has an average particle size that is 0.6 times smaller than the maximum particle size; and the middle portion has an average particle size that is 0.4 times smaller than the maximum particle size.

[0116] In another embodiment, a method for forming a metal structure in a trench is provided and includes: depositing a barrier layer along the sidewalls and bottom surface of the trench; depositing a metal layer over the barrier layer, wherein the metal layer has a vertical thickness above the bottom surface of the trench and a reduced sidewall thickness along the sidewalls from the opening of the trench toward the bottom surface of the trench; removing the metal layer from the bottom surface of the trench; and forming metal in the trench.

[0117] In some embodiments, the method further includes: depositing an adhesive layer along the sidewalls and bottom surface of the trench, wherein a barrier layer is deposited above the adhesive layer, and wherein the adhesive layer has a vertical thickness above the bottom surface of the trench and a reduced sidewall thickness is formed along the sidewall from the opening of the trench toward the bottom surface of the trench.

[0118] In some embodiments of the method, the trench has a lateral critical dimension; the adhesive layer has a first lateral thickness (T1) at a selected height above the bottom surface; the first lateral thickness (T1) is greater than 2 nanometers (nm); the barrier layer has a second lateral thickness (T2) at the selected height; the second lateral thickness (T2) is greater than 25 nanometers (nm); the metal layer has a third lateral thickness (T3) at the selected height; and the third lateral thickness (T3), measured in nanometers (nm), is greater than or equal to 60,000 divided by the lateral critical dimension measured in nanometers (nm).

[0119] In some embodiments of the method, the deposited adhesive layer comprises depositing titanium using a physical vapor deposition (PVD) process; the deposited barrier layer comprises depositing titanium nitride using a chemical vapor deposition (CVD) process; the deposited metal layer comprises depositing titanium using a physical vapor deposition (PVD) process; and removing the metal layer from the bottom surface of the trench comprises performing an ion etching process.

[0120] In some embodiments of the method, removing the metal layer from the bottom surface of the trench involves redepositing the metal layer material onto the sidewalls of the trench.

[0121] In some embodiments, the method further includes depositing an insulating liner in the trench, wherein the deposited barrier layer comprises depositing a barrier layer over the insulating liner.

[0122] In some embodiments of the method, forming metal in the trench includes: depositing a seed layer over a metal layer; and depositing a metal filler over the seed layer; and the method further includes: performing an annealing process to grow metal particles having a desired particle distribution from the seed layer and the metal filler.

[0123] In another embodiment, the semiconductor device includes a metal interconnect comprising: a copper core; and a titanium-copper alloy surrounding the copper core.

[0124] In some embodiments of the semiconductor device, the copper core includes copper particles; the copper core includes a top portion, a bottom portion, and an intermediate portion between the top and bottom portions; the copper particles in the top portion have a first average particle size; the copper particles in the bottom portion have a second average particle size; the copper particles in the intermediate portion have a third average particle size; the first average particle size is greater than the third average particle size; and the second average particle size is greater than the third average particle size.

[0125] In some embodiments of the semiconductor device, the metal interconnect further includes a titanium layer of a titanium-copper alloy surrounding the top portion of the copper core.

[0126] In some embodiments of the semiconductor device, the metal interconnect further includes a titanium nitride layer that surrounds the titanium-copper alloy below the top portion of the copper core and surrounds the titanium layer at the top portion of the copper core.

[0127] In some embodiments of the semiconductor device, the metal interconnect further includes a titanium nitride layer surrounding the titanium-copper alloy.

[0128] In some embodiments of the semiconductor device, the metal interconnect further includes an outer titanium layer surrounding the titanium nitride layer.

[0129] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0130] 20: Apparatus 22:Substrate 22a: Front surface 24: Integrated circuits / transistors / active integrated circuit devices / semiconductor devices 26: Interconnection Structure 28:ILD 30: Contact plug 34:IMD 38, 38A, 38B: Metal wire / solder pad 40: Through hole 44: Trench 46, 46A~46D: Grooves Floors 47 and 72 50: Optical Obscuration 52, 152: Insulation layer 54: Stacking 56: Light Mask 58, 111: Opening 60, 200: Conductive via / Conductive TSV 62: Deep through hole 66: Metal wire 67: Diffusion barrier layer 72: Passivation layer 74, 78: UBM 76, 80: Metal bumps 108: Total height 110: Device Layer 112: Trench sidewall 114: Groove bottom surface 120: Device 121: Device surface 141: Bottom sidewall position 142: Mid-height sidewall position 143: Top sidewall position 144: Trench 152: Floor 154, 158: Floors 156: Floor 159: Arrow 160: Gaseous materials 162: Floor 164: Conductive material / layer / copper core 166: Alloy / Alloy Layer 170:RDL 200: Conductive via / Conductive TSV / Conductive interconnect structure 201: Top surface 202: Bottom surface 208: Height / Depth 209: Lateral Critical Dimension 210: Part 220: Part 230: Part 300: Particles 310, 320, 330: Particles 399: Gap 900: Method D1~D5: Depth M1, M2, M3, Mtop: Metallization layers S902, S904, S906, S950, S954, S956, S958, S960, S962, S968, S970, S972, S980, S982, S994, S996, S998: Operation T1~T4: Thickness W1~W5: Horizontal Size

Claims

1. A conductive via, comprising: A copper core includes: a first end and a second end; a first portion adjacent to the first end; a second portion adjacent to the second end; and an intermediate portion located between the first portion and the second portion; a titanium-copper alloy surrounding the copper core; a titanium layer surrounding the titanium-copper alloy at the first portion of the copper core; and a titanium nitride layer surrounding the titanium-copper alloy, wherein the conductive via is composed of a plurality of metal particles, wherein the metal particles in the first portion have a first particle size; wherein the metal particles in the second portion have a second particle size; wherein the metal particles in the intermediate portion have a third particle size; wherein the first particle size is larger than the third particle size; and wherein the second particle size is larger than the third particle size.

2. The conductive via as claimed in claim 1, wherein the conductive via has a critical size of 1 micrometer to 10 micrometers.

3. The conductive via as claimed in claim 1, wherein the conductive via has an aspect ratio of 5 to 20.

4. The conductive via as described in claim 1, wherein the size of the first particle is larger than the size of the second particle.

5. The conductive via as described in claim 1, wherein the first particle size is a maximum particle size, and wherein the maximum particle size is 200 nanometers to 1000 nanometers.

6. A method for forming a metal structure in a trench, the method comprising the steps of: A barrier layer is deposited along multiple sidewalls and a bottom surface of the trench; a metal layer is deposited over the barrier layer, wherein the metal layer has a vertical thickness above the bottom surface of the trench and a decreasing sidewall thickness is formed along the sidewalls from an opening of the trench toward the bottom surface of the trench; the metal layer is removed from the bottom surface of the trench. And a metal is formed in the trench, wherein the metal includes: a first end and a second end; a first portion adjacent to the first end; A second portion adjacent to the second end; and an intermediate portion located between the first portion and the second portion, wherein the metal is composed of a plurality of metal particles, wherein the metal particles in the first portion have a first particle size; wherein the metal particles in the second portion have a second particle size; wherein the metal particles in the intermediate portion have a third particle size; wherein the first particle size is larger than the third particle size; and wherein the second particle size is larger than the third particle size.

7. The method of claim 6 further includes the steps of: depositing an adhesive layer along the sidewalls and bottom surface of the trench, wherein the barrier layer is deposited above the adhesive layer, and wherein the adhesive layer has a vertical thickness above the bottom surface of the trench, and has a reduced sidewall thickness along the sidewalls from an opening of the trench toward the bottom surface of the trench.

8. A semiconductor device, comprising: A metal interconnect includes: a copper core; a titanium-copper alloy surrounding the copper core; a titanium layer surrounding the titanium-copper alloy at a top portion of the copper core; and a titanium nitride layer surrounding the titanium-copper alloy below the top portion of the copper core and surrounding the titanium layer at the top portion of the copper core, wherein the copper core is composed of a plurality of copper particles; the copper core includes the top portion, a bottom portion, and an intermediate portion between the top portion and the bottom portion; the copper particles in the top portion have a first average particle size; the copper particles in the bottom portion have a second average particle size; the copper particles in the intermediate portion have a third average particle size; the first average particle size is larger than the third average particle size; and the second average particle size is larger than the third average particle size.

9. The semiconductor device as claimed in claim 8, wherein the metal interconnect further includes an outer titanium layer surrounding the titanium nitride layer.

10. The semiconductor device as claimed in claim 8, wherein the size of the first particle is larger than the size of the second particle.

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