A method of precisely controling frequency and frequency control apparatus using the same

Abstract

A frequency control device includes an inverter and a controller. The inverter has at least two switches electrically clamped between terminals electrically connected to a load and a DC power supply. The inverter applies an AC voltage to the load via the terminals, wherein the AC voltage has a frequency determined by the operation of the at least two switches. The controller has a processor that generates control signals based on the processor's clock cycle to control the operation of the at least two switches.

Description

Method for precisely controlling frequency and radio frequency generator using the same The present disclosure relates to a frequency control method for precisely controlling frequency and a frequency control apparatus using the same, and more particularly to a frequency control apparatus and a control method thereof, wherein when an alternating current (AC) voltage is supplied to a variable load whose impedance changes over time, the output frequency of the AC voltage is precisely controlled according to the impedance change of the variable load to maximize energy transfer efficiency, and the AC voltage having the precisely controlled frequency is output to the load. Technologies utilizing plasma are used in various industrial fields, including those for semiconductors, displays, and medical equipment; environmental technologies for air purification, water purification, soil purification, etc.; and energy technologies for solar cells, hydrogen energy, etc. There are many methods for generating such plasma, including methods for direct current discharge (such as corona discharge, glow discharge, and arc discharge), methods for alternating current discharge (such as capacitive coupling discharge and inductive coupling discharge), and methods for shock waves, high-energy beams, etc. Among these methods, the inductive coupling method, which has a simple configuration and high usability, is attracting attention. Meanwhile, in order to efficiently generate plasma, it is preferable to apply an AC voltage having a frequency identical to or similar to the resonance frequency of the load that generates plasma to the load. However, as plasma is generated, the resonant frequency of the load continuously changes, making it difficult to instantly control the frequency of the AC voltage applied to the load in response to this frequency change. Therefore, to generate and maintain stable plasma, a method is needed to precisely control the frequency of the AC voltage so that the frequency of the AC voltage applied to the load tracks the resonant frequency of the variable load as closely as possible. [Technical Issues] An object of the present disclosure to solve the problem is to provide a frequency control method and an apparatus for changing the frequency of an AC voltage supplied to a load using the frequency control method. An object of the present disclosure to solve the above-mentioned problem is to provide a frequency control method and an apparatus using the same, the apparatus being configured to predict an output voltage outputted from an inverter and to instantly change the frequency of an AC voltage supplied to a load based on a delay time between the predicted output voltage and an output current of the load. An object of the present disclosure to solve the above-mentioned problem is to provide a frequency control method and an apparatus using the same, the apparatus being configured to determine a frequency change degree of the AC voltage when the frequency of the AC voltage supplied to a load changes, and to change the frequency of the AC voltage accordingly. The present disclosure aims to solve the above-mentioned problem and provides a frequency control method and a device using the frequency control method. The device is configured to use a plurality of frequencies to generate a frequency closest to the frequency of the AC voltage to be changed when the frequency of the AC voltage to be changed cannot be generated by the clock of the processor of the frequency control device. The technical solutions disclosed herein are not limited to the above, and those skilled in the art should clearly understand other technical solutions not described herein based on this specification and the accompanying drawings. [Technical Solutions] The present disclosure discloses a frequency control apparatus that controls the frequency of an AC voltage applied to a load according to a variable resonant frequency of the load. The apparatus includes: an inverter having at least two switches electrically interposed between terminals electrically connected to a load and a DC power source, the inverter applying an AC voltage to the load via the terminals, wherein the AC voltage has a frequency determined by operation of the at least two switches; and a controller having a processor, the controller generating control signals for controlling the operation of the at least two switches based on a clock of the processor, wherein the controller is configured to: output a first control signal that controls the at least two switches so that a first AC voltage having a first frequency is applied to the load during a first period; present a wave of a virtual signal corresponding to the first frequency by shifting the wave of the first control signal by a predetermined time; determine a delay time between the wave of the virtual signal and a wave of an output current of the inverter during the first period based on the clock in at least a portion of the first period; determine a second frequency based on (i) the first frequency, (ii) the delay time, and (iii) at least one possible output frequency that can be determined using the clock; and output a second control signal that controls the at least two switches so that a second AC voltage having a second frequency is applied to the load during a second period immediately following the first period. In this article, the delay time is the difference between a first count value and a second count value, wherein the first count value is obtained by counting a first time length from a rising edge of a wave of a virtual signal to a falling edge of a wave of a virtual signal that first appears after the rising edge according to the clock, and wherein the second count value is obtained by counting a second time length from the rising edge to a falling edge of a wave of an output current that first appears after the rising edge according to the clock. In addition, when the delay time is greater than the first value, the second frequency increases from the first frequency, wherein when the delay time is less than the second value, the second frequency decreases from the first frequency, wherein when the delay time has a value between the first value and the second value, the second frequency is the same as the first frequency, and wherein the first value is the same as or different from the second value. Furthermore, the predetermined time is identical to a time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter. Furthermore, the predetermined time is smaller or larger than a time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter. Furthermore, the controller is configured to determine the second frequency based on multiplying a difference between the first frequency and a frequency adjacent to the first frequency among the at least one possible output frequency by a factor, wherein the factor is determined based on the delay time. In addition, the controller is configured to determine the delay time based on an average value of the last N delay times among a plurality of delay times between the wave of the output current and the wave of the virtual signal, both of which can be obtained during the first period. Furthermore, when the second frequency is not included in the at least one possible output frequency, the controller is configured to determine a difference between each of a plurality of possible output frequencies closest to the second frequency among the at least one possible output frequency and the second frequency, and output a plurality of third control signals corresponding to each of the plurality of possible output frequencies instead of the second control signal based on an output count of each of the plurality of possible output frequencies, wherein the output count is determined based on a ratio between the differences. Furthermore, the controller is configured to output the plurality of third control signals such that dispersions between the plurality of third control signals are evenly distributed according to an output count of each of the plurality of possible output frequencies. The present disclosure discloses a frequency control method for controlling the frequency of an AC voltage applied to a load using a frequency control device according to a variable resonant frequency of the load. The method includes: outputting a first control signal that controls application of a first AC voltage having a first frequency to the load during a first period; presenting a wave of a virtual signal corresponding to the first frequency by shifting the wave of the first control signal by a predetermined time; determining a delay time between the wave of the virtual signal and a wave of an output current of an inverter during the first period based on a clock corresponding to the frequency control device during at least a portion of the first period; determining a second frequency based on (i) the first frequency, (ii) the delay time, and (iii) at least one possible output frequency that can be determined using the clock; and outputting a second control signal that controls application of a second AC voltage having a second frequency to the load during a second period immediately following the first period. In this article, the delay time is the difference between a first count value and a second count value, wherein the first count value is obtained by counting a first time length from a rising edge of a wave of a virtual signal to a falling edge of a wave of a virtual signal that first appears after the rising edge according to the clock, and wherein the second count value is obtained by counting a second time length from the rising edge to a falling edge of a wave of an output current that first appears after the rising edge according to the clock. In addition, when the delay time is greater than the first value, the second frequency increases from the first frequency, wherein when the delay time is less than the second value, the second frequency decreases from the first frequency, wherein when the delay time has a value between the first value and the second value, the second frequency is the same as the first frequency, and wherein the first value is the same as or different from the second value. Furthermore, the predetermined time is identical to a time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter. Furthermore, the predetermined time is smaller or larger than a time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter. Furthermore, determining the second frequency includes determining the second frequency based on multiplying a difference between the first frequency and a frequency adjacent to the first frequency among the at least one possible output frequency by a factor, wherein the factor is determined based on the delay time. In addition, the delay time is determined based on the average value of the last N delay times among a plurality of delay times between the wave of the output current and the wave of the virtual signal, both of which can be obtained in the first period. In addition, the method further includes: when the second frequency is not included in the at least one possible output frequency, determining a difference between each of a plurality of possible output frequencies closest to the second frequency among the at least one possible output frequency and the second frequency, and outputting a plurality of third control signals corresponding to each of the plurality of possible output frequencies instead of the second control signal based on an output count of each of the plurality of possible output frequencies, wherein the output count is determined based on a ratio between the differences. Furthermore, outputting the plurality of third control signals includes outputting the plurality of third control signals such that dispersion between the plurality of third control signals is evenly distributed according to the output count of each of the plurality of possible output frequencies. [Beneficial Effect] According to the present disclosure, plasma generation can be induced and the generated plasma can be maintained by applying an AC voltage with a suitable frequency to a variable load. According to the present disclosure, the frequency of the AC voltage applied to the load can be controlled to correspond to the resonant frequency of the variable load, thereby stably maintaining plasma generated from the load. According to the present disclosure, the plasma sustaining capability can be improved by determining the degree of frequency change of the AC voltage applied to the load and generating a frequency closest to the frequency of the corresponding AC voltage by using a plurality of frequencies. The effects of the present disclosure are not limited to the above-mentioned contents, and those skilled in the art to which the present disclosure pertains should clearly understand other effects not described herein based on the present specification and the accompanying drawings. The above-mentioned objects, features and advantages of the present disclosure will become more apparent by reading the following detailed description with reference to the accompanying drawings. Since the present disclosure is susceptible to various modifications and embodiments, specific embodiments will be shown in the accompanying drawings and described in detail in the detailed description. The embodiments described in this specification are intended to clearly illustrate the scope of the present disclosure to those skilled in the art, and are not intended to limit the present disclosure. It should be understood that the present disclosure may include alternative forms and modifications within the technical scope of the present disclosure. The accompanying drawings are provided to facilitate explanation of the present disclosure, and the shapes in the drawings may be exaggerated for ease of explanation. Therefore, the present disclosure should not be limited to the drawings. In addition, detailed descriptions of well-known functions or configurations associated with the present disclosure will be omitted to avoid unnecessarily obscuring the essence of the present disclosure. It should also be noted that although ordinal numbers (such as first and second) are used in the following description, these ordinal numbers are only used to distinguish similar components. In addition, the terms “module,” “unit,” and “part” used for elements in the following description are given or used interchangeably for the convenience of preparing this specification, and thus these terms are not given specific meanings or functions. The present disclosure discloses a frequency control apparatus that controls the frequency of an AC voltage applied to a load according to a variable resonant frequency of the load. The apparatus includes: an inverter having at least two switches electrically interposed between terminals electrically connected to a load and a DC power source, the inverter applying an AC voltage to the load via the terminals, wherein the AC voltage has a frequency determined by operation of the at least two switches; and a controller having a processor, the controller generating control signals for controlling the operation of the at least two switches based on a clock of the processor, wherein the controller is configured to: output a first control signal that controls the at least two switches so that a first AC voltage having a first frequency is applied to the load during a first period; present a wave of a virtual signal corresponding to the first frequency by shifting the wave of the first control signal by a predetermined time; determine a delay time between the wave of the virtual signal and a wave of an output current of the inverter during the first period based on the clock in at least a portion of the first period; determine a second frequency based on (i) the first frequency, (ii) the delay time, and (iii) at least one possible output frequency that can be determined using the clock; and output a second control signal that controls the at least two switches so that a second AC voltage having a second frequency is applied to the load during a second period immediately following the first period. In this article, the delay time is the difference between a first count value and a second count value, wherein the first count value is obtained by counting a first time length from a rising edge of a wave of a virtual signal to a falling edge of a wave of a virtual signal that first appears after the rising edge according to the clock, and wherein the second count value is obtained by counting a second time length from the rising edge to a falling edge of a wave of an output current that first appears after the rising edge according to the clock. In addition, when the delay time is greater than the first value, the second frequency increases from the first frequency, wherein when the delay time is less than the second value, the second frequency decreases from the first frequency, wherein when the delay time has a value between the first value and the second value, the second frequency is the same as the first frequency, and wherein the first value is the same as or different from the second value. Furthermore, the predetermined time is identical to a time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter. Furthermore, the predetermined time is smaller or larger than a time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter. Furthermore, the controller is configured to determine the second frequency based on multiplying a difference between the first frequency and a frequency adjacent to the first frequency among the at least one possible output frequency by a factor, wherein the factor is determined based on the delay time. In addition, the controller is configured to determine the delay time based on an average value of the last N delay times among a plurality of delay times between the wave of the output current and the wave of the virtual signal, both of which can be obtained during the first period. Furthermore, when the second frequency is not included in the at least one possible output frequency, the controller is configured to determine a difference between each of a plurality of possible output frequencies closest to the second frequency among the at least one possible output frequency and the second frequency, and output a plurality of third control signals corresponding to each of the plurality of possible output frequencies instead of the second control signal based on an output count of each of the plurality of possible output frequencies, wherein the output count is determined based on a ratio between the differences. Furthermore, the controller is configured to output the plurality of third control signals such that dispersions between the plurality of third control signals are evenly distributed according to an output count of each of the plurality of possible output frequencies. The present disclosure discloses a frequency control method for controlling the frequency of an AC voltage applied to a load using a frequency control device according to a variable resonant frequency of the load. The method includes: outputting a first control signal that controls application of a first AC voltage having a first frequency to the load during a first period; presenting a wave of a virtual signal corresponding to the first frequency by shifting the wave of the first control signal by a predetermined time; determining a delay time between the wave of the virtual signal and a wave of an output current of an inverter during the first period based on a clock corresponding to the frequency control device during at least a portion of the first period; determining a second frequency based on (i) the first frequency, (ii) the delay time, and (iii) at least one possible output frequency that can be determined using the clock; and outputting a second control signal that controls application of a second AC voltage having a second frequency to the load during a second period immediately following the first period. In this article, the delay time is the difference between a first count value and a second count value, wherein the first count value is obtained by counting a first time length from a rising edge of a wave of a virtual signal to a falling edge of a wave of a virtual signal that first appears after the rising edge according to the clock, and wherein the second count value is obtained by counting a second time length from the rising edge to a falling edge of a wave of an output current that first appears after the rising edge according to the clock. In addition, when the delay time is greater than the first value, the second frequency increases from the first frequency, wherein when the delay time is less than the second value, the second frequency decreases from the first frequency, wherein when the delay time has a value between the first value and the second value, the second frequency is the same as the first frequency, and wherein the first value is the same as or different from the second value. Furthermore, the predetermined time is identical to a time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter. Furthermore, the predetermined time is smaller or larger than a time difference between a first time point at which the wave of the first control signal is input to the inverter and a second time point at which the wave of the first control signal is expected to be output from the inverter. Furthermore, determining the second frequency includes determining the second frequency based on multiplying a difference between the first frequency and a frequency adjacent to the first frequency among the at least one possible output frequency by a factor, wherein the factor is determined based on the delay time. In addition, the delay time determination includes determining the delay time based on an average value of the last N delay times among a plurality of delay times between the wave of the output current and the wave of the virtual signal, both of which can be obtained in the first period. In addition, the method further includes: when the second frequency is not included in the at least one possible output frequency, determining a difference between each of a plurality of possible output frequencies closest to the second frequency among the at least one possible output frequency and the second frequency, and outputting a plurality of third control signals corresponding to each of the plurality of possible output frequencies instead of the second control signal based on an output count of each of the plurality of possible output frequencies, wherein the output count is determined based on a ratio between the differences. Furthermore, outputting the plurality of third control signals includes outputting the plurality of third control signals such that dispersions between the plurality of third control signals are evenly distributed according to an output count of each of the plurality of possible output frequencies. This specification relates to a frequency control method for accurately controlling frequency and a frequency control device using the frequency control method. Specifically, based on the frequency control method according to the exemplary embodiment of this specification and the frequency control device using the frequency control method, when the frequency control device applies a voltage, current or power with a specific frequency to a load, the frequency control device can periodically or non-periodically change the corresponding specific frequency. Here, the specific frequency means the frequency of voltage, current, or power applied to a load, and may mean a driving frequency. Here, a load may refer to a component to which power is supplied. For example, a load may refer to an electrical component including electrical elements such as a resistor, inductor, or capacitor. The load may have a resonant frequency that depends on the electrical properties or characteristics of the electrical elements comprising the load. In this case, if the electrical properties or characteristics of the load change over time, the resonant frequency of the load may also change over time. For ease of explanation, the following describes a frequency control method for a plasma system and a frequency control device using the method. However, the technical concepts of this specification are not limited to this, and the frequency control device can naturally be similarly applied to devices or applications that require supplying AC power by periodically or aperiodically controlling a specific frequency (e.g., a drive frequency). For example, in fields such as wireless power transmission and induction heating, the frequency control method and device using the method described below can be used to control the frequency of AC power to a variable resonant frequency corresponding to a load. According to exemplary embodiments of the present disclosure, a frequency control method may be used to apply power to an antenna or antenna structure in a plasma system for generating and maintaining plasma. Here, plasma is a stage in which a substance is subjected to high energy and separated into negatively charged electrons and positively charged ions, and plasma can be induced or generated by various methods. Among these methods, inductively coupled plasma (ICP) is plasma generated by supplying power to a coil, antenna, or similar component to form an inductive electric field or a capacitive electric field in a specific space, and can generally be driven by a high-frequency power source such as radio frequency (RF). At the same time, for ease of explanation, the following description assumes that the plasma generated by the plasma system is inductively coupled plasma. However, the technical concept of this specification is not limited to this. Here, an antenna is an inductive element or load that generates an electric field or magnetic field around it when voltage or current is applied, and such an antenna may refer to a coil, an inductor, or the like, and may further refer to an equivalent circuit implemented using elements other than an inductive element. Here, the antenna structure may refer to a structure including at least one antenna. In addition, the antenna structure may include at least one or more capacitive elements or loads, and may be implemented in a form in which at least one or more antennas or capacitive elements are connected or arranged in a specific manner. Meanwhile, the plasma system according to the exemplary embodiments of this specification can be widely used in various fields such as semiconductors, display processing, environment, energy, etc. It should be noted that the plasma generating apparatus described below is not limited to use in a specific field, but can be generally used in fields utilizing plasma. Hereinafter, a plasma system according to an exemplary embodiment of the present specification will be explained with reference to FIG. 1 . FIG1 is a diagram illustrating a plasma system 100 according to an exemplary embodiment of the present disclosure. Referring to FIG1 , the plasma system 100 may include a radio frequency (RF) generator 1000, an antenna structure 2000, and a plasma generator 3000. The plasma system 100 may induce inductively coupled plasma generation in the plasma generator 3000 by supplying an RF AC voltage or RF AC current (or, correspondingly, RF AC power) to the antenna structure 2000 using the RF generator 1000. The RF generator 1000 may provide voltage, current, or power to the antenna structure 2000. For example, the RF generator 1000 may apply an AC voltage, current, or power having a specific frequency (e.g., a driving frequency) to the antenna structure 2000. In this case, the frequency of the AC power, the frequency of the AC current, or the frequency of the AC voltage provided to the antenna structure 2000 may be varied as described below. In the following, for ease of description, it is described that an AC voltage having a frequency is applied to the antenna structure 2000 or the load. However, those skilled in the art can easily understand that an AC current having a frequency or AC power can also be applied to the antenna structure 2000 or the load in this manner. The antenna structure 2000 may include at least one antenna. Alternatively, the antenna structure 2000 may include at least one antenna and at least one capacitor. The antenna structure 2000 may be electrically connected to the RF generator 1000. The antenna structure 2000 may be connected to the RF generator 1000 in series or in parallel via wiring, or may be connected to the RF generator 1000 in series or in parallel via electrical components. The antenna structure 2000 may be physically or electrically connected to the plasma generator 3000. Detailed description of the connection between the antenna structure 2000 and the plasma generator 3000 will be provided below. When the antenna structure 2000 receives RF power from the RF generator 1000 , a current (i.e., AC current) whose phase (or direction and magnitude) varies with time flows through the antenna structure 2000 , thereby generating an inductive electric field in the plasma generator 3000 , thereby inducing plasma. The antenna structure 2000 may have a resonant frequency determined by the electrical properties and / or characteristics of the components within the antenna structure 2000. Here, the resonant frequency is determined by the inductance and / or capacitance included in the antenna structure 2000 and may be defined as the resonant frequency of the antenna structure 2000. In the present disclosure, the resonant frequency of a load may also refer to the resonant frequency of the synthetic impedance, which takes into account the effects of the antenna structure 2000 and the plasma. For example, while the plasma system 100 generates and maintains plasma, in order to minimize the phase difference between the voltage and current applied to the load comprising the corresponding plasma and the antenna structure 2000, the frequency applied to the antenna structure 2000 by the RF generator 1000 may vary over time. In this case, it can be seen that the synthetic impedance of the plasma generated by the antenna structure 2000 and the plasma generator 3000 (i.e., the synthetic impedance of the load comprising the antenna structure 2000 and the time-varying plasma) varies over time, thereby changing the resonant frequency of the load. The plasma generator 3000 may include a region or space where plasma generation is induced. Specifically, the plasma generator 3000 may refer to a space, such as a chamber or a tube, in which plasma may be generated and maintained. Hereinafter, the configuration and structure of the RF generator 1000 will be described with reference to FIG. 2 . FIG. 2 is a view illustrating a radio frequency generator 1000 according to an exemplary embodiment of this specification. 2 , RF generator 1000 may include an AC power source 1100, a rectifier 1200, an inverter 1300, a controller 1500, and a sensor module 1400. RF generator 1000 may convert alternating current (AC) supplied from AC power source 1100 into another AC power and supply the converted AC power to a load. For example, RF generator 1000 may convert AC power used in typical homes or industries into another AC power having a frequency of several hundred kilohertz to several tens of megahertz and a power of several kilowatts or more, and supply the converted AC power to the load. Meanwhile, RF generator 1000 and the load can be electrically and / or physically connected to each other via one or more nodes. Referring to FIG2 , two nodes 1610 and 1630 on the RF generator 1000 side and two nodes 1710 and 1730 on the load side can be electrically and / or physically connected. For example, node 1610 can be connected to node 1710, and node 1630 can be connected to node 1730. For example, node 1610 can be connected to node 1710 using a conductive wire, and node 1630 can be connected to node 1730 using another conductive wire. Meanwhile, nodes 1610, 1630, 1710, and 1730 may also be implemented in the form of terminals. In this case, the terminal of node 1610 and the terminal of node 1710 may be connected to each other via a wire, a cable, or a connector, and the terminal of node 1630 and the terminal of node 1730 may be connected to each other via a wire, a cable, or a connector. For ease of description, it is assumed below that RF generator 1000 and the load are connected to each other via nodes 1610, 1630, 1710, and 1730. That is, for ease of description, the configuration of nodes 1610, 1630, 1710, and 1730 may be omitted from the drawings or from the detailed description in this specification. However, those skilled in the art can easily infer from the above description that RF generator 1000 and the load are connected to each other via nodes 1610, 1630, 1710, and 1730. Here, the load may include the antenna structure 2000 and the plasma generated by the antenna structure 2000. In this case, the impedance of the load becomes the combined impedance of the impedance of the antenna structure 2000 and the impedance of the plasma. Since the impedance of the plasma varies with time depending on the state of the plasma, the load has a resonant frequency that varies with time depending on the plasma-induced resonance. The rectifier 1200 may convert the output of the AC power source 1100 into direct current (DC). The rectifier 1200 may convert the AC power supplied from the AC power source 1100 into DC power and apply the DC power to both ends of the inverter 1300 (eg, input terminals of the inverter 1300). Inverter 1300 can receive direct current (DC) from rectifier 1200 and supply AC power to a load. For example, inverter 1300 can receive a control signal from controller 1500 and use the received control signal to supply AC power to the load. Inverter 1300 may include at least one switching element controlled by the control signal, and the AC power supplied from inverter 1300 to the load may have a specific frequency (e.g., a driving frequency) set based on the control signal provided to inverter 1300 from controller 1500. According to some exemplary embodiments disclosed in this application, the inverter 1300 may be provided as a half-bridge type or a full-bridge type. Meanwhile, a capacitive element may be disposed between the rectifier 1200 and the inverter 1300. For example, the RF generator 1000 includes a capacitor connected in parallel to the rectifier 1200 and the inverter 1300, and the capacitor may discharge the AC component of the voltage or current applied to the inverter 1300 to the ground node (GND). Controller 1500 can receive data sensed by sensor module 1400 (described below) and generate a control signal. For example, controller 1500 can be implemented to obtain resonant frequency-related data (e.g., load current and voltage) from sensor module 1400 to generate the control signal. Specifically, controller 1500 can use information about the output current waveform of inverter 1300 (this information obtained from sensor module 1400) to obtain a phase difference or delay time of a virtual signal waveform. This virtual signal delays the waveform of a control signal used to convert a DC voltage applied to inverter 1300 into an AC voltage by a predetermined time. Based on the obtained phase difference or delay time, controller 1500 can generate a control signal for controlling the frequency of the AC voltage output from inverter 1300. Here, obtaining the phase difference or delay time can mean detecting / sensing the phase difference or delay time. In the following, it should be noted that, also in the description of this specification, obtaining the phase difference or delay time may be interpreted as detecting / sensing the phase difference or delay time. Field Programmable Gate Array (FPGA) technology can be used to implement the controller 1500. The specific configuration and structure of the controller 1500 will be described below. The output current wave sensed by sensor module 1400 can be a signal or data regarding the direction of the current applied to the load (i.e., the current output from inverter 1300) and the time the current flows in each direction. In other words, the output current wave can be a square wave signal, a digitized signal obtained by measuring the direction of current flow and the time the current flows in each corresponding direction. For example, in the output current wave, when the current flows in one direction for the first time, a +I (where I is an integer) value is output for the first time, and when the current flows in the other direction for the second time, which is the same as or different from the first time, a -I value is output for the second time. For example, the output current wave can be output in the form of wave 510, such as shown in FIG6 . Sensor module 1400 can obtain data regarding the resonant frequency of the load or the current or power supplied to the load for controller 1500. Referring back to FIG. 2 , sensor module 1400 may include a current transformer 1410, a filter 1420, and a comparator 1430. Sensor module 1400 can receive a current signal or a voltage signal flowing through the load via current transformer 1410, convert this signal into a current signal or a voltage signal having different magnitudes, filter the converted current signal or voltage signal using filter 1420, and output an output current waveform to controller 1500 via comparator 1430. Here, the converter 1410 may be inductively coupled to the distribution wiring between the inverter 1300 and the load, and may convert a voltage signal or a current signal applied to the load and provide it to the filter 1420. Specifically, the converter 1410 may convert the current flowing in the conductive wiring connected to the load into a voltage signal. Here, the filter 1420 can remove high frequency noise from the input current or voltage signal and output the current or voltage signal with the noise removed to the comparator 1430. To this end, the filter 1420 can perform high-pass filtering or low-pass filtering. Here, comparator 1430 can obtain information about the output current waveform. For example, comparator 1430 can obtain information about the output current waveform by comparing the voltage signal obtained from converter 1410 or filter 1420 with a predetermined value. In this case, information about the output current waveform can refer to phase information of the current applied to the load (i.e., the current output from inverter 1300) or information about the magnitude and direction of the current. At least one of the components included in the sensor module 1400 may be omitted. Although not shown in FIG. 2 , the RF generator 1000 may include a memory. Here, the memory can store various data. Various data can be stored temporarily or semi-permanently in the memory. Examples of memory include hard disk drives (HDDs), solid state drives (SSDs), flash memory, read-only memory (ROM), random access memory (RAM), etc. The memory can be embedded in the RF generator 1000 or provided in a removable form. As described above, RF generator 1000 can control the frequency of the AC power supplied to the load based on information about the load's resonant frequency. In other words, RF generator 1000 can track changes in the load's resonant frequency depending on changes in the plasma state, controlling the frequency of the output AC power to correspond to the load's resonant frequency, and outputting AC power with a controlled frequency. This prevents unnecessary power consumption and improves the durability of the plasma system. At least one component of the RF generator 1000 described above may be omitted. For example, the RF generator 1000 may obtain electrical data about the load from an external sensor without including the sensor module 1400. As another example, the RF generator 1000 may be provided with direct current (DC) or rectified DC power from an external source without including the AC power source 1100 and the rectifier 1200. The following describes a frequency control method according to an exemplary embodiment of the present disclosure. The RF generator 1000 can use this frequency control method to control the frequency of alternating current applied to a load, such as the antenna structure 2000. Specifically, the RF generator 1000 can detect the resonant frequency of the load, including the antenna structure 2000, or can detect electrical properties such as current, voltage, and the like over time to periodically or non-periodically change or set the frequency of the output used to generate or maintain plasma (e.g., the frequency of the output AC voltage or the frequency of the output AC current). Hereinafter, a method of controlling the frequency of alternating current applied to a load by a frequency control apparatus will be described with reference to FIG. 3 to FIG. 13 . FIG. 3 is a diagram illustrating a structure of a radio frequency generator 1000 for performing frequency control according to an exemplary embodiment of this specification. 3 , RF generator 1000 may include an inverter 1300, a sensor module 1400, and a controller 1500. Controller 1500 includes a processor 1510, a current detector 1530, a frequency determination unit 1550, and a control signal output unit 1570. RF generator 1000 may use sensor module 1400 to obtain information about the waveform of the output current of inverter 1300 (the output current being applied to a load) and transmit this information to current detector 1530. Furthermore, current detector 1530 may transmit information about the received waveform of the output current to frequency determination unit 1550. Inverter 1300 receives direct current (DC) power, converts it into alternating current (AC), and supplies the AC power to a load. To this end, inverter 1300 can be configured as a half-bridge or full-bridge type. Hereinafter, for ease of explanation, inverter 1300 is described as being configured as a full-bridge type, but the technical concepts of this specification are not limited thereto. In other words, inverter 1300 can also be configured as a half-bridge type. The inverter 1300 may include a first switch S1 , a second switch S2 , a third switch S3 , and a fourth switch S4 . Here, each of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 can be turned on or off by receiving a control signal from the controller 1500. In this case, when the first switch S1 and the third switch S3 are turned on and the second switch S2 and the fourth switch S4 are turned off, a positive voltage can be applied to the load, and when the first switch S1 and the third switch S3 are turned off and the second switch S2 and the fourth switch S4 are turned on, a negative voltage can be applied to the load. In this way, the inverter 1300 can apply an AC voltage having a specific frequency to the load by alternating between positive and negative voltages. For ease of explanation in this specification, when the voltage applied to nodes 1610 and 1710 shown in FIG. 2 is higher than the voltage applied to nodes 1630 and 1730 shown in FIG. 2 , the voltage applied to the load is described as a "positive voltage," and when the voltage applied to nodes 1610 and 1710 shown in FIG. 2 is lower than the voltage applied to nodes 1630 and 1730 shown in FIG. 2 , the voltage applied to the load is described as a "negative voltage." Furthermore, node 1610 shown in FIG. 2 is node 1310 located between first switch S1 and second switch S2 shown in FIG. 3 , and node 1630 shown in FIG. 2 is node 1320 located between third switch S3 and fourth switch S4 shown in FIG. 3 . Sensor module 1400 can detect the phase (or direction and / or magnitude) of the current flowing to the load. As illustrated in FIG2 , sensor module 1400 is electrically coupled to the load so as to obtain a current signal corresponding to the current flowing in the load, and based on the obtained current signal, obtain information about the wave of the output current flowing in the load. Here, the wave of the output current is represented as a square wave by sensing a signal related to the phase and / or direction of the output current flowing to the load (refer to the sensed output current of the inverter shown in FIG8 ). Hereinafter, the signal related to the phase and / or direction of the output current flowing to the load is referred to as the signal of the output current. In other words, the wave of the output current may include multiple output current signals. Specifically, this will be explained with reference to FIG4 . Here, the square waveform disclosed in FIG4 may be a waveform obtained by sensing a signal related to the phase and / or direction of the output current flowing to the load. The output current wave may be defined as a set of multiple output current signals that are continuous in time. For example, the output current signal may include a rising edge and a falling edge separated by a first time width. In other words, the output current signal may be referred to as having the following shape: the shape increases in magnitude to +A along a rising edge, remains at +A for an interval equal to the first time width, then decreases in magnitude to 0 or -B along a falling edge, and again remains at 0 or -B for an interval equal to the second time width. Here, A and B may have the same value or different values. In addition, the first time width and the second time width may be the same width or different widths. The controller 1500 may output a first control signal wave corresponding to the first frequency to the inverter 1300 via the control signal output unit 1570 . As described above, the first control signal can be used to appropriately turn on and / or off the four switches included in inverter 1300, thereby applying a first AC voltage having a first frequency to the load. In other words, control signal output unit 1570 can generate and output a control signal wave corresponding to the frequency determined by frequency determination unit 1550, thereby applying an AC voltage having the frequency determined by frequency determination unit 1550 to the load. The first control signal can be expressed as, for example, the control signal shown in FIG8 . Here, a control signal wave means one that includes multiple control signals. Similar to the above description, referring to FIG. 4 , the square waveform shown in FIG. 4 may represent the signal currently being output to inverter 1300 via control signal output unit 1570. A control signal wave can be defined as a temporally continuous group of the multiple control signals. For example, a control signal may include a rising edge and a falling edge separated by a first time width. In other words, the control signal may have a shape that increases in magnitude to +A along a rising edge, remains at +A for an interval equal to the first time width, then decreases in magnitude to 0 or -B along a falling edge, and again remains at 0 or -B for an interval equal to the second time width. Here, A and B may have the same value or different values. Furthermore, the first time width and the second time width may have the same width or different widths. Furthermore, to facilitate understanding in the description of the control signal, the same terms as A, B, the first time width, and the second time width are used in the description of the output current signal. However, it is apparent to those skilled in the art that A, B, the first time width, and the second time width in the control signal and A, B, the first time width, and the second time width in the output current signal are not necessarily the same values. In other words, A, B, the first time width, and the second time width are arbitrarily set for ease of description and should not be construed as being limited to any specific values. A, B, the first time width, and the second time width in the output current signal and A, B, the first time width, and the second time width in the control signal can have different values. At the same time, in some exemplary embodiments disclosed in the present application, the time points corresponding to the multiple corresponding rising edges of the control signal may mean the time points when the control signals for turning on the first switch S1 and the third switch S3 and turning off the second switch S2 and the fourth switch S4 are output from the controller 1500; and the time points corresponding to the multiple corresponding falling edges of the control signal may mean the time points when the control signals for turning off the first switch S1 and the third switch S3 and turning on the second switch S2 and the fourth switch S4 are output from the controller 1500. According to the above description, in the following description, the first control signal wave may include a plurality of first control signals, and the second control signal wave may include a plurality of second control signals. At the same time, frequency determination unit 1550 can present a virtual signal wave, which is the received first control signal wave offset by a predetermined time. Presenting a virtual signal wave here means that the corresponding virtual signal wave is not generated using a physical or electrical signal and is not output to another device or module. That is, frequency determination unit 1550 can use the virtual signal wave to calculate the delay time or phase difference relative to the output current wave by implementing the virtual signal wave in software or virtually presenting the virtual signal wave without generating a physical or electrical signal. Here, calculating the phase difference or delay time may mean detecting / sensing the phase difference or delay time. In the following, it should be noted that calculating the phase difference or delay time may also be interpreted as detecting / sensing the phase difference or delay time in the description of this specification. However, exemplary embodiments according to the present disclosure are not necessarily limited to this. For example, as described above, the virtual signal wave can be implemented in software or virtually presented, but it can also be a signal actually output as a physical signal or an electrical signal. For example, the frequency determination unit 1550 can physically or electrically generate a virtual signal wave by offsetting the control signal wave output from the control signal output unit 1570 by a predetermined time based on the circuit configured within the frequency determination unit 1550. This can then calculate the delay time or phase difference between the output current wave and the physically or electrically generated virtual signal wave. At the same time, because the virtual signal wave is a shifted first control signal wave, the multiple first control signals included in the first control signal wave can respectively correspond to the multiple virtual signals included in the virtual signal wave. In other words, the multiple virtual signals included in the virtual signal wave can respectively correspond to the multiple first control signals in the order described. For example, offsetting the first control signal wave to generate a virtual signal wave includes: determining a time point corresponding to a rising edge of the virtual signal wave by adding a value corresponding to a predetermined time to each of the time points corresponding to a rising edge of the first control signal or subtracting a value corresponding to the predetermined time from each of the time points corresponding to the rising edge of the first control signal; determining a time point corresponding to a falling edge of the virtual signal wave by adding a value corresponding to the predetermined time to each of the time points corresponding to a falling edge of the first control signal or subtracting a value corresponding to the predetermined time from each of the time points corresponding to the falling edge of the first control signal; and then generating a square wave corresponding to the determined time point of the rising edge and the determined time point of the falling edge. Here, the predetermined time can be determined based on the time difference between the time point at which the rising edge or falling edge of the first control signal is output from the controller 1500 to the inverter 1300 and the time point at which the inverter 1300 is expected to output the AC voltage generated by the operation of the first switch S1, the second switch S2, the third switch S3, and the fourth switch S4 controlled by the first control signal wave. That is, the predetermined time can be determined to be the same as the time difference, or it can be determined to be a value longer or shorter than the corresponding time difference. For example, determining the predetermined time to be the same as the time difference can be referred to as fully resonant driving, determining the predetermined time to be a value longer than the time difference can be referred to as inductive driving, and determining the predetermined time to be a value shorter than the time difference can be referred to as capacitive driving. The following will provide a detailed description of the fully resonant drive, inductive drive, and capacitive drive based on FIG. 7 and FIG. 8 . In the following, for ease of explanation, the time difference between the wave of the first control signal and the wave of the (expected ideal) output voltage refers to the actual (or expected) time difference between the timing of the rising edge and falling edge of the above-mentioned first control signal and the timing of the ideal rising edge and ideal falling edge of the AC voltage actually output by the inverter. Figure 5 is a diagram illustrating the time difference between the first control signal wave and the output voltage wave. However, the components shown in Figure 5 (e.g., control signal output unit 1570, buffer, isolator, gate driver, and / or multiple switches) merely illustrate exemplary embodiments of components constituting controller 1500 and inverter 1300 and are not limited thereto. In other words, at least one of the components shown in Figure 5 may be omitted, and additional components may also be included in Figure 5. Furthermore, each component shown in Figure 5 may be configured as a separate chip or circuit, or two or more components may be configured as a single chip or circuit. Referring to Figure 5 , when the first control signal waveform is output from controller 1500 and applied to the multiple switches of inverter 1300, the DC voltage applied to inverter 1300 according to the first control signal waveform is output as an AC voltage via the buffer, gate driver, and multiple switches. At this point, it takes a specific amount of time for the AC voltage to be output via the buffer, gate driver, and multiple switches. This predetermined amount of time is the difference between the time the first control signal waveform is input from controller 1500 to inverter 1300 and the time the AC voltage generated by the first control signal waveform is expected to be output from inverter 1300. By utilizing this time difference to offset the first control signal waveform, a virtual signal waveform can be created. In other words, the virtual signal waveform can have the waveform of an ideal output voltage that would be expected if the output voltage from inverter 1300 were output without any noise. In this case, as described below, the virtual signal wave is used to calculate the delay time and / or phase difference with respect to the output current wave. As described above, the frequency determination unit 1550 presents the virtual signal wave to calculate the delay time and / or phase difference between the output current wave of the inverter 1300 and the output voltage wave of the inverter 1300. Meanwhile, in the exemplary embodiment of the present specification, the reason why the wave of the output voltage is not directly sensed to directly calculate the delay time and / or phase difference with respect to the wave of the output current is as follows. 6, in most cases, by i RFThe waveform of the output current of the indicated load is obtained in the form of a pure sine wave (or cosine wave). Therefore, via sensor module 1400 , a wave for measuring the phase of the output current (i.e., the output current wave) can be relatively easily obtained in the form of, for example, wave 510 . However, the output voltage at the load is determined by V RF In the illustrated embodiment, it is very difficult to accurately and reliably obtain a waveform for output voltage phase measurement due to high-frequency resonance noise generated by the switching of the multiple switches included in inverter 1300. Therefore, it is very difficult to relatively accurately sense / detect the phase difference or delay time between the output voltage of the load and the output current of the load by directly sensing and comparing the output voltage of the load and the output current of the load. Furthermore, when the phase difference or delay time between the output voltage and the output current of the load cannot be accurately sensed / detected, it may be difficult to control the frequency of the AC voltage applied to the load by tracking the resonant frequency of the variable load. Therefore, the present specification aims to present the wave of a virtual signal obtained by shifting the wave of the control signal that controls the operation of the switch of the inverter 1300 by the controller 1500 by a predetermined time based on the time difference described in Figure 5, so as to calculate the phase difference or delay time between the wave of the virtual signal and the wave of the output current of the load sensed by the sensor module 1400, thereby implementing frequency tracking. The reason why the virtual signal wave obtained by shifting the control signal wave can be used instead of the load output voltage is that, assuming the load output voltage is ideally output without noise, the load output voltage wave differs only in magnitude from the control signal wave, and the output pattern (or phase) of the load output voltage wave and the control signal wave are identical. In other words, the load output voltage wave, which will be output with the time difference described in FIG5 , can be easily predicted. Only the magnitude of the control signal wave changes depending on the magnitude of the DC voltage applied to inverter 1300, while the length or pattern (or phase) of the control signal included in the control signal wave remains unchanged. Therefore, since the wave of the virtual signal, which is shifted by the time difference described in Figure 5 relative to the wave of the control signal, is different from the wave of the output voltage of the ideal load only in magnitude and is the same in pattern (or phase), there is no problem when comparing the phase difference or delay time between the output current of the load and the output voltage of the load. Meanwhile, the time difference in FIG5 can be inferred by experimental measurement or by the specifications of the components included in the inverter 1300, but is not limited thereto, and the time difference can be determined by various methods. In addition, when the inverter 1300 itself or the structure of the inverter 1300 is unchanged, the time difference in FIG5 can be preset and constant. During at least a certain duration within the first period, frequency determination unit 1550 may use the clock of processor 1510 to detect / sense the delay time between the waveform of the virtual signal (i.e., the waveform of the ideal output voltage) and the waveform of the output current of inverter 1300 during the first period. A detailed method for detecting / sensing the delay time will be described below with reference to FIG. Furthermore, frequency determination unit 1550 may determine a second frequency of the second AC voltage applied to the load during a second period immediately following the first period based on at least one possible output frequency. The at least one possible output frequency may be determined based on properties including: the first frequency of the first AC voltage to be generated by the waveform of the first control signal; the detected / sensed delay time; and the clock of processor 1510. A detailed method for determining the second frequency will be described below with reference to FIG. 7 and FIG. 11. Here, the first period may refer to the duration corresponding to the current time when the RF generator 1000 operates according to the first frequency. In addition, the second period is the duration immediately after the end of the first period and may refer to the duration corresponding to the next time after the end of the first period that the RF generator 1000 operates according to the second frequency. At the same time, there may also be a third period, which is the duration immediately after the end of the second period. According to the exemplary embodiments described in the present disclosure, the third period may refer to the duration corresponding to the time when the RF generator 1000 applies an AC voltage having a third frequency to the inverter 1300 after the end of the second period. Here, the third frequency is a frequency determined for the third period based on the second frequency according to the exemplary embodiments of the present disclosure. For example, the exemplary embodiments of the present disclosure can be equally applied to determine the third frequency of the third period. For example, since the method for determining the third frequency based on the second frequency is the same as the method for determining the second frequency based on the first frequency, the method for determining the third frequency in the exemplary embodiments of the present disclosure can be explained and applied by replacing the “first frequency” and “first AC voltage” with “second frequency” and “second AC voltage”, and replacing the “second frequency” and “second AC voltage” with “third frequency” and “third AC voltage”, respectively. In addition, for ease of explanation, it is assumed that the first frequency of the first AC voltage output during the first period is any one of at least one possible output frequency. The at least one possible output frequency can be determined using the clock of the processor 1510, but is not limited thereto. For example, the first frequency may not be included in the at least one possible output frequency. In this case, the first frequency may be output using the multiple possible output frequencies described in FIG12 . FIG12 details a method for generating the first frequency or the second frequency using the multiple possible output frequencies. Even in this case, the method of determining the second frequency output during the second period can be applied in the same manner as the exemplary embodiment disclosed in this specification so that the second frequency can be determined, which will be apparent to those skilled in the art. Control signal output unit 1570 can output a second control signal waveform that controls the switches of inverter 1300, thereby applying a second AC voltage having a determined second frequency to the load during a second period. Furthermore, when the second control signal waveform is input to inverter 1300, the switches of inverter 1300 are turned on and / or off, thereby generating a second AC voltage having a second frequency, which can be applied to the load. Referring now to FIG. 7 , a method for performing frequency control according to an exemplary embodiment of this specification will be described. The frequency control method described in FIG. 7 can be implemented under the control of controller 1500 . That is, unless otherwise specified, the following description can be controlled or implemented by controller 1500 of RF generator 1000 . For ease of explanation, components including the processor 1510, current detector 1530, frequency determination unit 1550, and control signal output unit 1570 included in controller 1500 illustrated in FIG3 are distinguished based on the functions performed by each component, and are not limited to hardware components. That is, each component included in controller 1500 can be implemented in the form of software or program code, or in the form of circuits using various components. Therefore, each component included in controller 1500 may not be physically distinguishable. In other words, each component included in controller 1500 can be functionally distinguishable from each other. Therefore, unless otherwise specifically described, each process or each step described below in FIG. 7 should be understood as being controlled or performed by the controller 1500, and should not be understood as being performed by each specific, separate, and distinct component within the controller 1500. In addition, even when described without specific distinction, a person skilled in the art will be able to easily understand which components of the controller 1500 control and perform the corresponding process or step described in FIG. 7 through the description associated with FIG. 3 . Referring to FIG7 , controller 1500 may execute step S705 to output a first control signal waveform to inverter 1300, thereby applying a first AC voltage having a first frequency to the load during a first period. Furthermore, controller 1500 may execute step S710 to assume a virtual signal waveform obtained by shifting the first control signal waveform by a predetermined time. In this case, the predetermined time is determined based on the time difference described in FIG5 , but is not necessarily the same as the corresponding time difference. 8 , controller 1500 can generate a virtual signal wave by shifting the first control signal wave by a corresponding time difference, thereby achieving a phase identical to the phase of the output voltage wave of ideal inverter 1300 (which is intended to be output according to the corresponding time difference). This can be referred to as a fully resonant drive mode. For example, referring to FIG8 , in the fully resonant drive mode, the predetermined time can be equal to the corresponding time difference, such as a duration of (1-1). Alternatively, it can be assumed that controller 1500 shifts the first control signal by an amount greater than the corresponding time difference, causing the virtual signal to follow (i.e., lag) the output voltage of ideal inverter 1300 (which is intended to be output according to the corresponding time difference). This can be referred to as an inductive drive mode. For example, referring to FIG. 8 , in the inductive drive mode, the predetermined time can be longer than the corresponding time difference, such as a duration of (1-2). Alternatively, it may be assumed that controller 1500 shifts the first control signal by an amount smaller than the corresponding time difference, such that the virtual signal's wave leads the output voltage wave of ideal inverter 1300 (i.e., is ahead of the output voltage wave of ideal inverter 1300) (which is intended to be output according to the corresponding time difference), and this may be referred to as a capacitive drive mode. For example, referring to FIG. 8 , in the capacitive drive mode, the predetermined time may be shorter than the corresponding time difference, such as a duration of (1-3). When the voltage generated by the passive elements (e.g., inductors and capacitors) included in the load is biased as precisely as possible, a fully resonant drive mode can be used to reduce the voltage across the inductor (e.g., a coil) included in the load. For example, when the load is a plasma generator for generating plasma, it may be desirable to bias the LC voltage of the plasma source as precisely as possible to reduce the voltage across the plasma generator's antenna and maintain the plasma discharge at maximum power factor. The inductive driving mode may be appropriate when the plurality of switches included in the inverter 1300 perform soft switching and maintain a specific load state (eg, plasma discharge). When it is desired to stably maintain a gas that is sensitive to the surrounding environment such as flow rate, power and pressure (e.g., NF 3) in certain states (e.g., plasma discharge), the capacitive driving mode may be appropriate. In other words, by selecting one of the three aforementioned drive modes depending on the specific load state (e.g., plasma discharge state), controller 1500 can shift the first control signal's waveform by a predetermined time according to the selected drive mode. Specifically, by determining the predetermined time to be longer, shorter, or equal to the time difference illustrated in FIG. 5 , it is possible to implement operations appropriate for the specific load state (e.g., operations suitable for maintaining plasma discharge). When RF generator 1000 operates in capacitive drive mode or inductive drive mode, it is necessary to determine how much larger or smaller the first control signal should be offset compared to the time difference illustrated in FIG5 . This determination depends primarily on the specific state of the load (e.g., plasma discharge state), but is preferably selected within a range of 10 nanoseconds or greater, or 40 nanoseconds or less. For example, when RF generator 1000 operates in capacitive drive mode, controller 1500 may present a virtual signal wave obtained by offsetting the first control signal wave by a shorter time than the time difference illustrated in FIG5 (i.e., 10 nanoseconds or greater, or 40 nanoseconds or less). For example, when the RF generator 1000 operates in the inductive driving mode, the controller 1500 may present a wave of a virtual signal obtained by shifting the wave of the first control signal by a time longer than the time difference illustrated in FIG. 5 (i.e., 10 nanoseconds or greater or 15 nanoseconds or less). Meanwhile, the selection of a driving mode for shifting the wave of the first control signal can be performed by a user who monitors a specific load state (e.g., plasma discharge state) and then inputs or sets a driving mode or predetermined time for shifting. Alternatively, the controller 1500 may periodically or aperiodically monitor a specific load state (e.g., plasma discharge state) to adaptively determine a predetermined time for shifting the wave of the first control signal or may determine and apply a driving mode. Meanwhile, among the three driving modes mentioned above, the capacitive driving mode is generally the most widely used because operating in the capacitive driving mode is effective in maintaining a specific state of the load (eg, plasma discharge). This will be explained with reference to Fig. 9. Fig. 9(a) shows a change in the resonance frequency in the case of operating in the capacitive driving mode, and Fig. 9(b) shows a change in the resonance frequency in the case of operating in the inductive driving mode. For example, in a case where the inductive coupling between an antenna for plasma discharge and a specific plasma is weakened during the plasma discharge, the effective inductance may increase as the resonant frequency of the antenna may be reduced. In this case, when frequency tracking is performed according to the capacitive drive mode, as shown in Figure 9(a), the magnitude of the current flowing from the RF generator 1000 to the antenna (i.e., the load) increases as the antenna's resonant frequency decreases. When this occurs, the power applied to the plasma increases, and the antenna's resonant frequency can increase again as the inductive coupling between the antenna and the plasma strengthens. As a result, the antenna's resonant frequency can be restored to its original state, and stable negative feedback can be achieved. That is, when operating in the capacitive drive mode, stable negative feedback is achieved when the antenna's resonant frequency changes, thereby maintaining stable plasma discharge and enabling stable frequency tracking. Meanwhile, when frequency tracking is performed in the inductive drive mode, as shown in Figure 9(b), the magnitude of the current flowing from RF generator 1000 to the antenna (i.e., the load) decreases as the antenna's resonant frequency decreases. Consequently, as the power applied to the plasma decreases, the inductive coupling between the antenna and the plasma weakens, and the antenna's resonant frequency decreases. When this occurs, the power applied to the plasma further decreases, leading to unstable positive feedback, in which the antenna's resonant frequency further decreases, making it impossible to maintain a stable plasma discharge. For the reasons stated above, it is generally preferred to perform frequency tracking operation in capacitive drive mode rather than inductive drive mode. However, the capacitive driving mode is not always preferred over the inductive driving mode, and the inductive driving mode may also be preferred depending on the plasma state and the application field of frequency tracking. Table 1: NF comparison between the case where the frequency tracking operation is performed by the capacitive driving mode and the case where the frequency tracking operation is performed by the inductive driving mode. Comparison of discharge stabilization effects of 3 gases. [Table 1] [Table 1] shows that performing the frequency tracking operation in the capacitance mode is more effective in terms of the plasma discharge effect. Meanwhile, FIG. 10 shows the injection of NF during argon (Ar) plasma discharge according to some cases in [Table 1]. 3 gas is used. In both FIG10(a) and FIG10(b), NF is injected approximately 20 milliseconds after the start of argon (Ar) plasma discharge. 3 gas. Figure 10(a) shows the NF according to case number 4 (ie, inductive mode) in [Table 1]. 3 injection. According to Figure 10 (a), due to the continuously increasing current, interlock occurs after the time point indicated by the dotted line, thereby preventing the voltage and current from flowing and causing the discharge effect to disappear. In contrast, Figure 10 (b) shows the injection of NF according to Case No. 1 (i.e., capacitance mode) in [Table 1]. 3, and shows that the discharge effect is stably maintained. Referring to FIG10, it can be seen that the discharge effect is stably maintained in the capacitive driving mode. Meanwhile, if, according to step S710, the wave of the virtual signal is offset by a predetermined time based on the selected driving mode, the controller 1500 may determine the delay time between the wave of the corresponding virtual signal and the wave of the output current of the inverter 1300 during the first period in step S715. Here, determining the phase difference or delay time may refer to detecting / sensing the phase difference or delay time. It should be noted that, in the following description of this specification, determining the phase difference or delay time may also be interpreted as detecting / sensing the phase difference or delay time. For example, referring to FIG. 8 described above, the controller 1500 may present a virtual signal wave obtained by shifting the control signal by a predetermined time of any one of (1-1), (1-2), or (1-3), depending on the selected driving mode. Furthermore, for example, in the time lengths (2-1), (2-2), or (2-3), the controller 1500 may obtain a first count value by counting a first time length from a rising edge of the virtual signal wave (i.e., (4-1), (4-2), or (4-3)) to a first falling edge occurring after the rising edge, based on a clock signal from the processor 1510. For example, if the clock frequency of processor 1510 is 200 MHz, the minimum time unit that can be counted using the corresponding clock frequency is 1 / (200 * 10^6) = 5 nanoseconds. Therefore, when the first time length is 100 nanoseconds, the first count value based on the first time length is 20. Similarly, when the first time length is 105 nanoseconds, the first count value based on the first time length is 21. Meanwhile, if the first time length is not an integer multiple of the minimum time unit, the first count value may be determined based on the cycle of each pulse wave generated by the clock. For example, when counting is performed based on the end point of the cycle of each pulse wave, if the first time length is 103 nanoseconds, the first count value based on the first time length may be 20, and if the first time length is 97 nanoseconds, the first count value based on the first time length may be 19. This yields the same result as applying the basis function to the first time length divided by the value of the minimum time unit. When counting is performed based on the starting point of the cycle of each generated pulse wave, in the case where the first time length is 103 nanoseconds, the count value according to the first time length may be 21, and in the case where the first time length is 97 nanoseconds, the count value according to the first time length may be 20. This can obtain the same result as applying the ceil function to the first time length divided by the value of the minimum time unit. For ease of explanation, the following description of this specification will be based on counting from the end point of each pulse wave cycle. However, this is not limited to this. That is, since it is obvious to those skilled in the art that the exemplary embodiments of this specification can be applied by counting based on the starting point of each pulse wave cycle in the description of this specification, it is obvious that the implementation of the exemplary embodiments described in this specification can be easily replaced with an example in which counting is performed based on the starting point of the pulse wave cycle. Referring back to FIG. 8 , as in (3-1), (3-2), or (3-3), controller 1500 can count the second time length from the rising edge of the virtual signal wave (i.e., (4-1), (4-2), or (4-3)) to the falling edge of the output current wave of inverter 1300 according to the clock of processor 1510. As described above, the falling edge first occurs after the corresponding rising edge. In other words, controller 1500 can obtain the second count value of the second time length by using the minimum time unit according to the clock of processor 1510. At the same time, when obtaining the first count value and the second count value, when the first time length used as a reference is determined to be the length from the rising edge of the wave of the control signal to the falling edge of the wave of the virtual signal, or the second time length is determined to be the length from the rising edge of the wave of the virtual signal to the rising edge of the wave of the next output current that appears after the corresponding rising edge or the length from the rising edge of the wave of the control signal to the falling edge of the wave of the output current that appears after the corresponding rising edge, the following problems may occur. First, when the second time length is determined as the length from the rising edge of the virtual signal wave to the rising edge of the next output current wave that occurs after the corresponding rising edge, when the inverter 1300 operates in the capacitive region, the rising edge of the output current wave may occur earlier in time than the rising edge of the virtual signal wave corresponding to the corresponding rising edge. However, in this case, when counting begins at the rising edge of the virtual signal wave, the controller 1500 detects the next rising edge of the output current wave instead of the rising edge of the output current wave corresponding to the corresponding rising edge, thereby erroneously detecting that the inverter 1300 is operating in the inductive region, even though the inverter 1300 is actually operating in the capacitive region. Meanwhile, when the first time length is determined as the length from the rising edge of the control signal wave to the falling edge of the dummy signal wave, or when the second time length is determined as the length from the rising edge of the control signal wave to the falling edge of the next output current wave that occurs after the corresponding rising edge, when the inverter 1300 operates in the inductive region, the output current wave is delayed in time compared to the dummy signal wave. In this case, if the delay is significant and the falling edge of the output current wave occurs later in time than the second falling edge of the dummy signal wave, it may be erroneously detected that the inverter 1300 is operating in the capacitive region, even though the inverter 1300 is actually operating in the inductive region. At the same time, in a case where the first time length is set to the length from the rising edge (or falling edge) of the wave of the virtual signal to the next rising edge (or next falling edge) that appears after the relevant rising edge (or relevant falling edge), and the second time length is set to the length from the rising edge (or falling edge) of the wave of the virtual signal to the rising edge (or falling edge) of the wave of the output current that first appears after the relevant rising edge (or relevant falling edge), the delay time may be erroneously detected depending on the phase difference or degree of delay between the wave of the ideal output voltage and the wave of the above-mentioned output current, and the degree to which the virtual signal is offset compared to the wave of the ideal output voltage. For example, as shown in FIG8 , in a case where the ideal output voltage wave is ahead of the output current wave in phase, the first time length is set to the length from the rising edge of the virtual signal wave to the next rising edge that occurs after the corresponding rising edge, and the second time length is set to the length from the rising edge of the virtual signal wave to the first rising edge of the output current wave that occurs after the corresponding rising edge. Depending on the degree of delay between the ideal output voltage wave and the output current wave, the delay time may be erroneously detected in at least one of capacitive driving, fully resonant driving, and inductive driving. For example, when describing the fully resonant driving shown in FIG8 as an example, the second count value is calculated by setting the length from time point (4-1) to the first rising edge of the output current wave that occurs after (4-1) as the second time length. However, to correctly calculate the delay time, the first rising edge of the output current wave should correspond to the end point of the first time length. However, in the above example, the first actually occurring rising edge of the output current wave is the rising edge corresponding to the starting point of the first time length (ie, the rising edge corresponding to (4-1)), and thus an error may occur in detecting the delay time. Similarly, even when the first time length is set to the length from the falling edge of the virtual signal wave to the next falling edge that occurs after the corresponding falling edge, and the second time length is set to the length from the falling edge of the virtual signal wave to the first falling edge that occurs after the corresponding falling edge of the output current wave, if the ideal output voltage wave lags behind the output current wave, depending on the degree of lag, the falling edge at the end point of the second time length may correspond to the falling edge corresponding to the starting point of the first time length, thereby causing an error in detecting the delay time. For the same reason as described above, as in time lengths (2-1), (2-2), or (2-3), the controller 1500 may preferably obtain a first count value by counting the first time length from the rising edge of the virtual signal wave (i.e., (4-1), (4-2), or (4-3)) to the first falling edge that occurs first after the corresponding rising edge according to the clock of the processor 1510. Similarly, as in the time length (3-1), (3-2) or (3-3), preferably, the controller 1500 obtains a second count value by counting a second time length from the rising edge of the wave of the virtual signal (i.e., (4-1), (4-2) or (4-3)) to the falling edge of the wave of the output current of the inverter 1300 according to the clock of the processor 1510, as described above, the falling edge first appears after the relevant rising edge. When the controller 1500 obtains the first count value and the second count value, the controller 1500 may execute step S715, which calculates the difference between the first count value and the second count value and determines the delay time between the wave of the virtual signal and the wave of the output current of the inverter 1300 during the first period. For example, the controller 1500 may determine the value obtained by subtracting the second count value from the first count value as the delay time between the wave of the virtual signal and the wave of the output current of the inverter 1300. In this case, as described above, the determined delay time cannot be regarded as the delay time between the actual voltage and current because the delay time is detected / sensed between the sensed output current and the virtual signal that is offset by a predetermined time according to the control signal and each mode. However, as already explained, the purpose of this specification is to utilize the various beneficial effects resulting from using a virtual signal rather than measuring the phase of the voltage. Therefore, the delay time between the voltage and the current should be understood as the delay time between the virtual signal and the current, rather than the delay time between the voltage and the current. Even without any specific limitation or explanation on the delay time between the virtual signal and the current, the delay time actually exists. In addition, the controller 1500 may perform step S720 of determining a second frequency, which is a frequency of the AC voltage output from the inverter 1300 in a second period immediately following the first period, based on the delay time. For example, when the corresponding delay time is within a preset range, controller 1500 may output a second control signal wave identical to the first control signal wave to inverter 1300, causing inverter 1300 to output an AC voltage having the same frequency as the first frequency during a second period immediately following the first period (i.e., causing the AC voltage to be applied to the load). In other words, when the corresponding delay time is within a preset range (e.g., greater than or equal to the first value and less than or equal to the second value), controller 1500 may maintain the frequency of the AC voltage without changing the frequency even during the second period immediately following the first period. Meanwhile, when the corresponding delay time is outside a predetermined range (e.g., greater than or equal to a first value and less than or equal to a second value), the controller may output a second control signal waveform different from the first control signal waveform to inverter 1300, causing inverter 1300 to output an AC voltage having a frequency different from the first frequency during a second period (i.e., applying an AC voltage to a load). For example, if the delay time is less than the first value, controller 1500 may determine a second frequency lower than the first frequency and output the second control signal waveform to inverter 1300, causing inverter 1300 to output an AC voltage having the second frequency during the second period (i.e., applying an AC voltage to a load). Furthermore, if the delay time is greater than the second value, controller 1500 may determine a second frequency greater than the first frequency and output the second control signal waveform to inverter 1300, causing inverter 1300 to output an AC voltage having the second frequency during the second period (i.e., applying an AC voltage to a load). Meanwhile, the first value and the second value can be determined based on a tolerance range. If the first value is -1 and the second value is +1, the tolerance range of the actual delay time can be from -10 nanoseconds to +10 nanoseconds. If both the first value and the second value are 0, the tolerance range of the actual delay time can be from -5 nanoseconds to +5 nanoseconds. Meanwhile, an example of the tolerance range of the actual delay time according to the first value and the second value can be shown in [Table 2]. [Table 2] Meanwhile, the first value and the second value may be different from or the same as each other, and the absolute values ​​of the first value and the second value are not necessarily the same. For example, when the tolerance range of the actual delay time is -5 nanoseconds to +10 nanoseconds, the first value may be 0 and the second value may be 1. Alternatively, when the tolerance range of the actual delay time is -10 nanoseconds to +15 nanoseconds, the first value may be -1 and the second value may be 2. At the same time, depending on the tolerance range of the actual delay time and the result value of the derived delay time, the first value and the second value can be set to rational numbers rather than integers. That is, the first value and the second value are not necessarily integers and can be rational numbers including decimal points. The above description shows that the controller 1500 uses a first count value and a second count value to calculate a delay time, and uses the calculated delay time to determine the second frequency. However, the controller 1500 may use multiple first count values ​​and multiple second count values ​​to calculate a delay time, and use the calculated delay time to determine the second frequency. In this case, the controller 1500 may use the difference between the multiple corresponding first count values ​​and the multiple corresponding second count values ​​to calculate the delay time, and use the average of the corresponding delay times to determine the second frequency. In this case, the first value and the second value are not necessarily integers, but may be rational numbers with decimal points, which may be determined according to the tolerance range of the actual delay time. Meanwhile, as mentioned in the above section, the controller 1500 may use the plurality of first count values ​​and the plurality of second count values ​​to determine the second frequency, an example of which is described below. The first and second periods are continuous in duration, and the second period may occur immediately after the first period. Furthermore, the first and second periods constitute the cycles in which controller 1500 determines whether to change the frequency of the currently output AC voltage. Specifically, while a first control signal wave for outputting a first AC voltage having a first frequency is output from the start of the first period, controller 1500 may output a second control signal wave for outputting a second AC voltage having a second frequency from the start of the second period. In this case, the length of the first period and the length of the second period may be the same as or different from each other. For example, during a first period, a first control signal wave including multiple first control signals and an output current wave including multiple output current signals may be output. Therefore, controller 1500 may present a virtual signal wave obtained by shifting the first control signal wave by a predetermined time during the first period, and the corresponding virtual signal wave may include multiple virtual signals. Here, as illustrated in FIG4 , since the virtual signal wave is obtained by shifting the control signal wave, each virtual signal may have the following shape: each control signal increases in magnitude to +A along a rising edge, remains at +A for an interval equal to a first time width, then decreases in magnitude to 0 or -B along a falling edge, and again remains at 0 or -B for an interval equal to a second time width. Here, A and B may have the same value or different values. Furthermore, the first time width and the second time width may have the same width or different widths. For example, if the first and second time widths are identical and the frequency of the control signal wave is 2 MHz, the frequency of the virtual signal wave will also be 2 MHz, so the sum of the first and second time widths can be 0.5 microseconds. Furthermore, each of the virtual signals included in the virtual signal wave can have the same first and second time widths, but can also have different first and second time widths. For example, as described below, a single frequency can be generated using multiple possible output frequencies determined by using the clock of processor 1510. In this case, the control signals included in the control signal wave can have different periods corresponding to the multiple possible output frequencies. For example, as shown in FIG12 , the control signal wave can include control signals having different periods. In this case, the first and second time widths of each virtual signal or each control signal can be different. For example, if the length of the first period and / or the second period is 10 microseconds, the virtual signal wave may include a total of 20 virtual signals, and therefore a total of 20 delay times may be calculated. However, as described below, of these 20 delay times, only the last N delay times are used to determine the second frequency during the second period. For example, controller 1500 may calculate the average of the last N (where N is a natural number) delay times of the multiple corresponding virtual signals and the multiple corresponding output current signals corresponding to the corresponding virtual signals, and determine the second frequency based on whether the corresponding average value is between the first and second values, less than the first value, or greater than the second value. In this case, the last N delay times can be integers, but may also be rational numbers containing decimal points. Therefore, in this case, the first and second values ​​may also be rational numbers containing decimal points rather than integers. At the same time, for example, in the case of outputting the first frequency by using a combination of multiple possible output frequencies in Figure 12, the controller 1500 can calculate the average value of the last N (where N is a natural number) delay times among the delay times of multiple corresponding virtual signals and multiple corresponding output current signals corresponding to the corresponding virtual signals, regardless of the period of the control signal or the virtual signal, and use the calculated average value to determine the second frequency. Furthermore, the value N, which represents the number of delay times used to calculate the average value, can be an integer. Furthermore, the reason for using only the average value of the last N delay times, rather than the average value of all delay times that can be calculated during the first period, is that even when using the average value of the last N delay times, when N is set sufficiently, controller 1500 can still very accurately calculate the delay time between the first control signal wave and the output current wave. Furthermore, since it takes a certain amount of time for the circuit to stabilize due to frequency changes after the start of each period, it is more advantageous to use only the average value of the delay times that can be calculated after the corresponding certain amount of time when determining a frequency close to the resonant frequency of the variable load. In summary, controller 1500 can calculate the delay times between the multiple first virtual signals and the multiple output current signals during at least a certain duration within the first period, and determine the second frequency during the second period based on an average of the calculated delay times. In this case, the at least certain duration can be the duration corresponding to the last N delay times. However, the exemplary embodiments described in this specification are not limited to determining the second frequency of the second period based on the average value of the generated delay times. For example, the controller 1500 may calculate the delay times of multiple first virtual signals and multiple output current signals for at least a certain duration within the first period, and determine the second frequency of the second period based on the pattern of the calculated delay times. In this case, the at least a certain duration may be the duration corresponding to the last N delay times. For example, among the calculated delay times, the delay time with the largest number of identical values ​​may be determined as the delay time in the first period. Here, when the identical values ​​are the same up to the Xth decimal point, the identical values ​​may be considered to be the same value. Meanwhile, when the controller 1500 determines the second frequency, it may further consider at least one possible output frequency that can be determined using the clock of the processor 1510. The method of determining the second frequency by further considering the at least one possible output frequency will be described in detail below. When determining the second frequency, controller 1500 may output a second control signal wave at S625 for controlling a second AC voltage having the second frequency (the second AC voltage will be applied to the load (i.e., output from inverter 1300) during the second period), and apply the second control signal wave to inverter 1300. Controller 1500 may also determine the second frequency by further considering at least one possible output frequency and output a corresponding second control signal wave accordingly. The detailed operation of controller 1500 in this case follows the description of FIG. 11 described below. At the same time, in the above description of step S720 shown in Figure 7, a method is disclosed in which the controller 1500 determines whether the second frequency is determined to be higher than the first frequency, whether the second frequency is determined to be lower than the first frequency, or whether the second frequency is maintained equal to the first frequency when the controller 1500 determines the second frequency. In this regard, in addition, details will be elaborated on how much higher the second frequency will be than the first frequency when the controller 1500 determines that the second frequency is higher than the first frequency, or how much lower the second frequency will be than the first frequency when the controller 1500 determines that the second frequency is lower than the first frequency. In other words, the exemplary embodiment described below describes a method in which the controller 1500 determines the gap, difference, or distance between the first frequency and the second frequency during step S720 . The controller 1500 may determine the second frequency using the delay time determined in step S715. In this case, when a method of calculating the delay time is expressed in an equation, the method is shown in the following [Equation 1]. [Equation 1] Here, td_count curr is the delay time, the "number of first CLK counts" is the count value of the wave of the virtual signal according to the clock of the processor 1510 within the period corresponding to the frequency of the AC voltage output in the first period and is a first count value, the first count value is the count value from the rising edge of the wave of the virtual signal to the first falling edge that appears after the corresponding rising edge, and the "number of second CLK counts" is the second count value, the second count value is the count value from the rising edge of the wave of the virtual signal to the falling edge of the wave of the output current. When td_count is determined by [Equation 1] curr When the controller 1500 is curr When the second frequency is less than the first value, it is determined that the second frequency is lower than the first frequency, and the td_count currIn the case where the second value is exceeded, it is determined that the second frequency is higher than the first frequency. curr When the value is greater than or equal to the first value and less than or equal to the second value, the second frequency is determined to be the same as the first frequency. If controller 1500 determines that the second frequency is higher or lower than the first frequency, a third count value can be determined by using the following [Equation 2] and the first frequency, which is the frequency of the first control signal or the first AC voltage output during the first period, and by counting the first frequency using the clock of processor 1510. Here, counting the frequency using the clock of processor 1510 means counting the time corresponding to a period (the period being the inverse of the frequency) based on the clock of processor 1510, and the counting method can be applied in the same manner as described above. [Equation 2] Here, CLK is a clock of the processor 1510 , and the “number of third CLK counts” is a third count value obtained by counting the first frequency using the clock of the processor 1510 . For example, since 200*10^6 / 100=2*10^6=2 MHz, when the clock frequency of the processor 1510 is 200 MHz and the first frequency is 2 MHz, the controller 1500 may determine the third count value to be 100. The controller 1500 may determine, as the candidate frequency, a frequency that can be generated by using a count value within a specific range of the third count value among a plurality of possible output frequencies that can be output according to the clock of the processor 1510 . For example, when the controller 1500 determines that the second frequency is higher than the first frequency, the candidate frequency may be determined according to the following [Equation 3]. [Equation 3] In contrast, when it is determined that the second frequency is lower than the first frequency, the candidate frequency may be determined according to the following [Equation 4]. [Equation 4] Here, the k value may be a natural number, and a predetermined value may be used for it. For example, k may be 1. For example, based on the above example, it can be assumed that the third count value is 100 and the clock frequency of processor 1510 is 200 MHz. When controller 1500 determines that the second frequency is higher than the first frequency and k=1, the candidate frequency can be determined as 200 MHz / (100 - 1) = 2.02 MHz according to [Equation 3]. In contrast, when the controller 1500 determines that the second frequency is lower than the first frequency and k=1, the candidate frequency may be determined as 200 MHz / (100 + 1) = 1.98 MHz according to [Equation 4]. Here, since controller 1500 determines how much to increase or decrease the first frequency, controller 1500 can subtract the first frequency according to Equation 2 from the candidate frequency according to Equation 3 or Equation 4 and define the corresponding value as the incremental frequency. In other words, the incremental frequency is the value obtained by subtracting the first frequency from the candidate frequency. For example, the incremental frequency can be expressed according to the following [Equation 5]. [Equation 5] As described above, in the case where the controller 1500 intends to increase the first frequency to determine the second frequency, the value -k may be used, and in the case where the controller 1500 intends to decrease the first frequency to determine the second frequency, the value +k may be used. means the incremental frequency, and f curr Means the first frequency. Meanwhile, in order to adaptively determine the second frequency according to the delay time determined in [Equation 1], the controller 1500 may determine a smoothing factor m using the delay time according to the following [Equation 6]. In other words, in order to adaptively determine the second frequency according to the difference between the wave of the virtual signal and the wave of the output current and / or according to the driving mode in which the controller 1500 operates, the controller 1500 can use the delay time to determine the smoothing factor m according to the following [Equation 6]. [Equation 6] Here, as explained above, td_count curr Means the delay time. At the same time, td_count max is a preset parameter value and may be a value stored in the controller 1500. For example, td_count max Can be set to an integer value. In addition, td_count max The value may be changed according to the user's input or command, and may also be changed according to the decision of the controller 1500. However, in the exemplary embodiment of this specification, it is assumed and described that td_count max It is a preset fixed value. The controller 1500 may ultimately determine how much to increase or decrease the first frequency by multiplying the increment frequency according to [Equation 5] by the smoothing factor m according to [Equation 6] to determine the first frequency as the second frequency. That is, the amount by which the controller 1500 increases or decreases the frequency can be determined according to [Equation 7]. [Equation 7] In other words, the controller 1500 may determine the second frequency by adding Δf to the first frequency or subtracting Δf from the first frequency. For example, in the case where the first frequency is 2 MHz, the delay time is 2, and the controller 1500 determines to increase the first frequency to determine the second frequency, the clock of the processor 1510 is 200 MHz, so ={200 MHz / (100 – 1)} –{200 MHz / 100} = 0.02 MHz (where k = 1) and m = 2 / 100 (where 100 is a fixed value), so ∆f becomes 0.02 x 0.02 = 0.0004 MHz. Therefore, the second frequency can be determined as (2 + 0.0004) = 2.0004 MHz. Meanwhile, in the case where the controller 1500 uses the delay time for determining the second frequency as the average value of the last N delay times among the delay times between the plurality of virtual signals and the plurality of output current signals that can be generated in the first period, the corresponding average value can be used as td_count curr . In the case where the average value is a rational number containing a decimal point, the corresponding average value can be used as td_count curr , or the value obtained by rounding the corresponding average value up, down, or up to the Mth decimal point may be used as td_count curr Therefore, td_count curr It can be a rational number including a decimal point. However, it is not limited thereto and depends on factors such as the convenience of calculation, the operating environment of the RF generator 1000, and the tolerance range between the resonant frequency of the load and the second frequency. curr It can also be an integer value rounded down or up from the first decimal place of the corresponding average. Meanwhile, the controller 1500 determines the second frequency according to the above description, but the corresponding second frequency may be a frequency that cannot be generated by the clock of the processor 1510. Therefore, in this case, there may be a problem in how the controller 1500 determines and generates the second frequency, which will be explained in detail below. The method for generating the second frequency described below has been mentioned with respect to step S720 shown in Figure 7. That is, the method for generating the second frequency described below is related to a method for determining and generating the second frequency by further considering at least one possible output frequency other than the first frequency and the clock of the processor 1510. At the same time, as described above, the third frequency and the first frequency output during the third period can also be generated according to the method described below. For example, when the first frequency is not included in the at least one possible output frequency, the controller 1500 can output a first AC voltage having the first frequency by using multiple possible output frequencies close to the first frequency among the at least one possible output frequency (for example, using not only the closest possible output frequency greater than the first frequency but also the closest possible output frequency less than the first frequency), as described in the method described below. The following [Table 3] shows possible output frequencies that can be output using the clock output of the processor 1510 when the clock of the processor 1510 is 200 MHz. [Table 3] Referring to Table 3 above, even when controller 1500 determines the second frequency to be 3 MHz, the second frequency of 3 MHz cannot actually be generated using the clock of processor 1510. In other words, referring to Table 3, a clock count of 66 generates a frequency of 3.03 MHz, while a clock count of 67 generates a frequency of 2.98 MHz. Therefore, it is impossible to generate a frequency of exactly 3 MHz using only a single clock count. However, since the resonant frequency of the load does not change considering the clock of the processor 1510 , a method is needed to generate a frequency as close as possible to the resonant frequency of the changing load using the limited clock of the processor 1510 . For example, when the quality factor of the load driven by RF generator 1000 is high, the magnitude and phase of the output current of inverter 1300 may change more dramatically depending on the frequency. Therefore, in order to more quickly track the resonant frequency of the changing load, it is necessary to be able to more accurately control and output the frequency. Meanwhile, the high quality factor of the load can be, for example, when a large flow rate of plasma is discharged. 11 , a method for generating a frequency as close as possible to the resonant frequency of the load by using a possible output frequency that can be output as a clock of the processor 1510 will be described. As described above, the series of processes described based on FIG11 can be regarded as a further specific example of step S720. Therefore, the series of processes S1105 to S1135 explained with reference to FIG. 11 may be carried out during the process corresponding to S720 to S725 in FIG. 7 . 11 , the controller 1500 may determine the second frequency based on the first frequency and the delay time according to the above method ( S1105 , S720 ). Controller 1500 determines whether the second frequency is included in the possible output frequencies that can be output according to the clock of processor 1510 (S1110). If the determined second frequency is included in the possible output frequencies that can be output according to the clock of processor 1510, controller 1500 may output a second control signal wave that controls inverter 1300 to output a second AC voltage having the second frequency during the second period (i.e., to apply the second AC voltage to the load) (S1115, S725). If the determined second frequency is not included in the possible output frequencies that can be output according to the clock of processor 1510, a plurality of possible output frequencies closest to the second frequency can be selected from the possible output frequencies in step S1120. In this case, the number of possible output frequencies selected by controller 1500 can be determined according to a predefined setting, or controller 1500 can select the number of possible output frequencies that can be used to generate a frequency closest to the second frequency by combining the numbers of each case. For example, when a close frequency having a difference less than or equal to a predetermined value can be generated from the second frequency by using a first possible output frequency that is the largest and closest to the second frequency and a second possible output frequency that is the smallest and closest to the second frequency, the controller 1500 may select two possible output frequencies. In the case where selecting four possible output frequencies can generate a frequency closer to the second frequency than selecting two possible output frequencies, the two first possible output frequencies that are the largest and closest to the second frequency and the two second possible output frequencies that are the smallest and closest to the second frequency may be selected. However, since a frequency close to the second frequency can be generated only when the largest possible output frequency and the smallest possible output frequency closest to the second frequency are selected among the plurality of possible output frequencies, it is preferable to select an even number of possible output frequencies. The controller 1500 may perform step S1125 of determining the difference between the second frequency and each of the selected plurality of closest possible output frequencies. For example, when the two closest possible output frequencies are selected, not only a first difference between the second frequency and the closest and largest first possible output frequency but also a second difference between the second frequency and the closest and smallest second possible output frequency may be determined. Controller 1500 may determine an output count for each of the plurality of closest possible output frequencies based on a ratio of the differences (S1130). For example, a difference between the first possible output frequency and the second possible output frequency, or a third difference that is the sum of the first difference and the second difference, may be determined, and an output count for each of the first possible output frequency and the second possible output frequency may be determined based on a ratio between (first difference / third difference) and (second difference / third difference). Controller 1500 may output multiple third control signals so that each of the multiple closest output frequencies can be output as evenly as possible during the second period based on the determined output count. For example, controller 1500 may output at least one third control signal corresponding to the first possible output frequency and one or more third control signals corresponding to the second possible output frequency to inverter 1300 as evenly as possible during the second period based on the number of corresponding relationships (S1135). It will be apparent to those skilled in the art that, when step S1135 is implemented, step S725 may be omitted or replaced by step S1135. That is, when the second frequency is not included in the multiple possible output frequencies, controller 1500 may output the multiple third control signals instead of the second control signal. At the same time, it can be observed that, compared to the case where controller 1500 first outputs at least one third control signal corresponding to the first possible output frequency among the plurality of closest possible output frequencies according to the number of correspondences and then subsequently outputs one or more third control signals corresponding to the second possible output frequency according to the number of correspondences, the case where controller 1500 outputs at least one third control signal corresponding to the first possible output frequency and one or more third control signals corresponding to the second possible output frequency as evenly as possible, an output current having an ideal frequency closer to the second frequency is sensed. The detailed effect of this will be described below with reference to FIG. 14. Meanwhile, here, the meaning of outputting the third control signal corresponding to the plurality of closest possible output frequencies as uniformly as possible may be interpreted as one of the following definitions. Firstly, this may mean that the dispersions between the third control signals respectively corresponding to the plurality of closest possible output frequencies are outputted to be uniform. Secondly, this may mean that the deviations between the third control signals respectively used for the plurality of closest possible output frequencies are output to be maximum. Third, this may mean implementing control such that, among the third control signals corresponding to the plurality of closest possible output frequencies, two third control signals corresponding to the largest number of possible output frequencies are respectively arranged at the beginning and end of a set, and third control signals corresponding to the remaining possible output frequencies are alternately arranged in the middle of the set, so as to sequentially output the plurality of sets generated by the above method. In this case, when the maximum number of times is an odd number, one or more sets that can be generated corresponding to the number of times may be generated, and the remaining third control signals corresponding to the same number of possible output frequencies corresponding to the corresponding number of times as the remaining number may be alternately arranged in the middle with the third control signals corresponding to the remaining possible output frequencies. Fourth, the last one may mean that the difference between the average distances measured for each pair of third control signals corresponding to the plurality of closest possible output frequencies is minimized. For example, when there are third control signals corresponding to four possible output frequencies, the difference between the average distances is minimized, the average distances including: the average distance between at least one third control signal corresponding to the first possible output frequency and one or more third control signals corresponding to the second possible output frequency; the average distance between at least one third control signal corresponding to the first possible output frequency and at least one third control signal corresponding to the third possible output frequency; the average distance between at least one third control signal corresponding to the first possible output frequency and one or more third control signals corresponding to the fourth possible output frequency; the average distance between at least one third control signal corresponding to the second possible output frequency and one or more third control signals corresponding to the fourth possible output frequency; and the average distance between at least one third control signal corresponding to the third possible output frequency and one or more second control signals corresponding to the fourth possible output frequency. Now, based on the above description of FIG. 11 , an example of a method for precisely controlling the frequency using the output possible frequency according to the clock of processor 1510 will be described. The following description is merely an example to facilitate understanding. Therefore, the following description should only be used to assist understanding, and the scope of this disclosure is not limited to these examples. As shown in Table 3, when the processor 1510's clock frequency is 200 MHz and the second frequency determined by steps S705 to S720 is 3.0 MHz, Table 3 shows that no clock count value can produce a frequency of 3.0 MHz, making it difficult to achieve precise frequency control. Therefore, in this case, the controller 1500 uses a table or list pre-stored in the controller 1500 (as shown in Table 3), or performs calculations performed by the controller 1500 to select 3.03 MHz (corresponding to clock count 66) and 2.98 MHz (corresponding to clock count 67), which are the frequencies closest to 3.0 MHz and can be produced using a 200 MHz clock. Controller 1500 determines the first difference = (3.03 – 3.0) = 0.03 MHz, the second difference = (3.0 – 2.98) = 0.02 MHz, and the third difference = (3.03 – 2.98) = (0.03 + 0.02) = 0.05 MHz. Since (first difference / third difference) = (0.03 / 0.05) = 0.6 and (second difference / third difference) = (0.02 / 0.05) = 0.4, controller 1500 outputs at least one third control signal corresponding to a frequency of 3.03 MHz and one or more third control signals corresponding to a frequency of 2.98 MHz at a ratio of 2:3. At the same time, in order to more accurately generate a frequency closer to 3.0 MHz, the controller 1500 outputs the at least one third control signal corresponding to the frequency of 3.03 MHz and the one or more third control signals corresponding to the frequency of 2.98 MHz at a ratio of 2:3, but outputs these signals to be distributed as evenly as possible. As in the above example, an example of outputting third control signals corresponding to frequencies of 3.03 MHz and 2.98 MHz by distributing the third control signals as evenly as possible is shown in FIG12 . Since frequency is the inverse of period, 335 nanoseconds corresponds to 2.98 MHz, and 330 nanoseconds corresponds to 3.03 MHz. As can be seen from FIG12 , the at least one third control signal corresponding to a frequency of 3.03 MHz and one or more third control signals corresponding to a frequency of 2.98 MHz are alternately output, but at a 2:3 ratio. In other words, FIG. 11 shows that the third control signal consisting of the set {2.98–3.03–2.98–3.03–2.98} is repeatedly output during the second period. FIG13 shows experimental results showing the degree to which each frequency is precisely controlled in the case where each frequency is output, as in FIG12 , compared to the case where no frequency is output. Referring to FIG13 , it can be seen that when each frequency of 2.98 MHz and each frequency of 3.03 MHz are output as evenly as possible at an appropriate ratio as shown in FIG13( b ), each frequency of 3.00 MHz is generated. However, as shown in FIG13( a ), it can be seen that when the frequency of 2.98 MHz is output at a ratio greater than the appropriate ratio, a frequency less than 3.00 MHz is generated, and as shown in FIG13( c ), when the frequency of 3.03 MHz is output at a ratio greater than the appropriate ratio, a frequency greater than 3.00 MHz is generated. FIG14 shows experimental results obtained by comparing a case where the third control signal at a frequency of 2.98 MHz and a third control signal at a frequency of 3.03 MHz were output at an appropriate ratio as uniformly as possible, and a case where the third control signal was output at an appropriate ratio but unevenly. Referring to FIG14 , it can be seen that when the third control signal at a frequency of 2.98 MHz and a third control signal at a frequency of 3.03 MHz were output at an appropriate ratio as uniformly as possible, the output current of inverter 1300 measured was output with a waveform close to the ideal waveform. However, it can be seen that when the third control signal at a frequency of 2.98 MHz and a third control signal at a frequency of 3.03 MHz were output at an appropriate ratio but unevenly, the output current of inverter 1300 measured did not form the ideal waveform. Hereinafter, the present disclosure will not only describe an example of the structure of the control signal output unit 1570 according to FIG. 7 , which outputs a wave of a second control signal for controlling a second AC voltage having a second frequency to be applied to a load, but will also describe other examples of using such a structure to precisely control the frequency. 15 shows an example of the structure of the control signal output unit 1570 . Referring to FIG 15 , the control signal output unit 1570 may include a digital signal output unit 1575 , a digital to analog converter (DAC) 1580 , a filter 1585 , and a comparator 1590 . The digital signal output unit 1575 can output a bit sequence of a preset size based on the second frequency and / or jump step determined by the frequency determination unit 1550. For example, when the preset size is 4, the digital signal output unit 1575 can output 4 bits. Furthermore, the digital signal output unit 1575 can output a bit sequence of the preset size at each time corresponding to the clock of the processor 1510. For example, when the clock of the processor 1510 is 5 nanoseconds, corresponding to a frequency of 200 MHz, the digital signal output unit 1575 can output a bit sequence every 5 nanoseconds based on the jump step. The following describes in detail the method by which the digital signal output unit 1575 determines the jump step and the method for outputting the bit sequence based on the jump step. Furthermore, the digital signal output unit 1575 can be a direct digital synthesizer (DDS), but is not limited thereto. Any device capable of outputting a bit sequence of a predetermined size according to the clock of the processor 1510 may be used as the digital signal output unit 1575 . At the same time, the digital signal output unit 1575 may map the 2^n points to their corresponding values ​​(e.g., bit sequences) and store the mapping result. Here, assuming that the 2^n points are arranged at equal intervals on the time axis within one cycle of the reference sine wave, the corresponding values ​​of the 2^n points may represent the magnitude of the reference sine wave at the time when the corresponding points are arranged. Here, the reference sine wave may correspond to the clock frequency of the processor 1510. For example, if the clock frequency of the processor 1510 is 200 MHz (i.e., a period of 5 nanoseconds), the reference sine wave may be a sine wave with a period of 5 nanoseconds. However, the reference sine wave is not necessarily limited to a sine wave having the clock frequency of the processor 1510 and may be any other sine wave. 16 , a more detailed description of the 2^n points stored in the digital signal output unit 1575 and the corresponding values ​​mapped to the 2^n points will be provided. Figure 16 shows 16 points p1 to p16, equally spaced on the time axis, within one cycle of a reference sine wave when n = 4. The magnitudes of the reference sine wave at the corresponding 16 equally spaced time points p1 to p16 (i.e., BS0 to BS8) can be mapped to corresponding points and stored in the digital signal output unit 1575. For example, referring to Figure 16 , points p1 and p9 can be mapped to and stored as BS0, points p2 and p8 can be mapped to and stored as BS1, points p3 and p7 can be mapped to and stored as BS2, and the remaining points can also be mapped to and stored as their corresponding BS values. Here, BS may refer to the bit sequence to be output from the digital signal output unit 1575. That is, the digital signal output unit 1575 can store the corresponding points by mapping the magnitudes of the reference square wave corresponding to the corresponding points into a bit sequence. However, the values ​​mapped to the corresponding points do not necessarily need to be mapped and stored in the form of a bit sequence and can be stored in another form corresponding to the bit sequence output by the digital signal output unit 1575. In addition, the size of the bit sequence output by the digital signal output unit 1575 can be n, but is not limited thereto. For example, the size of the bit sequence output by the digital signal output unit 1575 can be less than or equal to n. DAC 1580 receives the bit sequence output from digital signal output unit 1575 and generates an analog signal based on the bit sequence. Furthermore, since the bit sequence is output at each timing corresponding to the clock of processor 1510, DAC 1580 can also output an analog signal of the same magnitude at each timing corresponding to the clock of processor 1510. For example, if the clock of processor 1510 is 5 nanoseconds and the value of the bit sequence received from digital signal output unit 1575 is 1, DAC 1580 can output an analog signal with a magnitude of 1 for 5 nanoseconds. Filter 1585 can remove a specific frequency band from the analog signal output from DAC 1580. For example, filter 1585 can be a low-pass filter (LPF), which removes high-frequency components from the analog signal output from DAC 1580 and leaves only low-frequency components. Therefore, filter 1585 can convert the analog signal output from DAC 1580 into a sinusoidal analog signal. In other words, filter 1585 smoothes the envelope of the analog signal output from DAC 1580. Here, a sinusoidal analog signal is not necessarily defined as a perfect sinusoidal analog signal. That is, a sinusoidal analog signal is a sine wave or cosine wave signal with a smoother envelope obtained by passing it through a low-pass filter that removes high-frequency components. The comparator 1590 compares the magnitude of the analog signal in the form of a sine wave output from the filter 1585 with a specific value (e.g., 0) to output a signal with a magnitude of +A when the magnitude of the analog signal is greater than the specific value and outputs a signal with a magnitude of 0 or -B when the magnitude of the analog signal is less than the specific value. The output signal output from the comparator 1590 is used as a control signal. That is, the comparator 1590 outputs a control signal or a control signal wave for turning on / off the switches (eg, four switches) included in the inverter 1300. Meanwhile, as shown in FIG5 and FIG15, the wave of the control signal output from the comparator 1590 may be input to the switch included in the inverter 1300 via the buffer. 15 and 16 , an example of generating a wave of a control signal for outputting a second AC voltage having a second frequency determined by the frequency determination unit 1550 is described in FIG. 17 to FIG. 20 . 17 to 20 , the frequency determination unit 1550 performs step S1705 of determining the second frequency based on the first frequency and the delay time. In this case, the process and method for determining the second frequency can be applied in the same manner as described in steps S705 to S720 in FIG. 7 , and thus will not be described in detail. The frequency determination unit 1550 performs step S1710 of determining the jump step size of the wave used to generate the second control signal based on the determined second frequency. Here, the frequency determination unit 1550 determines the jump step size according to the following [Equation 8]. [Equation 8] Here, f c is the clock frequency of the processor 1510. M represents the jump step size. 2^n is the number of points stored in the digital signal output unit 1575. For example, when the frequency determination unit 1550 determines the second frequency to be 50 MHz, f c When the frequency is 200 MHz and n is 4, M can be determined to be 4 (M=4). At the same time, the digital signal output unit 1575 may output a value corresponding to at least one point based on a jump step size M. In this case, the digital signal output unit 1575 may execute step S1715, which outputs a value corresponding to at least one point for each clock of the processor 1510. For example, the digital signal output unit 1575 may output a value corresponding to each point in a four-point interval. For example, when describing such points with reference to FIG. 16 , the digital signal output unit 1575 may output BS0 corresponding to p1, BS4 corresponding to p5, BS0 corresponding to p9, and then BS8 corresponding to p13. After the digital signal output unit 1575 outputs BS8 corresponding to p13, it may again output BS0 corresponding to p1 using a jump step size of 4. In other words, the digital signal output unit 1575 may output a bit sequence corresponding to each point while cycling between p1 to p16 based on the determined jump step size. In this case, the digital signal output unit 1575 may output BS0 corresponding to p1, output BS4 corresponding to p5 5 nanoseconds after the clock cycle of the processor 1510, output BS0 corresponding to p9 again 5 nanoseconds after that, and output BS8 corresponding to p13 again 5 nanoseconds after that. 18 , it can be seen that the digital signal output unit 1575 outputs a bit sequence (BS) for each corresponding point. In step S1720, DAC 1580 may convert the bit sequence output from digital signal output unit 1575 into an analog signal. Here, since digital signal output unit 1575 outputs a bit sequence for each clock cycle of processor 1510, the analog signal converted by DAC 1580 can be output as an analog signal having the same value during a period corresponding to the clock cycle (e.g., 5 nanoseconds). For example, when digital signal output unit 1575 outputs a bit sequence of BS4, DAC 1580 may output an analog signal having a magnitude corresponding to the bit sequence of BS4 for 5 nanoseconds. Therefore, as can be seen in FIG. 18 , the analog signal output from DAC 1580 has a sinusoidal wave envelope formed in a staircase shape, meaning that the analog signal output from DAC 1580 includes a large amount of high-frequency components. The analog signal output from the DAC 1580 passes through the filter 1585 and is filtered in step S1725. As can be seen in FIG18, the analog signal having high frequency components passing through the filter 1585 is removed, thereby forming a smooth envelope. In step S1730, the filtered analog signal is input to comparator 1590, which compares the magnitude of the filtered analog signal with a specific value to generate a second control signal. Referring to FIG. 18 , the second control signal output from comparator 1590 has a second frequency determined by frequency determination unit 1550. Furthermore, the second control signal operates switches (e.g., four switches) included in inverter 1300, causing inverter 1300 to output a second AC voltage having the second frequency. 19 and 20 show that the digital signal output unit 1575 outputs a bit sequence according to the jump step size determined by the frequency determination unit 1550 , and the DAC 1580 outputs an analog signal based on the output bit sequence. Referring to FIG19 , digital signal output unit 1575 stores each of the 2^n points set at equal intervals within one cycle of the reference sine wave illustrated in FIG17 , and stores the value corresponding to each point. This storage format is expressed in the form of a digital phase wheel. However, the values ​​corresponding to the corresponding 2^n points may also be stored in the form of a lookup table in the digital signal output unit 1575. For example, the 2^n points may be respectively mapped to the values ​​corresponding to the corresponding points (e.g., BS 0 to BS 8) and stored in the form of a lookup table. FIG19 illustrates a case where the frequency determination unit 1550 determines the jump step size to be 1. In this case, the digital signal output unit 1575 outputs a bit sequence corresponding to each point in a one-point interval for each clock of the processor 1510. Furthermore, the DAC 1580 receives the bit sequence output from the digital signal output unit 1575 and outputs an analog signal having a corresponding value for each bit sequence. 20 , it shows analog signals output from the DAC 1580 in the case where the jump step size is 1 and the case where the jump step size is 2. FIG20( a ) shows the analog signal output when the jump step size is 1, and FIG20( b ) shows the analog signal output when the jump step size is 2. Comparing Figure 20(a) and Figure 20(b) , it can be seen that the frequency of the analog signal when the jump step size is 2 is twice the frequency of the analog signal when the jump step size is 1. In other words, it can be seen that the period of the analog signal when the jump step size is 2 is half the period of the analog signal when the jump step size is 1. By controlling the jump step size in this way, the period or frequency of the analog signal can be controlled, and the analog signal with a controlled period or frequency can be converted into a control signal with a controlled frequency by the filter 1585 and the comparator 1590, and the control signal with a controlled frequency can be applied to the switch of the inverter 1300, thereby outputting an AC voltage with a controlled frequency. 19 , 20 , and Equation 8, when the jump step size is 1, the DAC 1580 outputs an analog signal with a frequency 1 / (2^n) times the clock frequency of the processor 1510. When the jump step size is k, the DAC 1580 outputs an analog signal with a frequency K / (2^n) times the clock frequency of the processor 1510. As can be seen from this description, the larger n is, the more precisely the analog signal frequency can be controlled. For example, when the clock frequency of processor 1510 is 200 MHz and n is 4, the minimum frequency of the analog signal output from DAC 1580 is 12.5 MHz, and the analog signal frequency can be controlled in 12.5 MHz increments. In contrast, when the clock frequency of the processor 1510 is 200 MHz and n is 16, the minimum frequency of the analog signal output from the DAC 1580 is 3.052 kHz, and the frequency of the analog signal can be controlled in units of 3.052 kHz. That is, the larger the value of n, the more precisely the frequency of the analog signal output from DAC 1580 can be controlled. Furthermore, the analog signal output from DAC 1580 is converted into a second control signal by filter 1585 and comparator 1590. In this case, the second control signal has the same frequency as the analog signal, and the frequency of the second control signal becomes the same as the frequency of the output voltage of inverter 1300. Therefore, as the value of n increases, the frequency of the output voltage can also be controlled more precisely. 21 shows that the clock frequency of processor 1510 is 200 MHz (i.e., its period is 5 nanoseconds), and one period of the reference sine wave is set to 2^n points to generate a frequency of 3 MHz. Here, n is greater than or equal to 32 and less than or equal to 48. Referring to Figure 21 , to generate a frequency of 3 MHz, the jump step size is determined to be 1. For example, when n is 32, 1 can be determined to be 64, 424, 509, and when n is 48, 1 can be determined to be 4, 222, 124, 650, 659. Figure 21 shows that the digital signal output unit 1575 outputs a bit sequence corresponding to each point in the 1-point interval based on the clock of the processor 1510, and generates and outputs a second AC voltage having a frequency of 3 MHz based on the second control signal generated by the DAC 1580, the filter 1585, and the comparator 1590. As shown in FIG. 21 , it can be seen that the structure of the reference sine wave and control signal output unit 1570 disclosed in FIG. 15 is divided into 2^n points, the values ​​corresponding to the corresponding points are stored, and then a jump step is used to control the frequency of the sine wave, thereby enabling more precise frequency control. The methods according to the embodiments of the present disclosure can be implemented in the form of program instructions that can be executed by various computing components and can be recorded on a computer-readable medium. The computer-readable medium can include program instructions, data files, data structures, etc., either individually or in combination. The program instructions recorded on the medium can be specifically designed and configured for each embodiment, or can be generally known to those skilled in the art of computer software. Computer-readable recording media can include: magnetic media, such as hard disks, floppy disks, and magnetic tapes; optical media, such as compact disc read only memories (CD-ROMs) and digital versatile discs (DVDs); magneto-optical media, such as floppy disks; and hardware units, such as read-only memories (ROMs), random access memories (RAMs), flash memories, etc. The computer-readable recording media is intended to store and execute program instructions. The program instructions can include high-level language codes that can be executed by a computer using an interpreter, as well as machine language codes, such as those produced by a compiler. The hardware unit may be configured to function as one or more software modules to implement operations according to the embodiments of the present disclosure, and vice versa. Although the embodiments of the present disclosure have been shown and described with reference to the accompanying drawings, those skilled in the art will understand that various changes and modifications in form and detail may be made thereto. For example, although the embodiments of the present disclosure are implemented in a sequence other than that described, and / or components such as systems, structures, devices, circuits, etc. are combined or assembled in a manner other than that described, or are replaced or substituted with other components or their equivalents, the desired results can still be achieved. Therefore, other implementations, other embodiments and equivalents of the appended claims may also be included within the scope of the appended claims. 1-1, 1-2, 1-3: Duration / signal offset 2-1, 2-2, 2-3, 3-1, 3-2, 3-3: Time length 4-1, 4-2, 4-3: Rising edge 100: Plasma system 510: Wave 1000: Radio frequency (RF) generator 1100: AC power supply 1200: Rectifier 1300: Inverter 1310, 1320, 1610, 1630, 1710, 1730: Node 1400: Sensor module 1410: Converter 1420, 1585: Filter 1430, 1590: Comparator 1500: Controller 1510: Processor 1530: Current detector 1550: Frequency determination unit 1570: Control signal output unit 1575: Digital signal output unit 1580: Digital-to-analog converter (DAC) 2000: Antenna structure 3000: Plasma generator BS0, BS1, BS2, BS3, BS4, BS5, BS6, BS7, BS8: Amplitude value GND: Ground node C res :Capacitor i RF :Load output current L eff :Inductor R eff : Resistor S1: First switch S2: Second switch S3: Third switch S4: Fourth switch S625, S705, S710, S715, S720, S725, S1105, S1110, S1115, S1120, S1125, S1130, S1135, S1705, S1710, S1715, S1720, S1725, S1730: Steps p1, p2, p3, p4, p5, p6, p7, p8, p9, p10, p11, p12, p13, p14, p15, p16: Point V DD : Input voltage V RF :Output voltage FIG1 is a diagram illustrating a plasma system according to an exemplary embodiment of the present specification. FIG2 is a diagram illustrating an RF generator according to an exemplary embodiment of the present specification. FIG3 is a diagram illustrating the structure of an RF generator for frequency control according to an exemplary embodiment of the present specification. FIG4 is a diagram illustrating the relationship between a signal (controlling current or output current) and a wave (controlling signal or output current) in an exemplary embodiment of the present specification. FIG5 is a diagram illustrating the cause of delay time according to an exemplary embodiment of the present specification. FIG6 is a diagram illustrating the necessity of a frequency control method according to an exemplary embodiment of the present specification. FIG7 is a diagram illustrating a frequency control method according to an exemplary embodiment of the present specification. FIG8 is a diagram illustrating various examples of a wave representing a virtual signal according to an exemplary embodiment of the present specification. FIG9 is a diagram illustrating the process of changing the resonant frequency in each of the various examples of a wave representing a virtual signal according to an exemplary embodiment of the present specification, and illustrating the effects of the process. FIG10 is a diagram illustrating the discharge stabilization effect when using a capacitive mode among the various examples of a wave representing a virtual signal according to an exemplary embodiment of the present specification. Figures 11 and 12 are diagrams illustrating a method for generating an AC voltage having a frequency close to the resonant frequency of a variable load according to an exemplary embodiment of the present specification. Figures 13 and 14 are diagrams illustrating the effects of the above-described method for generating an AC voltage having a frequency close to the resonant frequency of a variable load according to an exemplary embodiment of the present specification. Figures 15 and 20 are diagrams illustrating a method for generating an AC voltage having a frequency close to the resonant frequency of a variable load according to another exemplary embodiment of the present specification. Figure 21 is a diagram illustrating the effects of the above-described method for generating an AC voltage having a frequency close to the resonant frequency of a variable load according to another exemplary embodiment of the present specification. 1300: Inverter 1310, 1320: Node 1400:Sensor module 1500: Controller 1510: Processor 1530: Current Detector 1550: Frequency determination unit 1570: Control signal output unit C res :capacitance i RF :Load output current L eff :inductance R eff:resistance S1: First switch S2: Second switch S3: The third switch S4: The fourth switch V DD :Input voltage V RF :Output voltage

Claims

1. A frequency control device for controlling the frequency of an AC voltage applied to a load based on the time-varying resonant frequency of the load, the frequency control device comprising: An inverter, electrically connected between the load and a DC power supply, is configured to apply the AC voltage to the load, wherein the inverter has at least two switches configured to convert the DC voltage into the AC voltage, wherein the AC voltage has a frequency determined by the operation of the at least two switches; and a controller having a processor, the controller generating a control signal based on a clock cycle of the processor to control the operation of the at least two switches, wherein the controller is configured to: output a wave of a first control signal to control the at least two switches such that a first AC voltage having a first frequency is applied to the load during a first time period; offset the wave of the first control signal by a predetermined time to generate a wave of a virtual signal corresponding to the first frequency; determine, based on the clock cycle, a delay time between the wave of the virtual signal and the wave of the output current of the inverter during at least a portion of the first time period; determine a second frequency based on (i) the first frequency, (ii) the delay time, and (iii) at least one possible output frequency that can be determined using the clock cycle; and output a wave of a second control signal to control the at least two switches such that a second AC voltage having the second frequency is applied to the load during a second time period immediately following the first time period. The predetermined time for the wave used to generate the virtual signal is set in the frequency control device based on the propagation delay between the input of the wave of the first control signal to the inverter and the output of the first AC voltage generated by the wave of the first control signal from the inverter.

2. The frequency control device of claim 1, wherein the controller is configured to, in determining the delay time: determine the delay time as the difference between a first count value and a second count value, the first count value being obtained by counting a first time length from the rising edge of the wave of the virtual signal to the first falling edge of the wave of the virtual signal after the rising edge, according to the clock of the processor, and wherein the second count value is obtained by counting a second time length from the rising edge of the wave of the virtual signal to the first falling edge of the wave of the output current after the rising edge, according to the clock of the processor.

3. The frequency control device as claimed in claim 1, wherein when the delay time is greater than a first value, the second frequency increases from the first frequency, wherein when the delay time is less than a second value, the second frequency decreases from the first frequency, wherein when the delay time has a value between the first value and the second value, the second frequency is the same as the first frequency, and wherein the first value and the second value are the same as or different.

4. The frequency control device as claimed in claim 1, wherein the predetermined time is configured to be the same as the propagation delay.

5. The frequency control device as claimed in claim 1, wherein the predetermined time is configured to be less than or greater than the propagation delay.

6. The frequency control device as claimed in claim 1, wherein the controller is configured to: determine the second frequency based on multiplying the difference between the first frequency and a frequency adjacent to the first frequency among the at least one possible output frequency by a factor, wherein the factor is determined based on the delay time.

7. The frequency control device as claimed in claim 1, wherein the controller is configured to: determine the delay time based on the average of the last N delay times among a plurality of delay times between the wave of the output current and the wave of the virtual signal, both the wave of the output current and the wave of the virtual signal being available during the first time period.

8. The frequency control device of claim 1, wherein the controller is configured to: when the second frequency is not included in the at least one possible output frequency: determine the difference between the second frequency and each of a plurality of possible output frequencies closest to the second frequency, and output a plurality of third control signals corresponding to each of the plurality of possible output frequencies instead of the second control signal based on an output count of each of the plurality of possible output frequencies, wherein the output count is determined based on a ratio between the differences.

9. The frequency control device as claimed in claim 8, wherein the controller is configured to: output the plurality of third control signals such that the deviation between the plurality of third control signals is uniformly distributed according to the output count of each of the plurality of possible output frequencies.

10. A frequency control method, wherein a frequency control device controls the frequency of an AC voltage applied to a load based on a time-varying resonant frequency of the load, the frequency control method comprising: The wave of the output first control signal is controlled such that a first AC voltage having a first frequency is applied to the load during a first time period; the wave of the first control signal is offset by a predetermined time to generate a wave of a virtual signal corresponding to the first frequency; based on the clock of the frequency control device, a delay time between the wave of the virtual signal and the wave of the output current of the inverter is determined in at least a portion of the first time period; a second frequency is determined based on (i) the first frequency, (ii) the delay time and (iii) at least one possible output frequency that can be determined using the clock; and the wave of the output second control signal is controlled such that a second AC voltage having the second frequency is applied to the load during a second time period immediately following the first time period, wherein the predetermined time for generating the wave of the virtual signal is set in the frequency control device based on the propagation delay from the input of the wave of the first control signal to the inverter to the output of the first AC voltage generated by the wave of the first control signal from the inverter.

11. The frequency control method of claim 10, wherein determining the delay time comprises: determining the delay time as the difference between a first count value and a second count value, wherein the first count value is obtained by counting a first time length from the rising edge of the wave of the virtual signal to the first falling edge of the wave of the virtual signal after the rising edge, according to the clock of the processor, and wherein the second count value is obtained by counting a second time length from the rising edge of the wave of the virtual signal to the first falling edge of the wave of the output current after the rising edge, according to the clock of the processor.

12. The frequency control method of claim 10, wherein when the delay time is greater than a first value, the second frequency increases from the first frequency, wherein when the delay time is less than a second value, the second frequency decreases from the first frequency, wherein when the delay time has a value between the first value and the second value, the second frequency is the same as the first frequency, and wherein the first value and the second value are the same as or different.

13. The frequency control method as described in claim 10, wherein the predetermined time is configured to be the same as the propagation delay.

14. The frequency control method as described in claim 10, wherein the predetermined time is configured to be less than or greater than the propagation delay.

15. The frequency control method as claimed in claim 10, wherein determining the second frequency includes: The second frequency is determined by multiplying the difference between the first frequency and a frequency adjacent to the first frequency among the at least one possible output frequency by a factor, wherein the factor is determined based on the delay time.

16. The frequency control method as claimed in claim 10, wherein determining the delay time includes: The delay time is determined based on the average of the last N delay times among a plurality of delay times between the wave of the output current and the wave of the virtual signal, both of which can be obtained during the first time period.

17. The frequency control method as claimed in claim 10, wherein the frequency control method further comprises: When the second frequency is not included in the at least one possible output frequency: determine the difference between each of the plurality of possible output frequencies closest to the second frequency and the second frequency, and output a plurality of third control signals corresponding to each of the plurality of possible output frequencies instead of the second control signal based on the output count of each of the plurality of possible output frequencies, wherein the output count is determined based on the ratio between the differences.

18. The frequency control method as claimed in claim 17, wherein outputting the plurality of third control signals includes: The plurality of third control signals are output such that the deviations between the plurality of third control signals are uniformly distributed according to the output count of each of the plurality of possible output frequencies.

Images