Display device

Abstract

A display device is provided. One embodiment of the display device includes a plurality of sub-pixels, a plurality of data lines connected to each of the plurality of sub-pixels, and a multiplexer (MUX) circuit connected to a pair of adjacent data lines. The multiplexer circuit includes a charging transistor connected to each pair of data lines and a discharging transistor connected to each pair of data lines. Therefore, the multiplexer circuit includes a discharging transistor to discharge the voltage of the data lines to reduce or minimize abnormal driving faults of sub-pixels connected to a portion of the data lines.

Description

Technical Field

[0001] The present disclosure relates to a display device, and in particular to a display device using a light emitting diode (LED). Prior Art

[0002] Display devices used in computer monitors, TVs, mobile phones, etc. include organic light emitting display (OLED) devices that emit light on their own, and liquid crystal display (LCD) devices that require an independent light source.

[0003] Display devices have been widely used in devices such as computer monitors, TVs, and personal mobile devices, and research has been conducted on the display devices to ensure reduction in size and weight as well as to have a wide display area.

[0004] In recent years, display devices including LEDs have attracted significant attention as next-generation display devices. LEDs are made of inorganic rather than organic materials, ensuring superior reliability and a longer lifespan than liquid crystal displays or organic light-emitting diodes. Furthermore, LEDs offer excellent luminous efficiency, superior shock resistance, and reliability, along with fast lighting speeds and the ability to display high-brightness images. Summary of the Invention

[0005] Various embodiments of the present disclosure provide a display device that can alternately drive a pair of sub-pixels that emit light of the same color.

[0006] Various embodiments of the present disclosure provide a display device that can alternately drive a plurality of sub-pixels by using a multiplexer (MUX) circuit.

[0007] Various embodiments of the present disclosure provide a display device that can ensure that a data driver has a simplified structure.

[0008] Various embodiments of the present disclosure provide a display device in which the number of data pads can be reduced.

[0009] Various embodiments of the present disclosure provide a display device in which the number of data pads can be reduced, thereby reducing the number of channels, and ensuring a simplified structure of a data driver.

[0010] Various embodiments of the present disclosure provide a display device that can ensure a simplified structure of a data driver and a simplified structure of multiple data pads, thereby reducing costs.

[0011] Various embodiments of the present disclosure provide a display device that can discharge the voltage of a data line connected to a sub-pixel that is not driven during a non-driving period, thereby reducing or minimizing abnormal driving failures of the sub-pixel.

[0012] Various embodiments of the present disclosure provide a display device that can reduce or minimize non-luminous failures of some sub-pixels in low-level images.

[0013] Various embodiments of the present disclosure provide a display device in which another component can be disposed in an empty space between a data line and a data pad that are not connected to a multiplexer circuit, thereby effectively utilizing the surface area of ​​a non-active region.

[0014] The technical effects of the present invention are not limited to the aforementioned effects, and other effects not mentioned above can be clearly understood by those with ordinary knowledge in the field from the following description.

[0015] According to one aspect of the present disclosure, a display device includes a plurality of sub-pixels, a plurality of data lines connected to each of the plurality of sub-pixels, and a multiplexer circuit connected to a pair of adjacent data lines among the plurality of data lines. The multiplexer circuit includes a charge transistor connected to each pair of data lines and a discharge transistor connected to each pair of data lines. Therefore, the multiplexer circuit includes a discharge transistor for discharging the voltage of the data lines, thereby reducing or minimizing abnormal driving failures of sub-pixels connected to some of the data lines.

[0016] According to another aspect of the present disclosure, a display device includes a substrate configured to include an active region and an inactive region, a plurality of data lines configured to extend from the inactive region to the active region, a plurality of data pads disposed in the inactive region, and a plurality of multiplexer circuits disposed in the inactive region and connected between the data lines and the data pads. Each of the multiplexer circuits includes a plurality of first charging transistors connected to a portion of the plurality of data lines, a plurality of second charging transistors connected to the remaining portion of the plurality of data lines, a plurality of first discharging transistors connected to some of the data lines, and a plurality of second discharging transistors connected to the remaining data lines. The plurality of first charging transistors and the plurality of first discharging transistors are turned on in different cycles, and the plurality of second charging transistors and the plurality of second discharging transistors are turned on in different cycles. Thus, the multiplexer circuits can be used to alternately drive a plurality of sub-pixels connected to some of the data lines and a plurality of sub-pixels connected to the remaining data lines.

[0017] Additional details of exemplary embodiments are included in the detailed description and drawings.

[0018] According to the present disclosure, the display device can alternately drive a pair of sub-pixels that emit light of the same color.

[0019] According to the present disclosure, the display device can alternately drive multiple sub-pixels by using a multiplexer circuit.

[0020] According to the present disclosure, the display device can ensure a simplified structure of the data driver.

[0021] According to the present disclosure, the display device can have a simplified structure with a reduced number of data pads.

[0022] According to the present disclosure, the display device can reduce the number of channels by reducing the number of data pads, and ensure a simplified structure and low cost of the data driver.

[0023] According to the present disclosure, the display device can reduce or minimize abnormal driving failures of sub-pixels by discharging the voltage of the data line.

[0024] According to the present disclosure, the display device can reduce the failure of some sub-pixels not emitting light in low-level images.

[0025] According to the present disclosure, such a display device can enable another component to be arranged in the blank space between the data line and the data pad that are not connected to the multiplexer circuit, so as to effectively utilize the surface area of ​​the non-active region.

[0026] The effects of the present disclosure are not limited to the aforementioned examples, and more various effects are included in this specification. Simple diagram description

[0027] The foregoing and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which: Figure 1 is a schematic diagram of a display device according to an embodiment; Figure 2 is a schematic block diagram of a sub-pixel and a multiplexer circuit MUX of a display device according to one embodiment; Figure 3 is an exemplary circuit diagram of a sub-pixel of a display device according to one embodiment; Figure 4 is another exemplary circuit diagram of a sub-pixel of a display device according to one embodiment; Figure 5 is a circuit diagram of a multiplexer circuit of a display device according to an embodiment; Figure 6 is a driving timing diagram of a multiplexer circuit of a display device according to an embodiment; Figure 7 is a schematic plan view of a multiplexer circuit of a display device according to an embodiment; FIG8 is a cross-sectional diagram of a multiplexer circuit of a display device according to an embodiment; and FIG. 9 is a block diagram of a sub-pixel and a multiplexer circuit of a display device according to another embodiment. Implementation Method

[0028] The following examples are explained with reference to the accompanying drawings to provide a clearer understanding of the advantages and features of the present disclosure, as well as methods for achieving these advantages and features. However, the present disclosure is not limited to the following examples and can be implemented in a variety of different forms. These exemplary embodiments are provided solely by way of illustration to enable those skilled in the art to fully understand the scope of the present disclosure.

[0029] The shapes, sizes, proportions, angles, and quantities used in the drawings to describe the embodiments of the present disclosure are merely examples and are not intended to limit the present disclosure. Throughout this specification, identical reference symbols generally denote identical elements. Furthermore, when describing the present disclosure, detailed descriptions of conventional technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. When words such as "including," "having," and "comprising" are used in this specification, additional components may be included unless "only" is used. Components listed in the singular include the plural unless otherwise expressly stated.

[0030] Even if not explicitly stated, components are interpreted as including ordinary margins of error.

[0031] When describing a positional relationship, for example, when the positional relationship between two components is described as "on," "above," "below," "next to," etc., unless "immediately" or "directly" is used, one or more other components may exist between the two components.

[0032] When an element or layer is referred to as being “on” another element or layer, the other element or layer may be directly on or between the other element or layer.

[0033] When a first element is referred to as being "connected or coupled," "contacting or overlapping," etc., with a second element, it should be understood that the first and second elements can not only be "directly connected or coupled," "directly contacting or overlapping," but also that a third element can be "interposed" between the first and second elements, or that the first and second elements can be "connected or coupled," "contacting or overlapping," etc., with each other through a fourth element. Here, the second element may be included in at least one of the two or more elements that are "connected or coupled," "contacting or overlapping," etc., with each other.

[0034] Although terms such as "first" and "second" are used to describe various components, these components are not limited by these terms. These terms are simply used to distinguish one component from other components. Therefore, the first component mentioned below can also be the second component in the technical concept of this disclosure.

[0035] The features of the various embodiments disclosed herein may be partially or completely joined or combined with each other, and may be technically related and operated in various ways, and the various embodiments may be implemented independently or in conjunction with each other.

[0036] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the drawings.

[0037] FIG1 is a schematic diagram of a display device according to an embodiment of the present invention. In FIG1 , among various components of the display device 100 , a display panel PN, a gate driver GD, a data driver DD, and a timing controller TC are shown for ease of description only.

[0038] 1 , a display device 100 includes a display panel PN including a plurality of sub-pixels SP, a gate driver GD and a data driver DD for providing various types of signals to the display panel PN, and a timing controller TC for controlling the gate driver GD and the data driver DD.

[0039] The gate driver GD provides multiple scan signals to the multiple scan lines SL based on multiple gate control signals provided by the timing controller TC. In Figure 1 , one gate driver GD is positioned on one side of the display panel PN, with a gap between the gate driver GD and the display panel PN. However, the number and arrangement of gate drivers GD are not limited to this.

[0040] Based on a plurality of data control signals provided by the timing controller TC, the data driver DD converts the image data input from the timing controller TC into data voltages using reference gamma voltages. The data driver DD can then provide the converted data voltages to a plurality of data lines DL.

[0041] The display panel PN, which displays images to a user, includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL intersect with each other, and each of the plurality of sub-pixels SP is connected to a scan line SL and a data line DL. Furthermore, although not shown in the figure, each of the plurality of sub-pixels SP can be connected to a high-potential power line VDD, a low-potential power line VSS, a reference line RL, and the like.

[0042] In the display panel PN, an active area AA and a non-active area NA surrounding the active area AA are defined.

[0043] The active area AA is the area of ​​the display device 100 that displays images. Multiple sub-pixels SP, which constitute multiple pixels, and circuits for driving the sub-pixels SP may be disposed within the active area AA. The sub-pixels SP are the smallest unit constituting the active area AA, with n sub-pixels SP constituting one pixel. Within each of the sub-pixels SP, a light-emitting diode 130 and a thin-film transistor (TFT) for driving the light-emitting diode 130 may be disposed. Depending on the type of display panel PN, the number of light-emitting diodes 130 may be defined in different ways. For example, if the display panel PN is an inorganic light-emitting display panel PN, the light-emitting diode 130 may be a light-emitting diode (LED) or a micro light-emitting diode (LED).

[0044] In the active area AA, multiple lines are provided to provide various types of signals to the multiple sub-pixels SP. For example, these lines may include multiple data lines DL that provide data voltages to each of the multiple sub-pixels SP, multiple scan lines SL that provide scan signals to each of the multiple sub-pixels SP, and the like. The multiple scan lines SL may extend in one direction and connect to the multiple sub-pixels SP in the active area AA, while the multiple data lines DL may extend in a direction different from the one direction and connect to the multiple sub-pixels SP in the active area AA. Furthermore, a low-potential power line VSS and a high-potential power line VDD may be further provided in the active area AA, but the present disclosure is not limited thereto.

[0045] The non-active area NA is defined as a region extending from the active area AA and is a non-image display area. Connecting lines and pad electrodes for providing signals to the sub-pixels SP or driver integrated circuits (ICs), such as gate driver ICs and data driver ICs, in the active area AA may be provided in the non-active area NA.

[0046] However, the non-active area NA may be placed on the back side of the display panel PN, ie, on a surface without the sub-pixels SP, or may be omitted, and may not be limited to the area shown in the drawings.

[0047] Furthermore, drivers such as the gate driver GD, data driver DD, and timing controller TC can be connected to the display panel PN in various ways. For example, the gate driver GD can be installed in the non-active area NA using a gate-in-panel (GIP) method, or installed between multiple sub-pixels SP in the active area AA using a gate-in-active (GIA) method.

[0048] For example, the data driver DD and the timing controller TC may be formed on separate flexible films and printed circuit boards, and the flexible films and printed circuit boards may be bonded to pad electrodes formed in the non-active area NA of the display panel PN, so that the data driver DD and the timing controller TC may be electrically connected to the display panel PN.

[0049] In addition, when the gate driver GD is mounted based on the GIP method and the data driver DD and the timing controller TC provide signals to the display panel PN through the pad electrodes of the non-active area NA, a predetermined level or larger surface area of ​​the non-active area NA is required to arrange the gate driver GD and the pad electrodes, and the frame may be increased accordingly.

[0050] In another example, by mounting the gate driver GD in the active area AA using the GIA method and forming side traces SRL for connecting to signal traces on the front surface of the display panel PN with pad electrodes on the rear surface of the display panel PN, the flexible film and printed circuit board can be bonded to the rear surface of the display panel PN. This reduces or minimizes the non-active area NA on the front surface of the display panel PN. In other words, when the gate driver GD, data driver DD, and timing controller TC are connected to the display panel PN in the aforementioned manner, a zero-bezel design can be achieved, essentially eliminating any borders.

[0051] 2 to 4 , a sub-pixel SP of the display device 100 according to an embodiment will be described in detail.

[0052] Figure 2 is a block diagram of a sub-pixel and a multiplexer circuit MUX of a display device according to an embodiment. Figure 3 is an exemplary circuit diagram of a sub-pixel of a display device according to an embodiment. Figure 4 is another exemplary circuit diagram of a sub-pixel of a display device according to an embodiment.

[0053] 2 , the plurality of sub-pixels SP may include a plurality of first sub-pixels SP1, a plurality of second sub-pixels SP2, and a plurality of third sub-pixels SP3. For example, the first sub-pixels SP1 may be red sub-pixels SP, the second sub-pixels SP2 may be green sub-pixels SP, and the third sub-pixels SP3 may be blue sub-pixels SP, but the present disclosure is not limited thereto.

[0054] A pair of first sub-pixels SP1 may be adjacent to each other, a pair of second sub-pixels SP2 may be adjacent to each other, and a pair of third sub-pixels SP3 may be adjacent to each other. Therefore, in the same column, the pair of first sub-pixels SP1, the pair of second sub-pixels SP2, and the pair of third sub-pixels SP3 may be consecutively arranged.

[0055] Each of the multiple sub-pixels SP includes a pixel circuit PC and a light-emitting diode 130. The pixel circuit PC, which drives the light-emitting diode 130, can include multiple transistors and multiple capacitors. The pixel circuit PC can be connected to various lines, such as a scan line SL, a data line DL, a high-voltage power line VDD, a low-voltage power line VSS, and a light-emission control signal line EL, and receives signals from these lines to drive the pixel circuit PC. The pixel circuit PC supplies a driving current to the light-emitting diode 130, thereby causing the light-emitting diode 130 to emit light.

[0056] The light-emitting diode 130 receives a driving current from the pixel circuit PC and emits light. For example, the light-emitting diode 130 may be a micro light-emitting diode (LED) or a light-emitting diode. The light-emitting diode 130 may be connected between the pixel circuit PC and a high-voltage power line VDD, or between the pixel circuit PC and a low-voltage power line VSS.

[0057] The light-emitting diode 130 includes a first light-emitting diode 130R, a second light-emitting diode 130G, and a third light-emitting diode 130B. The first light-emitting diode 130R can be disposed in the first sub-pixel SP1, the second light-emitting diode 130G can be disposed in the second sub-pixel SP2, and the third light-emitting diode 130B can be disposed in the third sub-pixel SP3. For example, the first light-emitting diode 130R can be a red light-emitting diode, the second light-emitting diode 130G can be a green light-emitting diode, and the third light-emitting diode 130B can be a blue light-emitting diode, but the present disclosure is not limited thereto.

[0058] Furthermore, data lines DL are connected to each of the plurality of sub-pixels SP. The data lines DL include a first data line DL1, a second data line DL2, and a third data line DL3. For example, the first data line DL1 may be connected to the first sub-pixel SP1, the second data line DL2 may be connected to the second sub-pixel SP2, and the third data line DL3 may be connected to the third sub-pixel SP3.

[0059] The first data lines DL1 may include a 1-1 data line DL1a connected to one of a pair of adjacent first sub-pixels SP1 and a 1-2 data line DL1b connected to the other of the pair of adjacent first sub-pixels SP1. The second data lines DL2 may include a 2-1 data line DL2a connected to one of a pair of adjacent second sub-pixels SP2 and a 2-2 data line DL2b connected to the other of the pair of adjacent second sub-pixels SP2. The third data lines DL3 may include a 3-1 data line DL3a connected to one of a pair of adjacent third sub-pixels SP3 and a 3-2 data line DL3b connected to the other of the pair of adjacent third sub-pixels SP3.

[0060] Furthermore, when using micro-LEDs as the light-emitting diodes 130, multiple micro-LEDs are formed on a wafer and transferred to the substrate of the display panel PN to form the display device 100. However, during the process of transferring the multiple micro-LEDs, each having a small size, from the wafer to the display panel PN, failures may occur, such as failures of untransferred micro-LEDs or failures of micro-LEDs being transferred out of their proper positions due to misalignment, leading to failures in sub-pixels SP. Therefore, to account for failures during the transfer of micro-LEDs, light-emitting diodes 130 emitting the same color are transferred to a pair of sub-pixels SP, and the pair of light-emitting diodes 130 are alternately driven to prepare for sub-pixel SP failures. For example, even if either of the pair of sub-pixels SP, each including a light-emitting diode 130, fails, the other sub-pixel SP can be driven normally for at least a portion of the driving cycle, compensating for the defective sub-pixel SP and preventing the defective sub-pixel SP from being detected.

[0061] One of the LEDs 130 in a pair of sub-pixels SP can be defined as a main LED 130, while the other LED 130 can be defined as a redundant LED 130. The redundant LED 130 can be a spare LED 130 that is additionally transferred for use in the event that the main LED 130 fails. Even if the main LED 130 is not transferred or is not transferred to its correct position due to an alignment error, the redundant LED 130 can still emit light normally. Therefore, the main LED 130 and the redundant LED 130 are arranged together, thereby reducing or minimizing display quality degradation caused by failure of the main LED 130 or the redundant LED 130.

[0062] For example, referring to FIG2 , one of the first light-emitting diodes 130R in the pair of first sub-pixels SP1 can be defined as the main first light-emitting diode 130R, and the other can be defined as the redundant first light-emitting diode 130R. One of the second light-emitting diodes 130G in the pair of second sub-pixels SP2 can be defined as the main second light-emitting diode 130G, and the other can be defined as the redundant second light-emitting diode 130G. One of the third light-emitting diodes 130B in the pair of third sub-pixels SP3 can be defined as the main third light-emitting diode 130B, and the other can be defined as the redundant third light-emitting diode 130B.

[0063] In the display device 100 of one embodiment, a multiplexer circuit MUX can be connected to a pair of data lines DL connected to a pair of sub-pixels SP that emit light of the same color, thereby alternately driving the main LED (LED 130) and the redundant LED (LED 130) in each of the sub-pixels SP. Therefore, since the multiplexer circuit MUX is connected to the pair of data lines DL, the main LED (LED 130) and the redundant LED (LED 130) can be alternately driven. Even if one of the main LED (LED 130) and the redundant LED (LED 130) fails, either of the main LED (LED 130) and the redundant LED (LED 130) can be driven normally in another driving cycle.

[0064] A multiplexer circuit MUX connected to the data lines DL is disposed in the display panel PN. The multiplexer circuit MUX can be connected between a data pad DP and a pair of data lines DL. In this case, the data pad DP is a pad electrically connected to the data driver DD and receives a data voltage. The data pad DP can be formed in the non-active area NA of the display panel PN. Alternatively, the multiplexer circuit MUX can be formed together with the data pad DP in the non-active area NA. The multiplexer circuit MUX can selectively provide a data voltage supplied from a data pad DP to one of the pair of data lines DL. The multiplexer circuit MUX can electrically connect only one of the pair of data lines DL to the data pad DP.

[0065] For example, a pair of first data lines DL1 connected to a pair of adjacent first sub-pixels SP1 can be connected to the same multiplexer circuit MUX, a pair of second data lines DL2 connected to a pair of adjacent second sub-pixels SP2 can be connected to the same multiplexer circuit MUX, and a pair of third data lines DL3 connected to a pair of adjacent third sub-pixels DL3 can be connected to the same multiplexer circuit MUX. The 1-1 data line DL1a and the 1-2 data line DL1b can be connected to the same multiplexer circuit MUX, the 2-1 data line DL2a and the 2-2 data line DL2b can be connected to the same multiplexer circuit MUX, and the 3-1 data line DL3a and the 3-2 data line DL3b can be connected to the same multiplexer circuit MUX.

[0066] The multiplexer circuit MUX can provide a data voltage to any one of the pair of first data lines DL1, and accordingly, any one of the pair of adjacent first sub-pixels SP1 can be driven. The multiplexer circuit MUX can provide a data voltage to any one of the pair of second data lines DL2, and accordingly, any one of the pair of adjacent second sub-pixels SP2 can be driven. The multiplexer circuit MUX can provide a data voltage to any one of the pair of third data lines DL3, and accordingly, any one of the pair of adjacent third sub-pixels SP3 can be driven.

[0067] The pair of first sub-pixels SP1 can be driven at different cycles via the multiplexer circuit MUX. Similarly, the pair of second sub-pixels SP2 can be driven at different cycles, and the pair of third sub-pixels SP3 can be driven at different cycles. For example, the pair of first sub-pixels SP1 can be driven alternately based on a frame unit, the pair of second sub-pixels SP2 can be driven alternately based on a frame unit, and the pair of third sub-pixels SP3 can be driven alternately based on a frame unit. Thus, the pair of sub-pixels SP can be driven alternately using the multiplexer circuit MUX.

[0068] Furthermore, as previously described, when the first LEDs 130R of the pair of first sub-pixels SP1 are defined as a main first LED 130R and a redundant first LED 130R, respectively, the main first LED 130R can be driven in the Nth frame via the multiplexer circuit MUX, while the redundant first LED 130R can be driven in the N+1th frame. In other words, the main first LED 130R and the redundant first LED 130R can be alternately driven on a frame-by-frame basis. If a failure occurs in the main first LED 130R, the redundant first LED 130R, which is normally driven in the N+1th frame, can be used to reduce or minimize the recognition of the failure of the main first LED 130R in the Nth frame. Similarly, since the second light-emitting diode 130G of the pair of second sub-pixels SP2 and the third light-emitting diode 130B of the pair of third sub-pixels SP3 are alternately driven based on the frame unit, even if the second sub-pixel SP2 and the third sub-pixel SP3 fail, the failure can be compensated, thereby making the failure unrecognizable.

[0069] The multiplexer circuit MUX may include a plurality of transistors to provide a data voltage to only one of the pair of data lines DL. The multiplexer circuit MUX will be described in detail below with reference to FIG. 5 and FIG. 6 .

[0070] In addition, the pixel circuit PC of the sub-pixel SP can be composed of various types of circuits including multiple transistors and multiple capacitors. An exemplary circuit of the pixel circuit PC according to one embodiment is described below with reference to FIG3 and FIG4.

[0071] 3 , each of the plurality of sub-pixels SP includes a pixel circuit PC and a light-emitting diode 130 connected to the pixel circuit. For example, the exemplary pixel circuit PC of each of the plurality of sub-pixels SP may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0072] Each of the first transistor T1 , the second transistor T2 , the third transistor T3 , the fourth transistor T4 , the fifth transistor T5 , the sixth transistor T6 , and the seventh transistor T7 of the pixel circuit PC includes a gate electrode, a source electrode, and a drain electrode.

[0073] The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can be either N-type transistors or P-type transistors. In the case of an N-type transistor, since electrons are current carriers, electrons can flow from the source electrode to the drain electrode, and current can flow from the drain electrode to the source electrode. In the case of a P-type transistor, since holes are current carriers, holes can flow from the source electrode to the drain electrode, and current can flow from the source electrode to the drain electrode. For example, one of the multiple transistors can be an N-type transistor, while another of the multiple transistors can be a P-type transistor.

[0074] In the following, it is assumed that the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 are N-type transistors, but these transistors are not limited thereto.

[0075] The first transistor T1 includes a first gate electrode, a first source electrode, and a first drain electrode. The first gate electrode is connected to the first scan line SL1, the first source electrode is connected to the data line DL, and the first drain electrode is connected to the first node N1. The first transistor T1 can provide a data voltage from the data line DL to the first node N1 based on a scan signal from the first scan line SL1. Therefore, the first transistor T1 configured to provide a data voltage to the sub-pixel SP can also be referred to as a switching transistor.

[0076] At this time, the first transistor T1 of the first sub-pixel SP1 can be connected to the first data line DL1, the first transistor T1 of the second sub-pixel SP2 can be connected to the second data line DL2, and the first transistor T1 of the third sub-pixel SP3 can be connected to the third data line DL3.

[0077] The second transistor T2 includes a second gate electrode, a second source electrode, and a second drain electrode. The second gate electrode is connected to the first scan line SL1, the second source electrode is connected to the second node N2, and the second drain electrode is connected to the third node N3. The second transistor T2 can short-circuit the sixth gate electrode and the sixth drain electrode of the sixth transistor T6, thereby forming a diode connection of the sixth transistor T6. A diode connection means short-circuiting the gate electrode to the source electrode or the drain electrode, causing the transistor to operate as a diode. In this case, the second transistor T2 can be implemented as an oxide semiconductor transistor with a low off-current, reducing or minimizing current leakage from the sixth gate electrode of the sixth transistor T6.

[0078] The third transistor T3 includes a third gate electrode, a third source electrode, and a third drain electrode. The third gate electrode is connected to the light-emission control signal line EL, the third source electrode is connected to the reference line RL, and the third drain electrode is connected to the first node N1. Based on the light-emission control signal on the light-emission control signal line EL, the third transistor T3 can provide a reference voltage from the reference line RL to the first node N1.

[0079] The fourth transistor T4 includes a fourth gate electrode, a fourth source electrode, and a fourth drain electrode. The fourth gate electrode is connected to the light-emission control signal line EL, the fourth source electrode is connected to the third node N3, and the fourth drain electrode is connected to the low-potential power line VSS. The fourth transistor T4 can electrically connect the third node N3 to the low-potential power line VSS in response to the light-emission control signal EL, thereby allowing a driving current to flow from the high-potential power line VDD to the low-potential power line VSS.

[0080] The fifth transistor T5 includes a fifth gate electrode, a fifth source electrode, and a fifth drain electrode. The fifth gate electrode is connected to the second scan line SL2, the fifth source electrode is connected to the reference line RL, and the fifth drain electrode is connected to the third node N3. The fifth transistor T5 can provide a reference voltage to the third node N3 based on the scan signal of the second scan line SL2 and reset the third node N3, i.e., the sixth drain electrode of the sixth transistor T6, to the reference voltage.

[0081] The sixth transistor T6 includes a sixth gate electrode, a sixth source electrode, and a sixth drain electrode. The sixth gate electrode is connected to the second node N2, the sixth source electrode is connected to the fourth node N4, and the sixth drain electrode is connected to the third node N3. The sixth transistor T6 can be turned on to control the driving current flowing through the light-emitting diode 130. Accordingly, the sixth transistor T6, which controls the driving current provided to the light-emitting diode 130, can be defined as a driving transistor.

[0082] The seventh transistor T7 includes a seventh gate electrode, a seventh source electrode, and a seventh drain electrode. The seventh gate electrode is connected to the first scan line SL1, the seventh source electrode is connected to the high-potential power line VDD, and the seventh drain electrode is connected to the fourth node N4. The seventh transistor T7 can provide a high-potential power voltage to the fourth node N4 based on the scan signal of the first scan line SL1 and prevent the light-emitting diode 130 from emitting light during the data voltage charging period.

[0083] The first capacitor C1 includes a capacitor electrode connected to a first node N1 and a capacitor electrode connected to a second node N2. The first capacitor C1 can utilize its coupling characteristics to adjust the voltage at the second node N2, thereby maintaining a constant voltage supplied to the sixth gate electrode of the sixth transistor T6 and emitting light from the light-emitting diode 130 while maintaining a constant driving current.

[0084] The second capacitor C2 includes a capacitor electrode connected to the second node N2 and a capacitor electrode connected to the fourth node N4. In other words, the second capacitor C2 is connected between the sixth gate electrode and the sixth source electrode of the sixth transistor T6, that is, between the sixth gate electrode and the first electrode of the light-emitting diode 130.

[0085] Furthermore, when the voltage at the first node N1 changes, the voltage at the second node N2 can also change. In this case, the second capacitor C2, connected in series with the first capacitor C1, can be coupled to the first capacitor C1 and, based on the capacitance ratio between the first capacitor C1 and the second capacitor C2, can shift the voltage at the first node N1 to the voltage at the second node N2. Therefore, the transfer rate of the data voltage from the first node N1 to the second node N2 is reduced by the second capacitor C2. Furthermore, if the light-emitting diode 130 is composed of micro-LEDs with a large IV curve gradient, the second capacitor C2 can be used to reduce the data voltage transfer rate to display finer gradations.

[0086] The third capacitor C3 includes a capacitor electrode connected to the fourth node N4 and a capacitor electrode connected to the high-potential power line VDD. In other words, the third capacitor C3 includes a capacitor electrode connected to the first electrode and the second electrode of the light-emitting diode 130. The third capacitor C3 can increase the inherent capacitance of the light-emitting diode 130, thereby emitting higher brightness light from the light-emitting diode 130.

[0087] The light emitting diode 130 includes a first electrode connected to the high potential power line VDD and a second electrode connected to the fourth node N4. The light emitting diode 130 can be connected between the high potential power line VDD and the sixth transistor T6.

[0088] 4 , another exemplary pixel circuit PC for each of the plurality of sub-pixels SP may further include an eighth transistor T8, and except for the connection structure of the fifth transistor T5, this exemplary pixel circuit PC may be the same as the exemplary pixel circuit PC in FIG3 . For example, another exemplary pixel circuit PC may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a first capacitor C1, a second capacitor C2, and a third capacitor C3.

[0089] The eighth transistor T8 includes an eighth gate electrode, an eighth source electrode, and an eighth drain electrode. The eighth gate electrode is connected to the second scan line SL2, the eighth source electrode is connected to the data line DL, and the eighth drain electrode is connected to the first node N1. The eighth transistor T8 can provide a data voltage to the first node N1 based on a scan signal from the second scan line SL2. The eighth transistor T8 is configured to partially charge the first capacitor C1 with the data voltage when initializing the voltage of the sixth gate electrode of the sixth transistor T6, which is a driving transistor. Although the eighth transistor T8 partially charges the first capacitor C1 with the data voltage, voltage variations at the sixth gate electrode can be reduced or minimized.

[0090] A fifth drain electrode of the fifth transistor T5 is connected to the second node N2. The fifth transistor T5 can provide a reference voltage to the second node N2 based on a scan signal of the second scan line SL2.

[0091] Therefore, the pixel circuit PC may include multiple transistors and multiple capacitors to provide driving current to the light-emitting diode 130. However, the pixel circuit PC may be composed of other circuits instead of the schematic circuits in Figures 3 and 4, which does not constitute a limitation of the present disclosure.

[0092] 5 and 6 , a circuit of the multiplexer circuit MUX of the display device 100 according to an embodiment will be described in detail.

[0093] Figure 5 is a circuit diagram of a multiplexer circuit of a display device according to an embodiment. Figure 6 is a driving timing diagram of a multiplexer circuit of a display device according to an embodiment.

[0094] 5 and 6, the multiplexer circuit MUX connected to a pair of data lines DL includes a first charging transistor CT1, a second charging transistor CT2, a first discharging transistor DCT1, and a second discharging transistor DCT2.

[0095] The first charging transistor CT1 and the second charging transistor CT2 are transistors used to transmit a data voltage to the data line DL. The first charging transistor CT1 and the second charging transistor CT2 can provide the data voltage to the data line DL, thereby charging the data line DL with the data voltage. One of the pair of data lines DL can be connected to the data pad DP via the first charging transistor CT1, while the other of the pair of data lines DL can be connected to the data pad DP via the second charging transistor CT2.

[0096] Furthermore, the first charging transistor CT1 and the second charging transistor CT2 can electrically connect either of the pair of data lines DL to the data pad DP during different cycles. When the first charging transistor CT1 connects the data pad DP to one data line DL, the second charging transistor CT2 can be turned off, thereby preventing the data pad DP from being connected to the other data line DL. Conversely, when the second charging transistor CT2 connects the data pad DP to the other data line DL, the first charging transistor CT1 can be turned off, thereby preventing the data pad DP from being electrically connected to the other data line DL.

[0097] The first charging transistor CT1 can be connected to one of the data lines DL in the pair of data lines DL, and the second charging transistor CT2 can be connected to the other data line DL. For example, the first charging transistor CT1 can be connected to the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a, and the second charging transistor CT2 can be connected to the 1-2 data line DL1b, the 2-2 data line DL2b, and the 3-2 data line DL3b. Furthermore, the first charging transistor CT1 can be turned on or off by a first select signal on the first select line SEL1, and the second charging transistor CT2 can be turned on or off by a second select signal on the second select line SEL2.

[0098] For example, in a multiplexer circuit MUX connected to a pair of first data lines DL1, the source and drain electrodes of the first charging transistor CT1 may be connected to the data pad DP and the 1-1 data line DL1a, respectively, while the gate electrode may be connected to the first select line SEL1. In the multiplexer circuit MUX connected to the pair of first data lines DL1, the source and drain electrodes of the second charging transistor CT2 may be connected to the data pad DP and the 1-2 data line DL1b, respectively, while the gate electrode may be connected to the second select line SEL2.

[0099] For example, in the multiplexer circuit MUX connected to the pair of second data lines DL2, the source electrode and drain electrode of the first charging transistor CT1 can be connected to the data pad DP and the 2-1 data line DL2a, respectively, while the gate electrode can be connected to the first selection line SEL1. In the multiplexer circuit MUX connected to the pair of second data lines DL2, the source electrode and drain electrode of the second charging transistor CT2 can be connected to the data pad DP and each of the 2-2 data lines DL2b, respectively, while the gate electrode can be connected to the second selection line SEL2.

[0100] For example, in a multiplexer circuit MUX connected to a pair of third data lines DL3, the source and drain electrodes of the first charging transistor CT1 can be connected to the data pad DP and the 3-1 data line DL3a, respectively, while the gate electrode can be connected to the first select line SEL1. In a multiplexer circuit MUX connected to a pair of third data lines DL3, the source and drain electrodes of the second charging transistor CT2 can be connected to the data pad DP and the 3-2 data line DL3b, respectively, while the gate electrode can be connected to the second select line SEL2.

[0101] Furthermore, multiple data lines DL can be arranged to pass through the active area AA, and these data lines DL can overlap or be connected to various components disposed in the active area AA. For example, the data lines DL can overlap or be adjacent to various lines, such as the scan lines SL and the emission control signal lines EL. Therefore, when the data lines DL overlap other components in the active area AA, a parasitic capacitor Cp is formed between the data lines DL and the other components. In this case, the data voltage charged on the DL data lines cannot be properly discharged through the parasitic capacitance of the parasitic capacitor Cp. If the data voltage on the DL data lines cannot be properly discharged, the sub-pixels SP connected to the data lines DL may abnormally emit light during periods when the sub-pixels SP are not emitting light. To prevent this, in one embodiment of the display device 100, a discharge transistor and a discharge line DCL can be connected to each of the multiple data lines DL to charge the data voltage charged in the multiple data lines DL and prevent the sub-pixels SP from malfunctioning during periods other than periods in which the sub-pixels SP are driven.

[0102] Specifically, the first discharge transistor DCT1 and the second discharge transistor DCT2 are transistors used to discharge the voltage charged into the data line DL. Each of the first discharge transistor DCT1 and the second discharge transistor DCT2 can connect the data line DL to the discharge line DCL and discharge the voltage charged into the data line DL. Either of the pair of data lines DL can be connected to the discharge line DCL via the first discharge transistor DCT1, while the other of the pair of data lines DL can be connected to the discharge line DCL via the second discharge transistor DCT2.

[0103] The first discharge transistor DCT1 can be connected to one of the pair of data lines DL, and the second discharge transistor DCT2 can be connected to the other of the pair of data lines DL. For example, the first discharge transistor DCT1 can be connected to the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a, and the second discharge transistor DCT2 can be connected to the 1-2 data line DL1b, the 2-2 data line DL2b, and the 3-2 data line DL3b. Furthermore, the first discharge transistor DCT1 can be turned on or off by a second select signal on the second select line SEL2, and the second discharge transistor DCT2 can be turned on or off by a first select signal on the first select line SEL1.

[0104] Furthermore, the first discharge transistor DCT1 and the second discharge transistor DCT2 can connect any of the data lines DL to the discharge line DCL in different cycles. When the first discharge transistor DCT1 connects the discharge line DCL to one data line DL, the second discharge transistor DCT2 can be turned off, thereby disconnecting the discharge line DCL from the other data line DL. When the second discharge transistor DCT2 connects the discharge line DCL to another data line DL, the first discharge transistor DCT1 can be turned off, thereby disconnecting the discharge line DCL from the data line DL. For example, the discharge line DCL can be a line supplied with a constant voltage, such as a low-potential power line VSS or a reference line RL, but the present disclosure is not limited thereto.

[0105] For example, in the multiplexer circuit MUX connected to the pair of first data lines DL1, the source electrode and drain electrode of the first discharge transistor DCT1 can be connected to the 1-1 data line DL1a and the discharge line DCL, respectively, while the gate electrode can be connected to the second selection line SEL2. In the multiplexer circuit MUX connected to the pair of first data lines DL1, the source electrode and drain electrode of the second discharge transistor DCT2 can be connected to the 1-2 data line DL1b and the discharge line DCL, respectively, while the gate electrode can be connected to the first selection line SEL1.

[0106] For example, in the multiplexer circuit MUX connected to the pair of second data lines DL2, the source electrode and drain electrode of the first discharge transistor DCT1 can be connected to the 2-1 data line DL2a and the discharge line DCL, respectively, while the gate electrode can be connected to the second selection line SEL2. In the multiplexer circuit MUX connected to the pair of second data lines DL2, the source electrode and drain electrode of the second discharge transistor DCT2 can be connected to the 2-2 data line DL2b and the discharge line DCL, respectively, while the gate electrode can be connected to the first selection line SEL1.

[0107] For example, in the multiplexer circuit MUX connected to the pair of third data lines DL3, the source electrode and drain electrode of the first discharge transistor DCT1 can be connected to the 3-1 data line DL3a and the discharge line DCL, respectively, while the gate electrode can be connected to the second selection line SEL2. In the multiplexer circuit MUX connected to the pair of third data lines DL3, the source electrode and drain electrode of the second discharge transistor DCT2 can be connected to the 3-2 data line DL3b and the discharge line DCL, respectively, while the gate electrode can be connected to the first selection line SEL1.

[0108] Referring to FIG. 6 , in the nth frame (Frame(n), a first select signal having an on-level may be output from the first select line SEL1, and a second select signal having an off-level may be output from the second select line SEL2. For example, if the plurality of charging transistors and the plurality of discharging transistors are P-type transistors, the first select signal may be a low-level signal having an on-level, while the second select signal may be a high-level signal having an off-level.

[0109] A first select signal having an on-level and a second select signal having an off-level can turn on the first charge transistor CT1 and turn off the second charge transistor CT2. Each of the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a can be electrically connected to the data pad DP via the on-state first charge transistor CT1. Conversely, each of the 1-2 data line DL1b, the 2-2 data line DL2b, and the 3-2 data line DL3b can be disconnected from the data pad DP via the off-state second charge transistor CT2. Therefore, the multiplexer circuits MUX can provide the data voltage for the nth frame (Frame(n)) period only from the data pad DP to the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a of the plurality of data lines DL.

[0110] During the nth frame (Frame(n)), the second discharge transistor DCT2 can be turned on and the first discharge transistor DCT1 can be turned off via a first select signal having an on level and a second select signal having an off level. The 1-2 data line DL1b, the 2-2 data line DL2b, and the 3-2 data line DL3b can each be connected to the discharge line DCL via the turned-on second discharge transistor DCT2. The voltages charged in the 1-2 data line DL1b, the 2-2 data line DL2b, and the 3-2 data line DL3b can be discharged to the discharge line DCL via the second discharge transistor DCT2. Each of the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a can be disconnected from the discharge line DCL via the turned-off first discharge transistor DCT1. Therefore, the data voltages charged in the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a can be prevented from being discharged.

[0111] Therefore, during the nth frame (Frame(n)), the first charging transistor CT1 is turned on to supply a data voltage from the data pad DP to the plurality of sub-pixels SP connected to the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a. Furthermore, during the nth frame (Frame(n), the second discharging transistor DCT2 is turned on to discharge the voltage charged in the 1-2 data line DL1b, the 2-2 data line DL2b, and the 3-2 data line DL3b, thereby controlling the sub-pixels SP connected to the 1-2 data line DL1b, the 2-2 data line DL2b, and the 3-2 data line DL3b, thereby preventing the sub-pixels SP from emitting light.

[0112] Then, for a period from the blank period (Blank) between the nth frame Frame(n) and the n+1th frame Frame(n+1) to the n+1th frame Frame(n+1), a first select signal having an off-level may be output from the first select line SEL1, and a second select signal having an on-level may be output from the second select line SEL2. For example, if the plurality of charging transistors and the plurality of discharging transistors are N-type transistors, a high-level first select signal may be provided as an off-level signal, and a low-level second select signal may be provided as an on-level signal.

[0113] A first select signal having an off-level and a second select signal having an on-level can turn off the first charge transistor CT1 and turn on the second charge transistor CT2. Each of the 1-2 data lines DL1b, 2-2 data lines DL2b, and 3-2 data lines DL3b can be electrically connected to the data pad DP via the turned-on second charge transistor CT2. Conversely, each of the 1-1 data lines DL1a, 2-1 data lines DL2a, and 3-1 data lines DL3a can be disconnected from the data pad DP via the turned-off first charge transistor CT1. Therefore, during the period of the n+1th frame (Frame(n+1),) the multiplexer circuits MUX can supply data voltages from the data pad DP only to the 1-2 data lines DL1b, 2-2 data lines DL2b, and 3-2 data lines DL3b among the plurality of data lines DL.

[0114] During the period of the (n+1)th frame (Frame(n+1),) the second discharge transistor DCT2 can be turned off and the first discharge transistor DCT1 can be turned on via a first select signal having an off level and a second select signal having an on level. Each of the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a can be connected to the discharge line DCL via the turned-on first discharge transistor DCT1. The voltage charged into each of the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a can be discharged into the discharge line DCL via the first discharge transistor DCT1. Each of the 1-2 data line DL1b, the 2-2 data line DL2b, and the 3-2 data line DL3b can be separated from the discharge line DCL via the turned-off second discharge transistor DCT2. Therefore, the voltage charged into each of the 1-2 data line DL1b, the 2-2 data line DL2b, and the 3-2 data line DL3b can be prevented from being discharged.

[0115] Therefore, during the period of the (n+1)th frame (Frame(n+1),) the second charging transistor CT2 can be turned on to supply a data voltage from the data pad DP to the plurality of sub-pixels SP connected to each of the 1-2 data line DL1b, the 2-2 data line DL2b, and the 3-2 data line DL3b. Furthermore, during the period of the (n+1)th frame (Frame(n+1),) the first discharging transistor DCT1 can be turned on to discharge the voltage charged in the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a, thereby controlling the sub-pixels SP connected to the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a to prevent the sub-pixels SP from emitting light.

[0116] Furthermore, the first select signal on the first select line SEL1 and the second select signal on the second select line SEL2 can be signals with opposite phases. If the phase of the first select signal is reversed, the first select signal can become the same as the second select signal. The first and second select signals can be signals with opposite phases. Therefore, the first and second select signals cannot be output as either on-level or off-level signals simultaneously.

[0117] Furthermore, each of the first charging transistor CT1 and the first discharging transistor DCT1 connected to the same data line DL can be controlled by a different select line, and each of the second charging transistor CT2 and the second discharging transistor DCT2 connected to the same data line DL can be controlled by a different select line. Therefore, the first charging transistor CT1 and the first discharging transistor DCT1 connected to the same data line DL can be turned on in different cycles, and the second charging transistor CT2 and the second discharging transistor DCT2 connected to the same data line DL can be turned on in different cycles.

[0118] Therefore, in one embodiment of the display device 100, a discharge transistor is formed in the multiplexer circuit MUX, thereby preventing the malfunction of some sub-pixels SP emitting light abnormally. If the multiplexer circuit MUX only includes a charge transistor and no discharge transistor, the voltage on the data line DL connected to the sub-pixels SP in the non-emitting state cannot be properly discharged, resulting in the malfunction of some sub-pixels SP emitting light, as described above. For example, during the period of frame (n+1), in which only the first sub-pixel SP1 connected to the 1-2 data line DL1b emits light, the voltage on the 1-1 data line DL1a is not properly discharged, as shown by the dashed waveform WV1 in FIG6 . This may cause the first sub-pixel SP1 connected to the 1-1 data line DL1a to also emit light. To prevent this, the multiplexer circuit MUX of the display device 100 in one embodiment includes a discharge transistor that selectively connects the voltage on the data line DL to the discharge line DCL, thereby preventing the malfunction of some sub-pixels SP emitting light during the non-emitting period.

[0119] Furthermore, in one embodiment of the display device 100, only one of a pair of sub-pixels SP emitting the same color light is selected and driven to increase the drive current provided to the LED 130 of each sub-pixel SP. This ensures that sufficient drive current is provided to the LED 130 even during low-gradation images, thereby reducing or minimizing the possibility of the LED 130 not emitting light. For example, in one embodiment of the display device 100, when a 1A drive current is required to display a specific low-gradation image, a 1A drive current is provided to the LED 130 of one of the sub-pixels SP pair to display the specific low-gradation image. Conversely, when a pair of sub-pixels SP are driven simultaneously to display the specific low-gradation image, a 0.5A drive current is provided to the LED 130 of each sub-pixel SP to display the specific low-gradation image. Therefore, when a pair of sub-pixels SP are driven simultaneously to display an image, the driving current supplied to the LED 130 of each sub-pixel SP may be reduced. Furthermore, in the case of low-quality images, the driving current value may be reduced, resulting in a malfunction in which some LEDs 130 fail to emit light normally. To prevent this, in one embodiment, the display device 100 selects and drives only one of a pair of sub-pixels SP that emit the same color light. This allows a larger driving current to be supplied to the LED 130 of each sub-pixel SP, thereby improving the display quality of low-quality images.

[0120] 7 and 8 , a detailed structure of the multiplexer circuit MUX of the display device 100 according to an embodiment will be described.

[0121] Figure 7 is a schematic plan view of a multiplexer circuit MUX of a display device according to an embodiment. Figure 8 is a schematic cross-sectional view of a multiplexer circuit MUX of a display device according to an embodiment.

[0122] As shown in Figures 7 and 8 , a display panel PN of a display device 100 according to one embodiment includes a substrate 110. The substrate 110, serving as a substrate support member disposed on the display device 100, may be an insulating substrate. A plurality of sub-pixels SP are formed on the substrate 110 to display an image. For example, the substrate 110 may be made of glass or resin. Furthermore, the substrate 110 may include a polymer or plastic. In some embodiments, the substrate 110 may be made of a flexible plastic material.

[0123] A buffer layer 111 is disposed on the substrate 110. The buffer layer 111 can reduce the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 can be composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx), or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but the present disclosure is not limited thereto. However, the buffer layer 111 can be omitted, depending on the type of substrate 110 or the type of thin film transistor, but the present disclosure is not limited thereto.

[0124] A multiplexer circuit MUX including a first charge transistor CT1, a second charge transistor CT2, a first discharge transistor DCT1, and a second discharge transistor DCT2 may be disposed on the buffer layer 111. The first charge transistor CT1 and the first discharge transistor DCT1 may be disposed adjacent to each other in the row direction, and the second charge transistor CT2 and the second discharge transistor DCT2 may be disposed adjacent to each other in the row direction. The first charge transistor CT1 and the second discharge transistor DCT2 may be disposed adjacent to each other in the column direction, and the second charge transistor CT2 and the first discharge transistor DCT1 may be disposed adjacent to each other in the column direction.

[0125] First, a first charging transistor CT1 including a first charging active layer CACT1, a first charging gate electrode CGE1, a first charging source electrode CSE1 and a first charging drain electrode CDE1 may be disposed on the buffer layer 111.

[0126] The first charging active layer CACT1 is disposed on the buffer layer 111. The first charging active layer CACT1 may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but the present disclosure is not limited thereto.

[0127] The gate insulating layer 112 is disposed on the first charge active layer CACT1. The gate insulating layer 112 serves as an insulating layer that electrically insulates the first charge active layer CACT1 from the first charge gate electrode CGE1. The gate insulating layer 112 may be composed of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx), or multiple layers of silicon oxide (SiOx) or silicon nitride (SiNx), but the present disclosure is not limited thereto.

[0128] The first charging gate electrode CGE1 is disposed on the gate insulating layer 112. The first charging gate electrode CGE1 can be electrically connected to the first select line SEL1. The first charging gate electrode CGE1 can be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but the present disclosure is not limited thereto.

[0129] A first interlayer insulating layer 113 and a second interlayer insulating layer 114 are provided on the first charging gate electrode CGE1. The first interlayer insulating layer 113 and the second interlayer insulating layer 114, which serve as insulating layers for protecting underlying devices, can be made of a single layer of silicon oxide (SiOx) or silicon nitride (SiNx), or multiple layers of silicon nitride (SiNx) or silicon oxide (SiOx), but the present disclosure is not limited thereto.

[0130] A first charging source electrode CSE1 and a first charging drain electrode CDE1 are disposed on the second interlayer insulating layer 114. The first charging source electrode CSE1 can be electrically connected to the data pad DP, and the first charging drain electrode CDE1 can be electrically connected to the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a. Furthermore, the first charging source electrode CSE1 and the first charging drain electrode CDE1 can be electrically connected to the first charging active layer CACT1 through contact holes penetrating the second interlayer insulating layer 114, the first interlayer insulating layer 113, and the gate insulating layer 112. The first charging source electrode CSE1 and the first charging drain electrode CDE1 can be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but the present disclosure is not limited thereto.

[0131] The second charging transistor CT2 including a second charging active layer CACT2 , a second charging gate electrode CGE2 , a second charging source electrode CSE2 and a second charging drain electrode CDE2 is disposed on the buffer layer 111 .

[0132] The second charging active layer CACT2 is disposed on the buffer layer 111. The second charging active layer CACT2 may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but the present disclosure is not limited thereto.

[0133] A gate insulating layer 112 is disposed on the second charging active layer CACT2, and a second charging gate electrode CGE2 is disposed on the gate insulating layer 112. The second charging gate electrode CGE2 can be electrically connected to the second select line SEL2. The second charging gate electrode CGE2 can be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but the present disclosure is not limited thereto.

[0134] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the second charging gate electrode CGE2, and the second charging source electrode CSE2 and the second charging drain electrode CDE2 are disposed on the second interlayer insulating layer 114. The second charging source electrode CSE2 can be electrically connected to the data pad DP, and the second charging drain electrode CDE2 can be electrically connected to the 1-2 data line DL1b, the 2-2 data line DL2b, and the 3-2 data line DL3b. Furthermore, the second charging source electrode CSE2 and the second charging drain electrode CDE2 can be electrically connected to the second charging active layer CACT2 through contact holes formed in the second interlayer insulating layer 114, the first interlayer insulating layer 113, and the gate insulating layer 112. The second charging source electrode CSE2 and the second charging drain electrode CDE2 can be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but the present disclosure is not limited thereto.

[0135] The first discharge transistor DCT1 including a first discharge active layer DCACT1 , a first discharge gate DCGE1 , a first discharge source electrode DCSE1 and a first discharge drain electrode DCDE1 is disposed on the buffer layer 111 .

[0136] The first discharge active layer DCACT1 is disposed on the buffer layer 111. The first discharge active layer DCACT1 may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but the present disclosure is not limited thereto.

[0137] A gate insulating layer 112 is disposed on the first discharge active layer DCACT1, and a first discharge gate electrode DCGE1 is disposed on the gate insulating layer 112. The first discharge gate electrode DCGE1 can be electrically connected to the second select line SEL2. The first discharge gate electrode DCGE1 can be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but the present disclosure is not limited thereto.

[0138] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the first discharge gate DCGE1. The first discharge source electrode DCSE1 and the first discharge drain electrode DCDE1 are disposed on the second interlayer insulating layer 114. The first discharge source electrode DCSE1 can be electrically connected to the 1-1 data line DL1a, the 2-1 data line DL2a, and the 3-1 data line DL3a. The first discharge drain electrode DCDE1 can be electrically connected to the discharge line DCL. Furthermore, the first discharge source electrode DCSE1 and the first discharge drain electrode DCDE1 can be electrically connected to the first discharge active layer DCACT1 through contact holes formed in the second interlayer insulating layer 114, the first interlayer insulating layer 113, and the gate insulating layer 112. The first discharge source electrode DCSE1 and the first discharge drain electrode DCDE1 can be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but the present disclosure is not limited thereto.

[0139] The second discharge transistor DCT2 disposed on the buffer layer 111 includes a second discharge active layer DCACT2 , a second discharge gate DCGE2 , a second discharge source electrode DCSE2 , and a second discharge drain electrode DCDE2 .

[0140] The second discharge active layer DCACT2 is disposed on the buffer layer 111. The second discharge active layer DCACT2 may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon, but the present disclosure is not limited thereto.

[0141] A gate insulating layer 112 is disposed on the second discharge active layer DCACT2, and a second discharge gate electrode DCGE2 is disposed on the gate insulating layer 112. The second discharge gate electrode DCGE2 can be electrically connected to the first select line SEL1. The second discharge gate electrode DCGE2 can be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but the present disclosure is not limited thereto.

[0142] The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are disposed on the second discharge gate DCGE2. The second discharge source electrode DCSE2 and the second discharge drain electrode DCDE2 are disposed on the second interlayer insulating layer 114. The second discharge source electrode DCSE2 can be electrically connected to the 1-2 data line DL1b, the 2-2 data line DL2b, and the 3-2 data line DL3b. The second discharge drain electrode DCDE2 can be electrically connected to the discharge line DCL. Furthermore, the second discharge source electrode DCSE2 and the second discharge drain electrode DCDE2 can be electrically connected to the second discharge active layer DCACT2 through contact holes formed in the second interlayer insulating layer 114, the first interlayer insulating layer 113, and the gate insulating layer 112. The second discharge source electrode DCSE2 and the second discharge drain electrode DCDE2 can be made of a conductive material, such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or alloys thereof, but the present disclosure is not limited thereto.

[0143] A first selection line SEL1 and a second selection line SEL2 are disposed between the gate insulating layer 112 and the first interlayer insulating layer 113. The first selection line SEL1 can be electrically connected to the first charging gate electrode CGE1 and the second discharging gate electrode DCGE2. For example, the first selection line SEL1, the first charging gate electrode CGE1, and the second discharging gate electrode DCGE2 can be integrally formed. The second selection line SEL2 can be electrically connected to the second charging gate electrode CGE2 and the first discharging gate electrode DCGE1. For example, the second selection line SEL2, the second charging gate electrode CGE2, and the first discharging gate electrode DCGE1 can be integrally formed.

[0144] The discharge line DCL is disposed between the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The discharge line DCL can extend in the column direction and be electrically connected to the first discharge source electrode DCSE1 and the second discharge source electrode DCSE2. The discharge line DCL can extend in the column direction and be disposed between the first charging transistor CT1 and the first discharging transistor DCT1, and between the second charging transistor CT2 and the second discharging transistor DCT2.

[0145] A plurality of data lines DL are disposed on the second interlayer insulating layer 114. The plurality of data lines DL can be electrically connected to each of the first charge drain electrode CDE1, the second charge drain electrode CDE2, the first discharge drain electrode DCDE1, and the second discharge drain electrode DCDE2. The first charge drain electrode CDE1 and the first discharge drain electrode DCDE1 can be electrically connected to the same data line DL, and the second charge drain electrode CDE2 and the second discharge drain electrode DCDE2 can be electrically connected to the same data line DL.

[0146] Furthermore, as the channel width of the multiple charging transistors increases, the data line DL can be charged more quickly with the data voltage. When the channel length of the multiple charging transistors decreases, the data line DL can be charged more quickly with the data voltage. Specifically, in the direction from the source electrode to the drain electrode, the channel of the transistor is the portion of the active layer that overlaps with the gate electrode. The channel width corresponds to the width of the gate electrode, and the channel length corresponds to the channel length. As the channel width increases or the channel length decreases, the resistance decreases, making it easier for current to flow. Conversely, as the channel width decreases or the channel length increases, the resistance increases, making it more difficult for current to flow. When the channel width / length ratio increases, more current can flow more easily through the channel. Accordingly, the channel width and length of the multiple charging transistors can be adjusted to quickly charge the data line DL with the data voltage.

[0147] Therefore, a multiplexer circuit MUX that only provides a data voltage to one of a pair of data lines DL is included in the display device 100 of one embodiment, thereby simplifying the structure of the data driver DD and reducing costs. The multiplexer circuit MUX can connect a pair of data lines DL to a single data pad DP. In the display device 100 of one embodiment, the number of data pads DP used to provide data voltages to multiple data lines DL can be half the number of data pads DP in a display device where one data line DL is connected to one data pad DP. Furthermore, as the number of data pads DP is reduced, the number of channels of the data driver DD that provides data voltages to multiple data pads DP is also reduced. Therefore, the structure of the data driver DD can be simplified and costs can be reduced. Therefore, in one embodiment, the display device 100 includes a multiplexer circuit MUX that connects multiple data lines DL to a single data pad DP, thereby reducing the number of channels and simplifying the structure of the data driver DD, thereby reducing costs and improving production yields.

[0148] FIG9 is a block diagram of subpixels and a multiplexer circuit MUX of a display device according to another embodiment. With the exception of the first subpixel SP1 and the first data line DL1, the display device 900 of FIG9 is substantially identical to the display device 100 of FIG1 through FIG8 . Therefore, descriptions of the identical components are omitted.

[0149] Referring to Figure 9 , each of the plurality of first data lines DL1 can be connected to each of the plurality of first sub-pixels SP1 and provide a data voltage to each of the plurality of first sub-pixels SP1. In this case, the plurality of first data lines DL1 can be directly connected to the plurality of data pads DP and provide the data voltage. Alternatively, all of the plurality of first data lines DL1 can be connected to different data pads DP and individually provided with data voltages. In this case, all of the plurality of first data lines DL1 can be provided with data voltages within a single frame period, and all of the plurality of first sub-pixels SP1 can be driven together.

[0150] In contrast, the plurality of second data lines DL2 and the plurality of third data lines DL3 may be connected to the multiplexer circuit MUX, and data voltages may be selectively provided to only a portion of the second data lines DL2 and a portion of the third data lines DL3 within one frame period.

[0151] Furthermore, the first LED 130R provided in the first sub-pixel SP1 is a red LED and is superior to the second LED 130G, which is a green LED, and the third LED 130B, which is a blue LED, in terms of low-current driveability. For example, even when the same drive current is supplied to the multiple LEDs 130, the first LED 130R, which is a red LED, can be driven more easily than the second LED 130G, which is a green LED, and the third LED 130B, which is a blue LED. The likelihood of driving failure can be further reduced compared to the second LED 130G, which is a green LED, and the third LED 130B, which is a blue LED. Therefore, a data voltage is simultaneously supplied to the first sub-pixel SP1 including the first LED 130R, which is advantageous for low-current drive, to display a low-level image.

[0152] Then, in the non-active area NA, the multiplexer circuit MUX can be disposed only in the area between the plurality of second data lines DL2 and the plurality of data pads DP, and in the area between the plurality of third data lines DL3 and the plurality of data pads DP. In contrast, in the non-active area NA, the multiplexer circuit MUX cannot be disposed in the area between the plurality of first data lines DL1 and the plurality of data pads DP. Therefore, other components of the display device 900 can be disposed in the area between the plurality of first data lines DL1 and the plurality of data pads DP, instead of the multiplexer circuit MUX. For example, an anti-static circuit is disposed in the area between the plurality of first data lines DL1 and the plurality of data pads DP to protect the display panel PN from static electricity. Therefore, the empty space between the plurality of first data lines DL1 and the plurality of data pads DP, without the multiplexer circuit MUX, helps ensure efficient utilization of the surface area of ​​the non-active area NA.

[0153] Exemplary embodiments of the present disclosure can also be described as follows:

[0154] According to one aspect of the present disclosure, a display device includes a plurality of sub-pixels, a plurality of data lines connected to each of the plurality of sub-pixels, and a multiplexer circuit connected to a pair of adjacent data lines among the plurality of data lines, the multiplexer circuit including a charging transistor connected to each pair of data lines and a discharging transistor connected to each pair of data lines.

[0155] The charging transistor may include a first charging transistor connected between one of the pair of data lines and the data pad, and a second charging transistor connected between the other of the pair of data lines and the data pad.

[0156] The discharge transistor may include a first discharge transistor connected between a data line and a discharge line, and a second discharge transistor connected between another data line and the discharge line.

[0157] The display device may further include a first selection line connected to the gate of the first charging transistor and the gate of the second discharging transistor, and a second selection line connected to the gate of the second charging transistor and the gate of the first discharging transistor.

[0158] The first selection signal of the first selection line and the second selection signal of the second selection line may be signals with opposite phases.

[0159] During a period of providing a first selection signal of an on-level and a second selection signal of an off-level, one data line can be electrically connected to a data pad through a first charging transistor, and another data line can be electrically connected to a discharge line through a second discharging transistor.

[0160] During the period of providing the second selection signal of the on-level and the first selection signal of the off-level, one data line can be electrically connected to the discharge line through the first discharge transistor, and the other data line can be electrically connected to the data pad through the second charge transistor.

[0161] The plurality of sub-pixels may include a pair of adjacent first sub-pixels, a pair of adjacent second sub-pixels, and a pair of adjacent third sub-pixels, and at least a portion of the first sub-pixels, the second sub-pixels, and the third sub-pixels are driven in different cycles.

[0162] The multiple data lines may include: data line 1-1 and data line 1-2, connected to each of a pair of first sub-pixels and connected to the same multiplexer circuit; data line 2-1 and data line 2-2, connected to each of a pair of second sub-pixels and connected to the same multiplexer circuit; data line 3-1 and data line 3-2, connected to each of a pair of third sub-pixels and connected to the same multiplexer circuit.

[0163] The plurality of data lines may include a plurality of first data lines connected to each of the first sub-pixel pairs, a 2-1 data line and a 2-2 data line connected to each of the second sub-pixel pairs and connected to the same multiplexer circuit, and a 3-1 data line and a 3-2 data line connected to each of the third sub-pixel pairs and connected to the same multiplexer circuit.

[0164] According to another aspect of the present disclosure, a display device includes a substrate configured to include an active region and an inactive region, a plurality of data lines configured to extend from the inactive region to the active region, a plurality of data pads disposed in the inactive region, and a plurality of multiplexer circuits disposed in the inactive region and connected between the data lines and the data pads. Each of the multiplexer circuits includes a plurality of first charging transistors connected to a portion of the plurality of data lines, a plurality of second charging transistors connected to the remaining portion of the plurality of data lines, a plurality of first discharging transistors connected to a portion of the data lines, and a plurality of second discharging transistors connected to the remaining data lines. The plurality of first charging transistors and the plurality of first discharging transistors are turned on in different periods, and the plurality of second charging transistors and the plurality of second discharging transistors are turned on in different periods.

[0165] Each of the plurality of first charging transistors may include a first charging active layer disposed on the substrate, a first charging gate electrode disposed on the first charging active layer, a first charging source electrode disposed on the first charging gate electrode and connected to each of the plurality of data pads. Each of the plurality of second charging transistors may include a second charging active layer disposed on the substrate, a second charging gate electrode disposed on the second charging active layer, a second charging source electrode disposed on the second charging gate electrode and connected to each of the plurality of data pads, and a second charging drain electrode disposed on the second charging gate electrode and connected to each of the remaining data lines.

[0166] Each of the plurality of first discharge transistors may include a first discharge active layer disposed on a substrate, a first discharge gate electrode disposed on the first discharge active layer, a first discharge source electrode disposed on the first discharge gate electrode and connected to each portion of the data lines, and a first discharge drain electrode disposed on the first discharge gate electrode and connected to the discharge lines. Each of the plurality of second discharge transistors may include a second discharge active layer disposed on the substrate, a second discharge gate electrode disposed on the second discharge active layer, a second discharge source electrode disposed on the second discharge gate electrode and connected to each of the remaining data lines, and a second discharge drain electrode disposed on the second discharge gate electrode and connected to the discharge lines.

[0167] While exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and may be embodied in many different forms without departing from the technical concepts of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concepts of the present disclosure. The scope of the technical concepts of the present disclosure is not limited thereto. Therefore, it should be understood that the aforementioned exemplary embodiments are illustrative in all respects and do not limit the present disclosure. All technical concepts within the scope of the present disclosure should be construed as falling within the scope of the present disclosure.

[0168] The various aforementioned embodiments can be combined to provide further embodiments. All U.S. patents, U.S. patent application publications, U.S. patent applications, foreign patents, foreign patent applications, and non-patent publications mentioned in this specification and / or listed in the Application Data Sheet are incorporated herein by reference in their entirety. If necessary, various aspects of the embodiments can be modified to provide further embodiments employing concepts from the various patents, applications, and publications.

[0169] These and other modifications can be made to the embodiments in light of the foregoing detailed description. Generally speaking, the terms used in the following claims should not be construed to limit the scope of the claims to the specific embodiments disclosed in this specification and claims, but rather should be construed to encompass all possible embodiments within the full scope of equivalents to the claims. Therefore, the scope of the claims is not limited by this disclosure.

[0170] 100: Display device 111: buffer layer 112: Gate insulation layer 130: Light-emitting diode 130R: First light-emitting diode 130G: Second light-emitting diode 130B: third light-emitting diode AA: Active Area NA: Non-active area PC: Pixel Circuit PN: Display Panel GD: Gate Driver DD: Data Drive DP: Data pad TC: Timing Controller SP: Sub-Pixel SP1: First sub-pixel SP2: Second sub-pixel SP3: The third sub-pixel SL: Scan Line SL1: first scan line SL2: Second scan line EL: luminous control signal line SEL1: First selection line SEL2: Second selection line CT1: First charging transistor CT2: Second charging transistor DCT1: First discharge transistor DCT2: Second discharge transistor DL: Data Line DL1: First Data Line DL1a:1-1 data line DL1b:1-2 data line DL2a:2-1 data line DL2b:2-2 data line DL3a:3-1 data line DL3b:3-2 data line DL2: Second data line DL3: Third Data Line VDD: high potential power line VSS: low potential power line RL: Reference Line SRL: Side Line Cp: ​​parasitic capacitor C1: First capacitor C2: Second capacitor C3: The third capacitor N1: first node N2: Second node N3: The third node N4: The fourth node T1: First transistor T2: Second transistor T3: The third transistor T4: The fourth transistor T5: The fifth transistor T6: The sixth transistor T7: Seventh transistor T8: Eighth transistor Blank: Blank period WV1: Dashed waveform CACT1: First charging active layer CACT2: Second charging active layer CGE1: First charging gate electrode CGE2: Second charging gate electrode CSE1: First charging source electrode CSE2: Second charging source electrode CDE1: First charge drain electrode CDE2: Second charge drain electrode Frame(n),Frame(n+1):frame MUX: Multiplexer circuit

Claims

1. A display device comprising: a plurality of sub-pixels; a plurality of data lines electrically connected to each of the sub-pixels; a plurality of multiplexer circuits, each of the multiplexer circuits electrically connected to a pair of adjacent data lines among the data lines; a first select line electrically connected to the multiplexer circuits; and a second select line electrically connected to the multiplexer circuits, wherein... Each of these multiplexer circuits includes: a charging transistor electrically connected to each of the pair of adjacent data lines; and a discharging transistor electrically connected to each of the pair of adjacent data lines, wherein the charging transistor includes: a first charging transistor electrically connected between one of the pair of adjacent data lines and a data pad; and a second charging transistor electrically connected between the other of the pair of adjacent data lines and the data pad, wherein the discharging transistor includes: a first discharging transistor electrically connected between the data line and a discharging line; and a second discharging transistor electrically connected between the other data line and the discharging line, wherein a first select line is electrically connected to the gate electrode of the first charging transistor and the gate electrode of the second discharging transistor, and a second select line is electrically connected to the gate electrode of the second charging transistor and the gate electrode of the first discharging transistor.

2. The display device as claimed in claim 1, wherein a first selection signal of one of the first selection lines and a second selection signal of one of the second selection lines are signals whose phases are opposite to each other.

3. The display device as claimed in claim 2, wherein during a cycle in which a first selection signal at an on level and a second selection signal at an off level are provided, one data line is electrically connected to the data pad via the first charging transistor, and the other data line is electrically connected to the discharge line via the second discharging transistor.

4. The display device as claimed in claim 2, wherein during a cycle in which a second selection signal at an on level and a first selection signal at an off level are provided, one data line is electrically connected to the discharge line via the first discharge transistor, and the other data line is electrically connected to the data pad via the second charge transistor.

5. The display device as claimed in claim 1, wherein the sub-pixels comprise: a pair of first sub-pixels adjacent to each other; a pair of second sub-pixels adjacent to each other; and a pair of third sub-pixels adjacent to each other, and wherein, At least a portion of the first sub-pixel pair, the second sub-pixel pair, and the third sub-pixel pair are driven at different periods.

6. The display device as claimed in claim 5, wherein the data lines comprise: a 1-1 data line and a 1-2 data line electrically connected to each of the pair of first sub-pixels and electrically connected to the same one of the multiplexer circuits; a 2-1 data line and a 2-2 data line electrically connected to each of the pair of second sub-pixels and electrically connected to the same one of the multiplexer circuits; and a 3-1 data line and a 3-2 data line electrically connected to each of the pair of third sub-pixels and electrically connected to the same one of the multiplexer circuits.

7. The display device as claimed in claim 8, wherein the data lines comprise: a plurality of first data lines electrically connected to each of the pair of first sub-pixels; a 2-1 data line and a 2-2 data line electrically connected to each of the pair of second sub-pixels and electrically connected to one of the same multiplexer circuits; and a 3-1 data line and a 3-2 data line electrically connected to each of the pair of third sub-pixels and electrically connected to one of the same multiplexer circuits.

8. A display device comprising: a substrate including an active region and a non-active region; a plurality of data lines configured to extend from the non-active region to the active region; a plurality of data pads disposed in the non-active region; and a plurality of multiplexer circuits disposed in the non-active region and electrically connected between the data lines and the data pads; wherein, Each of these multiplexer circuits includes: a plurality of first charging transistors electrically connected to a portion of the data lines; a plurality of second charging transistors electrically connected to the remaining data lines; a plurality of first discharging transistors electrically connected to the portion of the data lines; and a plurality of second discharging transistors electrically connected to the remaining data lines, wherein the first charging transistors and the first discharging transistors are turned on at different periods, and wherein the second charging transistors and the second discharging transistors are turned on at different periods, wherein each of the first charging transistors includes: a first charging active layer located on the substrate; and a first charging gate electrode located on the substrate. On a first active charging layer; a first charging source electrode located on the first charging gate electrode and electrically connected to each of the data pads; and a first charging drain electrode located on the first charging gate electrode and electrically connected to each of the data lines, wherein each of the second charging transistors comprises: a second active charging layer located on the substrate; a second charging gate electrode located on the second active charging layer; a second charging source electrode located on the second charging gate electrode and electrically connected to each of the data pads; and a second charging drain electrode located on the second charging gate electrode and electrically connected to each of the remaining data lines of the data lines.

9. The display device as claimed in claim 8, wherein each of the first discharge transistors comprises: a first discharge active layer located on the substrate; a first discharge gate electrode located on the first discharge active layer; a first discharge power electrode located on the first discharge gate electrode and electrically connected to each of the data lines; and a first discharge drain electrode located on the first discharge gate electrode and electrically connected to a discharge line, and wherein each of the second discharge transistors comprises: a second discharge active layer located on the substrate; a second discharge gate electrode located on the second discharge active layer; a second discharge power electrode located on the second discharge gate electrode and electrically connected to each of the remaining data lines; and a second discharge drain electrode located on the second discharge gate electrode and electrically connected to the discharge line.

10. The display device as claimed in claim 9, further comprising: a first selection line electrically connected to a plurality of gate electrodes of the first charging transistors and a plurality of gate electrodes of the second discharging transistors; and a second selection line electrically connected to the plurality of gate electrodes of the second charging transistors and the plurality of gate electrodes of the first discharging transistors.

11. The display device as claimed in claim 10, wherein a first selection signal of one of the first selection lines and a second selection signal of one of the second selection lines are signals whose phases are opposite to each other.

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