Semiconductor package and fabrication method thereof

Abstract

A semiconductor package includes a package substrate, an interposer disposed on the package substrate, a central logic chip and peripheral functional chips disposed on the interposer, and at least one dummy chip disposed between the central logic chip and the peripheral functional chips to form a rectangular chip arrangement. The at least one dummy chip is placed at a corner of the rectangular chip arrangement. A filler material fills the gap between the interposer and the package substrate. A pressure-reducing buffer structure is disposed on the bottom surface of the interposer.

Description

Technical Field

[0001] The present disclosure generally relates to the field of semiconductor packaging. More specifically, the present disclosure relates to a semiconductor package with a large-size interposer and a method for manufacturing the same. Prior Art

[0002] As the technology knows, Chip-on-Wafer-on-Substrate (CoWoS) is a 2.5D wafer-level multi-chip packaging technology that places multiple chips side by side on a silicon interposer substrate to achieve better interconnect density and performance. Individual chips are bonded to the silicon interposer substrate through microbumps to form a chip package on wafer (CoW). The CoW is then subsequently thinned to expose the through-hole (TSV) perforations through the substrate. This is followed by controlled collapse chip connection (Controlled Collapse Chip Connection, C4) bump formation and segmentation. The CoWoS package is completed by bonding with the packaging substrate.

[0003] A disadvantage of the prior art CoWoS package is that fatigue failures, such as filler material peeling, may be observed at the package corners during or after the thermal cycling test (TCT). Filler material peeling may cause reliability issues. Therefore, there is a need in the art to provide an improved CoWoS package to improve the reliability pass rate. Summary of the invention

[0004] An object of the present disclosure is to provide an improved semiconductor package having a large-sized interposer and a method for manufacturing the same to address the defects or deficiencies of the prior art.

[0005] One aspect of the present disclosure provides a semiconductor package, comprising a package substrate, an interposer disposed on and electrically connected to the package substrate, and at least one central logic chip disposed on and electrically connected to the interposer. A plurality of peripheral function chips are mounted on the interposer and located adjacent to the at least one central logic chip. At least one dummy chip is mounted on the interposer. The at least one dummy chip is disposed between the at least one central logic chip and the plurality of peripheral function chips so as to form a rectangular chip arrangement when viewed from above. The at least one dummy chip is disposed at a corner of the rectangular chip arrangement. A first filling material fills the gaps between the at least one central logic chip and the interposer, between the plurality of peripheral function chips and the interposer, between the at least one dummy chip and the interposer, between the at least one central logic chip and the plurality of peripheral function chips, and between the at least one central logic chip and the at least one dummy chip. A packaging compound encapsulates the at least one central logic chip, the plurality of peripheral function chips, and the at least one dummy chip. A second filling material fills the gap between the interposer and the package substrate. A decompression buffer structure is disposed on the bottom surface of the interposer.

[0006] According to some embodiments, the pressure relief structure includes a polymer layer.

[0007] According to some embodiments, the polymer layer includes polyimide (PI) or polybenzoxazole (PBO).

[0008] According to some embodiments, the decompression buffer structure is an annular structure, which is arranged along the periphery of the bottom surface of the intermediate layer.

[0009] According to certain embodiments, the at least one central logic chip includes a system-on-chip (SoC), a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a radio frequency (RF) chip, or an application processor (AP) chip.

[0010] According to some embodiments, the plurality of peripheral function chips include memory chips.

[0011] According to some embodiments, the at least one virtual wafer includes a silicon wafer.

[0012] According to some embodiments, the at least one dummy wafer includes ceramic, metal, polymer, or thermally conductive material.

[0013] According to some embodiments, the size of the interposer is greater than or equal to 2 mask sizes, where 1 mask size is 26 mm×34 mm.

[0014] According to some embodiments, the interposer includes a silicon interposer and includes a plurality of through silicon vias.

[0015] According to some embodiments, the interposer includes an organic material.

[0016] According to some embodiments, the at least one central logic chip, the plurality of peripheral function chips, and the at least one dummy chip have substantially the same chip thickness.

[0017] According to certain embodiments, the at least one central logic chip is mounted on the interposer via a first microbump, the plurality of peripheral function chips are mounted on the interposer via a second microbump, and the at least one dummy chip is mounted on the interposer via a third microbump.

[0018] According to some embodiments, the first, second and third microbumps are surrounded by the first filling material.

[0019] According to some embodiments, the interposer is connected to the package substrate via flip chip bumps or C4 bumps.

[0020] According to some embodiments, the flip wafer bump or C4 bump is surrounded by the second filling material.

[0021] According to some embodiments, the decompression buffer structure is in direct contact with the second filling material.

[0022] According to some embodiments, the thickness of the decompression buffer structure is 5 microns.

[0023] According to some embodiments, the semiconductor package further includes a reinforcement ring mounted on the top surface of the package substrate.

[0024] According to some embodiments, the reinforcement ring comprises metal.

[0025] These and other objects will no doubt become apparent to one having ordinary skill in the art after reading the following detailed description of the preferred embodiment which is depicted in the various figures and diagrams. Simple diagram description

[0026] The accompanying drawings are intended to provide a further understanding of the invention and are incorporated into and constitute a part of this specification. These drawings illustrate embodiments of the invention and, together with the description, serve to explain the principles of the invention. In the drawings: FIG. 1 is a schematic wafer placement diagram of a CoWoS package according to an embodiment of the present invention; Figure 2 is a cross-sectional view taken along line I-I 'of Figure 1; FIG. 3 is a schematic die placement diagram of a CoWoS package according to another embodiment of the present invention; and 4 to 14 are schematic diagrams showing an exemplary method of manufacturing a semiconductor package according to an embodiment of the present invention. Implementation

[0027] In the following detailed description of embodiments of the invention, reference is made to the accompanying drawings, which form a part hereof, and in which is shown by way of illustration specific preferred embodiments in which the disclosure may be practiced.

[0028] These embodiments are described in sufficient detail to enable a skilled artisan to practice them, and it is understood that other embodiments may be utilized, and mechanical, chemical, electrical, and procedural changes may be made without departing from the spirit and scope of the present disclosure. Therefore, the following detailed description should not be considered limiting, and the scope of the embodiments of the present invention is defined solely by the appended claims.

[0029] It should be understood that when an element or layer is referred to as being "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. Like numbers refer to like elements throughout this document. The term "and / or" as used herein includes any and all combinations of one or more of the associated listed items. The term "dummy wafer," or non-functional wafer, refers to a semiconductor wafer or wafer that does not have any electrical function.

[0030] Please refer to FIG. 1 and FIG. 2. FIG. 1 is a schematic die placement diagram of an exemplary CoWoS package according to an embodiment of the present invention. FIG. 2 is a cross-sectional view taken along line II' of FIG. 1. As shown in FIG. 1 and FIG. 2, a semiconductor package 1, such as a Chip-on-Wafer-on-Substrate (CoWoS) package, may include at least one central logic die 101 and a plurality of peripheral function die 102, which are located adjacent to the central logic die 101. At least one dummy die 103 is located between the central logic die 101 and the plurality of peripheral function die 102 so as to form a rectangular die arrangement when viewed from above. For example, according to one embodiment, the dummy die 103 may include, but is not limited to, a silicon die having a similar structure to the central logic die 101 or the peripheral function die 102, but without any electrical function. For example, according to one embodiment, at least one dummy die 103 is preferably placed at a corner position of the rectangular die arrangement.

[0031] For example, in FIG. 1, the rectangular die arrangement may include seven dies, including but not limited to a larger central logic die 101 having a shorter side S1 and a longer side S2, three smaller peripheral function dies 102 placed along the longer side S2 of the central logic die 101, and three dummy dies 103 placed at corresponding three corners. For example, according to one embodiment, the central logic die 101 may be a system-on-chip (SoC), a central processing unit (CPU) die, a graphics processing unit (GPU) die, a radio frequency (RF) die, or an application processor (AP) die, but is not limited thereto.

[0032] For example, according to one embodiment, the peripheral function die 102 may include a memory die, such as a high bandwidth memory (HBM) die, which includes a stack of DRAM dies, but is not limited thereto. For example, according to one embodiment, the peripheral function die 102 may be HBM2 or HBM3, but is not limited thereto. HBM is a memory die with low power consumption and ultra-wide communication channels.

[0033] For example, according to one embodiment, the dummy wafer 103 may be a passive silicon wafer. For example, according to one embodiment, the dummy wafer 103 may include any suitable material, such as ceramic, metal, polymer, or thermally conductive material.

[0034] As shown in FIG. 1 and FIG. 2 , the central logic die 101, the peripheral function die 102, and the dummy die 103 are mounted on the interposer 200. For example, according to one embodiment, the size of the interposer 200 may be greater than or equal to 2 mask sizes, where 1 mask size is 26 mm × 34 mm. For example, according to one embodiment, the interposer 200 may be a silicon interposer and may include a plurality of through silicon vias (TSVs) 201s. In some embodiments, the interposer 200 may include an organic material.

[0035] For example, according to one embodiment, the central logic wafer 101 may be mounted on the interposer 200 via microbumps 111, the peripheral function wafer 102 may be mounted on the interposer 200 via microbumps 112, and the dummy wafer 103 may be mounted on the interposer 200 via microbumps 113. For example, according to one embodiment, the microbumps 111, 112, 113 may include nickel, copper, gold, palladium, and / or SnAg solder. For example, according to one embodiment, the central logic wafer 101, the peripheral function wafer 102, and the dummy wafer 103 may have substantially the same wafer thickness.

[0036] It should be understood that other die arrangements may also be applicable. For example, in some embodiments, only two large dies or application specific integrated circuit (ASIC) dies, having substantially the same size, may be mounted on the interposer.

[0037] For example, according to one embodiment, the gap between the central logic wafer 101 and the interposer 200, the gap between the peripheral function wafer 102 and the interposer 200, the gap between the dummy wafer 103 and the interposer 200, the gap between the central logic wafer 101 and the peripheral function wafer 102, and the gap between the central logic wafer 101 and the dummy wafer 103 may be filled with the filling material 120. For example, according to one embodiment, the micro bumps 111, 112, 113 are surrounded by the filling material 120. In some embodiments, for example, the filling material 120 may be dispensed using a capillary process after the wafers are combined with the interposer 200.

[0038] For example, according to one embodiment, the central logic die 101, the peripheral function die 102, the dummy die 103, and the top surface of the interposer 200 may be encapsulated on the interposer 200 by the encapsulation compound 150, thereby forming a Chip-on-Wafer (CoW) package 10. For example, according to one embodiment, the CoW package 10 may be mounted on the top surface 20a of the package substrate 20. For example, according to one embodiment, the CoW package 10 may be connected to the package substrate 20 by a plurality of flip chip bumps or C4 bumps CB. According to one embodiment, the C4 bumps CB may form an array on the bottom surface 200b of the interposer 200. The C4 bumps CB may be attached to corresponding connection pads 220a of the package substrate 20.

[0039] According to one embodiment, a filling material 160 is disposed between the CoW package 10 and the package substrate 20 to prevent C4 bump corrosion and C4 bump fatigue failure due to thermal mismatch. The gap between the interposer 200 of the CoW package 10 and the package substrate 20 is filled with the filling material 160. The filling material 160 can be dispensed along one or more edges of the CoW package 10 and then flow under the CoW package 10 by capillary action. For example, the filling material 160 can be dispensed using a capillary flow process after the CoW package 10 is bonded to the package substrate 20.

[0040] According to one embodiment, a pressure relief structure SB is disposed on the bottom surface 200b of the interposer 200. According to one embodiment, the pressure relief structure SB may include a polymer layer, including but not limited to polyimide (PI) or polybenzoxazole (PBO). According to one embodiment, the pressure relief structure SB may be a continuous annular structure disposed along the periphery of the bottom surface 200b of the interposer 200. According to some embodiments, the pressure relief structure SB may be a discontinuous L-shaped structure disposed at each corner of the interposer 200, as shown in FIG. 3 .

[0041] According to one embodiment, the thickness of the decompression buffer structure SB may be about 5 microns. The decompression buffer structure SB of the interposer 200 increases the adhesion between the interposer 200 and the filling material, which can reduce or avoid fatigue failures such as filling material peeling at the corner of the package during the temperature cycle test (TCT) of the semiconductor package 1.

[0042] According to one embodiment, to address the warpage problem, a reinforcement ring 30, such as a metal ring, may be mounted on the top surface 20a of the package substrate 20 via an adhesive layer 310. According to one embodiment, the package substrate 20 may include a core 210, which may be made of a woven glass layer pre-impregnated with an epoxy resin material, such as a pre-impregnated layer FR-4 commonly used for printed circuit boards. A dielectric build-up layer 230 may be formed on both opposite sides of the core 210. Connection pads 220a, 220b and conductive copper wires 220 may be formed on the core 210 to provide interconnection between the CoW package 10 and its mounting system. On the bottom surface 20b of the package substrate 20, a plurality of solder balls BA may be provided on the corresponding connection pads 220b.

[0043] FIG. 4 to FIG. 14 are schematic diagrams of a method for manufacturing a semiconductor package according to an embodiment of the present invention, wherein the same numerals represent the same layers, components or regions. As shown in FIG. 4 , an interposer 200 having a wafer side S3 and a C4 side S4 is provided. According to an embodiment, for example, the interposer 200 may be a silicon interposer and may include a plurality of through silicon vias 201s formed in a silicon substrate 201.

[0044] A back-end metal interconnect structure 202 may be formed on the silicon substrate 201 and may be interconnected with the silicon through via 201s. According to one embodiment, the back-end metal interconnect structure 202 may include a dielectric layer and a metal layer manufactured using a metal process known in the art. According to one embodiment, the back-end metal interconnect structure 202 may include a connection pad layer 202p and micro bumps MB formed on the connection pad layer 202p.

[0045] As shown in FIG. 5 , a central logic wafer 101, at least one peripheral function wafer 102, and at least one dummy wafer 103 are bonded to the interposer 200 in a flip wafer manner through microbumps MB. According to one embodiment, for example, the microbumps MB may include nickel, copper, gold, palladium, and / or SnAg solder. According to one embodiment, for example, the central logic wafer 101, the peripheral function wafer 102, and the dummy wafer 103 may have substantially the same wafer thickness.

[0046] Subsequently, the gap between the central logic wafer 101 and the interposer 200, the gap between the peripheral function wafer 102 and the interposer 200, the gap between the dummy wafer 103 and the interposer 200, the gap between the central logic wafer 101 and the peripheral function wafer 102, and the gap between the central logic wafer 101 and the dummy wafer 103 may be filled with the filling material 120. In some embodiments, for example, the filling material 120 may be dispensed using a capillary flow process.

[0047] As shown in FIG. 6 , the central logic wafer 101, the peripheral function wafer 102, and the dummy wafer 103 are then packaged on the interposer 200 by the packaging compound 150. A grinding or polishing process may be performed to remove the packaging compound 150 directly above the central logic wafer 101, the peripheral function wafer 102, and the dummy wafer 103 to expose the rear surfaces of the central logic wafer 101, the peripheral function wafer 102, and the dummy wafer 103.

[0048] As shown in FIG. 7 , a carrier substrate 500 is provided. The carrier substrate 500 is attached to the exposed passive surfaces of the central logic wafer 101, the peripheral function wafer 102, and the dummy wafer 103 by using an adhesive layer 501. For example, the carrier substrate 500 may be a glass substrate, but is not limited thereto.

[0049] 8, a grinding or polishing process is then performed on the C4 side S4 of the interposer 200. A portion of the silicon substrate 201 is removed from the C4 side S4 of the interposer 200, thereby exposing the upper end of the through silicon via 201s.

[0050] As shown in FIG. 9 , a capping layer 610 is deposited on the polished surface of the silicon substrate 201. According to one embodiment, the capping layer 610 may include silicon nitride, but is not limited thereto. The capping layer 610 covers the protruding end of the through silicon via 201s. Subsequently, a chemical mechanical polishing (CMP) process is performed on the capping layer 610 to expose the end surface of the through silicon via 201s. According to one embodiment, after the CMP process, the end surface of the through silicon via 201s may be flush with the top surface of the capping layer 610.

[0051] As shown in FIG. 10 , an annular polymer layer BR is formed on the exposed end surface of each through silicon via 201s around the cap layer 610. According to one embodiment, the pressure relief structure SB is configured on the cap layer 610 around the top surface of the cap layer 610. The annular polymer layer BR and the pressure relief structure SB may include a polymer layer, including but not limited to polyimide (PI) or polybenzoxazole (PBO). According to one embodiment, the pressure relief structure SB may be a continuous annular structure.

[0052] According to one embodiment, the pressure relief structure SB may have a thickness of about 5 micrometers. According to one embodiment, the annular polymer layer BR and the pressure relief structure SB may have different thicknesses and / or widths, depending on design requirements.

[0053] As shown in FIG. 11 , a C4 bump CB is then formed on the exposed end surface of each through silicon via 201s. According to one embodiment, the C4 bump CB may be formed in an array on the interposer 200. C4 is an abbreviation for "controlled collapse chip connection". For example, the C4 bump CB may include a solder layer and a barrier layer located below the solder layer, but is not limited thereto.

[0054] As shown in FIG. 12 , the carrier substrate 500 is then removed to expose the surface of the interposer 200. After singulation, the CoW package 10 is formed.

[0055] As shown in FIG. 13 , the CoW package 10 is then mounted on the top surface 20 a of the package substrate 20. According to one embodiment, the CoW package 10 is connected to the package substrate 20 via the C4 bumps CB. For example, the package substrate 20 may have a size greater than 60 mm×60 mm, for example. The gap between the CoW package 10 and the package substrate 20 is then filled with a filling material 160. In some embodiments, for example, the filling material 160 may be dispensed using a capillary process after the CoW package 10 is combined with the package substrate 20. According to one embodiment, the decompression buffer structure SB is in direct contact with the filling material 160.

[0056] As shown in FIG. 14 , a reinforcement ring 30 such as a metal ring may be mounted on the top surface 20 a of the package substrate 20 via a glue layer 310 . According to one embodiment, for example, the reinforcement ring 30 may include copper, stainless steel, or aluminum, but is not limited thereto. Subsequently, solder balls BA may be mounted on the bottom surface of the package substrate 20 .

[0057] Those skilled in the art will readily observe that many modifications and variations of the apparatus and methods can be made while retaining the teachings of the invention. Therefore, the above disclosure should be limited only within the scope and metes and bounds of the appended claims. The above description is only a preferred embodiment of the present invention. All equivalent changes and modifications made according to the scope of the patent application of the present invention should fall within the scope of the present invention.

[0058] 1: Semiconductor packaging 10: CoW packaging 101: Central Logic Chip 102: Peripheral function chip 103: Virtual Chip 111: Micro bump 112: Micro bump 113: Micro bump 120: Filling material 150: Encapsulation compound 160: Filling material 20:Packaging substrate 20a: Top surface 20b: Bottom 200: Intermediary layer 200b: bottom 201:Silicon substrate 201s:Through Silicon Via 202: Back-end metal interconnect structure 202p: Connecting pad 210: Core 220: Conductive copper wire 220a: Connection pad 220b: Connection pad 230: Dielectric layer 30: Reinforcement ring 310: Adhesive layer 500: Carrier substrate 501: Adhesive layer 610: Covering layer BA: solder ball BR: Annular polymer layer CB:C4 bump I-I': line MB: Micro Bump S1: Side S2: Side S3: Wafer side S4: C4 side SB: Pressure relief buffer structure

Claims

1. A semiconductor package, comprising: A packaging substrate; An intermediary layer disposed on and electrically connected to the packaging substrate; At least one central logic chip disposed on and electrically connected to the interposer layer; a plurality of peripheral functional chips mounted on the interposer layer and located adjacent to the at least one central logic chip; at least one dummy chip mounted on the interposer layer, wherein the at least one dummy chip is placed between the at least one central logic chip and the plurality of peripheral functional chips to form a rectangular chip arrangement when viewed from above, wherein the at least one dummy chip is placed at a corner of the rectangular chip arrangement; a first filler material filling the gaps between the at least one central logic chip and the interposer layer, between the plurality of peripheral functional chips and the interposer layer, between the at least one dummy chip and the interposer layer, between the at least one central logic chip and the plurality of peripheral functional chips, and between the at least one central logic chip and the at least one dummy chip; an encapsulation compound encapsulating the at least one central logic chip, the plurality of peripheral functional chips, and the at least one dummy chip; a second filler material filling the gap between the interposer layer and the encapsulation substrate; and a decompression buffer structure disposed on the bottom surface of the interposer layer, wherein the decompression buffer structure is a ring structure and disposed along the periphery of the bottom surface of the interposer layer.

2. The semiconductor package as claimed in claim 1, wherein the decompression buffer structure includes a polymer layer.

3. The semiconductor package as claimed in claim 2, wherein the polymer layer comprises polyimide (PI) or polybenzoxazole (PBO).

4. The semiconductor package as claimed in claim 1, wherein the at least one central logic chip includes a system-on-a-chip (SoC), a central processing unit (CPU) chip, a graphics processing unit (GPU) chip, a radio frequency (RF) chip, or an application processor (AP) chip.

5. The semiconductor package as claimed in claim 1, wherein the plurality of peripheral functional chips includes a memory chip.

6. The semiconductor package as claimed in claim 1, wherein the at least one dummy wafer comprises a silicon wafer.

7. The semiconductor package as claimed in claim 1, wherein the at least one dummy wafer comprises ceramic, metal, polymer, or thermally conductive material.

8. The semiconductor package as claimed in claim 1, wherein the size of the interposer is greater than or equal to two photomask sizes, wherein one photomask size is 26 mm × 34 mm.

9. The semiconductor package as claimed in claim 1, wherein the interposer includes a silicon interposer and includes a plurality of silicon vias.

10. The semiconductor package as claimed in claim 1, wherein the interposer comprises an organic material.

11. The semiconductor package as claimed in claim 1, wherein the at least one central logic chip, the plurality of peripheral functional chips, and the at least one virtual chip have substantially the same chip thickness.

12. The semiconductor package of claim 1, wherein the at least one central logic chip is mounted on the interposer via a first microbump, the plurality of peripheral functional chips are mounted on the interposer via a second microbump, and the at least one dummy chip is mounted on the interposer via a third microbump.

13. The semiconductor package as claimed in claim 12, wherein the first, second, and third microbumps are surrounded by the first filler material.

14. The semiconductor package as claimed in claim 1, wherein the interposer is connected to the package substrate via flip-chip bumps or C4 bumps.

15. The semiconductor package as claimed in claim 14, wherein the flip-chip bump or C4 bump is surrounded by the second filler material.

16. The semiconductor package as claimed in claim 1, wherein the decompression buffer structure is in direct contact with the second filler material.

17. The semiconductor package as claimed in claim 1, wherein the thickness of the decompression buffer structure is 5 micrometers.

18. The semiconductor package as claimed in claim 1, further comprising: A reinforcing ring is mounted on the top surface of the packaging substrate.

19. The semiconductor package as claimed in claim 18, wherein the reinforcing ring comprises metal.

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