Semiconductor structure, semiconductor device and method of forming semiconductor device

Abstract

This disclosure describes a semiconductor device having a semiconductor seed layer on an S / D dielectric structure. The semiconductor structure includes: a channel structure on a substrate; a gate structure covering the channel structure; an internal spacer adjacent to a plurality of end portions of the gate structure and the channel structure; a dielectric structure on the substrate and adjacent to the internal spacer; an amorphous semiconductor material on the dielectric structure; and an epitaxial structure on the amorphous semiconductor material and a plurality of top surfaces of the dielectric structure.

Description

[Technical Field]

[0001] None [Previous Technology]

[0002] With advancements in semiconductor technology, there is an increasing demand for higher storage capacity, faster processing systems, higher efficiency, and lower costs. To meet these demands, the semiconductor industry continues to scale down semiconductor devices, such as MOSFETs including planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and fin field-effect transistors (finFETs). This scaling down has increased the complexity of semiconductor manufacturing processes and the difficulty of process control in semiconductor devices. [Summary of the Invention]

[0003] None

Implementation Method

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. Of course, these components and configurations are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. As used herein, the formation of a first feature over a second feature means that the first and second features are formed in direct contact. Furthermore, references to numbers and / or letters may be repeated in various instances of this disclosure. This repetition itself does not indicate a relationship between the various embodiments and / or configurations discussed.

[0006] In addition, spatial relative terms, such as "below," "below," "lower part," "above," "upper part," and the like, may be used herein for ease of description to describe the relationship between one or more elements or features illustrated in the figures and another element or feature. Spatial relative terms are intended to cover different orientations of the device in use or operation other than those depicted in the figures. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] It should be noted that references to "an embodiment," "an example embodiment," "an exemplary embodiment," "illustrative," etc., in the specification may describe embodiments that include specific features, structures, or characteristics, but each embodiment may not necessarily include such specific features, structures, or characteristics. Furthermore, such phrases do not necessarily refer to the same embodiment. Additionally, when a specific feature, structure, or characteristic is described in conjunction with an embodiment, implementing such a feature, structure, or characteristic in conjunction with other embodiments, whether explicitly described or not, is within the scope of knowledge of those skilled in the art.

[0008] It should be understood that the wording or terminology used herein is for descriptive and non-limiting purposes, and that the wording or phrases in this specification should be interpreted by those skilled in the art in accordance with the teachings herein.

[0009] In some embodiments, the terms "about" and "substantially" may indicate a given quantity of values ​​that vary within 20% of a value (e.g., ±1%, ±2%, ±3%, ±4%, ±5%, ±10%, ±20% of the value). These values ​​are merely examples and are not intended to be limiting. The terms "about" and "substantially" may refer to a percentage of a value as interpreted by one skilled in the art in accordance with the teachings herein.

[0010] As the demand for lower power consumption, higher efficiency, and smaller semiconductor devices increases, the size of semiconductor devices continues to shrink proportionally. This continuous scaling down of device size and the need for increased device performance can necessitate various process and material improvements, presenting a range of challenges. For example, nanostructured transistors can provide improved device performance through channels configured as stacked nanosheets / nanowires. Nanostructured transistors can include finFETs, gate-all-around field-effect transistors (GAA FETs), nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and other similar structured transistors. Source / drain (S / D) dielectric structures can be formed on the substrate between the stacked nanosheets / nanowires to reduce leakage current through parasitic channels in the substrate beneath the stacked nanosheets / nanowires. However, the subsequently grown S / D structure can include amorphous portions on the S / D dielectric structure and crystalline portions on the amorphous portions. The amorphous portions can have higher resistance and lower carrier mobility compared to the crystalline portions. Furthermore, the amorphous portions can lead to strain losses in the channels of the nanostructured transistor. Therefore, the performance of direct current (DC) devices using nanostructured transistors can be reduced.

[0011] Various embodiments of this disclosure provide methods for forming a semiconductor seed layer on an S / D dielectric structure in a semiconductor device (e.g., a nanostructured transistor) and / or other semiconductor devices in an integrated circuit (IC). In some embodiments, a channel structure stacked on a fin structure may be formed on a substrate. A recess may be formed adjacent to the channel structure in the fin structure. The S / D dielectric structure and the semiconductor seed layer may be formed in the recess. The S / D dielectric structure and the semiconductor seed layer may be attached below the bottom surface of the channel structure. An epitaxial structure may be formed on the top surface of the S / D dielectric structure and the semiconductor seed layer. The epitaxial structure may include an amorphous portion and a crystalline portion. The crystalline portion may contact the channel structure, and the amorphous portion may be attached below the bottom surface of the channel structure. By means of the amorphous portion of the S / D dielectric structure, the semiconductor seed layer, and the epitaxial structure below the bottom surface of the channel structure, the resistance between the epitaxial structure and the channel structure may be reduced. The carrier mobility in the epitaxial structure may be increased. The strain applied to the channel structure by the epitaxial structure can be increased. Therefore, the DC device performance of the semiconductor device can be improved.

[0012] Figure 1 illustrates an isometric view of a semiconductor device 100 having a semiconductor seed layer on an S / D dielectric structure according to some embodiments. Figure 2 illustrates a partial cross-sectional view of the semiconductor device 100 having a semiconductor seed layer on an S / D dielectric structure according to some embodiments, taken across line AA shown in Figure 1.

[0013] In some embodiments, the semiconductor device 100 may include transistors 102A to 102C, as illustrated in Figure 1. In some embodiments, transistors 102A to 102C may include nanostructured transistors. Nanostructured transistors may include finFETs, GAAFETs, nanosheet transistors, nanowire transistors, multi-bridge channel transistors, nanoribbon transistors, and other similar structured transistors. Nanostructured transistors may provide channels through a stacked nanosheet / nanowire configuration. In some embodiments, transistors 102A to 102C may be n-type field-effect transistors (NFETs). In some embodiments, transistors 102A to 102C may be p-type field-effect transistors (PFETs). In some embodiments, any of transistors 102A to 102C may be an NFET or a PFET. Although Figure 1 illustrates three transistors, the semiconductor device 100 may have any number of transistors. Furthermore, semiconductor device 100 may be incorporated into the IC by using other structural components, such as conductive vias, conductive wiring, dielectric layers, passivation layers, and interconnects, which are not illustrated for simplicity. The descriptions of transistors 102A to 102C with the same annotations apply to each other unless otherwise stated. And similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements.

[0014] Referring to Figures 1 and 2, a semiconductor device 100 having transistors 102A to 102C may be formed on a substrate 104 and may be isolated by a shallow trench isolation (STI) region 106. Each of transistors 102A to 102C may include a fin structure 108, sidewall spacers 109, a gate dielectric layer 124, a gate structure 112, a gate spacer 114, an internal spacer 121, an S / D dielectric structure 111, a semiconductor seed layer 113, an S / D structure 110, an etch stop layer (ESL) 116, an interlayer dielectric (ILD) layer 118, and an S / D contact structure 130. In some embodiments, as illustrated in Figure 2, transistors 102A to 102C may have nanostructures 122-1, 122-2 and 122-3 (collectively referred to as "nanostructure 122") on fin structure 108.

[0015] Referring to Figures 1 and 2, substrate 104 may include a semiconductor material, such as silicon. In some embodiments, substrate 104 includes a crystalline silicon substrate (e.g., a silicon wafer). In some embodiments, substrate 104 includes (i) an elemental semiconductor, such as germanium; (ii) a compound semiconductor, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; (iii) an alloy semiconductor, including silicon germanium carbide, silicon germanium, gallium arsenide phosphide, and / or aluminum gallium arsenide; or (iv) a combination of the foregoing. Additionally, substrate 104 may be doped according to design requirements (e.g., a p-type substrate or an n-type substrate). In some embodiments, substrate 104 may be doped with a p-type dopant (e.g., boron, indium, aluminum, or gallium) or an n-type dopant (e.g., phosphorus or arsenic).

[0016] The STI region 106 provides electrical isolation between transistors 102A to 102C, and electrical isolation from adjacent transistors (not shown) on the substrate 104 and / or adjacent active and passive components (not shown) integrated into or deposited on the substrate 104. The STI region 106 may be made of a dielectric material. In some embodiments, the STI region 106 may include silicon oxide, silicon nitride, silicon oxynitride, fluorine-doped silicate glass (FSG), low-k dielectric materials, and / or other suitable insulating materials. In some embodiments, the STI region 106 may include a multilayer structure.

[0017] Referring to Figures 1 and 2, the nanostructure 122 and the fin structure 108 can be formed on a patterned portion of the substrate 104. The embodiments of the nanostructures and fin structures disclosed herein can be patterned by any suitable method. For example, the nanostructures and fin structures can be patterned using one or more optical lithography processes, including dual or multiple patterning processes. Dual or multiple patterning processes can combine optical lithography processes with self-alignment processes to form patterns that have, for example, smaller spacing than spacing otherwise obtainable using a single direct optical lithography process. For example, a sacrificial layer is formed over the substrate and patterned using an optical lithography process. Spacers can be formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the nanostructures and fin structures.

[0018] As illustrated in Figures 1 and 2, the nanostructure 122 and fin structure 108 may extend along the X-axis relative to transistors 102A to 102C. In some embodiments, the nanostructure 122 and fin structure 108 may be disposed on a substrate 104. The nanostructure 122 may include a stack of nanostructures 122-1, 122-2, and 122-3, each of which may be in the form of nanosheets, nanowires, or nanoribbons. Each of the nanostructures 122 may serve as a channel structure and form a channel region underlying the gate structure 112 of transistors 102A to 102C. In some embodiments, the nanostructure 122 and fin structure 108 may include a semiconductor material similar to or different from that of the substrate 104. In some embodiments, the nanostructure 122 and fin structure 108 may include silicon. In some embodiments, the nanostructure 122 and fin structure 108 may include silicon germanium. The semiconductor material of nanostructure 122 and fin structure 108 may be undoped or may be in-situ doped during their formation process. In some embodiments, as illustrated in Figure 2, nanostructure 122 below gate structure 112 may form a channel region of semiconductor device 100 and represent the current carrying channel structure of semiconductor device 100. Although three layers of nanostructure 122 are illustrated in Figure 2, transistors 102A to 102C may have any number of nanostructures 122. In some embodiments, nanostructure 122 may have a thickness 122t ranging from about 3 nm to about 8 nm along the Z-axis. In some embodiments, the spacing between adjacent nanostructures 122 along the Z-axis may range from about 5 nm to about 12 nm.

[0019] Referring to Figures 1 and 2, the gate dielectric layer 124 may be formed on the nanostructure 122, the fin structure 108, and the STI region 106. In some embodiments, the gate dielectric layer 124 may be a multilayer structure and may include an interface layer and a high-k dielectric layer. In some embodiments, the gate dielectric layer 124 may not include an interface layer, and the high-k dielectric layer may be in direct contact with the nanostructure 122. In some embodiments, the interface layer may include silicon oxide formed by a deposition process or an oxidation process. In some embodiments, the interface layer may have a thickness ranging from about 0.1 nm to about 1.5 nm. In some embodiments, the high-k dielectric layer may include hafnium oxide, zirconium oxide, or other suitable high-k dielectric materials.

[0020] In some embodiments, as illustrated in Figures 1 and 2, the gate structure 112 may be disposed on the gate dielectric layer 124. In some embodiments, the gate structure 112 may include one or more work function metal layers and metal fillers. The one or more work function metal layers may include work function metals to tune the threshold voltage (Vt) of transistors 102A to 102C. In some embodiments, the gate structure 112 for NFET and PFET devices may have substantially the same work function metal. In some embodiments, the gate structure 112 for NFET and PFET devices may have different work function metals. In some embodiments, as illustrated in Figure 2, each of the nanostructures 122 may be covered by the gate structure 112, which may be referred to as a "gate-all-around (GAA) structure," and the transistors 102A to 102C may also be referred to as "GAA FETs 102A to 102C." One or more work function metal layers may cover the nanostructure 122 and may include work function metals to tune the Vt of transistors 102A to 102C. In some embodiments, transistors 102A to 102C may include any number of work function metal layers for Vt tuning (e.g., ultra-low Vt, low Vt, and standard Vt).

[0021] In some embodiments, NFETs 102A to 102C may include an n-type work function metal layer. The n-type work function metal layer may include aluminum, titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum aluminum carbide, tantalum silicon carbide, hafnium carbide, silicon, titanium nitride, titanium silicon nitride, or other suitable work function metals. In some embodiments, PFETs 102A to 102C may include a p-type work function metal layer. The p-type work function metal layer may include titanium nitride, titanium silicon nitride, tantalum nitride, tungsten carbide nitride, tungsten, molybdenum, or other suitable work function metals. In some embodiments, the work function metal layer may include a single metal layer or a stack of metal layers. The metal layer stack may include work function metals having work function values ​​equal to or different from each other. In some embodiments, the metal filler may include titanium, tantalum, aluminum, cobalt, tungsten, nickel, ruthenium, or other suitable conductive materials.

[0022] Referring to Figures 1 and 2, according to some embodiments, gate spacer 114 may be disposed on the sidewall of gate structure 112 and in contact with gate dielectric layer 124. Sidewall spacer 109 may be disposed on the sidewall of fin structure 108. Internal spacer 121 may be adjacent to the end portion of nanostructure 122 and disposed between S / D structure 110 and gate structure 112. Gate spacer 114, sidewall spacer 109 and internal spacer 121 may include insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, silicon oxycarbide, silicon oxycarbonitride, alumina, low-k materials, and combinations thereof. In some embodiments, gate spacer 114, sidewall spacer 109 and internal spacer 121 may include the same insulating material. In some embodiments, the gate spacer 114, sidewall spacer 109, and internal spacer 121 may comprise different insulating materials. In some embodiments, the gate spacer 114, sidewall spacer 109, and internal spacer 121 may comprise a single layer or a stack of insulating layers. In some embodiments, the gate spacer 114, sidewall spacer 109, and internal spacer 121 may have a low-k material with a dielectric constant less than about 3.9 (e.g., about 3.5, about 3.0, or about 2.8).

[0023] In some embodiments, the S / D dielectric structure 111 may be disposed on the fin structure 108. In some embodiments, the S / D dielectric structure 111 may include aluminum oxide (AlO x), silicon carbide (SiC x), silicon nitride (SiN x), silicon carbonitride (SiC xN 1-x), silicon oxycarbonitride (SiO yC xN 1-xy), low-k materials, or combinations thereof. In some embodiments, the S / D dielectric structure 111 may reduce leakage current through the fin structure 108 and improve device performance. In some embodiments, the S / D dielectric structure 111 may have a thickness 111t ranging from about 3 nm to about 5 nm. The ratio of thickness 111t to thickness 122t may range from about 0.2 to about 0.8. If the thickness 111t is less than about 3 nm or the ratio is less than about 0.2, the S / D dielectric structure 111 may not reduce leakage current in the semiconductor device 100, and device performance may not be improved. If the thickness 111t is greater than about 5 nm or the ratio is greater than about 0.8, the S / D dielectric structure 111 may come into contact with the nanostructure 122, which may result in reduced device current and degraded device performance.

[0024] In some embodiments, as illustrated in Figures 1 and 2, the S / D dielectric structure 111 may extend into the fin structure 108. In some embodiments, the S / D dielectric structure 111 may extend a distance 111d below the bottom surface of the gate structure 112. In some embodiments, the distance 111d may range from about 4 nm to about 12 nm. The ratio between the distance 111d and the thickness 122t may range from about 1 to about 2. If the distance 111d is less than about 4 nm or the ratio is less than about 1, the device current between the nanostructure 122 and the S / D structure 110 may be reduced, and the device performance may be degraded. If the distance 111d is greater than about 12 nm or the ratio is greater than about 2, the device performance may not be further improved, but the manufacturing cost may increase.

[0025] In some embodiments, the S / D dielectric structure 111 may be attached below the bottom surface of the bottom nanostructure 122-1 to avoid contact between the S / D dielectric structure 111 and the nanostructure 122. If the S / D dielectric structure 111 contacts the nanostructure 122, the device current between the nanostructure 122 and the S / D structure 110 may be reduced, and the device performance may be degraded. In some embodiments, as illustrated in Figure 2, the S / D dielectric structure 111 may have a "U-shaped" shape, and the end portion of the S / D dielectric structure 111 may cover the internal spacer 121 below the bottom nanostructure 122-1. In some embodiments, as illustrated in Figure 2, the end portion of the S / D dielectric structure 111 may have a sloping top surface, wherein the inner edge of the end portion is lower than the outer edge of the end portion. In some embodiments, the height difference between the inner edge and the outer edge of the end portion of the S / D dielectric structure 111 may range from about 5 nm to about 12 nm. In some embodiments, when the end portion of the S / D dielectric structure 111 is covered by the internal spacer 121, the parasitic capacitance between the S / D structure 110 and the gate structure 112 can be reduced, and the device performance can be improved.

[0026] In some embodiments, as illustrated in Figure 2, a semiconductor seed layer 113 may be disposed on and surrounded by the S / D dielectric structure 111. In some embodiments, the semiconductor seed layer 113 may include amorphous silicon, amorphous silicon-germanium, or other suitable amorphous semiconductor materials. In some embodiments, the semiconductor seed layer 113 may include amorphous semiconductor materials, such as amorphous silicon or polycrystalline silicon. In some embodiments, the semiconductor seed layer 113 may act as a seed layer for the subsequent growth of the S / D structure 110. The semiconductor seed layer 113 may promote the growth of the S / D structure 110 without forming a void between the S / D structure 110 and the S / D dielectric structure 111. In some embodiments, the semiconductor seed layer 113 may be attached below the bottom surface of the bottom nanostructure 122-1. If the semiconductor seed layer 113 is located above the bottom surface of the bottom nanostructure 122-1, the nanostructure 122 can contact the S / D dielectric structure 111 and / or the semiconductor seed layer 113. The device current between the nanostructure 122 and the S / D structure 110 can be reduced, and the device performance can be degraded.

[0027] In some embodiments, the semiconductor seed layer 113 may have a thickness 113t ranging from about 1 nm to about 7.5 nm. The ratio of thickness 113t to thickness 122t may range from about 0.1 to about 0.9. If the thickness 113t is less than about 1 nm or the ratio is less than about 0.1, pores may be formed between the S / D dielectric structure 111 and the S / D structure 110, and device performance may be degraded. If the thickness 113t is greater than about 7.5 nm or the ratio is greater than about 0.9, the nanostructure 122 may contact the amorphous semiconductor material in the semiconductor seed layer 113 and / or the S / D structure 110, and device performance may be reduced.

[0028] Referring to Figures 1 and 2, the S / D structure 110 may be disposed on the top surface of the semiconductor seed layer 113 and the S / D dielectric structure 111. The S / D structure 110 may serve as the S / D region of transistors 102A to 102C. In some embodiments, the S / D structure 110 may have any geometry, such as polygonal, conical, rhomboid, elliptical, and circular. In some embodiments, the S / D structure 110 may include epitaxially grown semiconductor material, such as silicon (e.g., the same material as substrate 104). In some embodiments, the S / D structure 110 may include an epitaxially grown semiconductor material different from the material of substrate 104, such as silicon germanium; and may impart strain to the channel region of nanostructure 122 below gate structure 112. Since the lattice constant of such epitaxially grown semiconductor material is different from that of substrate 104, the channel region of nanostructure 122 is strained to increase the carrier mobility in the channel region of semiconductor device 100. The semiconductor materials for epitaxial growth may include: (i) semiconductor materials, such as germanium and silicon; (ii) compound semiconductor materials, such as gallium arsenide and aluminum gallium arsenide; or (iii) semiconductor alloys, such as silicon germanium and gallium arsenide phosphide.

[0029] In some embodiments, the S / D structure 110 may include silicon and be in-situ doped using n-type dopants such as phosphorus and arsenic during the epitaxial growth process. For n-type in-situ doping, n-type doping precursors such as phosphorus, arsenic, and other n-type doping precursors may be used. In some embodiments, the S / D structure 110 may include silicon, silicon germanium, germanium, or group III-V materials (e.g., indium antimonide, gallium antimonide, or indium gallium antimonide), and may be in-situ doped using p-type dopants such as boron, indium, and gallium during the epitaxial growth process. For p-type in-situ doping, p-type doping precursors such as diborane (B₂H₆), boron trifluoride (BF₃), and other p-type doping precursors may be used.

[0030] In some embodiments, as illustrated in Figure 2, the S / D structure 110 may have a height 110h ranging from about 50 nm to about 80 nm along the Z-axis. In some embodiments, the S / D structure 110 may have a width 110w ranging from about 20 nm to about 40 nm along the X-axis. In some embodiments, as illustrated in Figure 2, the S / D structure 110 may include an amorphous portion 110A and a crystalline portion 110B. In some embodiments, the amorphous portion 110A may include an amorphous semiconductor material, such as amorphous silicon or a polycrystalline semiconductor material. In some embodiments, the amorphous portion 110A may be attached below the bottom surface of the bottom nanostructure 122-1. If the amorphous portion 110A is attached above the bottom surface of the bottom nanostructure 122-1, the size of the crystalline portion 110B may be reduced, the strain imparted to the channel region of the nanostructure 122 may be reduced, and the carrier mobility in the channel region of the nanostructure 122 may be reduced. In addition, if the amorphous portion 110A is located above the bottom surface of the bottom nanostructure 122-1, the nanostructure 122 can contact the amorphous portion 110A, the device current between the nanostructure 122 and the S / D structure 110 can be reduced, and the device performance can be degraded.

[0031] In some embodiments, the amorphous portion 110A may have a thickness 110At ranging from about 1 nm to about 6 nm along the Z-axis. In some embodiments, the ratio between the thickness 110At and the thickness 122t may range from about 0.3 to about 0.7. When the thickness 110At is less than about 1 nm or the ratio is less than about 0.3, the crystalline portion 110B of the S / D structure may become amorphous. If the thickness 110At is greater than about 6 nm or the ratio is greater than about 0.7, the size of the crystalline portion 110B may be reduced, the strain on the nanostructure 122 and the carrier mobility in the nanostructure 122 may be reduced, the amorphous portion 110A may contact the nanostructure 122, the drive current of the semiconductor device 100 may be reduced, and the device performance of the semiconductor device 100 may be degraded.

[0032] In some embodiments, the crystalline portion 110B of the S / D structure 110 may include one or more epitaxial layers, wherein each epitaxial layer may have a different composition. In some embodiments, each of the one or more epitaxial layers may include Si and differ from each other based on, for example, doping concentration and / or epitaxial growth process conditions. In some embodiments, each of the one or more epitaxial layers may include silicon-germanium and differ from each other based on, for example, doping concentration, epitaxial growth process conditions and / or the relative concentration of germanium with respect to silicon.

[0033] Referring to Figures 1 and 2, the ESL 116 may be disposed on the sidewalls of the S / D structure 110, the gate spacer 114, and the sidewall spacer 109. The ESL 116 may be used to protect the S / D structure 110, the S / D dielectric structure 111, and the gate structure 112 during the formation of the S / D contact structure 130 on the S / D structure 110. In some embodiments, the ESL 116 may include, for example, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, silicon carbonitride, boron nitride, boron silicon nitride, silicon carbide, or combinations thereof.

[0034] The ILD layer 118 may be disposed on the ESL 116 over the S / D structure 110 and the STI region 106. In some embodiments, the ILD layer 118 may include a dielectric material deposited using a deposition method suitable for flowing dielectric materials. For example, flowing silicon oxide may be deposited using flowable chemical vapor deposition (FCVD). In some embodiments, the dielectric material may include silicon oxide.

[0035] In some embodiments, as illustrated in Figures 1 and 2, the semiconductor device 100 may further include an S / D contact structure 130. In some embodiments, the S / D contact structure 130 may be disposed on an S / D structure 110. In some embodiments, the S / D contact structure 130 may include a silicate layer 130A and a metal contact 130B. In some embodiments, the silicate layer 130A may include a metal silicate and may provide a lower resistance interface between the metal contact 130B and the S / D structure 110. Examples of metals used to form the metal silicate include cobalt, titanium, and nickel. In some embodiments, the metal contact 130B may include a conductive material such as tungsten, aluminum, and cobalt. In some embodiments, as illustrated in Figures 1 and 2, the S / D contact structure 130 may extend through the ILD layer 118 and into the S / D structure 110. In some embodiments, the top surfaces of the gate structure 112, gate spacer 114, ESL 116, ILD layer 118, and S / D contact structure 130 may be coplanar. In some embodiments, the semiconductor device 100 may further include metal wiring, metal vias, interconnects, and additional ILD layers.

[0036] Figure 3 is a flowchart of a method 300 for manufacturing a semiconductor device 100 having a semiconductor seed layer on an S / D dielectric structure, according to some embodiments. Method 300 may not be limited to nanostructure transistor devices and may be applicable to other devices that would benefit from a semiconductor seed layer on an S / D dielectric structure. Additional manufacturing operations may be performed between various operations of method 300 and may be omitted for clarity and ease of description only. Additional processes may be provided before, during, and / or after method 300; one or more of these additional processes are briefly described herein. Furthermore, not all operations are necessary to perform the disclosures provided herein. Additionally, some of the operations may be performed simultaneously or in a different order than that shown in Figure 3. In some embodiments, one or more other operations may be performed in addition to or in lieu of the previously described operations.

[0037] For illustrative purposes, the operations illustrated in Figure 3 will be referred to in the example manufacturing process description for manufacturing the semiconductor device 100 illustrated in Figures 4 through 12. According to some embodiments, Figures 4 through 12 illustrate partial cross-sectional views of the semiconductor device 100 along line AA as shown in Figure 1 at various manufacturing stages. Elements in Figures 4 through 12 with the same annotations as those in Figures 1 and 2 are those described above.

[0038] Referring to Figure 3, method 300 begins with operation 310 and a process of forming a channel structure stacked on the fin structure on a substrate. For example, as illustrated in Figure 4, nanostructures 122 and 420-1, 420-2, and 420-3 (collectively referred to as "nanostructure 420") stacked on the fin structure 108 may be formed on the substrate 104. In some embodiments, nanostructures 122 and 420 may be stacked alternately. In some embodiments, nanostructures 122 and 420 may be epitaxially grown on the substrate 104 and subsequently patterned to form nanostructures 122 and 420 stacked on the fin structure 108. In some embodiments, nanostructures 122 and 420 may be in the form of nanosheets, nanowires, or nanoribbons. In some embodiments, nanostructures 122 and 420 may include semiconductor materials similar to or different from the substrate 104. In some embodiments, fin structure 108 may include a semiconductor material identical to that of substrate 104. In some embodiments, nanostructures 122 and 420 may include different semiconductor materials. For example, nanostructure 122 may include silicon, and nanostructure 420 may include silicon germanium, wherein the percentage of germanium atoms is from about 10% to about 40%.

[0039] The embodiments of the fin structure 108 and nanostructures 122 and 420 disclosed herein can be patterned by any suitable method. For example, the fin structure and nanostructure can be patterned using one or more optical lithography processes, including dual patterning or multiple patterning processes. Dual patterning or multiple patterning processes can combine optical lithography processes with self-alignment processes to form patterns that have, for example, smaller spacing than the spacing that can be obtained otherwise using a single direct optical lithography process. For example, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers can be formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fin structure and nanostructure.

[0040] The formation of nanostructure 122 may subsequently form an STI region 106 between adjacent stacks of nanostructures 122 and 420, and a sacrificial gate structure 412 on nanostructure 122, as illustrated in Figure 4.

[0041] Referring to Figure 3, in operation 320, a recess is formed adjacent to the channel structure in the fin structure. For example, as illustrated in Figure 4, nanostructures 122 and 420 and fin structure 108 may be recessed to form a recess 108r in fin structure 108 adjacent to nanostructures 122 and 420. In some embodiments, the recess 108r may extend below nanostructures 122 and 420 into fin structure 108. In some embodiments, as illustrated in Figure 4, the recess 108r in fin structure 108 may have a recessed profile and a depth 108d ranging from about 4 nm to about 12 nm along the Z-axis. In some embodiments, the depth 108d may ensure complete removal of the bottom nanostructure 420 and formation of the S / D dielectric structure 111, semiconductor seed layer 113, and amorphous portion 110A of S / D structure 110 below the bottom surface of the bottom nanostructure 122-1.

[0042] In some embodiments, forming the recess 108r may subsequently form the internal spacer 121, as illustrated in Figure 4. In some embodiments, forming the internal spacer 121 may include lateral recesses of the nanostructure 420, deposition of the spacer layer, and trimming of the spacer layer.

[0043] Referring to Figure 3, in operation 330, dielectric material is deposited in a recess on the fin structure. For example, as illustrated in Figure 5, dielectric material 511 may be deposited in a recess 108r on the fin structure 108 and on the sacrificial gate structure 412. In some embodiments, dielectric material 511 may be conformally deposited on the fin structure 108, the nanostructure 122, the internal spacer 121, and the sacrificial gate structure 412. In some embodiments, dielectric material 511 may be deposited by furnace baking, plasma-assisted atomic layer deposition (plasma-assisted ALD), conformal chemical vapor deposition (conformal CVD), or other suitable deposition methods. In some embodiments, dielectric material 511 may include AlO x, SiC x, SiN x, SiC xN 1-x, SiO yC xN 1-xy, low-k materials, or combinations thereof. In some embodiments, dielectric material 511 may have a thickness 511t ranging from about 3 nm to about 5 nm.

[0044] Referring to Figure 3, in operation 340, an amorphous semiconductor material is deposited on the dielectric material. For example, as illustrated in Figure 6, an amorphous semiconductor material 613 may be deposited on the dielectric material 511. In some embodiments, the amorphous semiconductor material 613 may be directionally deposited on the dielectric material 511 by furnace baking, chemical vapor deposition (CVD) with a potential bias, or other suitable deposition methods. In some embodiments, the amorphous semiconductor material 613 may be deposited using a silane precursor. In some embodiments, the amorphous semiconductor material 613 may include amorphous or polycrystalline semiconductor materials. In some embodiments, the amorphous semiconductor material 613 may include amorphous silicon, amorphous silicon germanium, or other suitable amorphous semiconductor materials. In some embodiments, as illustrated in Figure 6, the amorphous semiconductor material 613 may be deposited primarily on the top surface of the dielectric material 511 and in small amounts on the sidewall surfaces of the dielectric material 511.

[0045] In some embodiments, the deposition of the amorphous semiconductor material 613 may be followed by etching of the amorphous semiconductor material 613. For example, as illustrated in Figure 7, the amorphous semiconductor material 613 on the sidewall surface of the dielectric material 511 and on the top surface of the dielectric material 511 above the sacrificial gate structure 412 may be removed by an etching process. In some embodiments, the etching process may use etching gases, such as hydrogen plasma and chloride plasma. In some embodiments, the etching gas may not reach the amorphous semiconductor material 613 in the recess 108r, and the remaining amorphous semiconductor material 613 in the recess 108r may form a semiconductor seed layer 113.

[0046] In some embodiments, etching the amorphous semiconductor material 613 may be followed by treating the top portion of the semiconductor seed layer 113. For example, as illustrated in Figure 8, the top portion of the semiconductor seed layer 113 may be oxidized by an oxygen-containing source or nitrided by a nitrogen-containing source. In some embodiments, the top portion of the semiconductor seed layer 113 may be oxidized or nitrided by a plasma process, a thermal process, a placement process, or other suitable process. In some embodiments, after oxidation or nitriding treatment, the top portions of the semiconductor seed layer 113 and the dielectric material 511 may have substantially the same thickness, substantially the same strength, and substantially the same wet etching rate. In some embodiments, as illustrated in Figure 8, the top treated portion of the semiconductor seed layer may have a thickness 113d ranging from about 3 nm to about 5 nm along the Z-axis.

[0047] Referring to Figure 3, in operation 350, a portion of the dielectric material is removed to form a dielectric structure. For example, as illustrated in Figures 9 and 10, a portion of the dielectric material 511 on the sacrificial gate structure 412, nanostructure 122, and internal spacer 121 may be removed to form an S / D dielectric structure 111 and expose the top surface of the semiconductor seed layer 113. In some embodiments, a portion of the dielectric material 511 may be removed by an isotropic etching process. In some embodiments, the isotropic etching process may include nitrogen trifluoride (NF3) dry etching, phosphoric acid and diluted hydrofluoric acid (H3PO4 / HF) wet etching, or a combination of dry and wet etching. In some embodiments, when the thickness 113d is greater than the thickness 511t, the S / D dielectric structure 111 may have a "U" shape, and the end portion of the S / D dielectric structure 111 may be attached above the top surface of the semiconductor seed layer 113 and cover the internal spacer 121 below the bottom nanostructure 122-1, as illustrated in Figure 9. In some embodiments, when the thickness 113d is equal to or less than the thickness 511t, the end portion of the S / D dielectric structure 111 may be attached at the same level as or below the top surface of the semiconductor seed layer 113, as illustrated in Figure 10.

[0048] In some embodiments, as illustrated in Figure 9, the end portion of the S / D dielectric structure 111 may have a sloping top surface, wherein the inner edge of the end portion is lower than the outer edge of the end portion. In some embodiments, when the end portion of the S / D dielectric structure 111 covers the internal spacer 121 as illustrated in Figure 9, the parasitic capacitance between the S / D structure 110 and the gate structure 112 may be reduced, and the device performance may be further improved.

[0049] Referring to Figure 3, in operation 360, the epitaxial structure may be grown on the top surface of the amorphous semiconductor material. For example, as illustrated in Figures 11 and 12, the S / D structure 110 may be epitaxially grown on the top surfaces of the amorphous semiconductor seed layer 113 and the S / D dielectric structure 111, as illustrated in Figures 9 and 10, respectively. In some embodiments, as illustrated in Figures 11 and 12, the S / D structure 110 may include an amorphous portion 110A grown on the semiconductor seed layer 113 and the S / D dielectric structure 111, and a crystalline portion 110B grown on the amorphous portion 110A. In some embodiments, the amorphous portion 110A may include an amorphous semiconductor material, such as amorphous silicon or a polycrystalline semiconductor material. In some embodiments, the amorphous portion 110A may be attached below the bottom surface of the bottom nanostructure 122-1. If the amorphous portion 110A is located above the bottom surface of the bottom nanostructure 122-1, the size of the crystalline portion 110B can be reduced, the strain imparted to the channel region of the nanostructure 122 can be reduced, and the carrier mobility in the channel region of the nanostructure 122 can be decreased. Furthermore, if the amorphous portion 110A is located above the bottom surface of the bottom nanostructure 122-1, the nanostructure 122 can contact the amorphous portion 110A, the device current between the nanostructure 122 and the S / D structure 110 can be reduced, and the device performance can be degraded.

[0050] In some embodiments, the crystalline portion 110B of the S / D structure 110 may include one or more epitaxial layers, wherein each epitaxial layer may have a different composition. In some embodiments, each of the one or more epitaxial layers may include Si and differ from each other based on, for example, doping concentration and / or epitaxial growth process conditions. In some embodiments, each of the one or more epitaxial layers may include silicon-germanium and differ from each other based on, for example, doping concentration, epitaxial growth process conditions and / or the relative concentration of germanium with respect to silicon.

[0051] In some embodiments, the formation of the S / D structure 110 may be followed by the deposition of ESL 116 and ILD layer 118, replacing the sacrificial gate structure 412 with a metal gate structure 112, and forming an S / D contact structure 130 on the S / D structure 110, as illustrated in Figure 2. In some embodiments, replacing the sacrificial gate structure 412 may include removing the sacrificial gate structure 412, removing the nanostructure 420, and depositing the metal gate structure 112. In some embodiments, after depositing the gate structure 112 and forming the S / D contact structure 130, a CMP process may planarize the top surfaces of the gate structure 112, the gate spacer 114, the ESL 116, and the ILD layer 118, as illustrated in Figure 2.

[0052] Various embodiments of this disclosure provide a method for forming a semiconductor seed layer 113 in an S / D dielectric structure 111 in a semiconductor device 100. In some embodiments, a nanostructure 122 stacked on a fin structure 108 may be formed on a substrate 104. A recess 108r may be formed adjacent to the nanostructure 122 in the fin structure 108. The S / D dielectric structure 111 and the semiconductor seed layer 113 may be formed in the recess 108r. The S / D dielectric structure 111 and the semiconductor seed layer 113 may be attached below the bottom surface of the bottom nanostructure 122-1. An S / D structure 110 may be formed on the top surface of the S / D dielectric structure 111 and the semiconductor seed layer 113. The S / D structure 110 may include an amorphous portion 110A and a crystalline portion 110B. The crystalline portion 110B can contact the nanostructure 122, and the amorphous portion 110A can be attached below the bottom surface of the bottom nanostructure 122-1. Through the S / D dielectric structure 111, the semiconductor seed layer 113, and the amorphous portion 110A of the S / D structure 110 below the bottom surface of the bottom nanostructure 122-1, the resistance between the S / D structure 110 and the nanostructure 122 can be reduced. The carrier mobility in the S / D structure 110 can be increased. The strain applied to the nanostructure 122 by the S / D structure 110 can be increased. Therefore, the DC device performance of the semiconductor device 100 can be improved.

[0053] In some embodiments, a semiconductor structure includes: a channel structure on a substrate; a gate structure covering the channel structure; an internal spacer adjacent to a plurality of end portions of the gate structure and the channel structure; a dielectric structure on the substrate and adjacent to the internal spacer; an amorphous semiconductor material on the dielectric structure; and an epitaxial structure on the amorphous semiconductor material and a plurality of top surfaces of the dielectric structure.

[0054] In some embodiments, a semiconductor device includes a first channel structure and a second channel structure stacked on a fin structure, and a dielectric structure on the fin structure and between the first channel structure and the second channel structure. The dielectric structure extends into the fin structure and is attached to an amorphous semiconductor material below the first channel structure and the second channel structure, on the dielectric structure, and to a source / drain (S / D) structure on the top surface of the amorphous semiconductor material. The S / D structure is adjacent to the amorphous semiconductor material and the dielectric structure.

[0055] In some embodiments, a method includes: forming a channel structure stacked on a fin structure on a substrate; forming a recess in the fin structure adjacent to the channel structure; depositing a dielectric material in the recess on the fin structure; depositing an amorphous semiconductor material on the dielectric material; removing a portion of the dielectric material to form a dielectric structure; and growing an epitaxial structure on a plurality of top surfaces of the amorphous semiconductor material and the dielectric structure.

[0056] It should be understood that the [Implementation] section, and not the [Abstract] section, is not intended to interpret the scope of the claim. The [Abstract] section may describe one or more, but not all, possible embodiments of this disclosure as anticipated by the discloser, and is therefore not intended to limit the scope of the supplementary claim in any way.

[0057] The foregoing disclosure summarizes the features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure. [Simplified Explanation of the Diagram]

[0004] The present disclosure is best understood from the following detailed description when read in conjunction with the accompanying drawings. Figure 1 illustrates an isometric view of a semiconductor device having a semiconductor seed layer on a source / drain dielectric structure according to some embodiments. Figure 2 illustrates a cross-sectional view of a semiconductor device having a semiconductor seed layer on a source / drain dielectric structure according to some embodiments. Figure 3 is a flowchart of a method for manufacturing a semiconductor device having a semiconductor seed layer on a source / drain dielectric structure according to some embodiments. Figures 4 through 12 illustrate cross-sectional views of a semiconductor device having a semiconductor seed layer on a source / drain dielectric structure according to some embodiments at various manufacturing stages. Illustrative embodiments will now be described with reference to the accompanying drawings. In the drawings, similar reference numerals generally indicate identical, functionally similar, and / or structurally similar elements. [Biomaterial Storage]

[0059] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A semiconductor structure comprising: a channel structure on a substrate; a gate structure covering the channel structure; an internal spacer adjacent to a plurality of end portions of the gate structure and the channel structure; a dielectric structure on the substrate and adjacent to the internal spacer; an amorphous semiconductor material on the dielectric structure; and an epitaxial structure on a plurality of top surfaces of the amorphous semiconductor material and on the dielectric structure.

2. The semiconductor structure as claimed in claim 1, wherein one of the top surfaces of the dielectric structure is located below a bottom surface of the channel structure.

3. The semiconductor structure as claimed in claim 1, wherein the ratio of the thickness of one dielectric structure to the thickness of one channel structure ranges from about 0.2 to about 0.

8.

4. The semiconductor structure as claimed in claim 1, wherein the epitaxial structure comprises an amorphous portion on the amorphous semiconductor material and a crystalline portion on the amorphous portion.

5. A semiconductor device comprising: a first channel structure and a second channel structure stacked on a fin structure; a dielectric structure on the fin structure and between the first channel structure and the second channel structure, wherein the dielectric structure extends into the fin structure and below the first channel structure and the second channel structure; an amorphous semiconductor material on the dielectric structure; and a source / drain structure on a top surface of the amorphous semiconductor material, wherein the source / drain structure is adjacent to the amorphous semiconductor material and the dielectric structure.

6. The semiconductor device as claimed in claim 5, wherein one of the top surfaces of the dielectric structure is located below a plurality of bottom surfaces of the first channel structure and the second channel structure.

7. The semiconductor device as claimed in claim 5, wherein the ratio of the thickness of one of the dielectric structures to the thickness of one of the first channel structures or the second channel structures ranges from about 0.2 to about 0.

8.

8. A method of forming a semiconductor device, comprising the steps of: forming a channel structure stacked on a fin structure on a substrate; forming a recess in the fin structure adjacent to the channel structure; depositing a dielectric material in the recess on the fin structure; depositing an amorphous semiconductor material on the dielectric material; removing a portion of the dielectric material to form a dielectric structure; and growing an epitaxial structure on a plurality of top surfaces of the amorphous semiconductor material and the dielectric structure.

9. The method as described in claim 8, wherein the step of depositing the dielectric material comprises the following steps: conformally depositing the dielectric material on the channel structure and the fin structure.

10. The method of claim 8, wherein the step of removing the portion of the dielectric material comprises the following steps: treating a top portion of the amorphous semiconductor material to form a dielectric layer; and etching the dielectric layer on the amorphous semiconductor material and the dielectric material on the channel structure to expose the top surface of the amorphous semiconductor material.

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