Data voltage generating circuit and method, source driver and display device

Abstract

A data voltage generation circuit and method for a display device, a source driver, and a display device are disclosed. The data voltage generation circuit for the display device includes: an analog-to-digital converter (ADC) configured to convert an input power supply voltage into a power supply voltage code; an offset value determination module configured to determine, at least partially, an offset value for adjusting a grayscale mapping value based on the power supply voltage code, wherein the grayscale mapping value is a mapping value corresponding to grayscale data; a grayscale mapping value adjustment module configured to adjust the grayscale mapping value based on the offset value to generate an adjusted mapping value; and a digital-to-analog converter (DAC) configured to generate a data voltage for driving data lines based on the adjusted mapping value.

Description

[Technical Field]

[0001] The present invention relates generally to the field of display technology, and more specifically to a data voltage generation circuit and a data voltage generation method, a source driver and a display device. [Previous Technology]

[0002] In AMOLED (Active Matrix Organic Light Emitting Diode) display technology, the luminous brightness of each sub-pixel mainly depends on the power supply voltage and data voltage applied to the sub-pixel driving circuit. Typically, the power supply voltage is provided by a dedicated power module outside the display panel, and ideally, the power supply voltage should have a fixed value. However, due to factors such as trace resistance, the power supply voltage applied to the sub-pixel driving circuit will deviate, thus affecting the display brightness of the sub-pixels and consequently the display quality of the screen.

[0003] Therefore, it is necessary to control and compensate for the deviation of the power supply voltage in order to achieve a higher quality display effect. [Summary of the Invention]

[0004] According to one aspect of the present invention, a data voltage generation circuit for a display device is provided, comprising: an analog-to-digital converter (ADC) configured to convert an input power supply voltage into a power supply voltage code; an offset value determination module configured to determine, at least in part, an offset value for adjusting a grayscale mapping value based on the power supply voltage code, wherein the grayscale mapping value is a mapping value corresponding to grayscale data; a grayscale mapping value adjustment module configured to adjust the grayscale mapping value based on the offset value to generate an adjusted mapping value; and a digital-to-analog converter (DAC) configured to generate a data voltage for driving a data line based on the adjusted mapping value.

[0005] According to another aspect of the present invention, a source driver is also provided, comprising: a data voltage generation circuit as described above; and a plurality of source buffers configured to receive the data voltage generated by the data voltage generation circuit and apply the data voltage to corresponding data lines.

[0006] According to another aspect of the present invention, a display device is also provided, comprising: a display panel; and a source driver as described above for driving the display panel.

[0007] According to another aspect of the present invention, a method for generating a data voltage for a display device is also provided, comprising: converting an input power supply voltage into a power supply voltage code; determining, at least in part, an offset value for adjusting a grayscale mapping value based on the power supply voltage code, wherein the grayscale mapping value is a mapping value corresponding to grayscale data; adjusting the grayscale mapping value based on the offset value to generate an adjusted mapping value; and generating a data voltage for driving a data line based on the adjusted mapping value.

[0008] The data voltage generation circuit and method according to embodiments of the present invention can adjust the magnitude of the data voltage based on the deviation of the power supply voltage to compensate for the power supply voltage deviation, so that the voltage difference between the power supply voltage and the data voltage remains constant when the power supply voltage changes, thereby ensuring the display brightness of the sub-pixels and improving the display quality. Furthermore, by converting the power supply voltage into digital voltage codes to calculate the offset value for adjusting the grayscale mapping value, even if different power supply voltages are provided for sub-pixels of different colors, a single compensation circuit can be used to compensate for the deviation of different power supply voltages for different color sub-pixels, reducing the number of required components and effectively reducing the size and cost of the DDIC.

Implementation Method

[0010] It should be understood that other embodiments may be utilized and structural changes may be made without departing from the scope of the invention. Furthermore, it should be understood that the wording and terminology used herein are for descriptive purposes and should not be considered limiting. The use of “comprising,” “including,” or “having,” and variations thereof, is intended to cover the items listed thereafter and their equivalents, as well as additional items. Unless otherwise limited, the term “connection” and its variations herein are used broadly and cover both direct and indirect connections, and may include electrical or physical connections.

[0011] Figure 1 shows an exemplary circuit diagram of an AMOLED sub-pixel driving circuit 100 for driving a single sub-pixel.

[0012] As shown in Figure 1, the AMOLED sub-pixel driving circuit 100 includes a switching thin-film transistor (TFT) Q1 used as a sub-pixel switch, a driving TFT Q2 used to control the driving current through the sub-pixel, and a capacitor C used for voltage holding. After a driving signal is applied to the gate terminal of Q1 to control Q1 to conduct, the data voltage applied to the source terminal can drive Q2 to generate a driving current Id that flows through the light-emitting diode LED1 to drive LED1 to emit light. The magnitude of the driving current Id flowing through LED1 is determined by the power supply voltage ELVDD and the data voltage. More specifically, the magnitude of the driving current Id is equal to , where k is a constant related to the characteristics of Q2, is the power supply voltage ELVDD, is the data voltage, and is the threshold voltage of Q2. It can be seen from the above formula that the magnitude of the driving current Id is actually determined by the voltage difference between the power supply voltage ELVDD and the data voltage.

[0013] Typically, the power supply voltage ELVDD (and another power supply voltage ELVSS shown in Figure 1) is provided by a dedicated power supply module outside the display panel. However, due to factors such as the trace resistance between the power supply module and the display panel, the power supply voltage ELVDD applied to the sub-pixel driving circuit will deviate, thus affecting the magnitude of the driving current and consequently the display brightness of the sub-pixels. Furthermore, since the power supply modules and trace resistance used by the panel manufacturer and the terminal manufacturer may differ, this difference will cause deviations in the optical characteristics that have been adjusted at the panel manufacturer after the display panel is applied to the terminal at the terminal manufacturer. This may also lead to deviations in the power supply voltage ELVDD. Therefore, it is necessary to compensate for the deviation in the power supply voltage ELVDD to ensure display quality.

[0014] Figure 2 shows a schematic diagram of a data voltage generation circuit 200 for a display device in the prior art. As shown in Figure 2, the data voltage generation circuit 200 includes a mapping module 201, a digital-to-analog converter (DAC) 202, and a voltage generator 203. The mapping module 201 stores a mapping table that records the correspondence between grayscale data and grayscale mapping values. For example, Figure 2 shows a mapping table 2011 as an example, which records a 12-bit grayscale mapping value corresponding to each grayscale data from 0 to 255. Accordingly, the mapping module 201 can output a grayscale mapping value corresponding to the input grayscale data based on the stored mapping table.

[0015] This grayscale mapping value can then be used by the digital-to-analog converter (DAC) 202 to select the corresponding voltage from the voltages provided by the voltage generator 203 as the data voltage Vdata for output. More specifically, as shown in Figure 2, there is a resistor string 2031 inside the voltage generator 203, which is formed by multiple resistors connected in series. The highest reference voltage and the lowest reference voltage are applied to the head and tail of the resistor string 2031, respectively. Furthermore, multiple output nodes 2032 corresponding to different output voltage magnitudes are provided on the resistor string 2031. Thus, the voltage generator 203 can output multiple voltages of different magnitudes to the DAC 202. The grayscale mapping value output by the mapping module 201 can be used to select the corresponding voltage from the multiple voltages provided by the voltage generator 203 as the data voltage Vdata output by the DAC 202.

[0016] It should be noted that the data voltage generation circuit 200 shown in Figure 2 is only an example. In fact, the data voltage generation circuit 200 may include more or fewer modules or components, which is not limited here.

[0017] Figure 3 illustrates an exemplary architecture 300 for providing power voltages to a plurality of sub-pixels on a display panel. As shown in Figure 3, the display panel 301 includes a plurality of red, green, or blue R / G / B sub-pixels, and provides power voltages ELVDD and ELVSS to these sub-pixels via a power module 302, wherein each sub-pixel shares the same power voltages ELVDD and ELVSS.

[0018] Referring again to Figure 2, in the prior art, in order to compensate for power supply voltage deviation, a deviation compensation circuit (not shown) can be used. This deviation compensation circuit can detect the magnitude of the power supply voltage ELVDD in real time and compare it with the power supply voltage ELVDD reference value to obtain the deviation of the power supply voltage ELVDD. Based on this deviation, the highest and lowest reference voltages of the digital-to-analog converter DAC 202 are adjusted to change the magnitude of the data voltage output by the digital-to-analog converter DAC 202. As mentioned above, since the magnitude of the drive current is determined by the voltage difference between the power supply voltage ELVDD and the data voltage, the deviation of the power supply voltage ELVDD can be compensated by adjusting the magnitude of the data voltage, keeping the voltage difference constant to ensure the display brightness of the sub-pixels. When using the architecture shown in Figure 3 to provide power supply voltage to the sub-pixels, since each sub-pixel shares the same power supply voltage ELVDD, the deviation of the power supply voltage ELVDD applied to all sub-pixels can be compensated using only a single deviation compensation circuit.

[0019] However, to reduce power consumption, it is possible to use an architecture different from Figure 3 to provide different power supply voltages ELVDD for sub-pixels of different colors. Specifically, due to the different material properties of organic light-emitting diodes (OLEDs) of different colors, OLEDs of different colors will have different luminous efficiencies, with green OLEDs having the highest luminous efficiency, followed by red OLEDs, and blue OLEDs having the lowest luminous efficiency. Accordingly, in order to drive RGB sub-pixels to emit light to display a full white image, the voltage difference between the power supply voltage ELVDD and the data voltage required to drive the green sub-pixel will be less than the voltage difference required to drive the red sub-pixel, and both will be less than the voltage difference required to drive the blue sub-pixel. Based on the above principle, different power supply voltages ELVDD can be provided for sub-pixels of different colors, and the power supply voltages ELVDD for green and red sub-pixels can be reduced to reduce power consumption. Accordingly, Figure 4 shows another exemplary architecture 400 for providing power supply voltages to multiple sub-pixels on a display panel. As shown in Figure 4, specific power supply voltages ELVDD_R, ELVDD_G, and ELVDD_B are provided for red, green, and blue sub-pixels respectively. By utilizing the architecture shown in Figure 4 to apply a lower power supply voltage ELVDD to the green and red sub-pixels, power consumption can be reduced while the current remains constant, whereas the architecture shown in Figure 3 allows sub-pixels of different colors to share the same power supply voltage ELVDD.

[0020] However, if the architecture of Figure 4 is used to provide specific power supply voltages ELVDD for sub-pixels of different colors, and the method of adjusting the highest and lowest reference voltages of the digital-to-analog converter (DAC) is still used to compensate for the deviation of the power supply voltage ELVDD, then three deviation compensation circuits are required to compensate for the deviations of ELVDD_R, ELVDD_G and ELVDD_B respectively. This will greatly increase the size and cost of the display driver integrated circuit (DDIC).

[0021] To this end, the present invention proposes a novel data voltage generation circuit with power supply voltage ELVDD deviation compensation function. It can achieve that even if the architecture of Figure 4 is used to provide different power supply voltages ELVDD for different color sub-pixels, a single compensation circuit can be used to compensate for the deviation of different power supply voltages ELVDD for different color sub-pixels, thereby reducing the number of required components and effectively reducing the size and cost of DDIC.

[0022] In the following text, for the purpose of simplification, “power supply voltage ELVDD” will be referred to as “power supply voltage”, and unless otherwise expressly indicated, “power supply voltage” as used herein refers to power supply voltage ELVDD.

[0023] Figure 5 shows a schematic diagram of a data voltage generation circuit 500 for a display device with power supply voltage deviation compensation function according to an embodiment of the present invention.

[0024] As shown in Figure 5, compared to the data voltage generation circuit 200 shown in Figure 2, in addition to the mapping module 501 and the digital-to-analog converter DAC 502, the data voltage generation circuit 500 according to an embodiment of the present invention may further include an analog-to-digital converter ADC 503, an offset value determination module 504, and a grayscale mapping value adjustment module 505. The specific details of the mapping module 501 and the digital-to-analog converter DAC 502 are the same as those described for the mapping module 201 and the digital-to-analog converter DAC 202 in Figure 2, and will not be repeated here. Furthermore, to avoid obscuring the focus of the present invention, the voltage generator (e.g., voltage generator 203) for providing multiple voltages to the DAC for its selective output is omitted in Figure 5 and the subsequent Figure 6, and those skilled in the art will understand that such a voltage generator may be included in the data voltage generation circuit according to an embodiment of the present invention to provide multiple voltages of different magnitudes to the DAC.

[0025] The analog-to-digital converter (ADC) 503 can be configured to convert an input power supply voltage in analog form into a power supply voltage code in digital form. The input power supply voltage is the actual value of the power supply voltage applied to the sub-pixel. When applying the same power supply voltage to each sub-pixel using the architecture shown in Figure 3, the ADC 503 only needs to convert a single power supply voltage into a single power supply voltage code. However, the invention is not limited to this. As previously mentioned, the architecture of Figure 4 may also be used to provide different power supply voltages for sub-pixels of different colors. In this case, the power supply voltages shown in Figure 5 may include power supply voltages ELVDD_R, ELVDD_G, and ELVDD_B for red, green, and blue sub-pixels, respectively, and the ADC 503 needs to convert all three power supply voltages into their corresponding power supply voltage codes. In one example, the analog-to-digital converter ADC 503 can convert the three power supply voltages in a time-division manner, for example, converting ELVDD_R, ELVDD_G and ELVDD_B into the corresponding power supply voltage codes one by one in sequence. Therefore, the analog-to-digital converter ADC 503 can be implemented by a single analog-to-digital converter ADC.

[0026] However, in another example, to accelerate the conversion speed for real-time calculation and compensation, multiple analog-to-digital converters (ADCs) can be used to synchronously convert multiple power supply voltages respectively. Figure 6 shows a schematic diagram of another data voltage generation circuit 600 for a display device with power supply voltage deviation compensation function according to an embodiment of the present invention. As shown in Figure 6, three analog-to-digital converters (ADCs) 503_1, 503_2, and 503_3 convert the power supply voltages ELVDD_R, ELVDD_G, and ELVDD_B for the red, green, and blue sub-pixels, respectively. Furthermore, Figure 6 specifically illustrates how the offset value determination module 504 determines the offset values ​​OFFSET_R, OFFSET_G, and OFFSET_B corresponding to the red, green, and blue sub-pixels based on the power supply voltage codes corresponding to the red, green, and blue sub-pixels converted by the analog-to-digital converters ADCs 503_1, 503_2, and 503_3. This allows for the adjustment of the grayscale mapping values ​​of the red, green, and blue sub-pixels to obtain the data voltages Vdata_R, Vdata_G, and Vdata_B used to drive the red, green, and blue sub-pixels. The components shown in Figure 6 can be implemented based on the specific details of the corresponding components described in Figure 5 (for example, the mapping modules 501_1, 501_2, and 501_3 shown in Figure 6 can be implemented based on the specific details of the mapping module 501 described in Figure 5), and will not be elaborated further hereafter.

[0027] Continuing with Figure 5, the offset value determination module 504 can be configured to determine, at least in part, an offset value for adjusting the grayscale mapping value based on the power supply voltage code output from the analog-to-digital converter ADC 503 and a power supply voltage code reference value, wherein the power supply voltage code reference value can be a digital reference value determined based on an analog power supply voltage reference value. As previously described, when using the architecture of Figure 4 to provide different power supply voltages for sub-pixels of different colors, the power supply voltage code and the power supply voltage code reference value can include multiple power supply voltage codes and multiple power supply voltage code reference values ​​corresponding to a specific sub-pixel color (e.g., red, green, or blue), and the offset value determination module 504 can determine the offset value corresponding to the specific sub-pixel color based on the power supply voltage code and the power supply voltage code reference value corresponding to the specific sub-pixel color.

[0028] Specific details of the offset value determination module 504 according to an embodiment of the present invention will now be described. Figure 7 shows an exemplary module diagram of the offset value determination module 504 according to an embodiment of the present invention. As shown in Figure 7, the offset value determination module 504 may include a voltage difference determination module 701 and a voltage difference conversion module 702, wherein the voltage difference determination module 701 may be configured to determine the voltage difference at least in part based on the power supply voltage code output from the analog-to-digital converter ADC 503 and a power supply voltage code reference value, while the voltage difference conversion module 702 may be configured to convert the voltage difference output from the voltage difference determination module 701 into an offset value for adjusting the grayscale mapping value.

[0029] In determining the voltage difference, the voltage difference determination module 701 can first calculate the voltage code deviation based on the difference between the power supply voltage code and the power supply voltage code reference value, and then convert the voltage code deviation into a voltage difference based on the operating parameters of the analog-to-digital converter (ADC) 503. More specifically, assuming is the power supply voltage code, is the power supply voltage code reference value, and and are the top voltage and bottom voltage of the ADC 503 respectively (their magnitude is determined by the range of power supply voltage variation), and K is the number of bits of the ADC 503 (that is, the ADC 503 can convert analog voltages ranging from to into K-bit digital voltage codes ranging from 0 to 2K-1), then the voltage difference determination module 701 can determine the voltage code deviation as and determine the voltage per code of the ADC 503 as , and then multiply the voltage code deviation by the voltage per code to obtain the voltage difference, as follows:

[0030] Subsequently, the voltage difference conversion module 702 can be configured to convert the voltage difference into an offset value for adjusting the grayscale mapping value based on the operating parameters of the digital-to-analog converter DAC 502. More specifically, assuming that VGMP and VGSP are the highest and lowest reference voltages of the digital-to-analog converter DAC 502, respectively, and N is the number of bits of the digital-to-analog converter DAC 502 (that is, the digital-to-analog converter DAC 502 can convert N-bit grayscale mapping values ​​ranging from 0 to 2N-1 into analog voltages ranging from VGMP to VGSP, where the magnitudes of the VGMP and VGSP voltages are determined by the brightness range of the display panel), then the voltage difference conversion module 702 can determine the per-code voltage of the digital-to-analog converter DAC 502 as VGMP, and then divide the voltage difference by this per-code voltage to obtain the offset value for adjusting the grayscale mapping value, as follows:

[0031] Figure 8 shows a schematic diagram of the hardware circuit implementation of the voltage difference determination module 701 and the voltage difference conversion module 702 according to an embodiment of the present invention.

[0032] As shown in Figure 8, the voltage difference determination module 701 may include a subtractor 801, a multiplier 802, and a shifter 803. The subtractor 801 can be used to subtract the power supply voltage code from the power supply voltage code reference value to obtain the voltage code deviation. The multiplier 802 can be used to multiply the voltage code deviation by a , and the shifter 803 can be used to right-shift the result output by the multiplier 802 by K bits (equivalent to division in binary arithmetic). The voltage difference conversion module 702 may include a shifter 804 and a multiplier 805. The shifter 804 can left-shift the result output by the voltage difference determination module 701 by N bits (equivalent to multiplication in binary arithmetic), and the multiplier 805 can multiply the result output by the shifter 804 by a .

[0033] It should be noted that the hardware circuit implementation shown in Figure 8 is only schematic. The voltage difference determination module 701 and voltage difference conversion module 702 according to the embodiments of the present invention can also be implemented in other ways. For example, the order of some devices shown in Figure 8 can be changed, which is not limited here.

[0034] Referring again to Figure 5, after the offset value determination module 504 determines and outputs the offset value to the grayscale mapping value adjustment module 505, the grayscale mapping value adjustment module 505 can be configured to adjust the grayscale mapping value based on the offset value to produce an adjusted mapping value. More specifically, the grayscale mapping value adjustment module 505 can correspondingly increase or decrease the grayscale mapping value based on the offset value to obtain the adjusted mapping value. In one example, the grayscale mapping value adjustment module 505 can be implemented using an adder / subtractor.

[0035] Subsequently, after the grayscale mapping value adjustment module 505 outputs the adjusted mapping value to the digital-to-analog converter DAC 502, the digital-to-analog converter DAC 502 can generate the data voltage Vdata for driving the data line based on the adjusted mapping value.

[0036] In summary, the data voltage generation circuit according to embodiments of the present invention can adjust the magnitude of the data voltage based on the deviation of the power supply voltage to compensate for the deviation, so that the voltage difference between the power supply voltage and the data voltage remains constant when the power supply voltage changes, thereby ensuring the display brightness of the sub-pixels and improving the display quality. Furthermore, by converting the power supply voltage into digital voltage codes to calculate the offset value for adjusting the grayscale mapping value, even if different power supply voltages are provided for sub-pixels of different colors, a single compensation circuit can be used to compensate for the deviation of different power supply voltages for different color sub-pixels, reducing the number of required components and effectively reducing the size and cost of the DDIC.

[0037] Hereinafter, a source driver according to an embodiment of the present invention will be described, which may include: the data voltage generation circuit according to the embodiment of the present invention described above; and a plurality of source buffers, which may be configured to receive data voltage generated by the data voltage generation circuit and apply the data voltage to corresponding data lines for display. The source buffers may be used to increase the current or voltage driving capability of the output signal to adapt to external loads (e.g., data lines on a display panel).

[0038] Additionally, a display device according to an embodiment of the present invention is described, which may include: a display panel, and the source driver described above according to an embodiment of the present invention, for driving the display panel.

[0039] Hereinafter, a data voltage generation method for a display device according to an embodiment of the present invention will be described. Figure 9 illustrates a data voltage generation method 900 for a display device capable of power supply voltage deviation compensation according to an embodiment of the present invention.

[0040] As shown in Figure 9, in step S901, the input power supply voltage can be converted into a power supply voltage code.

[0041] In this step, the input power supply voltage is the actual value of the power supply voltage applied to the sub-pixel. As mentioned earlier, when applying the same power supply voltage to each sub-pixel using the architecture shown in Figure 3, it is only necessary to convert the input single power supply voltage into a single power supply voltage code. However, the present invention is not limited to this. As mentioned earlier, the architecture of Figure 4 can also be used to provide different power supply voltages for sub-pixels of different colors. In this case, it is necessary to convert all of these power supply voltages into corresponding power supply voltage codes.

[0042] In step S902, the offset value for adjusting the grayscale mapping value can be determined at least in part based on the power supply voltage code, wherein the grayscale mapping value is the mapping value corresponding to the grayscale data.

[0043] In this step, determining the offset value for adjusting the grayscale mapping value based at least in part on the power supply voltage code may include: determining the voltage difference based at least in part on the power supply voltage code and the power supply voltage code reference value; and converting the voltage difference into an offset value for adjusting the grayscale mapping value.

[0044] When determining the voltage difference, the voltage code deviation can first be calculated based on the difference between the power supply voltage code and the power supply voltage code reference value. Then, based on the operating parameters of the analog-to-digital converter (ADC) used to convert the input power supply voltage into a power supply voltage code (e.g., the analog-to-digital converter ADC 503 described above), this voltage code deviation can be converted into a voltage difference. More specifically, the voltage difference can be calculated using the following formula:

[0045] where is the power supply voltage code, is the power supply voltage code reference value, and are the top voltage and bottom voltage of the analog-to-digital converter (ADC), respectively, and K is the number of bits of the analog-to-digital converter (ADC).

[0046] Subsequently, the voltage difference can be converted into an offset value for adjusting the grayscale mapping value based on the operating parameters of the digital-to-analog converter DAC (e.g., the digital-to-analog converter DAC 502 described above) used to generate the data voltage. More specifically, the offset value can be calculated using the following formula:

[0047] wherein, is the bias transfer, is the voltage difference, and are the highest and lowest reference voltages of the digital-to-analog converter (DAC), respectively, and N is the number of bits of the DAC.

[0048] In step S903, the grayscale mapping value can be adjusted based on the offset value to generate an adjusted mapping value. In this step, the grayscale mapping value can be increased or decreased accordingly based on the offset value to obtain the adjusted mapping value.

[0049] In step S904, a data voltage for driving the data line can be generated based on the adjusted mapping value.

[0050] In summary, the data voltage generation method according to embodiments of the present invention can adjust the magnitude of the data voltage based on the deviation of the power supply voltage to compensate for the deviation, so that the voltage difference between the power supply voltage and the data voltage remains constant when the power supply voltage changes, thereby ensuring the display brightness of the sub-pixels and improving the display quality. Furthermore, by converting the power supply voltage into digital voltage codes to calculate the offset value for adjusting the grayscale mapping value, even if different power supply voltages are provided for sub-pixels of different colors, a single compensation circuit can be used to compensate for the deviation of different power supply voltages for different color sub-pixels, reducing the number of required components and effectively reducing the size and cost of the DDIC.

[0051] The basic principles of the present invention have been described above with reference to specific embodiments. It should be noted that the advantages, benefits, and effects mentioned in the embodiments of the present invention are merely examples and not limitations, and should not be considered as essential features of each embodiment of the present invention. Furthermore, the specific details disclosed above are for illustrative and facilitative purposes only, and are not limitations; the above details do not limit the present invention to the necessity of employing the above specific details. It should also be noted that in the apparatus and method of the present invention, the components or steps can be decomposed and / or recombined. These decompositions and / or recombinations should be considered equivalent solutions of the present invention.

[0052] It will be understood by those skilled in the art that all or any part of the methods and apparatus of the present invention can be implemented in hardware, firmware, software, or a combination thereof in any computing device (including processors, storage media, etc.) or network of computing devices. The hardware can be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device (PLD), discrete gate or transistor logic, discrete hardware components, or any combination thereof, designed to perform the functions described herein. The general-purpose processor can be a microprocessor, but alternatively, it can be any commercially available processor, controller, microcontroller, or state machine. The processor can also be implemented as a combination of computing devices, such as a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors cooperating with a DSP core, or any other such configuration. The software can reside in any form of computer-readable tangible storage medium. By way of example and not limitation, such computer-readable tangible storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage, disk storage or other magnetic storage devices, or any other tangible medium that may be used to carry or store desired program code in the form of instructions or data structures and that may be accessible by a computer. As used herein, disks include compact discs (CDs), laser discs, optical discs, digital versatile discs (DVDs), magnetic discs, and Blu-ray discs.

[0053] The block diagrams of elements, components, devices, apparatuses, and systems involved in the embodiments of the present invention are merely illustrative examples and are not intended to require or imply that they must be connected, arranged, or configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these elements, components, devices, apparatuses, and systems can be connected, arranged, and configured in any manner.

[0054] Furthermore, the scope of protection claimed by the present invention is not limited to the specific aspects of the processes, machines, manufacturing, events, means, methods, and actions described above. Currently existing or later-developed processes, machines, manufacturing, events, means, methods, or actions that perform substantially the same functions or achieve substantially the same results as the corresponding aspects described herein can be utilized.

[0055] Furthermore, words such as “including,” “contains,” “has,” etc., are open-ended terms meaning “including but not limited to,” and are used interchangeably with them. The words “or” and “and” as used herein refer to the words “and / or,” and are used interchangeably with them unless the context explicitly indicates otherwise. The word “such as” as used herein refers to the phrase “such as but not limited to,” and is used interchangeably with it.

[0056] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the invention. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the invention. Therefore, the invention is not intended to be limited to the aspects shown herein, but rather to be carried out within the widest scope consistent with the principles and novel features disclosed herein. The above description is merely a preferred embodiment of the invention, and all equivalent variations and modifications made within the scope of the claims of this invention should be considered within the scope of this invention. [Simplified Explanation of the Diagram]

[0009] Figure 1 shows an exemplary circuit diagram of an AMOLED sub-pixel driving circuit 100 for driving a single sub-pixel. Figure 2 shows a schematic diagram of a data voltage generation circuit 200 for a display device in the prior art. Figure 3 shows an exemplary architecture 300 for providing power supply voltage to a plurality of sub-pixels on a display panel. Figure 4 shows another exemplary architecture 400 for providing power supply voltage to a plurality of sub-pixels on a display panel. Figure 5 shows a schematic diagram of a data voltage generation circuit 500 for a display device with power supply voltage deviation compensation function according to an embodiment of the present invention. Figure 6 shows a schematic diagram of another data voltage generation circuit 600 for a display device with power supply voltage deviation compensation function according to an embodiment of the present invention. Figure 7 shows an exemplary module diagram of an offset value determination module 504 according to an embodiment of the present invention. Figure 8 shows a schematic diagram of the hardware circuit implementation of a voltage difference determination module 701 and a voltage difference conversion module 702 according to an embodiment of the present invention. Figure 9 shows a data voltage generation method 900 for a display device capable of implementing power supply voltage deviation compensation according to an embodiment of the present invention.

Claims

1. A data voltage generation circuit for a display device, comprising: An analog-to-digital converter (ADC) is configured to convert an input power supply voltage into a power supply voltage code. An offset value determination module is configured to determine, at least in part, an offset value for adjusting a grayscale mapping value based on the power supply voltage code, wherein the grayscale mapping value is a mapping value corresponding to grayscale data; a grayscale mapping value adjustment module is configured to adjust the grayscale mapping value based on the offset value to generate an adjusted mapping value; and a digital-to-analog converter (DAC) is configured to generate a data voltage for driving data lines based on the adjusted mapping value.

2. The data voltage generation circuit as described in claim 1, wherein, The offset value determination module includes: a voltage difference determination module configured to determine the voltage difference based at least in part on the power supply voltage code and a power supply voltage code reference value; and a voltage difference conversion module configured to convert the voltage difference into the offset value for adjusting the grayscale mapping value.

3. The data voltage generation circuit as described in claim 2, wherein, The voltage difference determination module is configured to determine the voltage difference based on the power supply voltage code, the power supply voltage code reference value, and the operating parameters of the analog-to-digital converter (ADC).

4. The data voltage generation circuit as described in claim 3, wherein, The voltage difference determination module determines the voltage difference as: where is the voltage difference, is the power supply voltage code, is the power supply voltage code reference value, and are the top voltage and bottom voltage of the analog-to-digital converter (ADC) respectively, and K is the number of bits of the analog-to-digital converter (ADC).

5. The data voltage generation circuit as described in claim 2, wherein, The voltage difference conversion module is configured to convert the voltage difference into an offset value for adjusting the grayscale mapping value based on the operating parameters of the digital-to-analog converter (DAC).

6. The data voltage generation circuit as described in claim 5, wherein, The voltage difference conversion module determines the offset value as: where and are the highest and lowest reference voltages of the digital-to-analog converter (DAC), respectively, and N is the number of bits of the DAC.

7. The data voltage generation circuit as described in any one of claims 1-6, wherein, The power supply voltage includes multiple power supply voltages specific to the sub-pixel color; and the analog-to-digital converter (ADC) includes a single analog-to-digital converter (ADC) that converts the multiple power supply voltages in a time-division manner, or the analog-to-digital converter (ADC) includes multiple analog-to-digital converters (ADCs) that convert the multiple power supply voltages individually.

8. The data voltage generation circuit as described in any one of claims 1-6, wherein, The data voltage generation circuit also includes a mapping module configured to generate the grayscale mapping value based on the input grayscale data and a pre-configured mapping table.

9. A source driver, comprising: The data voltage generation circuit as described in any one of claims 1-8; In addition, multiple source buffers are configured to receive the data voltage generated by the data voltage generation circuit and apply the data voltage to the corresponding data lines.

10. A display device, comprising: Display panel; And a source driver as described in claim 9, for driving the display panel.

11. A method for generating data voltage for a display device, comprising: Convert the input power supply voltage into a power supply voltage code; An offset value for adjusting the grayscale mapping value is determined at least in part based on the power supply voltage code, wherein the grayscale mapping value is the mapping value corresponding to the grayscale data; the grayscale mapping value is adjusted based on the offset value to produce an adjusted mapping value; And, based on the adjusted mapping value, a data voltage for driving the data line is generated; wherein, determining the offset value for adjusting the grayscale mapping value based at least in part on the power supply voltage code includes: determining a voltage difference based at least in part on the power supply voltage code and a power supply voltage code reference value; and converting the voltage difference into the offset value for adjusting the grayscale mapping value; wherein, determining the voltage difference based at least in part on the power supply voltage code and the power supply voltage code reference value includes: determining the voltage difference based on the power supply voltage code, the power supply voltage code reference value, and the operating parameters of the analog-to-digital converter (ADC) for converting the input power supply voltage into a power supply voltage code.

12. The data voltage generation method as described in claim 11, wherein, The voltage difference is determined as: where is the voltage difference, is the power supply voltage code, is the power supply voltage code reference value, and are the top and bottom voltages of the analog-to-digital converter (ADC), respectively, and K is the number of bits of the analog-to-digital converter (ADC).

13. The data voltage generation method as described in claim 11, wherein, Converting the voltage difference into an offset value for adjusting the grayscale mapping value includes: converting the voltage difference into an offset value for adjusting the grayscale mapping value based on the operating parameters of the digital-to-analog converter (DAC) used to generate the data voltage.

14. The data voltage generation method as described in claim 13, wherein, The offset value is determined as: where is the offset value, is the voltage difference, and are the highest and lowest reference voltages of the digital-to-analog converter (DAC), respectively, and N is the number of bits of the DAC.

15. The data voltage generation method as described in any one of claims 11-14, further comprising: Before adjusting the grayscale mapping value based on the offset value, the grayscale mapping value is generated based on the input grayscale data and the pre-configured mapping table.