Passive noise-shaping successive-approximation analog-to-digital converter with residual amplification and associated method

Abstract

A passive noise-shaping successive approximation analog-to-digital converter (SAR ADC) includes a SAR ADC circuit and a passive noise-shaping circuit. The SAR ADC circuit converts an analog input signal and extracts the residual at the end of the conversion. The passive noise-shaping circuit processes the residual and feeds the processed residual back to the SAR ADC circuit. The passive noise-shaping circuit includes at least one passive element with an adjustable capacitor for performing residual amplification.

Description

Technical Field

[0001] This invention relates to the conversion of analog signals to digital signals, and more specifically, to a passive noise-shaping successive approximation (also known as successive approximation register) analog-to-digital converter (SAR ADC) with residual amplification and related methods. Prior Technology

[0002] SAR ADCs are popular in wireless applications due to their low power consumption and small footprint. Comparator noise and quantization noise are often the main noise sources limiting the signal-to-noise ratio (SNR). Recently, noise-shaping SAR ADCs have become popular because they can reduce these two noise sources through noise shaping, thereby improving SNR. Traditional SAR ADCs use the comparator output to successively determine the bits of the digital output by gradually bringing the output of the digital-to-analog converter (DAC) closer to the sampled input voltage. Due to the limited resolution of the DAC, a small difference, called the residual, still exists between the DAC output and the sampled input voltage at the end of the conversion. Therefore, the conversion residual naturally exists in SAR ADCs, and the essence of the noise-shaping SAR ADC architecture is to utilize this residual for noise shaping. Noise-shaping SAR ADCs can be divided into active noise-shaping SAR ADCs and passive noise-shaping SAR ADCs. Traditional active noise-shaping SAR ADCs use an active integrator implemented by an operational amplifier to amplify and integrate the residual. Therefore, traditional active noise-shaping SAR ADCs consume a lot of power and cannot meet the requirements of low-power applications. Traditional passive noise-shaping SAR ADCs use passive integrators, providing lossy integration and lossy signal gain. Specifically, in a traditional passive noise-shaping SAR ADC without residual amplification, the residual amplitude decreases with each charge sharing event. Furthermore, traditional passive noise-shaping SAR ADCs may require a comparator with additional input differential pairs to process the residual, which increases comparator noise. Therefore, an innovative passive noise-shaping SAR ADC design is needed that enables residual amplification using passive components without requiring a multi-input pair comparator. Summary of the Invention

[0003] One objective of this invention is to provide a passive noise-shaping successive approximation analog-to-digital converter (SAR ADC) with residual amplification function and related methods.

[0004] According to a first aspect of the present invention, an exemplary passive noise-shaping SAR ADC is disclosed. The exemplary passive noise-shaping SAR ADC includes a SAR ADC circuit and a passive noise-shaping circuit. The SAR ADC circuit is configured to convert an analog input signal and extract a residual at the end of the conversion. The passive noise-shaping circuit is configured to process the residual and feed the processed residual back to the SAR ADC circuit. The passive noise-shaping circuit includes at least one passive element with an adjustable capacitor, configured to perform residual amplification.

[0005] According to a second aspect of the present invention, an exemplary analog-to-digital conversion method is disclosed. This exemplary analog-to-digital conversion method includes: performing a successive approximation analog-to-digital conversion on an analog input signal; extracting a residual at the end of the successive approximation analog-to-digital conversion; and processing the residual using only passive components and feeding the processed residual back to the successive approximation analog-to-digital conversion for noise shaping, comprising: performing residual amplification using at least one passive component having an adjustable capacitor.

[0006] These and other objectives of the present invention will undoubtedly become apparent to those of ordinary skill in the art upon reading the preferred embodiments described below in detail and upon referring to the various figures and diagrams. Simple Explanation of the Diagram

[0007] Figure 1 is a block diagram of a passive noise-shaping SAR ADC with residual amplification function according to an embodiment of the present invention. Figure 2 is a diagram of one possible implementation of the passive element of the adjustable capacitor according to an embodiment of the present invention. Figure 3 is a diagram illustrating the concept of residual amplification using an adjustable capacitor, according to an embodiment of the present invention. Figure 4 is a diagram illustrating the concept of residual amplification using an adjustable capacitor, according to an embodiment of the present invention. Figure 5 is a diagram of a first passive noise shaping SAR ADC design operating in the sampling phase and residual sharing / conversion phase according to an embodiment of the present invention. Figure 6 is a diagram of a first passive noise shaping SAR ADC design operating in residual storage stage 1 and residual storage stage 2 according to an embodiment of the present invention. Figure 7 is a diagram of a generalized signal model of the first passive noise shaping SAR ADC design according to an embodiment of the present invention. Figure 8 is a diagram of a second passive noise-shaping SAR ADC design operating in the sampling phase, according to an embodiment of the present invention. Figure 9 is a diagram of a second passive noise-shaping SAR ADC design operating in the conversion phase, according to an embodiment of the present invention. Figure 10 is a diagram of a second passive noise-shaping SAR ADC design operating in the residual collection stage, according to an embodiment of the present invention. Figure 11 is a diagram of a second passive noise-shaping SAR ADC design operating in the residual enhancement stage according to an embodiment of the present invention. Figure 12 is a diagram of a second passive noise-shaping SAR ADC design operating in the capacitor switching stage according to an embodiment of the present invention. Figure 13 is a diagram of a generalized signal model for a second passive noise-shaping SAR ADC design according to an embodiment of the present invention. Implementation

[0008] Certain terms are used in the following description and requests that refer to specific components. As will be understood by those skilled in the art, electronic device manufacturers may use different names to refer to a component. This document is not intended to distinguish between components with different names but identical functions. In the following description and requests, the terms “comprising” and “including” are used in an open-ended manner and should therefore be interpreted as “including, but not limited to…”. Furthermore, the term “connection” is intended to indicate an indirect or direct electrical connection. Thus, if one device is connected to another device, the connection may be through a direct electrical connection or an indirect electrical connection through other devices and connections.

[0009] Figure 1 is a block diagram illustrating a passive noise-shaping SAR ADC with residual amplification capability according to an embodiment of the present invention. The passive noise-shaping SAR ADC 100 includes a SAR ADC circuit 102 and a passive noise-shaping circuit 104. The SAR ADC circuit 102 is configured to convert an analog input signal V to produce a digital output signal D and extract a residual VRES at the end of the conversion, wherein the residual VRES is the difference between the DAC output and the sampled input voltage after the last SAR conversion cycle performed on the sampled input voltage. The passive noise-shaping circuit 104 is configured to process the residual VRES and feed the processed residual VRES' back to the SAR ADC circuit 102 for noise shaping. In this embodiment, the passive noise-shaping circuit 104 includes at least one passive element 106 with an adjustable capacitor, which is configured to perform residual amplification during the generation of the processed residual VRES'. Furthermore, the passive noise-shaping circuit 104 also includes a switching circuit 108 configured to control charge sharing associated with the passive element 106. For example, the switching circuit 108 may include one or more metal-oxide-semiconductor (MOS) switches, depending on the specific design considerations.

[0010] Figure 2 is a graph illustrating a possible implementation of a passive element with adjustable capacitance according to an embodiment of the present invention. The passive element 106 may be an adjustable capacitor implemented using a MOS variable capacitor 200, as shown in subplot (A) of Figure 2, wherein the capacitance of the MOS variable capacitor 200 is controlled by an external control voltage V. Subplot (B) of Figure 2 shows the capacitance-voltage (CV) curve CV of the MOS variable capacitor 200, where the capacitance of the MOS variable capacitor 200 may be 20 femtofarads (fF) when the control voltage V is set by Va, and may be 200 fF when the control voltage V is set by Vb (Vb > Va).

[0011] This invention proposes using a passive element 106 with adjustable capacitance to achieve residual amplification, thereby enhancing the noise transfer function (NTF) of the passive noise-shaping SAR ADC 100. Figures 3 and 4 are graphs illustrating the concept of achieving residual amplification using an adjustable capacitor C2 (e.g., a MOS variable capacitor 200 as shown in Figure 2) according to an embodiment of the invention. In step 1, the fixed capacitor C1 and the adjustable capacitor C2 have the same capacitance value C, the charge Q1 stored in the fixed capacitor C1 is the residual charge Q, the switch (e.g., a MOS switch) SW1 is turned off to disconnect the adjustable capacitor C2 from the fixed capacitor C1, and no charge is stored in the adjustable capacitor C2. The voltage VC1 on the top plate of the fixed capacitor C1 is V( In step 2, the control voltage of the adjustable capacitor C2 is adjusted so that the adjustable capacitor C2 has a larger capacitance value nC. That is, the capacitance value of the adjustable capacitor C2 increases from C to nC. In step 3, the switch (e.g., a MOS switch) SW1 is turned on to enable charge sharing between the fixed capacitor C1 (with capacitance value C) and the adjustable capacitor C2 (with capacitance value nC). After charge sharing, the charge Q1 stored in the fixed capacitor C1 becomes... The charge Q2 stored in the adjustable capacitor C2 becomes In step 4, the switch (e.g., a MOS switch) SW1 is turned off to disconnect the adjustable capacitor C2 from the fixed capacitor C1. In step 5, the control voltage of the adjustable capacitor C2 is adjusted so that the adjustable capacitor C2 has a smaller capacitance value C. That is, the capacitance value of the adjustable capacitor C2 is reduced from nC to C. Therefore, the voltage VC2 on the top plate of the adjustable capacitor C2 becomes... ( Therefore, the transfer function (TF) is equal to .

[0012] The residual charge collected by the adjustable capacitor C2 through charge sharing can be further shared with another fixed capacitor C3, as shown in Figure 4. The charge Q2 currently stored in the adjustable capacitor C2 is the collected residual charge. In step 6, the adjustable capacitor C2 has a capacitance value C under the control voltage Va, while the fixed capacitor C3 has a larger capacitance value mC. In step 7, switch SW2 (e.g., MOS switch) is turned off to disconnect the adjustable capacitor C2 from the fixed capacitor C3, and no charge is stored in the adjustable capacitor C3. In step 8, switch SW2 is turned on to enable charge sharing between the fixed capacitor C3 (with capacitance value mC) and the adjustable capacitor C2 (with capacitance value C). After charge sharing, the voltage VC3 on the top plate of the fixed capacitor C3 becomes... ( ).

[0013] The passive noise shaping circuit 104 can be constructed based on the above concept, achieving residual amplification through a passive element 106 with an adjustable capacitor. Figure 5 is a diagram illustrating a first passive noise-shaping SAR ADC design with residual amplification according to an embodiment of the present invention. The architecture of the passive noise-shaping SAR ADC 500 is based on the architecture of the passive noise-shaping SAR ADC 100. The passive noise-shaping SAR ADC 500 includes a SAR ADC circuit 510 and a passive noise shaping circuit 520, wherein the SAR ADC circuit 510 includes a sampling switch SW SH, a CDAC 502, and a comparator 504, and the passive noise shaping circuit 520 includes an adjustable capacitor Ctune and a control switch SW. It should be noted that only components relevant to the present invention are shown. In practice, the SAR ADC circuit 510 may also include SAR logic, a DAC, etc.

[0014] When the passive noise-shaping SAR ADC 500 operates during the sampling phase, the sampling switch SW SH is turned on for signal sampling, and the control switch SW is turned off to disconnect the adjustable capacitor Ctune (which stores the residual charge of the previous sample) from the output of CDAC 502 (which has a capacitance value of kC), and to control the adjustable capacitor Ctune to have a capacitance value of C. After the current sample is sampled and held by CDAC 502, the passive noise-shaping SAR ADC 500 enters the residual sharing / conversion phase to perform analog-to-digital conversion on the current sample. Therefore, the sampling switch SW SH is turned off, and the control switch SW is turned on to connect the adjustable capacitor Ctune to the output of CDAC 502 and the non-inverting input "+" of comparator 504, where the adjustable capacitor Ctune provides the collected residual charge of the previous sample for noise shaping. Next, the passive noise-shaping SAR ADC 500 performs normal SAR ADC operation.

[0015] After the conversion phase, the passive noise-shaping SAR ADC 500 sequentially enters residual storage phase 1 and residual storage phase 2, as shown in Figure 6. When the passive noise-shaping SAR ADC 500 operates in residual storage phase 1, the sampling switch SW SH is closed, the control switch SW is opened, and the adjustable capacitor Ctune is controlled to increase its capacitance value to nC to collect residual charge from CDAC 502. When the passive noise-shaping SAR ADC 500 operates in residual storage phase 2, the sampling switch SW SH is closed, and the control switch SW is closed to disconnect the adjustable capacitor Ctune (with capacitance value nC) from CDAC 502. Through the procedures shown in Figures 5 and 6, the residual charge stored in the adjustable capacitor Ctune is... Therefore, if Most of the residual charge Q of the current sample is stored in the adjustable capacitor Ctune. When the capacitance value of the adjustable capacitor Ctune changes from nC to C, the voltage on the top plate of the adjustable capacitor Ctune is approximately equal to the residual VRES of the current sample.

[0016] After residual storage phase 2, the passive noise shaping SAR ADC 500 re-enters the sampling phase. Specifically, the sampling phase (P1), residual sharing / conversion phase (P2), residual storage phase 1 (P3), and residual storage phase 2 (P4) are activated sequentially and cyclically, resulting in a sequence The adjustable capacitor C2 is used to collect more residual charge in the large capacitance mode (nC), and when the adjustable capacitor C2 is in the small capacitance mode (C), it feeds the collected residual charge to CDAC 502. In simple terms, the adjustable capacitor C2 has a first capacitance value (e.g., nC) in a first period (e.g., residual storage stage 1), during which a switching circuit (e.g., control switch SW) enables charge sharing between CDAC 502 and the adjustable capacitor C2, and a second capacitance value (e.g., C) in a second period (e.g., residual sharing stage), during which a switching circuit (e.g., control switch SW) enables charge sharing between CDAC 502 and the adjustable capacitor C2, wherein the first and second periods are non-overlapping periods, and the first capacitance value is greater than the second capacitance value.

[0017] Figure 7 is a diagram of a generalized signal model of a passive noise-shaping SAR ADC 500 according to an embodiment of the present invention. The transfer function of the passive noise-shaping SAR ADC 500 can be expressed by the following equation. (1)

[0018] Considering a case where k=4 and n=8, the transfer function of the passive noise-shaping SAR ADC 500 is represented by D=0.8V+(1-0.667z⁻¹)Q, where NTF=1-0.667z⁻¹. As shown in Figures 5 and 6, comparator 504 is a single-input pair comparator, and the passive noise-shaping circuit 520 uses all passive components without any operational amplifiers. Furthermore, the passive noise-shaping SAR ADC 500 with residual amplification achieves lower signal gain descent (i.e., lower SNR degradation) and lower residual gain descent (i.e., better NTF).

[0019] Figure 8 is a diagram of a second passive noise-shaping SAR ADC design with residual amplification according to an embodiment of the present invention. The architecture of the passive noise-shaping SAR ADC 800 is based on the architecture of the passive noise-shaping SAR ADC 100. The passive noise-shaping SAR ADC 800 includes a SAR ADC circuit and a passive noise-shaping circuit, wherein the SAR ADC circuit includes a sampling switch SW, two CDACs 802_1 and 802_2 and a comparator 804 (with a non-inverting input "+" and an inverting input "-"), and the passive noise-shaping circuit includes two adjustable capacitors Ctune_1 and Ctune_2, four fixed capacitors CRP1, CRP2, CRN1, and CR2, two integrating capacitors CINTN and CINTP, and a switching circuit (including control switches SW1-SW16). The fixed capacitors CRN1, CRN2, CRP1, and CRP2 may have the same capacitance value CR. The integrating capacitors CINTN and CINTP may have the same capacitance value CINT. The adjustable capacitors Ctune_1 and Ctune_2 may be controlled to have the same capacitance value selected from C and kC. It should be noted that only components relevant to this invention are shown. In practice, the SAR ADC circuitry of the passive noise-shaping SAR ADC 800 may also include SAR logic, a DAC, etc.

[0020] The switching circuit of the passive noise shaping circuit (including control switches SW1-SW16) is configured to control charge sharing between CDAC 802_1 and adjustable capacitor Ctune_1, charge sharing between adjustable capacitor Ctune_1 and one of fixed capacitors CRN1 and CRN2, charge sharing between adjustable capacitor Ctune_1 and one of fixed capacitors CRP1 and CRP2, the connection of another fixed capacitor CRN1 and CRN2 between CDAC 802_1 and comparator 804 (specifically, the non-inverting input "+" of comparator 804), and capacitance exchange between fixed capacitors CRN1 and CRN2. It is further configured to control charge sharing between CDAC 802_2 and adjustable capacitor Ctune_2, charge sharing between adjustable capacitor Ctune_2 and one of fixed capacitors CRP1 and CRP2, charge sharing between adjustable capacitor Ctune_2 and one of fixed capacitors CRN1 and CRN2, and the connection of another fixed capacitor CRP1 and CRN2 between CDAC 802_1 and comparator 804 (specifically, the non-inverting input "+" of comparator 804), and capacitance exchange between fixed capacitors CRN1 and CRN2. The connection of RP2 between CDAC 802_2 and comparator 804 (especially the inverting input "-" of comparator 804), and the capacitance exchange between fixed capacitors CRP1 and CRP2.

[0021] In this embodiment, the input voltage signal V is a differential signal composed of VIN and VIP. When the passive noise-shaping successive approximation analog-to-digital converter (SAR ADC) 800 operates during the sampling phase, as shown in Figure 8, the switching circuit (including control switches SW1-SW16) disconnects the adjustable capacitor Ctune_1 from one of the following: the output terminal of CDAC 802_1; the fixed capacitors CRN1 and CRN2 (e.g., CRN1 shown in Figure 8); and the fixed capacitors CRP1 and CRP2 (e.g., CRP1 shown in Figure 8). It then connects one of the fixed capacitors CRN1 and CRN2 (e.g., CRN1 shown in Figure 8) between the output terminals of CDACs 802_1 and 802_2, and connects the other fixed capacitor CRN1 and CRN2 (e.g., CRN2 shown in Figure 8) to the CDAC. Disconnect the adjustable capacitor Ctune_2 from one of the following: the output terminal of CDAC 801_1 and one of the inverting and non-inverting input terminals of comparator 804 (e.g., the non-inverting input terminal "+" of comparator 804 shown in Figure 8); disconnect the adjustable capacitor Ctune_2 from the output terminal of CDAC 802_2; disconnect one of the fixed capacitors C RN1 and C RN2 (e.g., C RN1 shown in Figure 8) and fixed capacitors C RP1 and C RP2 (e.g., C RP1 shown in Figure 8); connect one of the fixed capacitors C RP1 and C RP2 (e.g., C RP1 shown in Figure 8) between the output terminals of CDACs 802_1 and 802_2; and connect the other fixed capacitor C RP1 and C RP2 (e.g., C RP2 shown in Figure 8) between the output terminals of CDACs 801_1 and 802_2. The output terminal of 802_2 is connected to one of the inverting and non-inverting input terminals of comparator 804 (e.g., the inverting input terminal "-" of comparator 804 shown in Figure 8). Each adjustable capacitor Ctune_1, Ctune_2 can be controlled to have a capacitance value kC.

[0022] When the passive noise-shaping successive approximation analog-to-digital converter (SAR ADC) 800 is operating during the conversion phase, as shown in Figure 9, the switching circuit (including control switches SW1-SW16) disconnects one of the following: the adjustable capacitor Ctune_1 from the output terminal of CDAC 802_1; the fixed capacitors CRN1 and CRN2 (e.g., CRN1 shown in Figure 9); and the fixed capacitors CRP1 and CRP2 (e.g., CRP1 shown in Figure 9). It then connects one of the fixed capacitors CRN1 and CRN2 (e.g., CRN1 shown in Figure 9) between the output terminals of CDAC 802_1 and CDAC 802_2, and connects the other fixed capacitor CRN1 and CRN2 (e.g., CRN2 shown in Figure 9) to the CDAC 802_1. Disconnect the adjustable capacitor Ctune_2 from one of the following: the output terminal of CDAC 802_1 and one of the inverting and non-inverting input terminals of comparator 804 (e.g., the non-inverting input terminal "+" of comparator 804 shown in Figure 9); disconnect the adjustable capacitor Ctune_2 from the output terminal of CDAC 802_2; disconnect one of the fixed capacitors C RN1 and C RN2 (e.g., C RN1 shown in Figure 9) and fixed capacitors C RP1 and C RP2 (e.g., C RP1 shown in Figure 9); connect one of the fixed capacitors C RP1 and C RP2 (e.g., C RP1 shown in Figure 9) between the output terminal of CDAC 802_1 and the output terminal of CDAC 802_2; and connect the other fixed capacitor C RP1 and C RP2 (e.g., C RP2 shown in Figure 9) between the output terminal of CDAC 802_1 and the output terminal of CDAC 802_2. The output terminal of 802_2 is connected to one of the inverting input terminal and the non-inverting input terminal of comparator 804 (e.g., the inverting input terminal "-" of comparator 804 shown in Figure 9).

[0023] When the passive noise-shaping successive approximation analog-to-digital converter (SAR ADC) 800 operates during the residual collection phase, as shown in Figure 10, the switching circuit (including control switches SW1-SW16) connects the adjustable capacitor Ctune_1 to the output terminal of CDAC 802_1, disconnects the adjustable capacitor Ctune_1 from one of the fixed capacitors CRN1, CRN2 (e.g., CRN1 shown in Figure 10) and CRP1, CRP2 (e.g., CRP1 shown in Figure 10), disconnects the fixed capacitors CRN1, CRN2 (e.g., CRN1 shown in Figure 10) from the output terminals of CDAC 802_1 and CDAC 802_2, and connects the other fixed capacitor CRN1, CRN2 (e.g., CRN2 shown in Figure 10) to the CDAC 802_1. Between the output terminal of 802_1 and one of the inverting and non-inverting input terminals of comparator 804 (e.g., the non-inverting input terminal "+" of comparator 804 shown in Figure 10), connect the adjustable capacitor Ctune_2 to the output terminal of CDAC 802_2, disconnect the adjustable capacitor Ctune_2 from one of the fixed capacitors CRN1, CRN2 (e.g., CRN1 shown in Figure 10) and fixed capacitors CRP1, CRP2 (e.g., CRP1 shown in Figure 10), disconnect fixed capacitors CRP1, CRP2 (e.g., CRP1 shown in Figure 10) from the output terminals of CDAC 802_1 and CDAC 802_2, and connect the other fixed capacitor CRP1, CRP2 (e.g., CRP2 shown in Figure 10) to the output terminal of CDAC 802_2. The output terminal of 802_2 is connected to one of the inverting input terminals and the non-inverting input terminals of comparator 804 (e.g., the inverting input terminal "-" of comparator 804 shown in Figure 10).

[0024] When the passive noise-shaping SAR ADC 800 operates in the residual enhancement stage, as shown in Figure 11, the switching circuit (including control switches SW1-SW16) disconnects the adjustable capacitor Ctune_1 from the output terminal of CDAC 802_1, connects the adjustable capacitor Ctune_1 to one of the fixed capacitors CRN1, CRN2 (e.g., CRN1 shown in Figure 11) and CRP1, CRP2 (e.g., CRP1 shown in Figure 11), disconnects the fixed capacitors CRN1, CRN2 (e.g., CRN1 shown in Figure 11) from the output terminals of CDAC 802_1 and CDAC 802_2, and connects the other fixed capacitor CRN1, CRN2 (e.g., CRN2 shown in Figure 11) to the CDAC 802_1. Between the output terminal of 802_1 and one of the inverting and non-inverting input terminals of comparator 804 (e.g., the non-inverting input terminal "+" of comparator 804 shown in Figure 11), disconnect the adjustable capacitor Ctune_2 from the output terminal of CDAC 802_2, connect the adjustable capacitor Ctune_2 to one of the fixed capacitors CRN1, CRN2 (e.g., CRN1 shown in Figure 11) and fixed capacitors CRP1, CRP2 (e.g., CRP1 shown in Figure 11), disconnect the fixed capacitors CRP1, CRP2 (e.g., CRP1 shown in Figure 11) from the output terminals of CDAC 802_1 and CDAC 802_2, and connect the other fixed capacitor CRP1, CRP2 (e.g., CRP2 shown in Figure 11) to the CDAC. The output terminal of 802_2 is connected to one of the inverting input terminals and the non-inverting input terminals of comparator 804 (e.g., the inverting input terminal "-" of comparator 804 shown in Figure 11).

[0025] Fixed capacitors C RN1 and C RN2 are used in a ping-pong manner by the passive noise shaping circuit. Consider a case where fixed capacitor C RN1 currently acts as a residual capacitor storing the residual charge of the current sample (e.g., conceptually located between the output terminals of CDACs 802_1 and 802_2), while fixed capacitor C RN2 currently acts as a residual capacitor storing the residual charge of the previous sample (e.g., conceptually located between CDAC 802_1 and comparator 804). Therefore, after the capacitor swap, fixed capacitor C RN1 is used as the residual capacitor storing the residual charge of the previous sample (e.g., conceptually located between CDAC 802_1 and comparator 804), while fixed capacitor C RN2 is used as the residual capacitor storing the residual charge of the current sample (e.g., conceptually located between the output terminals of CDACs 802_1 and 802_2).

[0026] Consider another scenario where the fixed capacitor C RN2 currently serves as the residual capacitor storing the residual charge of the current sample (e.g., conceptually located between the output terminals of CDACs 802_1 and 802_2), while the fixed capacitor C RN1 currently serves as the residual capacitor storing the residual charge of the previous sample (e.g., conceptually located between CDAC 802_1 and comparator 804). Therefore, after the capacitor swap, the fixed capacitor C RN2 is used as the residual capacitor storing the residual charge of the previous sample (e.g., conceptually located between CDAC 802_1 and comparator 804), while the fixed capacitor C RN1 is used as the residual capacitor storing the residual charge of the current sample (e.g., conceptually located between the output terminals of CDACs 802_1 and 802_2).

[0027] Similarly, fixed capacitors CRP1 and CRP2 are also used in a ping-pong manner by the passive noise shaping circuit. Consider a case where fixed capacitor CRP1 currently acts as a residual capacitor storing the residual charge of the current sample (e.g., conceptually located between the output terminals of CDACs 802_1 and 802_2), while fixed capacitor CRP2 currently acts as a residual capacitor storing the residual charge of the previous sample (e.g., conceptually located between CDAC 802_2 and comparator 804). Therefore, after the capacitor swap, fixed capacitor CRP1 is used as a residual capacitor storing the residual charge of the previous sample (e.g., conceptually located between CDAC 802_2 and comparator 804), while fixed capacitor CRP2 is used as a residual capacitor storing the residual charge of the current sample (e.g., conceptually located between the output terminals of CDACs 802_1 and 802_2).

[0028] Consider another scenario where fixed capacitor CRP2 currently serves as a residual capacitor storing the residual charge of the current sample (e.g., conceptually located between the output terminals of CDACs 802_1 and 802_2), while fixed capacitor CRP1 currently serves as a residual capacitor storing the residual charge of the previous sample (e.g., conceptually located between CDAC 802_2 and comparator 804). Therefore, after the capacitor swap, fixed capacitor CRP2 is used as the residual capacitor storing the residual charge of the previous sample (e.g., conceptually located between CDAC 802_2 and comparator 804), while fixed capacitor CRP1 is used as the residual capacitor storing the residual charge of the current sample (e.g., conceptually located between the output terminals of CDACs 802_1 and 802_2).

[0029] When the passive noise-shaping SAR ADC 800 operates during the capacitor swapping phase, as shown in Figure 12, the switching circuit (including control switches SW1-SW16) disconnects the adjustable capacitor Ctune_1 from the output terminal of CDAC 802_1, fixed capacitors C RN1 and C RN2 (e.g., C RN1 is located between the output terminals of CDACs 802_1 and 802_2), and fixed capacitors C RP1 and C RP2 (e.g., C RP1 is located between the output terminals of CDACs 802_1 and 802_2), and then swaps fixed capacitors C RN1 and C RN2, such that fixed capacitor C RN1 now acts as a residual capacitor storing the residual charge of the previous sample, and fixed capacitor C RN2 now acts as a residual capacitor storing the residual charge of the current sample. Similarly, the switching circuit (including control switches SW1-SW16) disconnects the adjustable capacitor Ctune_2 from the output terminal of CDAC 802_2, the fixed capacitors CRN1 and CRN2 (e.g., CRN1 is located between the output terminals of CDACs 802_1 and 802_2), and the fixed capacitors CRP1 and CRP2 (e.g., CRP1 is located between the output terminals of CDACs 802_1 and 802_2), and then swaps the fixed capacitors CRP1 and CRP2, such that fixed capacitor CRP1 now acts as a residual capacitor storing the residual charge of the previous sample, and fixed capacitor CRP2 now acts as a residual capacitor storing the residual charge of the current sample.

[0030] After the capacitance exchange phase is completed, the passive noise shaping SAR ADC 800 re-enters the sampling phase. Specifically, the sampling phase P1, conversion phase P1, residual collection phase P3, residual enhancement phase P4, and capacitance exchange phase P5 are activated sequentially and cyclically, forming a [system / process]. sequence.

[0031] Figure 13 is a diagram depicting a generalized signal model of a passive noise-shaping SAR ADC 800 according to an embodiment of the present invention. The parameters c, g1, b, g2, a, and k in the generalized signal model can be defined as follows.

[0032] c = CDAC / (kC+CDAC) (2)

[0033] g 1 = kC / C (3)

[0034] b = C / [C+2*(CR*2)] (4)

[0035] g 2 = 2 (5)

[0036] a = CR / (C INT+CR) (6)

[0037] k = [cg 1b +(1-b)]g 2a (7)

[0038] The transfer function of the passive noise-shaping SAR ADC 800 can be expressed by the following equation.

[0039] As shown in Figure 8-12, comparator 804 is a single-input pair comparator. The passive noise shaping circuit uses all passive components and does not use any operational amplifiers. Furthermore, the passive noise-shaping SAR ADC 800 with residual amplification achieves lower signal gain degradation (i.e., lower SNR degradation) and lower residual gain degradation (i.e., better NTF). Specifically, NTF can be improved by using an adjustable capacitor to collect more residual charge in the large capacitance mode (kC), and when the adjustable capacitor is in the small capacitance mode (C), the residual charge collected by the adjustable capacitor is sent to an integrating capacitor. In simple terms, the adjustable capacitors Ctune_1 / Ctune_2 have a first capacitance value (e.g., kC) in the first period (e.g., the residual collection stage), during which the switching circuit enables charge sharing between CDAC 802_1 / 802_2 and the adjustable capacitors Ctune_1 / Ctune_2, and have a second capacitance value (e.g., C) in the second period (e.g., the residual enhancement stage), during which the switching circuit enables charge sharing between the adjustable capacitors Ctune_1 / Ctune_2 and the fixed capacitors C RN1 / C RP1 (or C RN2 / C RP2), wherein the first and second periods are non-overlapping periods, and the first capacitance value is greater than the second capacitance value.

[0040] Those skilled in the art will readily observe that numerous modifications and alterations can be made to the apparatus and method while retaining the edifying power of the invention. Therefore, the above disclosure should be interpreted only within the scope of the appended claims.

[0041] 100, 500, 800: Passive noise shaping SAR ADC 102: SAR ADC Circuit 104: Passive noise shaping circuit 106: Passive components 108: Switching Circuit 200: MOS variable capacitor 802_1, 802_2: CDACs 804: Comparator

Claims

1. A passive noise-shaping successive approximation analog-to-digital converter (SAR ADC), comprising: A SAR ADC circuit configured to convert an analog input signal and extract the residual at the end of the conversion; And a passive noise shaping circuit configured to process the residual and feed the processed residual back to the SAR ADC circuit, wherein the passive noise shaping circuit includes: at least one passive element having an adjustable capacitor configured to perform residual amplification, wherein the residual amplification is performed by reducing the adjustable capacitor from one capacitance value to another capacitance value.

2. The passive noise shaping SAR ADC as claimed in claim 1, wherein the SAR ADC circuit comprises: A first-capacitor digital-to-analog converter (CDAC); And a comparator with an inverting input and a non-inverting input; The passive noise shaping circuit includes: a first capacitor, wherein the first capacitor is an adjustable capacitor; a second capacitor; a third capacitor; and a switching circuit configured to control charge sharing between the first CDAC and the first capacitor, between the first capacitor and one of the second and third capacitors, connect another of the second and third capacitors between the first CDAC and the comparator, and between the second and third capacitors.

3. The passive noise-shaping SAR ADC as claimed in claim 2, wherein the first capacitor has a first capacitance value during a first period when the switching circuit enables charge sharing between the first CDAC and the first capacitor, and has a second capacitance value during a second period when the switching circuit enables charge sharing between the first capacitor and the second capacitor and one of the third capacitor, wherein the first period and the second period are non-overlapping periods, and the first capacitance value is greater than the second capacitance value.

4. The passive noise-shaping SAR ADC as claimed in claim 2, wherein when the passive noise-shaping SAR ADC operates in a sampling phase, the switching circuit disconnects the first capacitor from the output of the first CDAC and the second capacitor from one of the third capacitors, connects the second capacitor from one of the third capacitors to the output of the first CDAC, and connects the other second capacitor from the third capacitor between the output of the first CDAC and the comparator between the inverting input and the non-inverting input.

5. The passive noise-shaping SAR ADC as claimed in claim 2, wherein when the passive noise-shaping SAR ADC operates in a conversion phase, the switching circuit disconnects the first capacitor from the output of the first CDAC and the second capacitor from one of the third capacitors, connects the second capacitor from one of the third capacitors to the output of the first CDAC, and connects another second capacitor from one of the third capacitors between the output of the first CDAC and the comparator between the inverting input and the non-inverting input.

6. The passive noise-shaping SAR ADC as claimed in claim 2, wherein when the passive noise-shaping SAR ADC operates in a residual collection phase, the first capacitor is controlled to increase its capacitance value, and the switching circuit connects the first capacitor to the output of the first CDAC, disconnects the first capacitor from one of the second and third capacitors, disconnects one of the second and third capacitors from the output of the first CDAC, and connects another of the second and third capacitors between the output of the first CDAC and the comparator between the inverting input and the non-inverting input.

7. The passive noise-shaping SAR ADC as claimed in claim 2, wherein when the passive noise-shaping SAR ADC operates in a residual enhancement phase, the first capacitor is controlled to reduce its capacitance value, and the switching circuit disconnects the first capacitor from the output of the first CDAC, connects the first capacitor to one of the second and third capacitors, disconnects one of the second and third capacitors from the output of the first CDAC, and connects the other of the second and third capacitors between the output of the first CDAC and the comparator between the inverting input and the non-inverting input.

8. The passive noise-shaping SAR ADC as claimed in claim 2, wherein when the passive noise-shaping SAR ADC operates in the capacitor switching phase, the switching circuit disconnects the first capacitor from the output terminal of the first CDAC, disconnects one of the second and third capacitors, and swaps the second and third capacitors.

9. The passive noise-shaping SAR ADC as claimed in claim 2, wherein the analog input signal is a differential signal, and the SAR ADC circuit further comprises: a second CDAC; and the passive noise-shaping circuit further comprises: a fourth capacitor, wherein the fourth capacitor is an adjustable capacitor; a fifth capacitor; and a sixth capacitor; wherein the switching circuit is further configured to control charge sharing between the second CDAC and the fourth capacitor, charge sharing between the fourth capacitor and one of the fifth and sixth capacitors, charge sharing between the first capacitor and one of the fifth and sixth capacitors, charge sharing between the fourth capacitor and one of the second and third capacitors, connecting the other of the fifth and sixth capacitors between the second CDAC and the comparator, and capacitor swapping between the fifth and sixth capacitors.

10. The passive noise-shaping SAR ADC as claimed in claim 9, wherein the first capacitor and the fourth capacitor each have a first capacitance value during a first period in which the switching circuit enables charge sharing between the first CDAC and the first capacitor and between the second CDAC and the fourth capacitor, and each have a second capacitance value during a second period in which the switching circuit enables charge sharing between the first capacitor and one of the second and third capacitors and between the fourth capacitor and one of the fifth and sixth capacitors, wherein the first period and the second period are non-overlapping periods, and the first capacitance value is greater than the second capacitance value.

11. The passive noise-shaping SAR ADC as claimed in claim 9, wherein when the passive noise-shaping SAR ADC operates during the sampling phase, the switching circuit disconnects the first capacitor from the output terminal of the first CDAC, disconnects one of the second and third capacitors and one of the fifth and sixth capacitors, connects one of the second and third capacitors between the output terminal of the first CDAC and the output terminal of the second CDAC, connects the other of the second and third capacitors between the output terminal of the first CDAC and one of the inverting and non-inverting input terminals of the comparator, disconnects the fourth capacitor from the output terminal of the second CDAC, disconnects one of the second and third capacitors and one of the fifth and sixth capacitors, connects one of the fifth and sixth capacitors between the output terminal of the first CDAC and the output terminal of the second CDAC, and connects the other of the fifth and sixth capacitors between the output terminal of the second CDAC and one of the inverting and non-inverting input terminals of the comparator.

12. The passive noise-shaping SAR ADC as claimed in claim 9, wherein when the passive noise-shaping SAR ADC operates during the conversion phase, the switching circuit disconnects the first capacitor from the output terminal of the first CDAC, disconnects one of the second and third capacitors and one of the fifth and sixth capacitors, connects one of the second and third capacitors between the output terminal of the first CDAC and the output terminal of the second CDAC, connects the other of the second and third capacitors between the output terminal of the first CDAC and one of the inverting and non-inverting input terminals of the comparator, disconnects the fourth capacitor from the output terminal of the second CDAC, disconnects one of the second and third capacitors and one of the fifth and sixth capacitors, connects one of the fifth and sixth capacitors between the output terminal of the first CDAC and the output terminal of the second CDAC, and connects the other of the fifth and sixth capacitors between the output terminal of the second CDAC and one of the inverting and non-inverting input terminals of the comparator.

13. The passive noise-shaping SAR ADC as claimed in claim 9, wherein when the passive noise-shaping SAR ADC operates in the residual collection phase, both the first and second capacitors are controlled to increase their capacitance values, and a switching circuit connects the first capacitor to the output terminal of the first CDAC, disconnects the first capacitor from one of the second and third capacitors and one of the fifth and sixth capacitors, disconnects one of the second and third capacitors from the output terminals of the first and second CDACs, connects the other of the second and third capacitors between the output terminal of the first CDAC and one of the inverting and non-inverting input terminals and a comparator, connects a fourth capacitor to the output terminal of the second CDAC, disconnects the fourth capacitor from one of the second and third capacitors and one of the fifth and sixth capacitors, disconnects one of the fifth and sixth capacitors from the output terminals of the first and second CDACs, and connects the other of the fifth and sixth capacitors between the output terminal of the second CDAC and the other of the inverting and non-inverting input terminals and a comparator.

14. The passive noise-shaping SAR ADC as claimed in claim 9, wherein when the passive noise-shaping SAR ADC operates in the residual enhancement phase, both the first and second capacitors are controlled to reduce their capacitance values, and a switching circuit disconnects the first capacitor from the output terminal of the first CDAC, connects the first capacitor to one of the second and third capacitors and one of the fifth and sixth capacitors, disconnects one of the second and third capacitors from the output terminals of the first and second CDACs, connects the other of the second and third capacitors between the output terminal of the first CDAC and one of the inverting and non-inverting input terminals and a comparator, disconnects the fourth capacitor from the output terminal of the second CDAC, connects the fourth capacitor to one of the second and third capacitors and one of the fifth and sixth capacitors, disconnects one of the fifth and sixth capacitors from the output terminals of the first and second CDACs, and connects the other of the fifth and sixth capacitors between the output terminal of the second CDAC and the other of the inverting and non-inverting input terminals and a comparator.

15. The passive noise-shaping SAR ADC as claimed in claim 9, wherein when the passive noise-shaping SAR ADC operates in the capacitor switching phase, the switching circuit disconnects the first capacitor from the output terminal of the first CDAC, one of the second and third capacitors, and one of the fifth and sixth capacitors, swaps the second and third capacitors, disconnects the fourth capacitor from the output terminal of the second CDAC, one of the second and third capacitors, and one of the fifth and sixth capacitors, and swaps the fifth and sixth capacitors.

16. An analog-to-digital conversion method, comprising: Successive analog-to-digital conversion is performed on an analog input signal; Extract the residual at the end of the successive approximation analogy to the digital conversion; And using only passive components to process the residuals and feed the processed residuals back to a successive approximation analog-to-digital converter for noise shaping, including: performing residual amplification using a passive component with at least one adjustable capacitor, wherein the residual amplification is performed by reducing the adjustable capacitor from one capacitance value to another capacitance value.

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