Device for embedded memory

Abstract

A method for pocket integration and fabrication for high-density memory and logic applications is described. While the various embodiments are described with reference to FeRAM, the capacitive structures formed herein can be used in any application where capacitance is required. For example, the capacitive structures can be used to fabricate ferroelectric-based or paraelectric-based majority gates, minority gates, and / or limit gates.

Description

Technical Field

[0001] The present invention relates to a pocket integration process for embedded memory. Prior Art

[0002] Integrating ferroelectric random access memory (FeRAM) on the same plane as interconnects for logic devices can be challenging. FeRAM devices include materials that have various thicknesses and are difficult to etch. Aligning the device thickness in the memory region with the height constraints of the interconnects in the adjacent logic region is challenging. As such, alternative methods for patterning and forming devices that include ferroelectric materials are necessary to achieve high density arrays. Summary of the invention

[0003] none Simple diagram description

[0004] The material described herein is illustrated by way of example and not by limitation in the figures that follow. For simplicity and clarity of illustration, the elements shown in the figures are not necessarily depicted to scale. For example, the dimensions of certain elements may be exaggerated relative to other elements for clarity. Also, various physical features may be represented in their simplified "ideal" form and geometry for clarity of discussion, but it should not be understood that actual implementations may only approximate the illustrated ideal. For example, flat surfaces and square intersections may be drawn despite the finite roughness, rounded corners, and imperfect angular intersection characteristics resulting from nanofabrication. Furthermore, when appropriate, reference designations have been repeated between figures to indicate corresponding or similar elements.

[0005] [ [picture] [1A]] is a cross-sectional diagram of a plurality of ferroelectric memory devices in a memory region adjacent to an interconnect structure in a logic region, according to an embodiment of the present disclosure.

[0006] [ [picture] [1B]] is a cross-sectional illustration of a ferroelectric memory device on a transition electrode, wherein the lateral thickness of the transition electrode is equal to the lateral thickness of the ferroelectric memory device and twice the thickness of the spacer adjacent to the transition electrode, according to an embodiment of the present disclosure.

[0007] [ [picture] [1C]] is a cross-sectional illustration of layers within a ferroelectric memory device including a hard mask, according to an embodiment of the present disclosure.

[0008] [ [picture] [1D]] is a cross-sectional diagram of a ferroelectric memory device including a conductive hard mask, according to an embodiment of the present disclosure.

[0009] [ [picture] [1E]] is a cross-sectional diagram of a ferroelectric memory device including a dielectric hard mask, according to an embodiment of the present disclosure.

[0010] [[] [picture] [1F]] is a cross-sectional illustration of a ferroelectric memory device on a conductive interconnect, wherein the conductive interconnect has a lateral thickness greater than the lateral thickness of the ferroelectric memory device, according to an embodiment of the present disclosure.

[0011] [ [picture] [1G]] is a cross-sectional illustration of a ferroelectric memory device including a hard mask (which includes a dielectric material), according to an embodiment of the present disclosure.

[0012] [ [picture] [1H]] is a cross-sectional illustration of a ferroelectric memory device including a double hard mask including a layer of dielectric material on a layer of conductive material.

[0013] [ [picture] [1I]] is an isometric diagram of a plurality of ferroelectric memory devices in a memory region, wherein the top electrodes of individual ones of the plurality of ferroelectric memory devices are coupled to a common plane electrode, according to an embodiment of the present disclosure.

[0014] [ [picture] [1J]] is an isometric illustration of a plurality of ferroelectric memory devices in a memory region adjacent to an interconnect structure in a logic region, wherein the conductive interconnect in the memory region couples trenches of more than one ferroelectric memory device, according to an embodiment of the present disclosure.

[0015] [ [picture] [2A]] is an isometric illustration of multiple ferroelectric memory devices in a memory region, wherein a conductive interconnect in the memory region couples trenches of more than one ferroelectric memory device, according to an embodiment of the present disclosure.

[0016] [ [picture] [2B]] is an isometric illustration of a plurality of ferroelectric memory devices in a memory region, wherein a conductive interconnect in the memory region couples trenches of more than one ferroelectric memory device, and wherein an encapsulation layer extends continuously between a pair of ferroelectric memory devices and over respective trenches connecting the pair of ferroelectric memory devices, according to an embodiment of the present disclosure.

[0017] [ [picture] [3]] is an isometric diagram of multiple ferroelectric memory devices in a memory region, wherein a conductive interconnect in the memory region couples trenches of more than one ferroelectric memory device, according to an embodiment of the present disclosure.

[0018] [ [picture] [4]] is an isometric diagram of multiple ferroelectric memory devices in a memory region, wherein a conductive interconnect in the memory region couples trenches of more than one ferroelectric memory device, according to an embodiment of the present disclosure.

[0019] [ [picture] [5]] is a flow chart of a method for manufacturing a ferroelectric memory device with interconnects adjacent to a logic region, according to an embodiment of the present disclosure.

[0020] [ [picture] [6A]] is a cross-sectional diagram of a plurality of conductive interconnects formed in a first dielectric in a memory area and a logic area on a substrate and after formation of an etch stop layer connected to the conductive interconnects.

[0021] [ [picture] [6B] [picture] A cross-sectional view of the structure in [6A] following a process for etching a portion of the etch stop layer 126 from the memory region.

[0022] [ [picture] [6C]] Department [picture] A cross-sectional illustration of the structure in [6B], subsequent to a process for depositing electrode material on the conductive interconnect in the memory region, on the first dielectric and on the etch stop layer, and subsequent to formation of a material layer stack for forming a ferroelectric memory device.

[0023] [ [picture] [6D]] Department [picture] Cross-sectional view of the structure in [2D], following the process used to form a ferroelectric memory device.

[0024] [ [picture] [6E]] Department [picture] Cross-sectional illustration of the structure in [6D] following a process for depositing an encapsulation layer on the ferroelectric memory device and on the electrode material.

[0025] [ [picture] [6F]] Department [picture] A cross-sectional illustration of the structure in [6E] following a process for forming a blocking mask on the encapsulation layer to isolate each ferroelectric memory device.

[0026] [ [picture] [7A] Series [picture] Cross-sectional view of the structure in [6F] following the process used to etch the encapsulation layer.

[0027] [ [picture] [7B]] [picture] A plan view illustration of the structure in [7A], in an embodiment in which the conductive interconnects are discrete islands and the blocking mask forms a substantially circular encapsulation layer around the sidewalls of each ferroelectric memory device.

[0028] [ [picture] [7C] [picture] A plan view illustration of the structure in [7A], in an embodiment in which the conductive interconnect is a trench and a mask forms an encapsulation layer around the sidewalls of each ferroelectric memory device.

[0029] [ [picture] [7D]] Series [picture] A plan view illustration of the structure in [7A], in an embodiment in which the conductive interconnect is a trench and a mask forms an encapsulation layer around the sidewalls of each ferroelectric memory device.

[0030] [ [picture] [8A] Series [picture] A cross-sectional illustration of the structure in [7A] following a process for forming an opening in a second dielectric formed above a ferroelectric memory device.

[0031] [ [picture] [8B]] [picture] Cross-sectional illustration of the structure in [8A] following a process for removing the mask and depositing conductive material to form a through-hole electrode.

[0032] [ [picture] [8C] [picture] A cross-sectional view of the structure in [8B] following a process for forming a mask on the second dielectric and on the through-hole electrode.

[0033] [ [picture] [8D]] Series [picture] A cross-sectional view of the structure in [8C] following a process for etching a second dielectric to form a hanging trench in logic region 101B.

[0034] [ [picture] [8E]] System [picture] A cross-sectional illustration of the structure in [8D] following a process for etching a second dielectric to form a through hole in the hanging trench in the logic area.

[0035] [ [picture] [8F]] Department [picture] A cross-sectional view of the structure in [8E] following a process for removing the mask and depositing conductive material into the openings to form vias and metal lines.

[0036] [ [picture] [9A] Series [picture] Cross-sectional illustration of the structure in [6F] following a process for etching the encapsulation layer to remove or reduce the thickness of the remaining portions.

[0037] [ [picture] [9B]] [picture] Cross-sectional illustration of the structure in [9A] following a process used to etch and remove electrode material to form a ferroelectric memory device.

[0038] [ [picture]

[10] ] illustrates a computing architecture having a coherent cache or memory-side buffer chiplet (which includes a memory controller), wherein the coherent cache or memory-side buffer chiplet is coupled to an accelerator, a processor, and a memory, according to at least one embodiment.

[0039] [ [picture]

[11] ] illustrates the architecture of a coherent cache or memory-side buffer chiplet having multiple controllers and multiple cache banks, according to at least one embodiment.

[0040] [ [picture]

[12] ] illustrates a device comprising a memory and corresponding logic, wherein the memory comprises a ferroelectric (FE) memory bit cell, according to at least one embodiment.

[0041] [ [picture]

[13] ] illustrates a high-level architecture of an artificial intelligence (AI) machine comprising a compute die located on top of a memory die, according to at least one embodiment.

[0042] [ [picture]

[14] ] illustrates a 3-input majority gate using nonlinear input capacitors, according to at least one embodiment.

[0043] [ [picture]

[15] ] illustrates a complex logic gate implemented using a 5-input majority gate, according to at least one embodiment.

[0044] [ [picture] [16A]] shows [picture] The structure of [8E], subsequent to a process for forming an opening in a second dielectric formed above a ferroelectric memory device and forming a groove opening in a logic area, according to at least one embodiment.

[0045] [ [picture] [16B]] shows [picture] The structure of [16A], subsequent to a process for forming a mask on a second dielectric in an opening in a memory region, in a trench opening, wherein the mask forms a through-hole opening in one of the trench openings.

[0046] [ [picture] [16C]]Drawing [picture] The structure of [16B] is followed by a process for removing the mask and exposing the ferroelectric memory devices in each opening in the memory area, and removing the mask in the logic area.

[0047] [ [picture] [16D]] shows [picture] The structure of [16C] follows a process for forming a through-hole electrode in an opening in a memory area. Implementation

[0048] Pocket integration procedures for embedded memory are described. Although various embodiments are described with reference to FeRAM, the capacitive structures formed herein may be used in any application in which capacitance is required. For example, the capacitive structures may be used to fabricate ferroelectric-based or paraelectric-based majority gates, minority gates, and / or threshold gates. In the following description, a number of specific details, such as structural schemes and detailed manufacturing methods, are presented to provide a thorough understanding of the embodiments of the present disclosure. Those skilled in the art will appreciate that the embodiments of the present disclosure may be implemented without these specific details. In other examples, well-known features (such as process equipment and device operation) are described with less detail to avoid unnecessarily obscuring the embodiments of the present disclosure. Furthermore, it should be understood that the various embodiments shown in the figures thereof are illustrative representations and are not necessarily drawn to scale.

[0049] In some instances, in the following description, well-known methods and devices are shown in block diagram form (rather than in detail) to avoid obscuring the present disclosure. References throughout this specification to "an embodiment" or "an embodiment" indicate that a particular feature, structure, function, or characteristic described with respect to that embodiment is included in at least one embodiment of the present disclosure. The appearance of the phrase "in an embodiment" or "in an embodiment" in various places throughout this specification does not necessarily refer to the same embodiment of the present disclosure. Furthermore, particular features, structures, functions, or characteristics may be combined in any appropriate manner in one or more embodiments. For example, a first embodiment may be combined with a second embodiment wherever the particular features, structures, functions, or characteristics associated with the two embodiments are not mutually exclusive.

[0050] As used in the specification and the appended claims, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all combinations of one or more of the associated listed items.

[0051] The terms "coupled" and "connected" (along with their derivatives) may be used herein to describe functional or structural relationships between components. It should be understood that these terms are not intended to be synonymous with each other. Rather, in certain embodiments, "connected" may be used to indicate that two or more elements are in direct physical, optical, or electrical contact with each other. "Coupled" may be used to indicate that two or more elements are in direct or indirect (with other intervening elements) physical, electrical, or magnetic contact with each other, and / or that two or more elements cooperate or interact with each other (e.g., as in a cause and effect relationship).

[0052] As used herein, the terms "above," "below," "between," and "on" refer to the relative position of one component or material with respect to other components or materials where such physical relationships are significant. For example, in the context of materials, a material or materials disposed above or below another may be in direct contact or may have one or more intervening materials. Furthermore, a material disposed between two materials may be in direct contact with the two layers or may have one or more intervening layers. In contrast, a first material "above" a second material is in direct contact with the second material / materials. Similar distinctions will be made in the context of component combinations. As used throughout this specification (and in the claims), any combination of the listed items may be referred to by the terms "at least one of" or "one or more of."

[0053] The term "adjacent" herein generally refers to the position of something next to (eg, next to or close to, with one or more things interposed therebetween) or adjacent to (eg, next to) another thing.

[0054] The term "signal" may refer to at least one current signal, voltage signal, magnetic signal, or data / clock signal. The meanings of "a", "an", and "the" include plural references. The meaning of "in..." includes "in" and "on...".

[0055] The term "device" may generally refer to an apparatus depending on the context in which the term is used. For example, a device may refer to a stack of layers or structures, a structure or layer, a connection of structures having active and / or passive components, etc. In general, a device is a three-dimensional structure having a plane along the xy direction of an xyz Cartesian coordinate system and a height along its z direction. The plane of a device may also be the plane of the apparatus containing the device.

[0056] As used throughout this specification (and in the claims), the term "at least one of" or "one or more of" may mean any combination of the listed items.

[0057] Unless otherwise indicated in the clear context of its use, the terms "substantially equal to," "approximately equal to," and "approximately equal to" mean that there is no more than an incidental variation between the two things being described. In the art, such variations are typically no more than + / - 10% of the intended target value.

[0058] The terms "left", "right", "front", "back", "top", "bottom", "above", "below", etc., if any, in the specification and in the claims are used for descriptive purposes and are not necessarily used to describe permanent relative positions. For example, as used herein, the terms "above", "below", "front", "back", "top", "bottom", "above", "below", and "upper" refer to the relative position of a component, structure, or material relative to other referenced components, structures, or materials within a device where such physical relationships are significant. These terms are employed herein for descriptive purposes and primarily in the context of the z-axis of the device, and thus may be relative to the orientation of the device. Thus, in the context of the figures provided herein, a first material "above" a second material may also be "below" the second material if the device is oriented upside down relative to the context of the figures provided. In the context of materials, a material disposed above or below another may be in direct contact or may have one or more intermediate materials. Furthermore, a material disposed between two materials may directly contact the two layers or may have one or more intermediate layers. In contrast, a first material "on" a second material is in direct contact with the second material. Similar distinctions will be made in the context of component combinations.

[0059] The term "between" may be employed in the context of the z-axis, x-axis, or y-axis of a device. A material between two other materials may be in contact with one or both of those materials, or it may be separated from both of the other two materials by one or more intermediate materials. A material "between" two other materials may thus be in contact with either of the other materials, or it may be coupled to the other two materials through intermediate materials. A device between two other devices may be directly connected to one or both of those devices, or it may be separated from both of the other two devices by one or more intermediate devices.

[0060] Perovskite FeRAM devices are advantageous for high-density memory applications due to their low power consumption and high on / off ratio. Perovskite FeRAM devices are also superior to other forms of memory (such as magnetic tunneling junction-based devices) due to the relatively low number of layers implemented for device functionality. A typical FeRAM can fully operate with three layers, in which a ferroelectric dielectric is contained between two electrode layers. The electrode layers may also include perovskite materials to enable lattice matching and reduced resistance. The introduction of lead-free perovskite materials provides additional environmental benefits without sacrificing device performance.

[0061] Ferroelectric capacitors can be integrated with transistors to form FeRAM devices. FeRAM devices can be directly adjacent to logic regions to enable system functions. In particular, ferroelectric capacitors can be formed at the level of routing interconnects that are directly adjacent to the logic region. The height of the level can be affected by the total combined thickness of vias and metal lines in the routing interconnects in the logic region. However, the ferroelectric capacitor can include a total thickness that depends on the thickness of the individual layers in the memory device, where the thickness can be equal to the thickness of one or more levels of routing interconnects.

[0062] For manufacturability, the ferroelectric capacitors in the plurality of ferroelectric capacitors may generally be formed directly on respective transition electrodes. The transition electrodes may be directly between the ferroelectric capacitors and respective conductive interconnects (which are coupled to respective transistors at a lower level). The transition electrodes are widely implemented because the conductive interconnects are formed from materials such as copper. The transition electrodes may act as diffusion barriers, wherein the transition electrodes may have a surface area greater than the surface area of ​​the conductive interconnects to prevent copper from being exposed during formation of the ferroelectric capacitors.

[0063] However, the transition electrode may increase the overall thickness of the ferroelectric capacitor. The increase in thickness may require additional levels of routing interconnects in the logic area. The additional layers may be detrimental to cost as well as to resistance. For example, in some cases, the increase in thickness of the ferroelectric capacitor is incrementally smaller than what may be required for routing interconnects at a level greater than the logic area. In some such examples, the via electrode coupled to the ferroelectric capacitor may have to be unnecessarily taller to cover the total thickness of the routing interconnects at a level greater than the logic area. Increasing the thickness of the via electrode may increase the resistance of the wires in the ferroelectric capacitor.

[0064] However, to reduce the overall height of the ferroelectric capacitor, the transition electrode may be removed. However, the relative area of ​​the bottommost layer of the ferroelectric capacitor may be tuned relative to the area of ​​the top surface of the conductive interconnect, depending on the material of the conductive interconnect. In examples where the conductive interconnect may include copper, it is highly desirable that the ferroelectric capacitor have an area footprint where the perimeter of the area footprint overlaps the perimeter of the conductive interconnect. The overlap may prevent copper exposure while the patterning process is performed to form the ferroelectric capacitor. In other examples, when the conductive interconnect includes a material other than copper, the area footprint of the ferroelectric capacitor may be less than, equal to, or greater than the area footprint of the conductive interconnect.

[0065] Although the transition electrode can be removed in the memory region, in at least one embodiment, an insulator layer is implemented to facilitate the formation of the transition electrode, which can remain in the logic region. The insulator layer can be in direct contact with the conductive interconnects in the logic region. The insulator layer can be advantageously implemented in the logic region so as to target a known thickness of dielectric material for patterning vias between respective conductive interconnects and metal lines in the logic region.

[0066] The inventors have invented a method that provides a ferroelectric capacitor located on a conductive interconnect in the memory region and an insulator layer only in the logic region. The method further facilitates the formation of a ferroelectric capacitor having a thickness that can be tuned to a desired thickness that substantially falls within a level of a routing interconnect in the logic region. In addition, the method allows the implementation of an insulator layer having a substantially fixed thickness in the logic region. The method utilizes a multi-step subtractive patterning process, wherein a first operation forms a ferroelectric capacitor device and a second operation forms a routing interconnect in the logic region. In an exemplary embodiment, the second process also includes patterning an encapsulation around the device.

[0067] To enable high density FeRAM devices, the inventors have resorted to lead-free based perovskite materials due to their environmental friendliness for high volume manufacturing. The stack of ferroelectric capacitors may include one or more hard mask materials. The hard mask materials may include dielectric materials, metal materials, or a combination thereof. The implementation of an etch (such as a reactive ion etch, or plasma etch process) with high selectivity between the hard mask and the device layer may advantageously enable a total stack thickness that is less than the total thickness of the layers in the adjacent conductive interconnect level.

[0068] In at least one embodiment, the conductive interconnects coupled to the individual ferroelectric capacitors are discrete island structures. In other embodiments, the conductive interconnects may be continuous trench lines, where a plurality of capacitors may be coupled to the trench lines. In some such embodiments, the encapsulation layer may be continuous between the individual ferroelectric capacitors and extend along the length of the trench lines. In further embodiments, the conductive interconnects are discrete, but the top electrodes of the individual ferroelectric capacitors are coupled together by conductive plates. The conductive plates may be at the same level as the routing interconnects.

[0069] [picture] [1A] is a cross-sectional view of a device structure 100, including a region 101A adjacent to a region 101B. Regions 101A and 101B may be, for example, a memory region and a logic region, respectively or vice versa. In at least one embodiment, region 101A is a memory region and region 101B is a logic region. Memory region 101A includes a plurality of conductive interconnects, such as conductive interconnects 102 within level 104. Device structure 100 further includes a second level 106 above level 104. Second level 106 may include memory devices. In at least one embodiment, second level 106 includes a plurality of ferroelectric memory devices, such as ferroelectric memory devices 108 above respective conductive interconnects 102. To protect layers within ferroelectric memory device 108 from degradation during the manufacturing process, encapsulation layer 114 is adjacent to the sidewalls of ferroelectric memory device 108 and on the top surface of ferroelectric memory device 108. In at least one embodiment, the encapsulation layer 114 is on the sidewalls 108A and the top surface 108B of the ferroelectric memory device 108 .

[0070] The ferroelectric memory device 108 may be wider or narrower than the conductive interconnect 102, depending on the material of the conductive interconnect 102. In at least one embodiment, the ferroelectric memory device 108 is wider than the conductive interconnect 102 and may include a material such as copper or cobalt. The encapsulation layer 114 has a thickness, T EC, as measured from the sidewall 108A. In at least one embodiment, the encapsulation layer 114 also extends laterally over the uppermost surface 136A of the dielectric 136, beyond the thickness, T EC. The lateral extension 114B may have a length, L EX, as measured laterally from the outermost sidewall 114A of the encapsulation layer 114. The encapsulation layer 114 may extend laterally over a portion of the uppermost surface 136A of the dielectric 136, a distance that is at least 25% of the thickness, T EC, of ​​the encapsulation layer 114. L EX may be between 2 nm and 10 nm. The lateral extension 114B of the encapsulation layer 114 may not be symmetrical about the ferroelectric memory device 108 .

[0071] In at least one embodiment, the encapsulation layer 114 has a thickness that is large enough so that the encapsulation layer 114 does not extend laterally beyond the thickness, TEC, such as [picture] [1B] In at least one embodiment, TEc may also vary with the height or vertical thickness, TMD, of the ferroelectric memory device 108. TEc may increase or decrease with TMD.

[0072] In at least one embodiment, [picture] The encapsulation layer 114 shown in [1B] may further extend below the uppermost surface 136A of the dielectric 136 or the lowermost surface 108D of the ferroelectric memory device 108, such as [picture] [1C] is shown. In some such embodiments, dielectric 136 has an uppermost surface 136A and a lower surface 136B lower than uppermost surface 136A. In at least one embodiment, lower surface 136B is substantially flat. Lower surface 136B may be inclined. As shown, when the dielectric includes a recessed lower surface 136B, encapsulation layer 114 may further extend over lower surface 136B and over sidewall portion 136C. Sidewall portion 136C may be substantially aligned with sidewall 108A.

[0073] In other embodiments, the encapsulation layer 114 may also extend laterally to the lower surface 136B. [picture] In an embodiment, the dielectric 136 has one or more properties of the dielectric 136, and the encapsulation layer 114 has one or more properties of the encapsulation layer 114, as shown in FIG. [picture] [1C]. [picture] As shown in [1D], the lateral extension of the encapsulation layer 114 can be on the lower surface 136B. In other embodiments, the encapsulation layer 114 follows the surface topography of the lower surface 136B of the dielectric 136. The different surface topography discussed above is the result of the processing sequence used to manufacture the ferroelectric memory device 108.

[0074] Reference again [picture] [1A], the second level 106 also includes a via electrode 116, which is coupled to a respective ferroelectric memory device 108. As shown, the ferroelectric memory device 108 has a vertical thickness T MD, and the via electrode 116 has a vertical thickness, T VE. The second level 106 has a vertical thickness, T 106, which is substantially equal to the combined sum of T MD and T VE. The individual thicknesses T MD and T VE can be selected dependently to optimize the ferroelectric memory device 108. For example, a thicker T MD corresponds to a thinner T VE, and vice versa.

[0075] In at least one embodiment, logic region 101B includes an interconnect structure 117 covering level 104 and second level 106. Interconnect structure 117 includes one or more conductive interconnects at level 104 and one or more vias and metal lines coupled to conductive interconnect 118 at second level 106. In at least one embodiment, interconnect structure 117 includes conductive interconnect 118 at level 104 and a plurality of metal lines 120 and 122, wherein metal line 122 is coupled to conductive interconnect 118 through via 124. Metal line 122 may be coupled to conductive interconnect through vias on different planes, behind the plane of the illustration.

[0076] The via 124 has a vertical thickness TV, as measured from the lowest point of the level 104 or from the uppermost surface 118A of the conductive interconnect 118, and the metal line 122 has a vertical thickness TM. T106 is also substantially equal to the combined sum of TM and TV. In an exemplary embodiment, the combined sum of TM and TV is equal to the combined sum of the respective thicknesses TMD and TVE. In general, TM and TVE need not be equal. TM may be greater than TVE or vice versa. In at least one embodiment, TVE is greater than TM when TMD is less than TV. In at least one embodiment, TVE may be greater than four times TM when TMD is less than 20 nm. In some such embodiments, TM may be between 20 nm and 50 nm.

[0077] In other embodiments, when TMD is greater than TV, TVE is between 5% and 20% of TM. For example, TMD may be 100 nm. In other embodiments, TM may be between 20 nm and 200 nm.

[0078] The logic region 101B also includes an etch stop layer 126 between the conductive interconnect 118 and the metal line 122. In at least one embodiment, the etch stop layer 126 encompasses the logic region 101B and is directly above a portion of the conductive interconnect 118. The via 124 is coupled to the conductive interconnect 118 through the etch stop layer 126. The etch stop layer 126 has a thickness TL. TL can be selected based on the desired profile and thickness of the via 124, as will be discussed further below. The etch stop layer 126 includes a material different from the material of the encapsulation layer 114.

[0079] In at least one embodiment, a portion 108C (herein, stacked portion 108C), which includes one or more layers of the ferroelectric memory device 108, is disposed on the dielectric 136 adjacent to the etch stop layer 126, as shown. The stacked portion 108C may extend along the sidewalls 126A to various heights. The stacked portion 108C may be an artifact of a process used to manufacture the device structure 100. Other embodiments of the device structure 100 may not include the stacked portion 108C.

[0080] In at least one embodiment, each ferroelectric memory device 108 within the device structure 100 is substantially identical. Although two ferroelectric memory devices 108 are shown, an array may have more than 1000 substantially identical ferroelectric memory devices 108. Adjacent ferroelectric memory devices 108 may be laterally separated from each other by a distance SM. SM may range between 20 nm and 50 nm. The separation, SM, depends on the separation, S IC, between adjacent conductive interconnects 102; and depends on the lateral thickness, W CI, of the conductive interconnect 102, as will be discussed further below.

[0081] In an embodiment, the SM may depend on the stacking of layers within the ferroelectric memory device 108. Depending on the embodiment, the ferroelectric memory device 108 may have three or more layers. An embodiment of a ferroelectric memory device 108 including five layers is shown in FIG. [picture] [1E]. As shown, the ferroelectric memory device 108 includes a bottom electrode 128, a ferroelectric oxide layer 130, and a top electrode 132. In at least one embodiment, the ferroelectric memory device 108 also includes a diffusion barrier layer 135. The diffusion barrier layer 135 may be implemented when the conductive interconnect 102 includes a material such as copper or cobalt. The diffusion barrier layer 135 may include materials such as (but not limited to) Al2O3, AlOx, HfOx, ZrOx, TaOx, TiOx, SiOx, SiN, SiCN, SiC, SiON, AlSiOx, HfSiOx, TaSiOx, TiON, TaON. AlN, ZrN, HfN, TiAlN, TiAlO, TiAl, W, Ru, Ir, Mo, Ta, Zr, Hf, Nb.

[0082] In one embodiment, the bottom electrode 128 and the top electrode 132 include a conductive ferroelectric oxide. The conductive ferroelectric oxide includes one of the lead-free perovskite metal oxides, such as (but not limited to) La-Sr-CoO 3, SrRuO 3, La-Sr-MnO 3, YBa 2Cu 3O 7, Bi 2Sr 2CaCu 2O 8, or LaNiO 3.

[0083] In one embodiment, the ferroelectric oxide layer 130 is a ferroelectric dielectric layer that includes a lead-free perovskite material in the form of ABO 3, where A and B are two cations of different sizes and O is oxygen. The size of A is generally larger than that of B. In at least one embodiment, the lead-free perovskite may also be doped, for example, with La or lanthanides. The lead-free perovskite material may include one or more of the following: La, Sr, Co, Cr, K, Nb, Na, Sr, Ru, Y, Fe, Ba, Hf, Zr, Cu, Ta, Bi, Ca, Ti, and Ni.

[0084] In other embodiments, the ferroelectric dielectric layer includes a low voltage ferroelectric material between the top electrode 132 and the bottom electrode 128. These low voltage FE materials may be in the form of AA'BB'O 3, where A' is a dopant for atomic site A and may be an element selected from the lanthanide series, and where B' is a dopant for atomic site B and may be an element selected from transition metal elements, such as Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn. A' may have the same atomic valence of site A, with different ferroelectric polarizability. Voltages below X volts are low enough to be characterized as low voltages.

[0085] The ferroelectric memory device 108 may also include a hard mask 134, as shown. In at least one embodiment, the hard mask 134 may be a dielectric, wherein the dielectric includes a material such as silicon and one or more of nitrogen, oxygen, or carbon. In other embodiments, the hard mask includes a conductive material, such as tantalum, titanium, ruthenium, or an alloy of nitrogen and one or more of tantalum, titanium, and ruthenium. The combined thickness of the layers in the ferroelectric memory device 108 may range between 7 nm and 100 nm.

[0086] In at least one embodiment, where the ferroelectric memory device 108 includes a hard mask 134, the material of the hard mask 134 will determine whether the via electrode 116 contacts the hard mask 134 or extends through a portion of the hard mask 134 and contacts the top electrode 132. [picture] As shown in [1F], where the hard mask 134 comprises a conductive material, the via electrode 116 is in contact with the uppermost hard mask surface 134A. In other embodiments, where the hard mask 134 comprises a dielectric material, the via electrode 116 extends through the hard mask 134 and contacts the uppermost surface 108B, as shown in [1F]. [picture] As shown in [1G].

[0087] In a further embodiment, the ferroelectric memory device 108 includes a dual hard mask, wherein the hard mask 134 is a dielectric and the hard mask 144 includes a conductive material, such as [picture] [1H] [.] A dual hard mask including hard mask 144 may be advantageous when ferroelectric memory device 108 has a thickness T MD that is substantially less than TV (the thickness of via 124). For example, in at least one embodiment, T MD is between 10 nm and 30 nm and TV is 100 nm, where the ratio is between 1:3 and 1:10. In some such embodiments, hard mask 144 compensates for the shorter length of ferroelectric memory device 108.

[0088] Reference again [picture] [1A], conductive interconnect 118 has one or more properties of conductive interconnect 102. Conductive interconnects 102 and 118 include materials such as copper or tungsten. Conductive interconnects 102 and 118 have a thickness that covers a portion of dielectric 136 within level 104. There may be other vias and interconnect routing connections within level 104, which are not shown in the figure. In one embodiment, via electrode 116, via 124, metal lines 120 and 122 include the same or substantially the same material. In at least one embodiment, via electrode 116, via 124, metal lines 120 and 122 include the same or substantially the same material as conductive interconnect 102.

[0089] In various embodiments, the via electrode 116 , the via 124 , the conductive interconnects 102 and 118 may be discrete vias or continuous trenches.

[0090] According to the embodiments of the present disclosure, [picture] [1I] System [picture] [1A] isometric view of device structure 100, wherein conductive interconnect 102 is a discrete island. As shown, memory region 101A in device structure 100 further includes a plurality of memory devices, such as ferroelectric memory device 140 (illustrated through a cutout in encapsulation layer 114). Ferroelectric memory device 140 is on plane 141, behind ferroelectric memory device 108. Ferroelectric memory device 140 is substantially identical to ferroelectric memory device 108 and has all of its properties. In at least one embodiment, each ferroelectric memory device 108 or ferroelectric memory device 140 has a cylindrical shape. In at least one embodiment, each ferroelectric memory device 140 is coupled to conductive interconnect 102 (which is a discrete island). Ferroelectric memory device 140 can be isolated from ferroelectric memory device 108 by a distance, S M2. In at least one embodiment, discrete via electrodes 116 are coupled to respective ferroelectric memory devices 108 or ferroelectric memory devices 140 .

[0091] The ferroelectric memory device 108 may have a width WMD that is less than or greater than the width WCI of the conductive interconnect 102. In one embodiment, WCI is less than WMD when the conductive interconnect comprises, for example, copper. In another embodiment, WCI is greater than WMD (e.g., the conductive interconnect 102 in the dashed line in the figure) when the conductive interconnect comprises, for example, a conductive material other than copper.

[0092] In at least one embodiment, the conductive interconnect 118 is a conductive interconnect 118 and extends along the y direction. As shown, the metal lines 120 and 122 also extend along the y direction. In at least one embodiment, the via 124 may be the only conductive via between the metal line 122 and the conductive interconnect 118. In other embodiments, the interconnect structure 117 may include a plurality of vias, such as the via 124 between the metal line 122 and the conductive interconnect 118, to prevent an increase in line resistance.

[0093] In at least one embodiment, the stack portion 108C extends along the y-direction, parallel to the metal lines 120 and 122 .

[0094] In at least one embodiment, the via electrodes 116 coupled to the ferroelectric memory devices 108 and 140 may be further coupled together by a common plate electrode 142, such as in [picture] [1J] is shown in the cross-sectional view. The logic region 101B is not shown for the purpose of clarity. In one such embodiment, the plate electrode 142 can extend over the top of all memory devices (such as ferroelectric memory devices 108 and 140) and couple thereto through respective via electrodes 116. In an embodiment, the plate electrode 142 is within the second level 106.

[0095] In at least one embodiment, the conductive interconnect 102 includes a material other than copper, such as tungsten, ruthenium, titanium, tantalum, and / or a nitride of tungsten, ruthenium, titanium, or tantalum. In some such embodiments, the conductive interconnect 102 may be equal to or wider than the ferroelectric memory device 108, such as in [picture] [2A] is shown. In one such embodiment, the conductive interconnect 102 extends continuously along the longitudinal direction, such as (for example) from the ferroelectric memory device 108 to the ferroelectric memory device 140, as shown. In at least one embodiment, the ferroelectric memory device 108 has a width WMD that is less than the width WCI of the conductive interconnect 102 along the length LCI.

[0096] In at least one embodiment, in which the ferroelectric memory device 108 extends over a portion (but not all) of the conductive interconnect 102, the encapsulation layer 114 may also extend over the conductive interconnect 102 in one or both of the x and y directions, such as [picture] [2A] In at least one embodiment, the encapsulation layer 114 is above and adjacent to each of the ferroelectric memory devices 108 and 140.

[0097] In at least one embodiment, where the conductive interconnect 102 extends along the y-direction but includes a material other than copper, the encapsulation layer 114 may also extend continuously along the y-direction, such as [picture] [2B] is shown. Logic region 101B is omitted for clarity. In some such embodiments, ferroelectric memory device 108 may have a width W MD that is greater than or less than the width W CI of conductive interconnect 102. In at least one embodiment, W MD is greater than the width W CI of conductive interconnect 102.

[0098] In further such embodiments, encapsulation layer 114 has a lateral thickness W EC that is at least equal to or greater than W CI and a length L EC that extends along the y-direction. Encapsulation layer 114 can provide protection from oxidation of the uppermost surface of conductive interconnect 102 .

[0099] In at least one embodiment, each ferroelectric memory device 108 or ferroelectric memory device 140 has a cylindrical shape. In some such embodiments, WMD is the diameter of each ferroelectric memory device 108 or ferroelectric memory device 140.

[0100] In other embodiments, the encapsulation layer 114 is continuous between adjacent ferroelectric memory devices 108, between adjacent ferroelectric memory devices 140, and between ferroelectric memory devices 108 and 140. [picture] [3] In some such embodiments, the encapsulation layer 114 may also extend over the etch stop layer 126.

[0101] [picture] [4] Department [picture] An embodiment of the structure of [2A], wherein the encapsulation layer 114 has a lateral extension that extends beyond the thickness T EC of the encapsulation layer 114, but the lateral thickness (or width) W EC varies along the y-direction.

[0102] [picture] [5] A flow chart for forming a plurality of ferroelectric memory devices in a memory region and conductive interconnects in a logic region, according to an embodiment of the present disclosure. The method begins at operation 510, wherein the plurality of conductive interconnects are formed of a dielectric. The method 500 continues at operation 520, wherein an etch stop layer is deposited on the dielectric and on the plurality of conductive interconnects, and the etch stop layer is removed from the memory region but not from the logic region. The method continues at operation 530, wherein a stack of material layers is deposited to form a memory device on an electrode material. The method continues at operation 540, wherein the process patterns the stack of material layers to form a memory device on each conductive interconnect in the memory region. The method continues at operation 550, wherein an encapsulation layer is deposited on the memory device. The method continues at operation 560, wherein a mask is formed on the encapsulation layer and the encapsulation layer and the electrode material are patterned, wherein the mask is over each memory device. The method continues at operation 570, wherein a dielectric layer is deposited as a capping layer. The method continues at operation 580 where one or more openings are formed in the dielectric layer and expose one or more conductive interconnects in the logic region. The method continues at operation 590 where one or more interconnect vias are formed in the one or more openings and metal lines in respective interconnect vias. [] []

[0103] [picture] [6A] is a cross-sectional view of a plurality of conductive interconnects 102 and 118 formed in a dielectric 136 on a substrate 600. In at least one embodiment, the conductive interconnect 102 is formed in a memory region and the conductive interconnect 118 is formed in a logic region. In an exemplary embodiment, there may be one or more transistors and interconnects at different levels between the conductive interconnects 102 and 118 and the substrate 600. In high density memory applications, the number of conductive interconnects may range between 1K and 5K within a given array in the memory region 101A. The conductive interconnects 102 and 118 have a lateral thickness WCI, which may be determined by a minimum acceptable resistance value. In at least one embodiment, the conductive interconnect 102 is a discrete structure that is substantially circular or elliptical in shape; and the conductive interconnect 118 is a trench line. The conductive interconnect 102 may have a maximum lateral thickness between 20nm and 40nm. For example, the conductive interconnect 102 may have a lateral thickness between 20 nm and 40 nm, along the x-direction, as shown. In other embodiments, each of the conductive interconnects 102 and 118 is a line extending into the plane of the graphic. As shown, the conductive interconnects 102 and 118 have substantially the same lateral thickness to minimize variability in device performance.

[0104] In at least one embodiment, conductive interconnects 102 and 118 are electrically or mechanically coupled to vias and / or lines, such as vias 601 and / or lines 601 indicated in dashed boxes in the figure. Vias 601 and / or lines 601 may include the same or substantially the same material as conductive interconnects 102.

[0105] In one or more embodiments, the conductive interconnects 102 and 118 include copper. In at least one embodiment, the conductive interconnects 102 and 118 include a liner layer and a fill metal on the liner layer. For example, the liner layer may include a material such as (but not limited to) ruthenium, cobalt, or tantalum, and the fill metal may include copper or tungsten. In one embodiment, each of the conductive interconnects 102 is separated by a spacer SIC. The SIC is essentially determined by the design density of the ferroelectric memory device to be fabricated in a given area, and the underlying structure embedded in the layer below the conductive interconnect 102.

[0106] In one embodiment, an etch stop layer 126 is deposited on the conductive interconnects 102 and 118 and on the dielectric 136. The etch stop layer 126 is deposited to a thickness selected to accommodate the height of the vias to be formed and to target etching in the logic region 101B in downstream operations. In one embodiment, the etch stop layer 126 also acts as a diffusion barrier layer. The diffusion barrier layer is necessary to prevent diffusion of copper from the conductive interconnect 118 to the ferroelectric memory device to be formed. As such, the etch stop layer 126 includes materials such as (but not limited to) silicon and one or more of nitrogen, oxygen, or carbon.

[0107] [picture] [6B] [picture] [6A] is a cross-sectional view of the structure following a process for etching a portion of the etch stop layer 126 from the memory region. In one embodiment, a photoresist mask 602 is formed on the etch stop layer 126 by lithography. The exposed portion of the etch stop layer 126 can be etched through the opening in the photoresist mask 602 by a plasma etching process. The etching process isolates the etch stop layer 126 to the logic region 101B and exposes the dielectric 136 and the conductive interconnect 102 in the memory region. The substrate 600 is not shown in FIG. [picture] [6B-9B], for the sake of clarity.

[0108] [picture] [6C] Department [picture] [6B] is a cross-sectional view of the structure, following a blanket deposition process of a material layer stack 606 for forming memory devices on conductive interconnects 102 and 118 and on dielectric 136, followed by deposition of a hard mask layer 608 on the material layer stack 606 and formation of a photoresist mask 609 on the hard mask layer 608, in accordance with an embodiment of the present disclosure. In an exemplary embodiment, the etch stop layer 126 and all layers of the material layer stack 606 are deposited in situ, e.g., without breaking vacuum. The material layer stack 606 may be deposited by an atomic layer deposition (ALD) process, a plasma enhanced chemical vapor deposition (PECVD), a chemical vapor deposition (CVD), or a physical vapor deposition (PVD) process. In at least one embodiment, a conductive layer 606A is blanket deposited on the electrode material 604. In an exemplary embodiment, the conductive layer 606A comprises a conductive ferroelectric oxide. The conductive ferroelectric oxide includes one of the lead-free perovskite metal oxides, such as (but not limited to) La-Sr-CoO3, SrRuO3, La-Sr-MnO3, YBa2Cu3O7, Bi2Sr2CaCu2O8, or LaNiO3.

[0109] Conductive layer 606A is deposited to a thickness T1 that is suitable for minimizing resistance and outwardly tapering into the sidewalls during a patterning process used to fabricate a ferroelectric memory device. In at least one embodiment, conductive layer 606A has a thickness between 3 nm and 30 nm. A thickness less than 30 nm is highly desirable to prevent significant tapering of the sidewalls during the patterning process.

[0110] The deposition process continues with the deposition of a ferroelectric dielectric layer 606B. In an exemplary embodiment, the ferroelectric dielectric layer 606B is deposited as a blanket layer on the conductive layer 606A. The ferroelectric dielectric layer 606B has a thickness T2 between 1 nm and 30 nm. In at least one embodiment, the ferroelectric dielectric layer 606B includes a lead-free perovskite material in the form ABO3, where A and B are two cations of different sizes and O is oxygen. The size of A is typically larger than that of B. In at least one embodiment, the lead-free perovskite may also be doped, for example, with La or lanthanides. The lead-free perovskite material may include one or more of the following: La, Sr, Co, Cr, K, Nb, Na, Sr, Ru, Y, Fe, Ba, Hf, Zr, Cu, Ta, Bi, Ca, Ti, and Ni.

[0111] In other embodiments, the ferroelectric dielectric layer 606B includes a low voltage ferroelectric material between the conductive oxide layers (606A and 606C). The low voltage material can be of the form AA'BB'O3, where A' is a dopant for atomic site A and can be an element selected from the lanthanide series, and where B' is a dopant for atomic site B and can be an element selected from transition metal elements, such as Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn. A' can have the same atomic valence of site A, with different ferroelectric polarizability. Voltages below 3 volts are low enough to be characterized as low voltage.

[0112] The deposition process continues with the deposition of a conductive layer 606C on the ferroelectric dielectric layer 606B. In an exemplary embodiment, the conductive layer 606C comprises a material that is the same or substantially the same as the material of the conductive layer 606A. When the conductive layers 606A and 606C comprise the same material, the material layer stack is symmetrical. In various embodiments, the conductive layer 606C may have a different thickness than the conductive layer 606A. It is desirable for the conductive layer 606C to be as thin as possible to facilitate manufacturing. In an embodiment, the conductive layer 606C is deposited to a thickness T3 between 3 nm and 30 nm.

[0113] The deposition process ends with the formation of a hard mask layer 608 on the conductive layer 606C. In some embodiments, the hard mask layer 608 is deposited as a blanket layer by a PECVD, CVD, or PVD process. In one embodiment, the hard mask layer 608 comprises a material having a desired etch selectivity relative to the ferroelectric material in the material layer stack 606. In at least one embodiment, the hard mask layer 608 comprises a material that can be patterned with high fidelity relative to the masking layer formed on the hard mask layer 608, such as SiO 2, Si 3N 4, DLC (diamond-like carbon), or Al 2O 3. In at least one embodiment, the hard mask layer 608 may include a conductive material different from the conductive material of the ferroelectric material. In at least one embodiment, it is desired to deposit the hard mask layer 608 to a thickness T 4, which enables patterning of at least the conductive layer 606C. In other embodiments, the hard mask layer 608 may be deposited to a thickness T 4, which depends on the total thickness of the material layer stack 606. T4 may be at least 20 nm.

[0114] In one embodiment, a photoresist mask 609 is formed on the hard mask layer 608 and is formed by a lithography process. The photoresist mask 609 includes blocks 609A and 609B. Each block 609A-B is a mask for patterning discrete FeRAM devices.

[0115] [picture] [6D] Department [picture] [2D] is a cross-sectional view of the structure in Figure 1, following a process for patterning the hard mask layer and the layers in the material layer stack 606. In one embodiment, the hard mask layer is etched by a plasma etching process to form the hard mask 134. The plasma etching process may include a discharge generated by a magnetically enhanced reactive ion etching mechanism, an electron cyclotron resonance discharge, or an inductively coupled plasma discharge. The plasma parameters may be characterized by, for example, a plasma density range between 1e9-1e12 ions / cm3, a pressure in the range of 0.001 to 10 Torr, and an electron temperature in the range of 1-8 eV. It is highly desirable to pattern to form the hard mask 134 to have substantially vertical sidewalls to prevent an increase in lateral thickness when the remaining layers in the material layer stack 606 are patterned.

[0116] In an exemplary embodiment, the hard mask 134 has a substantially vertical profile relative to the uppermost surface 136A. In at least one embodiment, the photoresist mask 609 is removed after forming the hard mask 134. The plasma etching process is continued to pattern the conductive layer 606C. The hard mask 134 is utilized to pattern the conductive layer 606C. In one embodiment, the plasma etching process is utilized to etch the conductive layer 606C to form the top electrode 132. In at least one embodiment, the top electrode 132 has a substantially vertical sidewall 132A. In other embodiments, the sidewall 132A is non-vertical and has a slope that is different from 90° relative to the normal to the lowest surface 132B. In at least one embodiment, the hard mask 134 is removed during the plasma etching process (as shown) when the hard mask 134 includes a dielectric material. The etching process is continued to etch the ferroelectric dielectric layer 606B to form an etched ferroelectric oxide layer 130 (hereinafter, ferroelectric dielectric layer 130). In other embodiments, the sidewall 130A of the ferroelectric dielectric layer 130 is inclined.

[0117] The plasma etching process is continued to pattern and form the bottom electrode 128. In one embodiment, the conductive layer 606A ( [picture] [6C]) The process for forming the bottom electrode 128 can be substantially the same as the etching process used to form the top electrode 132. In at least one embodiment, the sidewall 108A of the ferroelectric memory device 108 is substantially perpendicular to the normal line of the uppermost surface 136A or the uppermost surface 108B. In other embodiments, the sidewall 108A is non-perpendicular and has a slope that is different from 90° relative to the normal line of the uppermost surface 136A or the uppermost surface 108B. The process of forming the top electrode 132, the ferroelectric dielectric layer 130, and the bottom electrode 128 also completes the formation of the ferroelectric memory device 108.

[0118] In one embodiment, a stack portion 108C including one or more layers of the ferroelectric memory device 108 is also left as a spacer adjacent to the sidewall 126A of the etch stop layer 126. In various embodiments, the stack portion 108C extends to various points along the sidewall 126A. In at least one embodiment, the dielectric 136 is also suspended from the uppermost surface 136A, as shown in the enhanced image in box 610 and indicated by the dashed line 137, during the patterning to form the bottom electrode 128.

[0119] [picture] [6E] Department [picture] [6D] is a cross-sectional view of the structure, subsequent to a process for depositing encapsulation layer 114 on ferroelectric memory device 108, on portion 108C, and on dielectric 136. In one embodiment, encapsulation layer 114 includes silicon and one or more of carbon, nitrogen, and oxygen. Encapsulation layer 114 may be deposited by a PVD, PECVD, or ALD process. In an exemplary embodiment, encapsulation layer 114 includes a material different from that of etch stop layer 126. Encapsulation layer 114 may include the same elemental composition but different dopant concentrations. The different dopant concentrations may enable etch stop layer 126 to have a higher etch selectivity relative to encapsulation layer 114.

[0120] The deposition process used to form the encapsulation layer 114 may result in conformal deposition on the uppermost surface 108B and on the sidewalls 108A of the ferroelectric memory device 108. In other embodiments, the etch stop layer 126 may be wider at the uppermost surface 108B of the ferroelectric memory device 108 and narrower at its base. The encapsulation layer 114 may be deposited to a thickness T EC between 5 nm and 30 nm. The thickness T EC depends on the maximum spacing S M1 between adjacent ferroelectric memory devices 108.

[0121] [picture] [6F] Department [picture] [6E] is a cross-sectional view of the structure, following a process for forming a mask 611 on the encapsulation layer 114 to isolate each ferroelectric memory device 108. As shown, the mask 611 includes a mask portion 611A at the interface between the memory region 101A and the logic region 101B. In one embodiment, the mask 611 is formed by lithography and includes a photoresist material. The mask portion 611A can be wider or narrower than that depicted. In an exemplary embodiment, the mask portion 611A can have a width WK that is narrow enough to remove the portion 108C.

[0122] Mask 611 may not be perfectly symmetrical about each ferroelectric memory device 108. Asymmetric masking may cause the lateral portions of encapsulation layer 114 to be disproportionate around sidewall 108A. For example, some portions may be wider than other portions. However, the disproportionate level may be retained across each ferroelectric memory device 108. This disproportion is not expected to cause degradation in device performance.

[0123] [picture] [7A] Series [picture] [6F] is a cross-sectional view of the structure of FIG. 6F, following a process for etching the encapsulation layer 114. In one embodiment, a plasma etching process is utilized to etch the encapsulation layer 114 selective to the etch stop layer 126. As discussed above, the encapsulation layer 114 and the etch stop layer 126 may include similar materials, such as silicon nitride doped with impurities. The difference in dopant species may provide selectivity to the etch stop layer 126 (which etches the encapsulation layer 114). In at least one embodiment, the encapsulation layer 114 is removed from a shielded area, such as from the sidewalls of the stack portion 108C, as will be discussed further below.

[0124] [picture] [7B] Series [picture] [7A] is a plan view illustration of the structure in an embodiment in which the conductive interconnect 102 is a discrete island and the mask forms a substantially circular encapsulation layer 114 around the sidewall 108A of the ferroelectric memory device 108. In other embodiments, the encapsulation layer 114 may be rectangular, as indicated by the dashed line 114D. The plan view profile of the ferroelectric memory device 108 may be independent of the plan view profile of the encapsulation layer 114.

[0125] [picture] [7D] Series [picture] [7A] is a plan view illustration of the structure in an embodiment in which the conductive interconnect 102 is a trench and the mask forms an encapsulation layer 114 around the sidewalls 108A of the ferroelectric memory device 108. As shown, the encapsulation layer 114 also extends parallel to the conductive interconnect 102, has a lateral extension LEX, and is similar to [picture] The structure depicted in [2B].

[0126] refer to [picture] [7B-7C], the outermost sidewall 114A of the encapsulation layer 114 may not be perfectly symmetrical about each ferroelectric memory device 108. The asymmetric mask discussed above may cause the lateral portions of the encapsulation layer 114 to be disproportionate around the sidewall 108A. For example, some portions may be wider than other portions. However, the disproportionate level may be retained across each ferroelectric memory device 108. This disproportion is not expected to cause degradation in device performance.

[0127] [picture] [8A] Series [picture] [7A] is a cross-sectional view of the structure, subsequent to a process for forming an opening in the dielectric above the ferroelectric memory device 108. In one embodiment, a capping layer deposition process is utilized to deposit the dielectric 138 on the encapsulation layer 114, on the dielectric 136, and on the etch stop layer 126. The deposition process may be performed by a PVD, PEVCD, or chemical vapor deposition (CVD) process. The dielectric 138 may be planarized after deposition. The mask 613 may be formed on the dielectric 138 by a lithography process. In one embodiment, the opening 615 may be formed in the dielectric 138 by a plasma etching process. The etching process is continued and the encapsulation layer 114 is completely etched above the ferroelectric memory device 108 in the opening 615. According to [picture] [1A] [1D] and [1E], the etching process is further continued to etch the hard mask (if present) and expose the uppermost surface 108B of each ferroelectric memory device 108; or if not present, expose the uppermost surface 108B, as shown. In at least one embodiment, the opening 615 is tapered. In other embodiments, the opening 615 is substantially vertical.

[0128] The total depth of the opening 615 depends on the vertical thickness TMD of the ferroelectric memory device 108. As shown, the dielectric 138 has a thickness approximately equal to the vertical thickness T106 of the second level 106. In other embodiments, the dielectric 136 is recessed as shown in FIG. [picture] [6D] As described above, dielectric 138 also extends below second level 106 into level 104.

[0129] [picture] [8B] Series [picture] [8A] is a cross-sectional view of the structure, following a process for removing mask 613 and depositing conductive material to form via electrode 116. In one embodiment, one or more liner layers are formed in opening 615 on the uppermost layer of ferroelectric memory device 108. In at least one embodiment, a fill metal such as copper, tungsten, nickel, cobalt is deposited on the liner layer. The liner layer includes ruthenium or tantalum. A planarization process may be performed to remove excess conductive material deposited on dielectric 138. In one embodiment, the planarization process includes a chemical mechanical polishing (CMP) process.

[0130] [picture] [8C] Series [picture] The cross-sectional view of the structure in [8B] follows a process for forming a mask 617 on the dielectric 138 and on the via electrode 116. The mask 617 is designed to form an interconnect structure in the logic area 101B. In one embodiment, the mask 617 is formed by lithography and includes a photoresist material.

[0131] [picture] [8D] Series [picture] [8C] is a cross-sectional view of the structure following a process for etching dielectric 138 to form trenches 619A and 619B in logic region 101B. In one embodiment, a plasma etching process is utilized to etch dielectric 138 through openings in mask 617 to form trenches 619A and 619B. Dielectric 138 may be etched to a depth TH and a width WH determined by the thickness TO of dielectric 138 above etch stop layer 126. In an embodiment, TH and WH range between 10 nm and 200 nm and between 10 nm and 50 nm, respectively. WH is determined by the width of the interconnect via to be formed in the trench. The height of the remaining dielectric 138, the difference between TO and TH, (as measured from the uppermost surface of etch stop layer 126), may also be determined by the height and width of the via to be formed in trench 619B. The height and width of the via are determined by the desired minimum line conductance of the via to be formed within trench 619B.

[0132] [picture] [8E] System [picture] [8D] is a cross-sectional view of the structure, following a process for etching dielectric 138 to form a via in a suspended trench in logic region 101B. In one embodiment, the mask used to form trenches 619A and 619B is removed and mask 621 is formed. In one embodiment, mask 621 is formed by lithography and includes a photoresist material. Mask 621 has an opening in trench 619A that is designed to enable etching of dielectric 138 to form via opening 619C, as shown. In at least one embodiment, mask 621 does not include an opening in trench 619A in the plane of the pattern, but may include an opening in a plane behind or before it. In one embodiment, a plasma etching process is utilized to form via opening 619C by etching dielectric 138 and etch stop layer 126. An advantage of the process method outlined herein is that the etch stop layer 126 has a thickness T EC that is determined by the deposition process and is unchanged by the formation of the ferroelectric memory device 108 in the memory region 101A. The formation of the via opening 619C in the stop layer 126 can be targeted and tuned by depositing the etch stop layer 126 to a desired thickness. In at least one embodiment, the formation of the via opening 619C exposes the uppermost surface 118A of the conductive interconnect 118.

[0133] [picture] [8F] Department [picture] [8E] is a cross-sectional view of the structure, subsequent to the process used to remove the mask and deposit conductive material into the openings to form the via 124, and metal lines 120 and 122. The mask used to form the via opening 619C is removed, and the conductive material is deposited into the trenches 619A, 619B and the via opening 619C. In one embodiment, the conductive material comprises a material that is the same or substantially the same as the material of the via electrode 116, including embodiments with or without a liner layer or a fill metal on the liner layer. In at least one embodiment, the fill metal comprises copper, tungsten, nickel, or cobalt, and the liner layer comprises ruthenium or tantalum. In some such embodiments, the liner layer is deposited on the uppermost surface 118A of the conductive interconnect 118, on the sidewalls of the etch stop layer 126, on the dielectric 138, on the uppermost dielectric surface 138A, and on the surface of the via electrode 116. In other embodiments, in which no liner is implemented, fill metal or conductive material is deposited directly on the topmost surface 118A of the conductive interconnect 118, on the sidewalls of the etch stop layer 126, on the dielectric 138, on the topmost dielectric surface 138A, and on the surface of the through-hole electrode 116.

[0134] A planarization process may be utilized to remove excess conductive material deposited on dielectric 138 and on via electrode 116. In one embodiment, the planarization process includes a chemical mechanical polishing (CMP) process. The CMP process isolates metal line 120 from metal line 122. Via 124 is formed at the same time as metal line 122.

[0135] In at least one embodiment, the uppermost surface 116A of the via electrode 116 and the uppermost surfaces 120A and 122A of the metal lines are coplanar or substantially coplanar after the CMP process.

[0136] Typically, the via electrode 116 can be fabricated before or after the via 124 and the metal line 122 are fabricated. [picture] [8A-F] The method described in connection with this may be performed to fabricate the via 124 and the metal line 122 prior to fabrication of the via electrode 116.

[0137] In other embodiments, such as [picture] [16A], opening 615, and trenches 619A and 619B may be formed simultaneously. In some such embodiments, opening 615, and trenches 619A and 619B may have substantially the same depth DH, as shown. DH is less than the total depth TO of dielectric 138, as shown. Trench 619A and 619B have a width WH. WH may be the same or different for trenches 619A and 619B. In one embodiment, a first plasma etch is utilized to etch dielectric 138 selective to encapsulation layer 114, and a second plasma etch selective to dielectric 138 is utilized to etch encapsulation layer 114. In at least one embodiment, depending on the thickness of dielectric 138 and encapsulation layer 114, DH in logic region 101B may be up to 5% greater than DH in memory region 101A.

[0138] The process may be continued to form a mask 621 that covers portions of the opening 615 and the trenches 619A and 619B, such as [picture] As shown in [16B]. [picture] [8E] The plasma etching process described in connection with the above may be performed to form the opening 619C. The plasma etching etches the entire thickness TEC and exposes the uppermost surface 118A. In at least one embodiment, the mask 621 may be removed after the formation of the opening 615 and the trenches 619A and 619B. [picture] As shown in [16C].

[0139] The process may be continued to fill opening 615, trenches 619A and 619B, and opening 619C, as shown in FIG. [picture] The process for filling the opening 615 and the trenches 619A and 619B and forming the via electrode 116, the via 124 and the metal lines 120 and 122 is the same or substantially the same as that of [picture] [8F] The methods described in connection therewith.

[0140] [picture] [9A] Series [picture] [6F] is a cross-sectional view of the structure following a process for etching encapsulation layer 114 to remove or reduce the thickness of portion 108C. In at least one embodiment, mask portion 611A (dashed box) has been removed to facilitate easier removal of encapsulation layer 114 from stack portion 108C and for removal of stack portion 108C in subsequent processing operations.

[0141] In at least one embodiment, plasma etching is utilized to etch the encapsulation layer 114 selectively with respect to the etch stop layer 126 and the dielectric 136 .

[0142] [picture] [9B] Series [picture] [6E] is a cross-sectional view of the structure of FIG. 6E, following a process for forming a mask 623 covering a substantial portion of memory region 101A and following a process for etching and removing encapsulation layer 114 (everything not covered by mask 623). In at least one embodiment, mask 623 exposes logic region 101B. As shown, a plasma etching process is utilized to etch encapsulation layer 114, such as with [picture] [7A] is described in connection with. [picture] [9B], the encapsulation layer remains in the memory region 101A, adjacent to the stack portion 108C and covering the dielectric 136. The encapsulation layer 114 extends continuously between each ferroelectric memory device 108, such as [picture] As shown in [3].

[0143] In other embodiments, the stack portion 108C (adjacent to the sidewall 126A) may be removed by an etching process after the encapsulation layer 114 is removed.

[0144] [picture]

[10] illustrates a computing architecture 1000 having a coherent cache or memory side buffer chiplet (which includes a memory controller), wherein the coherent cache or memory side buffer chiplet is coupled to an accelerator, a processor, and a memory, according to at least one embodiment. The computing architecture 1000 includes a coherent cache or memory side buffer chiplet 1001, an accelerator 1002 (e.g., a jammer chip), a processor 1020 (e.g., a central processing unit), and a memory die 1004. In at least one embodiment, the coherent cache or memory side buffer chiplet 1001 includes at least two channels 1015 that are configured to connect to the accelerator 1002 and the processor 1020. In at least one embodiment, the coherent cache or memory side buffer chiplet 1001 includes an I / O and controller 1010 to manage data traffic with the memory die 1004. By moving the controller 1010 from the processor 1020 to the coherent cache or memory side buffer chiplet 1001, the cost associated with power and die area for the processor 1020 is reduced. In at least one embodiment, the coherent cache or memory side buffer chiplet 1001 is a cache memory including ferroelectric memory cells. For example, the coherent cache or memory side buffer chiplet 1001 includes one or more of the following: FE-SRAM, FE-DRAM, SRAM, MRAM, resistive RAM (Re-RAM), embedded DRAM (e.g., 1T-1C based memory), or a combination thereof. Using FE-SRAM, MRAM, or Re-RAM allows for low power and high speed memory operations.

[0145] [picture]

[11] illustrates an architecture 1100 of a coherent cache or memory-side buffer chiplet (e.g., 1107) having multiple controllers and multiple cache banks, according to at least one embodiment. In at least one embodiment, the architecture 1100 includes channels (e.g., ch0 1115-1 and ch1 1115-2), cache banks 1101, local cache controllers 1102, non-volatile (NV) controllers 1103, and reliability logic 1104. The coherent cache or memory-side buffer chiplet 1107 functions as a cache or memory buffer. In at least one embodiment, a cache lookup table can map a large physical memory into a small physical cache through the use of indirect via tags. Here, indirect refers to the use of tags to indicate which address maps to which physical location. If multiple addresses can be mapped to a physical location, tags are used to determine which address is currently mapped.

[0146] In at least one embodiment, each cache 1101 includes a database 1105 (e.g., including memory cells) and an associated tag 1106. In at least one embodiment, the database 1105 includes ferroelectric memory cells. In at least one embodiment, the database 1105 includes one or more of the following: FE-SRAM, FE-DRAM, SRAM, MRAM, resistive RAM (Re-RAM), embedded DRAM (e.g., 1T-1C based memory), or a combination thereof. Using FE-SRAM, MRAM, or Re-RAM allows for low power and high speed memory operations. In at least one embodiment, when the database 1105 includes ferroelectric memory, it uses NV controller 1103 and stronger reliability logic (e.g., error correction code) for security compared to non-ferroelectric memory used for the database 1105.

[0147] When database 1105 is used to implement caching, tags may be used to identify which addresses map to which physical locations in the database. Caches may be associative, where a particular address may map to several physical locations. The particular physical location to which a newly allocated address is mapped may be determined by a replacement algorithm such as LRU (most recently used) or pseudo-LRU, or even random. On the other hand, caches may be direct mapped, where each address maps to only one physical cache line. In both associative and direct mapped caches, several addresses map to one physical cache line. To identify the address currently occupying a physical cache line, a tag 1106 may be coupled to each physical line. Tag 1106 may include a number of address bits sufficient to uniquely identify which address currently occupies the physical line to which the tag is coupled.

[0148] In at least one embodiment, cache controller 1102 may be used to control state transitions required for cache lookup tables, such as comparing a requested address with a tag 1106 stored in a tag array, and identifying candidates for replacement when a cache miss occurs (replacement algorithm). In addition, cache controller 1102 may be assigned to initialize cache operations when the cache is powered on. When the FE memory of database 1105 (which retains state across power cycles) is used, cache controller 1102 may write zeros to all memory locations to ensure that data associated with previously executed programs is erased, preventing any data from leaking to subsequently executed programs. Non-volatile memory may also include NV bits, which may indicate that cache data is intended to be non-volatile and persist across power cycles. Cache controller 1102 will therefore skip the marked locations when initializing memory.

[0149] In at least one embodiment, reliability logic 1104 performs error correction on the data. Any appropriate error correction scheme (e.g., utilizing error correction codes (ECC)) may be used by reliability logic 1104. In at least one embodiment, NV controller 1103 is provided to explicitly clear caches when non-volatile memory (such as FM memory) is used in data store 1105. NV controller 1103 may include NV bits that indicate cache lines that should not be cleared but are expected to retain their contents across power cycles. The functionality of NV controller 1103 may be incorporated into cache controller 1102, or vice versa.

[0150] [picture]

[12] A device 1200 is shown, which includes a memory and corresponding logic, wherein the memory includes a ferroelectric (FE) memory bit cell, according to at least one embodiment. The device 1200 includes an MxN memory array 1201 of bit cells, logic circuits 1202 for address decoding, sense amplifiers and write drivers 1203, and plate-line (PL) drivers 1204. The logic circuits 1202 include an address decoder for selecting a column of bit cells and / or a specific bit cell from the MxN memory array 1201, where M and N are integers of the same or different values. The write driver 1203 includes a sense amplifier for reading the values ​​from the selected bit cell, and the write driver is used to write the specific value to the selected bit cell. Here, a schematic diagram of a FE bit cell 1201 0,0 is shown. The same embodiment applies to other bit cells in the MxN array. In this example, a one transistor one capacitor (1T1C) bit cell is shown, but the embodiments are applicable to 1TnC bit cells and multi-element FE gain bit cells, as described herein.

[0151] In at least one embodiment, the bit cell 1201 0,0 includes a word line (WL), a plate line (PL), a bit line (BL), a complementary bit line (BLB), and two half bit cells 1201 0,0_A and 1201 0,0_B. In at least one embodiment, the bit cell 1201 0,0 includes an n-type transistor MN 1, and a FE capacitive structure Cfe 1. The gate of the transistor MN 1 is coupled to the common WL. In various embodiments, one terminal of the FE capacitive structure Cfe 1 is coupled to PL. The second terminal of the FE capacitive structure is coupled to the source or drain terminal of the transistor MN 1. In various embodiments, BL is coupled to the source or drain terminal of the first transistor MN 1. In at least one embodiment, the BL capacitor CBI 1 is coupled to the source or drain terminal of the first transistor MN 1 and to a reference node (e.g., grounded so that the FE capacitors are not coupled to the same source or drain terminal). In at least one embodiment, PL is parallel to BL and orthogonal to WL. In at least one embodiment, PL is parallel to WL and orthogonal to BL.

[0152] In at least one embodiment, the FE capacitor is a planar capacitor. In at least one embodiment, the FE capacitor is a pillar or non-planar capacitor. In at least one embodiment, when the bit cell is a 1TnC bit cell, the FE capacitor is configured in a tower structure, which allows the xy footprint to remain the same for the 1T1C bit cell but with a higher bit cell in the z direction. In at least one embodiment, when the bit cell is a multi-element FE gain bit cell, the bit cell allows decoupling of the storage node from the BL, allows reduced thickness scaling requirements for the pillar capacitor, and allows reduced polarization density requirements. Furthermore, by stacking 'n' capacitors in the z direction (forming a tower), the area is increased in the xy direction due to the two transistors. The increase in area (due to two transistors per bit cell) allows the size (or radius) of the capacitor to be expanded in the xy direction.

[0153] [picture]

[13] illustrates a high-level architecture of an artificial intelligence (AI) machine 1300, including a compute die on top of a memory die, according to at least one embodiment. The AI ​​machine 1300 includes a compute block 1301 or processor having a random access memory (RAM) 1302 and a compute die 1303; a first random access memory 1304 (e.g., static RAM (SRAM), ferroelectric or paraelectric RAM (FeRAM), ferroelectric or paraelectric static random access memory (FeSRAM)), a main processor 1305, a second random access memory 1306 (dynamic RAM (DRAM), FeRAM), and a solid-state memory or drive (SSD) 1307. In at least one embodiment, some or all of the components of the AI ​​machine 1300 are packaged in a single package forming a system-on-chip (SoC). The SoC can be configured as a logically logical configuration, which can be a 3D configuration or a 2.5D configuration.

[0154] In at least one embodiment, the computing block 1301 is packaged in a single package and then coupled to the processor 1305 and the first random access memory 1304, the second random access memory 1306, and the SSD 1307 on the printed circuit board (PCB). In at least one embodiment, the computing block 1301 is configured as a logical configuration, which can be a 3D configuration or a 2.5D configuration. In at least one embodiment, the computing block 1301 includes a special purpose computing die 1303 or a microprocessor. For example, the computing die 1303 is a computing chiplet that performs the function of an accelerator or inference. In at least one embodiment, the RAM 1302 is a DRAM that forms a special memory / cache for the special purpose computing die 1303. The DRAM can be an embedded DRAM (eDRAM), such as a 1T-1C (one transistor and one capacitor) based memory. In at least one embodiment, the RAM 1302 is a ferroelectric or paraelectric RAM (Fe-RAM).

[0155] In at least one embodiment, the computing die 1303 is specialized for applications such as artificial intelligence, graphics processing, and algorithms for data processing. In at least one embodiment, the computing die 1303 further has logical computing blocks, such as for multipliers and buffers, special data memory blocks (e.g., buffers), including DRAM, FeRAM, or a combination thereof. In at least one embodiment, the RAM 1302 has weights and inputs stored in sequence to improve computing efficiency. The interconnection between the processor 1305 (also called a special purpose processor), the first random access memory 1304, and the computing die 1303 is optimized for high bandwidth and low latency. [picture] The architecture of

[13] allows for highly efficient packaging to reduce energy, power, or cost, and provides ultra-high bandwidth between the RAM 1302 of the computing 1301 and the computing chiplet 1303.

[0156] In at least one embodiment, RAM 1302 is partitioned to store input data (or data to be processed) 1302a and weighting factors 1302b. In at least one embodiment, input data 1302a is stored in separate memories (e.g., separate memory chips), and weighting factors 1302b are stored in separate memories (e.g., separate memory chips).

[0157] In at least one embodiment, the computational logic or computational die 1303 includes matrix multipliers, adders, sequential logic, buffers, and combinatorial logic. In various embodiments, the computational die 1303 performs a multiplication operation on the input data 1302a and the weighting factors 1302b. In at least one embodiment, the weighting factors 1302b are fixed weights. For example, a processor 1305 (e.g., a graphics processor unit (GPU), a field programmable grid array (FPGA) processor, an application specific integrated circuit (ASIC) processor, a digital signal processor (DSP), an AI processor, a central processing unit (CPU), or any other high-performance processor) calculates the weights of the training model. Once the weights are calculated, they are stored in the RAM 1302. In various embodiments, the input data (which is analyzed using the training model) is processed by the computational block 1301 with the calculated weighting factors 1302b to generate an output (e.g., a classification result).

[0158] In at least one embodiment, the first random access memory 1304 is a ferroelectric or paraelectric based SRAM. For example, a six transistor (6T) SRAM bit cell with ferroelectric or paraelectric transistors is used to implement a non-volatile FeSRAM. In at least one embodiment, the SSD 1307 includes NAND flash cells. In at least one embodiment, the SSD 1307 includes NOR flash cells. In at least one embodiment, the SSD 1307 includes multi-threshold NAND flash cells.

[0159] In various embodiments, the non-volatility of FeRAM is used to introduce new features such as security, functional safety, and faster reboot times to the architecture of the AI ​​machine 1300. Non-volatile FeRAM is a low-power RAM that provides fast access to data and weights. The first random access memory 1304 can also serve as fast storage for the inference die 1301 (or accelerator), which typically has low capacity and fast access requirements.

[0160] In various embodiments, FeRAM (FeDRAM or FeSRAM) includes ferroelectric or paraelectric materials. The ferroelectric or paraelectric (FE) material can be in the transistor gate stack or in the capacitor of the memory. The ferroelectric material can be any suitable low voltage FE material that allows the FE material to switch its state by a low voltage (e.g., 1300 mV). The threshold in the FE material has a highly nonlinear transfer function in the polarization versus voltage response. The threshold is related to a) the nonlinearity of the switching transfer function, and b) the squareness of the FE switching. The nonlinearity of the switching transfer function is the width of the derivative of the polarization versus voltage plot. Squareness is defined by the ratio of the remnant polarization to the saturation polarization; perfect squareness would show a value of 1.

[0161] The squareness of FE switching can be tuned appropriately using chemical substitution. For example, in PbTiO 3, the PE (polarization-electric field) square loop will be modified by La or Nb substitution to produce an S-shaped loop. This shape can be systematically tuned to ultimately produce a nonlinear dielectric. The squareness of FE switching can also be changed by the grain size of the FE layer. A perfect epitaxial, crystalline FE layer will show a higher squareness (e.g., a ratio close to 1) compared to polycrystalline FE. Perfect epitaxy can be achieved using lattice-matched bottom and top electrodes. In one example, BiFeO (BFO) can be epitaxially synthesized using a lattice-matched SrRuO 3 bottom electrode, resulting in a square PE loop. Stepwise doping with La will reduce the squareness.

[0162] In at least one embodiment, the FE material comprises a perovskite of type ABO 3, wherein 'A' and 'B' are two cations of different sizes, and 'O' is oxygen, which is an anion bonded to the two cations. Generally, the size of the atom of A is greater than the size of the atom of B. In at least one embodiment, the perovskite may be doped (e.g., with La or lanthanides). In various embodiments, when the FE material is a perovskite, the conductive oxide is of type AA'BB'O 3. A' is a dopant at atomic site A, which may be an element from the lanthanide series. B' is a dopant at atomic site B, which may be an element from the transition metal elements, particularly Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn. A' may have the same atomic valence as site A, with different ferroelectric polarizability.

[0163] In at least one embodiment, the FE material comprises a hexagonal ferroelectric of type h-RMnO 3, wherein R is a rare earth element, including one of the following: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), thulium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), protium (Pr), protium (Pm), samarium (Sm), scandium (Sc), zirconium (Tb), thulium (Tm), ytterbium (Yb), and yttrium (Y). The ferroelectric phase is characterized by the bending of the layered MnO 5 polyhedrons, accompanied by the substitution of Y ions, which results in a net electric polarization. In at least one embodiment, the hexagonal FE comprises one of the following: YMnO 3 or LuFeO 3. In various embodiments, when the FE material comprises a hexagonal ferroelectric, the conductive oxide is of A 2 O 3 (eg, In 2 O 3, Fe 2 O 3) and ABO 3 type, where 'A' is a rare earth element and B is Mn.

[0164] In at least one embodiment, the FE material is a perovskite, which includes one or more of the following: La, Sr, Co, Sr, Ru, Y, Ba, Cu, Bi, Ca, and Ni. For example, metal perovskites such as: (La, Sr) CoO 3, SrRuO 3, (La, Sr) MnO 3, YBa 2Cu 3O 7, Bi 2Sr 2CaCu 2O 8, LaNiO 3, etc. can be used for FE materials. The perovskite can be appropriately doped to obtain spontaneous deformation in the range of 0.3 to 2%. For the chemically substituted BiFeO 3, BrCrO 3, BuCoO 3 types of materials, La or rare earth substitution into the Bi site can tune the spontaneous deformation. In at least one embodiment, the FE material is in contact with a conductive metal oxide, which includes one of the conductive perovskite metal oxides exemplified below: La-Sr-CoO 3, SrRuO 3, La-Sr-MnO 3, YBa 2Cu 3O 7, Bi 2Sr 2CaCu 2O 8, and LaNiO 3.

[0165] In at least one embodiment, the FE material comprises a stack of layers, including a low voltage FE material between conductive oxides. In various embodiments, when the FE material is a perovskite, the conductive oxide is of type AA'BB'O 3. A' is a dopant of atomic site A, which may be an element from the lanthanide series. B' is a dopant of atomic site B, which may be an element from the transition metal elements, in particular Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn. A' may have the same atomic valence of site A, with different ferroelectric polarizability. In various embodiments, when a metal perovskite is used for the FE material, the conductive oxide may include one or more of the following: IrO 2, RuO 2, PdO 2, OsO 2, or ReO 3. In at least one embodiment, the perovskite is doped with La or the lanthanide series. In at least one embodiment, a thin layer (e.g., approximately 10 nm) of perovskite template conductor, such as SrRuO3 coated on top of IrO2, RuO2, PdO2, PtO2, which has a non-perovskite structure but higher conductivity to provide a seed or template for the growth of pure perovskite ferroelectrics at low temperatures, is used as the conducting oxide.

[0166] In at least one embodiment, the ferroelectric material is doped with an s-orbital material (e.g., materials for the first period, the second period, and the third and fourth periods of ions). In at least one embodiment, an f-orbital material (e.g., lanthanide) is doped into the ferroelectric material to produce a paraelectric material. Examples of room temperature paraelectric materials include: SrTiO 3, Ba (x) Sr (y) TiO 3 (where x is -0.05 and y is 0.95), HfZrO 2, Hf-Si-O.

[0167] In at least one embodiment, the FE material comprises one or more of the following: hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), oxides thereof or alloy oxides thereof. In at least one embodiment, the FE material comprises one or more of the following: Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (1-xy) Mg (x) Nb (y) N, y-doped HfO 2, wherein x comprises one of the following: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein 'x' is a fraction. In at least one embodiment, the FE material comprises one or more of the following: bismuth ferrite (BFO), or BFO with doped materials.

[0168] In at least one embodiment, the FE material includes bismuth ferrite (BFO), BFO with a first doping material, wherein the first doping material is lanthanum, or any element from the lanthanide series of the periodic table. In at least one embodiment, the FE material includes a relaxant, and the ferroelectric includes one of barium titanium-bismuth zinc niobium tantalum (BT-BZNT) or barium titanium-barium strontium titanium (BT-BST).

[0169] In at least one embodiment, the FE material includes hafnium oxide in the form of Hf (1-x)E (x)O y, where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y. In at least one embodiment, the FE material includes niobate-type compounds LiNbO 3, LiTaO 3, lithium iron tantalum Oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate.

[0170] In at least one embodiment, the FE material comprises a plurality of layers. For example, alternating layers of [Bi 2 O 2] 2+, and pseudoperovskite blocks (Bi 4 Ti 3 O 12 and related Aurivillius phases) may be used, with the perovskite layer being n octahedral layers in thickness. In at least one embodiment, the FE material comprises an organic material. For example, polyvinylidene fluoride or polyvinylidene difluoride (PVDF).

[0171] In at least one embodiment, the FE material comprises a hexagonal ferroelectric of type h-RMnO 3, wherein R is a rare earth element, including one of the following: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), thulium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), protium (Pr), protium (Pm), samarium (Sm), scandium (Sc), zirconium (Tb), thulium (Tm), ytterbium (Yb), and yttrium (Y). The ferroelectric phase is characterized by the bending of the layered MnO 5 polyhedrons, accompanied by the substitution of Y ions, which results in a net electric polarization. In at least one embodiment, the hexagonal FE comprises one of the following: YMnO 3 or LuFeO 3. In various embodiments, when the FE material comprises a hexagonal ferroelectric, the conductive oxide is of A 2 O 3 (eg, In 2 O 3, Fe 2 O 3) and ABO 3 type, where 'A' is a rare earth element and B is Mn.

[0172] In at least one embodiment, the FE material comprises an improper FE material. An improper ferroelectric is a ferroelectric in which the dominant order parameter is an order mechanism, such as strain or bending of the atomic order. Examples of improper FE materials are the ferroelectric and paraelectric materials SnTiO 3 (STO), respectively, and LaAlO 3 (LAO) and STO, respectively, of the LuFeO 3 class of materials or superlattices. For example, a superlattice of [PTO / STO]n or [LAO / STO]n, where 'n' is between 1 and 1300. Although various embodiments herein are described with reference to ferroelectric materials for storing charge states, the embodiments are also applicable to paraelectric materials. In at least one embodiment, the paraelectric material comprises one of the following: SrTiO 3, Ba (x) Sr (y) TiO 3, HfZrO 2, Hf-Si-O.

[0173] The methods of forming the structures described herein can be applied to various logic embodiments. For example, the FeRAM devices or capacitive structures formed herein can be used to form other ferroelectric / paraelectric circuits. These circuits can implement majority gates, minority gates, and / or threshold gates.

[0174] Subsequent examples are provided to illustrate various embodiments. These examples can be combined with other examples. In this way, various embodiments can be combined with other embodiments without changing the scope of the invention.

[0175] [picture]

[14] illustrates a 3-input majority gate 1400 using nonlinear input capacitors, according to at least one embodiment. In at least one embodiment, the 3-input majority gate 1400 includes nonlinear input capacitors C1n1, C2n1, and C3n1, which receive digital signals a, b, and c, respectively. Herein, signal names and node names are used interchangeably. For example, 'a' refers to node 'a' or signal 'a', depending on the context of the sentence. One end or terminal of capacitor C1n1 is coupled to node a, and the other end of capacitor C1n1 is coupled to summing node Vs. The same is true for the other nonlinear capacitors C2n1 and C3n1, as shown. In at least one embodiment, the 3-input majority gate 1400 includes a driver circuit 1401. In this example, the driver circuit 1401 is an inverter. In other embodiments, other types of driver circuits may be used, such as NAND gates, NOR gates, multiplexers, buffers, and other logic gates. The majority function is performed at the summing node Vs as majority (a, b, c). In this example, because the driver circuit 1401 is an inverter, the minority function is performed at the output "out" as minority (a, b, c).

[0176] In at least one embodiment, in addition to the gate capacitance of the driver circuit 1401, an additional linear capacitor CL is coupled to the summing node Vs and ground, as shown. In at least one embodiment, this linear capacitor CL is a non-ferroelectric capacitor. In at least one embodiment, the non-ferroelectric capacitor includes one of the following: a dielectric capacitor, a paraelectric capacitor, or a nonlinear dielectric capacitor. The dielectric capacitor includes a first metal plate and a second metal plate with a dielectric therebetween. Examples of such dielectrics are: HfO X, ABO 3 perovskite, nitride, oxy-fluoride, oxide, etc. The paraelectric capacitor includes a first metal plate and a second metal plate with a paraelectric material therebetween. In at least one embodiment, an f-orbital material (e.g., lanthanide) is doped into a ferroelectric material to produce a paraelectric material. Examples of room temperature paraelectric materials include: SrTiO 3, Ba (x) Sr (y) TiO 3, HfZrO 2, Hf-Si-O, La-substituted PbTiO 3, PMN-PT based relaxor ferroelectrics. The dielectric capacitor includes a first metal plate and a second metal plate, with a nonlinear dielectric capacitance between them. The dielectric constant ranges from 1.2 to 10000. The capacitor CL can be implemented as MIM (metal insulator metal) capacitor technology, a transistor gate capacitor, a metal capacitor or a combination of a transistor capacitor. The capacitor CL can be implemented as MIM (metal insulator metal) capacitor technology, a transistor gate capacitor, or a combination of a metal capacitor or a transistor capacitor.

[0177] In at least one embodiment, the nonlinear input capacitors C1n1, C2n1, and C3n1 include nonlinear polar materials. In at least one embodiment, the nonlinear polar materials include one of the following: ferroelectric (FE) materials, paraelectric materials, relaxant ferroelectrics, or nonlinear dielectrics. In various embodiments, the paraelectric materials are the same as the FE materials, but utilize chemical doping of active ferroelectric ions by nonpolar deformed ions. In some cases, the nonpolar ions are non-s orbital ions formed with p, d, f outer orbitals. In at least one embodiment, the nonlinear dielectric material is the same as the paraelectric material, the relaxant, and the bipolar glass.

[0178] In at least one embodiment, an f-orbital material (e.g., lanthanide) is doped into a ferroelectric material to produce a paraelectric material. Examples of room temperature paraelectric materials include: SrTiO 3, Ba (x) Sr (y) TiO 3, HfZrO 2, Hf-Si-O.

[0179] In various embodiments, the FE material may be any suitable low voltage FE material that allows the FE material to switch its state by a low voltage (e.g., 100 mV). In at least one embodiment, the FE material comprises a perovskite of type ABO 3, where 'A' and 'B' are two cations of different sizes, and 'O' is oxygen, which is an anion bonded to the two cations. Generally, the size of the A atom is larger than the size of the B atom. In at least one embodiment, the perovskite may be doped (e.g., with La or lanthanides). The perovskite may be appropriately doped to obtain a spontaneous deformation in the range of 0.3 to 2%. For example, for chemically substituted lead titanates, such as Zr at the Ti site, La, Nb at the Ti site, the concentrations of these substitutions are such that they obtain a spontaneous deformation in the range of 0.3 to 2%. For chemically substituted BiFeO 3, BiCrO 3, BiCoO 3 types of materials, La or rare earth substitution into the Bi site can tune the spontaneous deformation. In at least one embodiment, the perovskite includes one of: BaTiO 3, KNbO 3, or NaTaO 3.

[0180] Threshold in FE materials has a highly nonlinear transfer function in the polarization versus voltage response. Threshold is related to: a) the nonlinearity of the switching transfer function; and b) the squareness of the FE switching. The nonlinearity of the switching transfer function is the width of the derivative of the polarization versus voltage plot. Squareness is defined by the ratio of the remnant polarization to the saturation polarization; perfect squareness would show a value of 1.

[0181] The squareness of FE switching can be tuned appropriately using chemical substitution. For example, in PbTiO 3, the PE (polarization-electric field) square loop will be modified by La or Nb substitution to produce an S-shaped loop. This shape can be systematically tuned to ultimately produce a nonlinear dielectric. The squareness of FE switching can also be changed by the grain size of the FE layer. A perfect epitaxial, crystalline FE layer will show a higher squareness (e.g., a ratio close to 1) compared to polycrystalline FE. This perfect epitaxy can be achieved by using lattice-matched bottom and top electrodes. In one example, BiFeO (BFO) can be epitaxially synthesized using a lattice-matched SrRuO 3 bottom electrode, resulting in a square PE loop. Stepwise doping with La will reduce the squareness.

[0182] In at least one embodiment, the FE material is in contact with a conductive metal oxide, which includes one of the conductive perovskite metal oxides exemplified below: La-Sr-CoO 3, SrRuO 3, La-Sr-MnO 3, YBa 2Cu 3O 7, Bi 2Sr 2CaCu 2O 14, LaNiO 3, and ReO 3.

[0183] In at least one embodiment, the FE material comprises a stack of layers, including a low voltage FE material between conductive oxides. In various embodiments, when the FE material is a perovskite, the conductive oxide is of type AA'BB'O 3. A' is a dopant of atomic site A, which may be an element from the lanthanide series. B' is a dopant of atomic site B, which may be an element from the transition metal elements, in particular Sc, Ti, V, Cr, Mn, Fe, Co, Ni, Cu, Zn. A' may have the same atomic valence as site A, but with different ferroelectric polarizability.

[0184] In at least one embodiment, the FE material comprises a hexagonal ferroelectric of type h-RMnO 3, wherein R is a rare earth element such as: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), gadolinium (Gd), thulium (Ho), lanthanum (La), lutetium (Lu), neodymium (Nd), protium (Pr), protium (Pm), samarium (Sm), scandium (Sc), zirconium (Tb), thulium (Tm), ytterbium (Yb), and yttrium (Y). The ferroelectric phase is characterized by the bending of the layered MnO 5 polyhedrons, accompanied by the substitution of Y ions, which results in a net electric polarization. In at least one embodiment, the hexagonal FE comprises one of the following: YMnO 3 or LuFeO 3. In various embodiments, when the FE material comprises a hexagonal ferroelectric, the conductive oxide adjacent to the FE material is of the A 2 O 3 (eg, In 2 O 3, Fe 2 O 3) and AB 2 O 3 type, where 'A' is a rare earth element and B is Mn.

[0185] In at least one embodiment, the FE material comprises an improper FE material. An improper ferroelectric is a ferroelectric in which the dominant order parameter is an order mechanism, such as strain or bending of the atomic order. Examples of improper FE materials are the LuFeO 3 class of materials or superlattices of ferroelectrics and paraelectric materials. Although various embodiments herein are described with reference to ferroelectric materials for storing charge states, the embodiments may also be applied to paraelectric materials. For example, the capacitors of various embodiments may be formed using paraelectric materials instead of ferroelectric materials.

[0186] In at least one embodiment, the FE material includes one of the following: hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), oxides thereof or alloy oxides thereof. In at least one embodiment, the FE material includes one of the following: Al (1-x) Sc (x) N, Ga (1-x) Sc (x) N, Al (1-x) Y (x) N or Al (1-xy) Mg (x) Nb (y) N, y-doped HfO 2, wherein x includes one of the following: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y, wherein 'x' is a fraction. In at least one embodiment, the FE material includes bismuth ferrite (BFO), or BFO with doped materials.

[0187] In at least one embodiment, the FE material comprises bismuth ferrite (BFO), BFO with a first doping material, wherein the first doping material is lanthanum, or one of any elements from the lanthanide series of the periodic table. In at least one embodiment, the FE material comprises a relaxor ferroelectric comprising one of barium titanium-bismuth zinc niobium tantalum (BT-BZNT), or barium titanium-barium strontium titanium (BT-BST).

[0188] In at least one embodiment, the FE material includes hafnium oxide in the form of Hf (1-x)E (x)O y, where E can be Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, or Y. In at least one embodiment, the FE material includes niobate-type compounds LiNbO 3, LiTaO 3, lithium iron tantalum Oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate.

[0189] In at least one embodiment, the FE material comprises multiple layers. For example, alternating layers of [Bi2O2]2+, and pseudo-perovskite blocks (Bi4Ti3O12 and related Aurivillius phases) may be used, with the perovskite layer being n octahedral layers in thickness.

[0190] In at least one embodiment, the FE material comprises an organic material. For example, polyvinylidene fluoride or polyvinylidene difluoride (PVDF). The FE material is between two electrodes. These electrodes are conductive electrodes. In at least one embodiment, the electrodes are perovskite template conductors. In this template structure, a thin layer (e.g., about 10 nm) of a perovskite conductor (such as SrSuO 3) is coated on top of IrO 2, RuO 2, PdO 2, or PtO 2 (which has a non-perovskite structure but higher conductivity) to provide a seed crystal or template for the growth of pure perovskite ferroelectrics at low temperatures. In at least one embodiment, when the ferroelectric comprises a hexagonal ferroelectric material, the electrodes may have a hexagonal metal, a spinel, or a cubic metal. Examples of hexagonal metals include: PtCoO 2, PdCoO 2, and other hexagonal metal oxides of the dolphite structure, such as Al-doped ZnO. Examples of spinels include Fe 3O 4 and LiV 2O 4. Examples of cubic metals include indium tin oxide (ITO), such as Sn-doped In 2O 3.

[0191] The charge generated on node Vs produces a voltage and current, which is the output of the 3-input majority gate 1400. Any suitable driver circuit 1401 can drive this output. For example, non-FE logic, FE logic, CMOS logic, BJT logic, etc. can be used to drive the output to a downstream logic. Examples of drivers include inverters, buffers, NAND gates, NOR gates, XOR gates, amplifiers, comparators, digital to analog converters, analog to digital converters, multiplexers, etc.

[0192] The majority function is performed at the summing node Vs, and the resulting voltage is projected onto the capacitor of the driver circuit 1401. For example, the majority function of the current (Ia, Ib, and Ic) at the node Vs results in a resulting current that charges the capacitor. Table 1 shows the majority function f (majority a, b, c).

[0193] The charge generated on node Vs produces a voltage and current, which is the output of the 3-input majority gate 1400. Any suitable driver circuit 1401 can drive this output. For example, non-FE logic, FE logic, CMOS logic, BJT logic, etc. can be used to drive the output to a downstream logic. Examples of drivers include inverters, buffers, NAND gates, NOR gates, XOR gates, amplifiers, comparators, digital to analog converters, analog to digital converters, multiplexers, etc.

[0194] Although [picture]

[14] A 3-input majority gate is shown, but the same concept can be extended to more than 3 inputs to make an N-input majority gate, where N is greater than 2. In various embodiments, 'N' is an odd number. For example, a 5-input majority gate is similar to the 3-input majority gate 1400, but for the additional inputs 'd' and 'e'. These inputs can come from the same driver or from different drivers.

[0195] In at least one embodiment, a 3-input majority gate can be configured as a fast inverter with much faster propagation delay than a similarly sized (for area footprint) CMOS inverter. This is particularly useful when the inputs have significantly slower slopes than the propagation delay through the nonlinear input capacitance. One way to configure a 3-input majority gate as an inverter is to set one input to a logic high (e.g., b=1) and another input to a logic low (e.g., b=0). The third input is the drive input that is to be inverted. The inversion will be at the Vs node. The same technique can also be applied to an N-input majority gate where 'N' is 1 or any other odd number. In an N-input majority gate, (N-1) / 2 inputs are set to '1' and (N-1) / 2 inputs are set to '0', and one input is used to determine the inversion function. While the various embodiments are described as majority gates, the same concepts can be applied to minority gates. In the minority gate, the drive circuit is coupled to an inverting circuit that sums node Vs. The minority function is seen at the output of the inverting circuit.

[0196] In at least one embodiment, the (2N-1) input majority gate may be operated as an N input AND gate, where the (N-1) input of the majority gate is set to zero. The AND function will be seen at the summing node Vs. Similarly, N input NAND, OR, NOR gates may be implemented. In various embodiments, the summing node Vs is driven by a driver circuit (e.g., an inverter, a buffer, a NAND gate, an AND gate, an OR gate, a NOR gate, or any other logic circuit). However, the driver circuit 1401 may be replaced with another majority or minority gate. In one such embodiment, the storage node Vs is directly coupled to the nonlinear capacitance of another majority or minority gate.

[0197] Any logical function can be represented by two levels of logic, as given by the minimum period expansion:

[0198] in is 0 or 1. When is 1, (The input is used in its original form.) When 0, (The input is used in its inverted form.) The first level of logic consists of at most AND Gate Indicated by 0 and 1 One for each possible combination, for The second level of logic is represented by the OR gate (⋁). The OR gate's operands are for The representation of the columns in the truth table of .

[0199] A (2N-1) input majority gate can represent an N-input AND gate by connecting (N-1) of the majority gate's inputs to ground potential. Similarly, a (2N-1) input majority gate can represent an N-input OR gate by connecting (N-1) of the majority gate's inputs to supply potential (Vdd). Because the majority gate can represent both AND and OR gates, and the inputs to both the AND and OR gates are either the original or inverted form of the input digital signal, any logic function can be represented by just the majority gates and inverters, according to at least one embodiment.

[0200] [picture]

[15] illustrates a composite logic gate 1500 implemented using a 5-input majority gate, according to at least one embodiment. In at least one embodiment, AOI (and-or-inversion) logic includes a 5-input majority gate. The 5-input majority gate includes nonlinear capacitors C1n1, C2n1, C3n1, C4n1, and C5n1 and a drive circuit 1501, which are coupled as shown. In various embodiments, both of the nonlinear capacitors receive the same input. Here, capacitors C3n1 and C4n1 receive input 'c'. In various embodiments, C5n1 is coupled to Vdd to generate an OR function at node Vs, where the OR function is OR(AND(a,b),c). In at least one embodiment, other logic gates can be implemented by changing Vdd to ground (for capacitor C5n1), and / or changing other inputs.

[0201] Subsequent examples are provided to illustrate various embodiments. These examples can be combined with other examples. In this way, various embodiments can be combined with other embodiments without changing the scope of the invention.

[0202] An abstract is provided that will allow the reader to ascertain the nature and gist of the invention in this technology. It should be understood that the presentation of the abstract should not be used to limit the scope or significance of the claims. The following claims are hereby incorporated into the detailed description, with each claim itself being a separate embodiment.

[0203] Example 1: A device, comprising: a first region. The first region comprises: a plurality of first conductive interconnects within a first level; a second level above the first level, the second level comprising: a plurality of ferroelectric memory devices, wherein an individual ferroelectric memory device among the plurality of ferroelectric memory devices is above a respective first conductive interconnect among the plurality of first conductive interconnects, and wherein the individual ferroelectric memory device among the plurality of ferroelectric memory devices comprises a first height; an encapsulation layer on a sidewall of the individual ferroelectric memory device among the plurality of ferroelectric memory devices; a through-hole electrode on the individual ferroelectric memory device among the plurality of ferroelectric memory devices, wherein the through-hole electrode comprises a second height; and a first conductive interconnect adjacent to the first region. A second region, the second region comprising an interconnect structure, the interconnect structure comprising: one or more second conductive interconnects within the first level; an etch stop layer comprising a dielectric material within the second level; a plurality of metal lines above the etch stop layer, wherein the plurality of metal lines are within the second level, wherein a respective individual metal line among the plurality of metal lines comprises a third height; and a via structure coupling a metal line among the plurality of metal lines with a second conductive interconnect among the one or more second conductive interconnects, wherein the via structure is within the second level and comprises a fourth height, wherein a combined sum of the first height and the second height is equal to a combined sum of the third height and the fourth height.

[0204] Example 2: A device as in Example 1, wherein each of the plurality of first conductive interconnects comprises one or more of copper, cobalt, tungsten, ruthenium, molybdenum, tantalum or titanium, and wherein each of the plurality of first conductive interconnects comprises a first lateral thickness.

[0205] Example 3: A device as in Example 2, wherein individual ones of the plurality of first conductive interconnects comprise copper and one or more of titanium or ruthenium, wherein individual ferroelectric memory devices in the plurality of ferroelectric memory devices comprise a respective second lateral thickness, and wherein the second lateral thickness is greater than the first lateral thickness.

[0206] Example 4: A device as in Example 3, wherein the individual ferroelectric memory devices in the plurality of ferroelectric memory devices further extend over a portion of a dielectric adjacent to the individual ones of the plurality of first conductive interconnects.

[0207] Example 5: A device as in Example 2, wherein individual ones of the plurality of first conductive interconnects comprise one or more of copper, cobalt, tungsten, ruthenium, molybdenum, tantalum or titanium but not copper, wherein individual ferroelectric memory devices in the plurality of ferroelectric memory devices comprise a respective second lateral thickness, and wherein the second lateral thickness is less than the first lateral thickness.

[0208] Example 6: A device as in Example 1, wherein the second height is greater than the third height, and wherein the first height is less than the fourth height.

[0209] Example 7: A device as in Example 1, wherein the second height is less than the third height and wherein the first height is greater than the fourth height.

[0210] Example 8: The device of Example 1, wherein the encapsulation layer comprises a thickness between 5 nm and 30 nm as measured from the sidewalls of the individual ones of the plurality of ferroelectric memory devices.

[0211] Example 9: A device as in Example 8, wherein the encapsulation layer includes an outer sidewall that is opposite to a sidewall of the sidewall adjacent to each of the plurality of ferroelectric memory devices, and wherein the encapsulation layer extends laterally over a portion of an uppermost surface of a dielectric adjacent to each of the plurality of first conductive interconnects.

[0212] Example 10: A device as in Example 10, wherein the encapsulation layer extends laterally over a portion of an uppermost surface of the dielectric by a distance that is at least 25% of the thickness of the encapsulation layer.

[0213] Example 11: A device as in Example 8, wherein the encapsulation layer includes an outer sidewall that is opposite to a sidewall of the sidewalls of the individual ones of the plurality of ferroelectric memory devices, and wherein the encapsulation layer extends laterally over a surface of the dielectric by a distance that is at least 25% of the thickness of the encapsulation layer, and wherein the surface of the dielectric is lower than an uppermost surface of the dielectric.

[0214] Example 12: A device as in Example 10, wherein the dielectric has a portion including a sidewall that is substantially aligned with the sidewalls of the individual ones of the plurality of ferroelectric memory devices, and wherein the encapsulation layer extends below an uppermost surface of the dielectric and over a portion of a sidewall of the dielectric.

[0215] Example 13: A device as in Example 8, wherein the surface of the dielectric below the uppermost surface is gradually inclined.

[0216] Example 14: A device as in Example 8, wherein the surface of the dielectric below the uppermost surface is substantially flat.

[0217] Example 15: A device as in Example 1, wherein the plurality of ferroelectric memory devices are a first plurality of memory devices, wherein the encapsulation layer is a first encapsulation layer, wherein the through-hole electrode is a first through-hole electrode, wherein the device further comprises: a third plurality of conductive interconnects on a plane behind a plane comprising the first plurality of conductive interconnects; a second plurality of ferroelectric memory devices, wherein an individual ferroelectric memory device among the second plurality of ferroelectric memory devices is on a respective one of the plurality of second conductive interconnects, and wherein the individual ferroelectric memory device among the second plurality of ferroelectric memory devices comprises the first height; a second encapsulation layer on a respective sidewall of the individual ferroelectric memory device among the second plurality of ferroelectric memory devices; and a second through-hole electrode on an individual one of the plurality of ferroelectric memory devices, wherein the second through-hole electrode comprises the second height.

[0218] Example 16: A device as in Example 15, wherein the first encapsulation layer is directly adjacent to the sidewall of a first ferroelectric memory device in the first plurality of memory devices and extends laterally toward and merges with the second encapsulation layer, the second encapsulation layer is directly adjacent to the sidewall of the second ferroelectric memory device in the second plurality of memory devices, wherein the second ferroelectric memory device is directly behind the first ferroelectric memory device.

[0219] Example 17: A device as in Example 16, wherein the first encapsulation layer or the second encapsulation layer between the first ferroelectric memory device and the second ferroelectric memory device has a lateral thickness that is constant along a direction from the first ferroelectric memory device to the second ferroelectric memory device.

[0220] Example 18: The device of Example 17, wherein the first encapsulation layer and the second encapsulation layer comprise the same material, and wherein the first encapsulation layer adjacent to the first plurality of memory devices and the second encapsulation layer adjacent to the second plurality of memory devices merge over the dielectric.

[0221] Example 19: A device comprises a first zone. The first region includes: a trench interconnect extending along a first direction; a second level above the first level, the second level including: a plurality of ferroelectric memory devices, wherein individual ferroelectric memory devices among the plurality of ferroelectric memory devices are laterally isolated above the trench interconnect; an encapsulation layer on the sidewalls of the individual ferroelectric memory devices among the plurality of ferroelectric memory devices; a via electrode on a respective individual ferroelectric memory device among the plurality of ferroelectric memory devices; and a second region adjacent to the first region, the second region including an interconnect structure, the interconnect structure including: one or more conductive interconnects within the first level; an etch stop layer of a dielectric material included in the second level; a plurality of metal lines above the etch stop layer, the plurality of metal lines in the second level; and a via structure, which couples a respective metal line among the plurality of metal lines and a conductive interconnect among the one or more conductive interconnects, and wherein a topmost surface of the via electrode is coplanar with a topmost surface of the metal lines.

[0222] Example 20: The device of Example 19, wherein the trench interconnect comprises one or more of copper, cobalt, tungsten, ruthenium, molybdenum, tantalum, or titanium, and wherein the trench interconnect comprises a first lateral thickness.

[0223] Example 21: A device as in Example 20, wherein the trench interconnect comprises copper and one or more of titanium or ruthenium, wherein the individual ferroelectric memory devices in the plurality of ferroelectric memory devices comprise a respective second lateral thickness, and wherein the second lateral thickness is greater than the first lateral thickness.

[0224] Example 22: A device as in Example 19, wherein the individual ferroelectric memory devices in the plurality of ferroelectric memory devices further extend over a portion of a dielectric adjacent to a sidewall of the trench interconnect.

[0225] Example 23: A device as in Example 19, wherein individual ones of the plurality of first conductive interconnects comprise one or more of cobalt, tungsten, ruthenium, molybdenum, tantalum or titanium but not copper, wherein individual ferroelectric memory devices in the plurality of ferroelectric memory devices comprise a respective second lateral thickness, and wherein the second lateral thickness is less than the first lateral thickness.

[0226] Example 24: A method of manufacturing a device structure, the method comprising: forming a plurality of conductive interconnects in a dielectric in a memory region and one or more conductive interconnects in a logic region; depositing an etch stop layer on the dielectric and on the plurality of conductive interconnects and on the one or more conductive interconnects; etching to remove the etch stop layer from a memory region but not from a logic region; depositing an electrode material on the plurality of conductive interconnects in the memory region and on the etch stop layer in the logic region; forming a plurality of memory devices by etching the material layer stack, wherein the etching forms a memory device of the plurality of memory devices in the memory region. The invention relates to a method for forming a plurality of conductive interconnects in a logic region by depositing an encapsulation layer on a respective conductive interconnect among the plurality of conductive interconnects in the logic region; depositing an encapsulation layer on the plurality of memory devices; depositing a dielectric layer on the encapsulation layer as a cover layer; forming one or more openings in the dielectric layer and in the encapsulation layer, the one or more openings exposing the one or more conductive interconnects in the logic region; forming an interconnection via in the respective one or more openings and a metal line on the respective interconnection via; forming an opening on a respective one of the plurality of memory devices; and filling the opening on the respective memory device in the plurality of memory devices with a conductive material to form a respective through-hole electrode.

[0227] Example 25: The method of Example 24, wherein the method further comprises: forming a mask on the encapsulation layer, wherein the mask covers a respective memory device among the plurality of memory devices; and etching the encapsulation layer.

[0228] Example 26: A device comprising a first region, the first region comprising: a first conductive interconnect within a first level; a second level above the first level, the second level comprising: a ferroelectric memory device comprising a first height and further comprising a cylindrical shape, the ferroelectric memory device being above the first conductive interconnect; an encapsulation layer on a sidewall of the ferroelectric memory device; a via electrode on the ferroelectric memory device, wherein the via electrode comprises a second height; and a second region adjacent to the first region, the second region comprising An interconnect structure comprising: a second conductive interconnect within the first level; and an etch stop layer comprising a dielectric material within the second level; a metal line above the etch stop layer, wherein the metal line is within the second level and wherein the metal line comprises a third height; and a via structure coupling the metal line and the second conductive interconnect, wherein the via structure is within the second level and comprises a fourth height, wherein a combined sum of the first height and the second height is equal to a combined sum of the third height and the fourth height.

[0229] Example 27: A device as in Example 26, wherein the first conductive interconnect comprises one or more of copper, cobalt, tungsten, ruthenium, molybdenum, tantalum or titanium, wherein the first conductive interconnect comprises a cylindrical profile and wherein the first conductive interconnect comprises a first lateral thickness, wherein the first lateral thickness is a first diameter.

[0230] Example 28: A device as in Example 27, wherein the first conductive interconnect comprises copper and one or more of titanium or ruthenium, wherein the ferroelectric memory device comprises a respective second lateral thickness, wherein the second lateral thickness is a second diameter, wherein the first diameter is smaller than the second diameter.

[0231] Example 29: A device as in Example 27, wherein the first conductive interconnect comprises one or more of cobalt, tungsten, ruthenium, molybdenum, tantalum or titanium, but not copper, wherein the ferroelectric memory device comprises a respective second lateral thickness, wherein the second lateral thickness is a second diameter, wherein the first diameter is greater than the second diameter.

[0232] Example 29: A device as in Example 27, wherein the first conductive interconnect comprises one or more of cobalt, tungsten, ruthenium, molybdenum, tantalum or titanium, but not copper, wherein the ferroelectric memory device comprises a respective second lateral thickness, wherein the second lateral thickness is a second diameter, wherein the first diameter is smaller than the second diameter.

[0233] Example 30: A device as in Example 26, wherein the second height is greater than the third height, and wherein the first height is less than the fourth height, and wherein the first height is less than 20 nm and the second height is greater than 50 nm but less than 200 nm.

[0234] Example 31: A device as in Example 26, wherein the ferroelectric memory device is a first memory device, wherein the encapsulation layer is a first encapsulation layer, wherein the through-hole electrode is a first through-hole electrode, wherein the device further comprises: a third conductive interconnect on a plane behind a plane comprising the first conductive interconnect; a second ferroelectric memory device on the third conductive interconnect and wherein the second ferroelectric memory device comprises the first height; a second encapsulation layer on a sidewall of the ferroelectric memory device; and a second through-hole electrode on the second ferroelectric memory device, wherein the second through-hole electrode comprises the second height.

[0235] Example 32: The device of Example 31, wherein the first encapsulation layer and the second encapsulation layer comprise the same material, and wherein the first encapsulation layer extends along a shortest direction from above the first conductive interconnect to the third conductive interconnect.

[0236] Example 33: A device as in Example 31, wherein the first encapsulation layer is directly adjacent to the sidewall of a first ferroelectric memory device and extends laterally toward and adjacent to the second encapsulation layer, which is directly adjacent to the sidewall of the second ferroelectric memory device, wherein the first encapsulation layer or the second encapsulation layer between the first ferroelectric memory device and the second ferroelectric memory device has a lateral thickness that is constant along a direction from the first ferroelectric memory device to the second ferroelectric memory device, and wherein the lateral thickness is greater than a first diameter of the first ferroelectric memory device or a second diameter of the second ferroelectric memory device to a thickness equal to a thickness of the encapsulation layer.

[0237] Example 34: A device as in Example 33, wherein the lateral thickness is greater than a first diameter of the first ferroelectric memory device or a second diameter of the second ferroelectric memory device to be equal to a thickness that is at least 25% greater than a thickness of the encapsulation layer.

[0238] Example 35: A device as in Example 31, wherein the first through-hole electrode and the second through-hole electrode are coupled by a plate electrode, the plate electrode extending from above the first ferroelectric memory device to a second ferroelectric memory device, wherein the plate electrode is within the second level.

[0239] Example 36: A device as in Example 26, wherein the first ferroelectric memory device includes a dielectric hard mask, wherein the through-hole electrode is coupled to the first ferroelectric memory device through an opening in the dielectric hard mask.

[0240] Example 37: A device as in Example 26, wherein the first ferroelectric memory device includes a conductive hard mask, wherein the through-hole electrode is coupled to the first ferroelectric memory device through the conductive hard mask.

[0241] Example 38: A device as in Example 26, wherein the first ferroelectric memory device includes a double-layer hard mask, which includes a conductive first layer and a second layer on the first layer, wherein the second layer is a dielectric, and wherein the through-hole electrode is coupled to the second layer through the first layer.

[0242] Example 39: A device as in Example 26, wherein the first ferroelectric memory device includes a sidewall that is substantially vertical relative to a lowest surface of the first ferroelectric memory device.

[0243] Example 41: A device as in Example 26, wherein the first ferroelectric memory device includes sidewalls having a slope different from 90° relative to a lowest surface of the first ferroelectric memory device.

[0244] Example 42: A device as in Example 26, wherein the device further includes a portion of one or more layers of the ferroelectric memory device that is adjacent to a sidewall of the etch stop layer at the interface between the memory region and the logic region.

[0245] Example 43: A method of manufacturing a device structure, the method comprising: forming a plurality of conductive interconnects in a dielectric in a memory region and one or more conductive interconnects in a logic region; depositing an etch stop layer on the dielectric and on the plurality of conductive interconnects and on the one or more conductive interconnects; etching to remove the etch stop layer from a memory region but not from a logic region; depositing an electrode material on the plurality of conductive interconnects in the memory region and on the etch stop layer in the logic region; forming a plurality of memory devices by etching the material layer stack, wherein the etching forms a memory device of the plurality of memory devices at a respective conductive interconnect of the plurality of conductive interconnects in the memory region. on; depositing an encapsulation layer on the plurality of memory devices; depositing a dielectric layer on the encapsulation layer as a covering layer; forming one or more first openings in the dielectric layer and in the encapsulation layer, the first one or more openings exposing the one or more conductive interconnections in the logic region and simultaneously forming a second one or more openings in the memory region, the second one or more openings exposing one or more devices among the plurality of memory devices; and forming an interconnection via in a respective first one or more openings and a metal line on a respective interconnection via; and forming a conductive via in the second one or more openings to form a respective through-hole electrode, by depositing a conductive material in the first and second one or more openings.

[0246] Example 44: A method as in Example 43, wherein the method of depositing the encapsulation layer includes depositing on a surface of a dielectric layer adjacent to the plurality of conductive interconnects, wherein the surface is tapered relative to a sidewall of an individual memory device in the plurality of memory devices.

[0247] Example 45: The method of Example 44, wherein the method further comprises depositing a portion of the encapsulation layer on a sidewall of the dielectric layer, wherein the sidewall of the dielectric layer and the sidewall of the individual memory device in the plurality of memory devices are substantially aligned.

[0248] Example 46: A method as in Example 43, wherein the method of forming the interconnect via in a respective first one or more openings further includes: masking the second one or more openings and a portion of the first one or more openings; forming a second opening within the portion of the first one or more openings; etching the dielectric exposed by the second opening; and etching the etch stop layer after etching the dielectric, the etching exposing a conductive interconnect among the one or more conductive interconnects in the logic region.

[0249] [] 100: Device structure 101A: District 101B: District 102: Conductive Interconnect 104: Level 106: Second place 108: Ferroelectric memory device 108A: Side wall 108B:Top surface 108C: Part 108D: bottom surface 114: Encapsulation layer 114A: Outermost wall 114B: Horizontal extension 114D: Dashed line 116:Through hole electrode 117: Interconnection structure 118: Conductive Interconnect 118A:Top surface 120, 122: Metal wire 124:Through hole 126: Etching stop layer 126A: Side wall 128: Bottom electrode 130: Ferroelectric oxide layer 132: Top electrode 134: Hard Mask 134A: Top hard mask surface 135: Diffusion barrier layer 136: Dielectric 136A:Top surface 136B: Lower surface 136C: Side wall part 137: Dashed Line 138: Dielectric 140: Ferroelectric memory device 141: Plane 142: Plate electrode 144:Hard Mask 600: Base material 601:Through hole 602: Photoresist mask 604: Electrode material 606: Material layer stacking 606A: Conductive layer 606B: Ferroelectric dielectric layer 606C: Conductive layer 608: Hard Mask Layer 609: Mask 609A, 609B: Block 610: Box 611: Mask 611A: Mask part 613: Mask 615: Opening 616: Opening 617: Opening 619A, 619B: Groove 619C: Through hole opening 621: Mask 623: Mask 1000: Computing Architecture 1001: Small chip 1002: Accelerator 1010: Controller 1015: Channel 1020: Processor 1100: Architecture 1101: Cache 1102: Local cache controller 1103: Non-volatile (NV) controller 1104: Reliability Logic 1105: Database 1106: Associated tags 1107: Small chip 1115-1:ch0 1115-2:ch1 1200: Equipment 1201:MxN memory array 1202:Logic Circuit 1203:Write to drive 1204: Plate-Line (PL) Driver 1300: Artificial Intelligence (AI) Machine 1301: Calculation block 1302: Random Access Memory (RAM) 1302a: Input data 1302b: Weighting Factors 1303: Calculate grains 1304: First random access memory 1305: Main processor 1306: Second random access memory 1307: Solid-state memory or drive (SSD) 1004:Memory chip 1400:3 Input majority gate 1401: Driver circuit 1500: Compound logic gate 1501: driving circuit

Claims

1. A device for embedded memory, comprising: a first region including: a first conductive interconnect laterally surrounded by a dielectric within a first primary level; and a second level above the first primary level, the second level including: a memory device above the first conductive interconnect, the memory device including a non-linear polar material and a cylindrical shape; an encapsulation layer on a first sidewall of the memory device; and a through-hole electrode on the memory device; and a second region adjacent to the first region, the second region including an interconnect structure, the interconnect structure including Includes: a second conductive interconnect surrounded by the dielectric within the first criterion; an etch stop layer contained in an insulator within the second criterion, wherein the etch stop layer is attached to the dielectric; a metal line above the etch stop layer, wherein the metal line is attached to the second criterion; and a via structure coupling the metal line to the second conductive interconnect, wherein the via structure is attached to the second criterion; and a portion of one or more layers of the memory device, which is adjacent to a second sidewall of the etch stop layer at an interface between the first and second regions.

2. The device of claim 1, wherein the first conductive interconnect comprises one or more of copper, cobalt, tungsten, ruthenium, molybdenum, tantalum or titanium, wherein the first conductive interconnect comprises a cylindrical profile and wherein the first conductive interconnect comprises a first lateral thickness and wherein the first lateral thickness is a first diameter, wherein the memory device comprises a second lateral thickness and wherein the second lateral thickness is a second diameter and wherein the first diameter is smaller than the second diameter.

3. The device of claim 1, wherein the first conductive interconnect comprises one or more of cobalt, tungsten, ruthenium, molybdenum, tantalum or titanium, but does not include copper, the first conductive interconnect comprises a cylindrical profile and wherein the first conductive interconnect comprises a third lateral thickness and wherein the third lateral thickness is a third diameter, wherein the memory device comprises a fourth lateral thickness and wherein the fourth lateral thickness is a fourth diameter, and wherein the third diameter is larger than the fourth diameter.

4. The device of claim 1, wherein the encapsulation layer extends over a first portion of the top surface of one of the memory devices and contacts the through-hole electrode.

5. The device of claim 1, wherein the encapsulation layer extends over a portion of the one or more layers of the memory device adjacent to the second sidewall.

6. The device of claim 1, wherein the encapsulation layer extends from the memory device above the dielectric and to a portion of the one or more layers of the memory device adjacent to the second sidewall.

7. The apparatus of claim 1, wherein the memory device is a first memory device, wherein the encapsulation layer is a first encapsulation layer, wherein the via electrode is a first via electrode, and wherein the apparatus further comprises: a third conductive interconnect on a first plane behind a second plane including the first conductive interconnect; a second memory device on the third conductive interconnect, wherein the second memory device includes the nonlinear polar material and the cylindrical shape; a second encapsulation layer on a third sidewall of the second memory device; and a second via electrode on the second memory device.

8. The apparatus of claim 7, wherein the first encapsulation layer and the second encapsulation layer comprise the same material, wherein the first encapsulation layer extends along a shortest direction from the first conductive interconnect to the third conductive interconnect, and wherein the first encapsulation layer is in contact with the dielectric between the first conductive interconnect and the third conductive interconnect.

9. The apparatus of claim 8, wherein the first encapsulation layer is directly adjacent to the first sidewall of the first memory device and includes a second portion extending laterally toward and merging with one of the second encapsulation layers, the second encapsulation layer being directly adjacent to the third sidewall of the second memory device, wherein the second portion extending between the first memory device and the second memory device includes a fifth lateral thickness that is constant along a direction from the first memory device to one of the second memory devices, and wherein the fifth lateral thickness is greater than a sixth lateral thickness of one of the first memory devices or the sixth lateral thickness of the second memory device by a thickness equal to a seventh lateral thickness of one of the encapsulation layers.

10. The apparatus of claim 9, wherein the fifth lateral thickness is at least 25% greater than the seventh lateral thickness.

11. The apparatus of claim 7, wherein the first via electrode and the second via electrode are coupled by a plate electrode extending from the first memory device to the second memory device, and wherein the plate electrode is within the second level.

12. The apparatus of claim 1, wherein the memory device includes a dielectric hard shield, and wherein the via electrode is coupled to the memory device through an opening in the dielectric hard shield.

13. The apparatus of claim 1, wherein the memory device includes a conductive hard shield, wherein the via electrode is coupled to the memory device through the conductive hard shield.

14. The apparatus of claim 1, wherein the memory device includes a double-layer hard mask comprising a conductive first layer and a second layer thereon the first layer, wherein the second layer comprises a dielectric material, and wherein the via electrode is coupled to the first layer through an opening in the second layer.

15. The apparatus of claim 1, wherein the nonlinear polar material comprises one of the following: bismuth ferrite (BFO) or BFO having a first dopant, wherein the first dopant is lanthanum or one of the lanthanides of the periodic table; lead zirconate titanate (PZT) or PZT having a second dopant, wherein the second dopant is one of La or Nb; a relaxer ferroelectric material comprising one of the following: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lanthanum lead zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobate tantalum (BT) -BZNT), or barium-titanium-barium-strontium-titanium (BT-BST); a perovskite material comprising one of the following: BaTiO3, PbTiO3, KNbO3, or NaTaO3; a hexagonal ferroelectric comprising one of the following: YMnO3, or LuFeO3; a hexagonal ferroelectric of type h-RMnO3, wherein the R-series rare earth elements include one of the following: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), thorium (Gd), holmium (Ho), lanthanum (La), argonium (Lu), neodymium (Nd), pterylene (Pr), gibbsite (Pm), samarium (S) m), scandium (Sc), tbium (Tb), thionium (Tm), ytterbium (Yb), or yttrium (Y); hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or alloy oxides thereof; Hf(1-x)E(x)Oy, wherein E may be one of the following: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y; Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N or Al(1-xy)Mg(x)Nb(y)N, Doped HfO2; niobate-type compounds LiNbO3, LiTaO3, lithium iron tantalum Oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or an unsuitable ferroelectric material comprising one of the following: [PTO / STO]n or [LAO / STO]n, wherein 'n' is between 1 and 100; or SrTiO3, Ba(x)Sr(y)TiO3 (where x is -0.05 and y is 0.95), HfZrO2, Hf-Si-O, La-substituted PbTiO3, or a PMN-PT-based relaxant ferroelectric.

16. A device for embedded memory, comprising: a first region including: a first conductive interconnect laterally surrounded by a dielectric within a first reference; and a second reference above the first reference, the second reference including: a memory device above the first conductive interconnect, the memory device including a non-linear polar material, a cylindrical shape, and a first height; an encapsulation layer on a first sidewall of the memory device; and a via electrode on the memory device, wherein the via electrode includes a second height; and a second region adjacent to the first region, the second region including an interconnect structure, the interconnect structure including: a first conductive interconnect laterally surrounded by the dielectric within the first reference. A second conductive interconnect; an etch stop layer comprising an insulator in the second level, wherein the etch stop layer is on the dielectric; a metal line above the etch stop layer, wherein the metal line is in the second level and comprises a third height; and a via structure coupling the metal line to the second conductive interconnect, wherein the via structure is in the second level and comprises a fourth height, wherein the sum of a first combination of the first height and the second height is equal to the sum of a second combination of the third height and the fourth height; and a portion of one or more layers of the memory device, which is adjacent to a second sidewall of the etch stop layer at an interface between the first region and the second region.

17. The apparatus of claim 16, wherein the second height is greater than the third height, and wherein the first height is less than the fourth height.

18. The apparatus of claim 16, wherein the first height is less than 20 nm and the second height is greater than 50 nm but less than 200 nm.

19. A system for embedded memory, the system comprising: a processor; a communication interface communicatively coupled to the processor; and a memory coupled to the processor, wherein the memory includes bit units, wherein one of the bit units includes: A first region comprising: a first conductive interconnect laterally surrounded by a dielectric within a first reference; and a second reference above the first reference, the second reference comprising: a memory device above the first conductive interconnect, the memory device comprising a non-linear polar material and a cylindrical shape; an encapsulation layer on a first sidewall of the memory device; and a via electrode on the memory device; a second region adjacent to the first region, the second region comprising an interconnect structure comprising: a second conductive interconnect surrounded by the dielectric within the first reference; an etch stop layer comprising an insulator in the second reference, wherein the etch stop layer is attached to the dielectric; a metal line above the etch stop layer, wherein the metal line is attached to the second reference; and a via structure coupling the metal line to the second conductive interconnect, wherein the via structure is attached to the second reference; and a portion of one or more layers of the memory device, which is adjacent to a second sidewall of the etch stop layer at an interface between the first region and the second region.

20. The system of claim 19, wherein the nonlinear polar material comprises one of the following: bismuth ferrite (BFO) or BFO having a first dopant, wherein the first dopant is lanthanum or one of the lanthanides of the periodic table; lead zirconate titanate (PZT) or PZT having a second dopant, wherein the second dopant is one of La or Nb; a relaxer ferroelectric material comprising one of the following: lead magnesium niobate (PMN), lead magnesium niobate-lead titanate (PMN-PT), lanthanum lead zirconate titanate (PLZT), lead scandium niobate (PSN), barium titanium-bismuth zinc niobate tantalum (BT-BZN). T), or barium-titanium-barium-strontium-titanium (BT-BST); a perovskite material comprising one of the following: BaTiO3, PbTiO3, KNbO3, or NaTaO3; a hexagonal ferroelectric comprising one of the following: YMnO3, or LuFeO3; a hexagonal ferroelectric of type h-RMnO3, wherein the R-series rare earth elements include one of the following: cerium (Ce), dysprosium (Dy), erbium (Er), europium (Eu), thorium (Gd), holmium (Ho), lanthanum (La), argonium (Lu), neodymium (Nd), plutonium (Pr), pyroxene (Pm), samarium (Sm), scandium (Sc), tungsten (Bt). (Tb), thorium (Tm), ytterbium (Yb), or yttrium (Y); hafnium (Hf), zirconium (Zr), aluminum (Al), silicon (Si), their oxides, or alloy oxides thereof; Hf(1-x)E(x)Oy, wherein E includes one of the following: Al, Ca, Ce, Dy, Er, Gd, Ge, La, Sc, Si, Sr, Sn, Zr, or Y, wherein x and y are first and second fractions, respectively; Al(1-x)Sc(x)N, Ga(1-x)Sc(x)N, Al(1-x)Y(x)N, or Al(1-xy)Mg(x)Nb (y)N, where x and y are the third and fourth fractions, respectively; doped HfO2; niobate type compounds LiNbO3, LiTaO3, lithium iron tantalum Oxy fluoride, barium strontium niobate, sodium barium niobate, or potassium strontium niobate; or an unsuitable ferroelectric material comprising one of the following: [PTO / STO]n or [LAO / STO]n, where 'n' is between 1 and 100; or a relaxer ferroelectric material based on SrTiO3, Ba(x)Sr(y)TiO3, HfZrO2, Hf-Si-O, La-substituted PbTiO3, or PMN-PT.

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