Manufacturing method of semiconductor memory device

Abstract

This invention suppresses uneven thickness of resist patterns on a plurality of contact holes with different depths. A method for manufacturing a semiconductor memory device according to an embodiment forms a stacked body, the stacked body being formed by alternating layers of a plurality of first insulating layers and a plurality of second insulating layers; forms a plurality of holes extending along the stacking direction of the stacked body within the stacked body and reaching different depths; fills the plurality of holes with a carbon-containing layer such that it has an upper surface at a predetermined depth from the upper end of each of the plurality of holes; forms a capping layer covering the upper surface of the carbon-containing layer in each of the plurality of holes; removes the carbon-containing layer through the capping layer; forms a resist pattern covering a portion of the plurality of holes blocked by the capping layer and having an opening for exposing another portion of the plurality of holes; removes the capping layer blocking the other portion of the plurality of holes exposed at the opening of the resist pattern; and further processes the other portion of the plurality of holes to increase the depth of the other portion of the plurality of holes.

Description

Technical Field

[0001] The present invention relates to a method for manufacturing a semiconductor memory device. Prior Technology

[0002] In semiconductor memory devices such as three-dimensional non-volatile memory, multiple conductive layers are stacked, and multiple contacts are formed to connect to each of these conductive layers at different depths. Such contacts can be obtained by repeatedly forming resist patterns and contact holes at different depths. When resist patterns are repeatedly formed on multiple contact holes at different depths, controlling the resist layer thickness becomes a problem. [Previous Technical Documents] [Patent Literature]

[0003] [Patent Document 1] Japanese Patent Application Publication No. Sho 58-052880 [Patent Document 2] Japanese Patent Application Publication No. 62-033431 [Patent Document 3] International Publication No. 2023 / 182195 Summary of the Invention

[0004] [The problem the invention aims to solve] One embodiment aims to provide a method for manufacturing a semiconductor memory device that can suppress uneven thickness of resist patterns reaching multiple contact holes of different depths. [Technical means to solve the problem]

[0005] The method for manufacturing a semiconductor memory device according to the embodiment involves forming a multilayer body, wherein a plurality of first insulating layers and a plurality of second insulating layers are alternately laminated layer by layer; forming a plurality of holes, which extend along the lamination direction of the multilayer body and reach different depths; filling the plurality of holes with a carbon-containing layer such that an upper surface is formed at a predetermined depth from the upper end of each of the plurality of holes; forming a coating layer that covers the upper surface of the carbon-containing layer in each of the plurality of holes; removing the carbon-containing layer through the coating layer; forming a resist pattern that covers a portion of the plurality of holes blocked by the coating layer and has an opening for exposing another portion of the plurality of holes; removing the coating layer that blocks the other portion of the plurality of holes exposed at the opening of the resist pattern, and further processing the other portion of the plurality of holes to increase the depth of the other portion of the plurality of holes. Simple Explanation of the Diagram

[0006] Figure 1 is a cross-sectional view showing a schematic configuration example of a semiconductor memory device according to an embodiment. Figures 2A and 2B are diagrams illustrating an example of the configuration of a semiconductor memory device according to an embodiment. Figures 3A to 3C are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to the embodiments in sequence. Figures 4A and 4B are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to the embodiments in sequence. Figures 5A and 5B are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to the embodiments in sequence. Figures 6A and 6B are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to the embodiments in sequence. Figures 7A to 7C are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to the embodiments in sequence. Figures 8A to 8C are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to the embodiments in sequence. Figures 9A to 9C are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to the embodiments in sequence. Figures 10A to 10C are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to an embodiment. Figures 11A to 11C are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to an embodiment. Figures 12A to 12C are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to the embodiments in sequence. Figures 13A to 13C are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to the embodiments in sequence. Figures 14A and 14B are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to the embodiments in sequence. Figures 15A and 15B are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to an embodiment. Figures 16A and 16B are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to an embodiment. Figures 17A and 17B are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to the embodiments in sequence. Figures 18A-18C are diagrams illustrating a portion of the procedure for forming contact holes in a comparative example semiconductor memory device. Figures 19A-19C are diagrams illustrating a part of the process of manufacturing a semiconductor memory device according to Example 1, a variation of the implementation method. Figures 20A-20C are diagrams illustrating a part of the process of manufacturing a semiconductor memory device according to Example 2 of the embodiment variation. Figures 21A-21C are diagrams illustrating a part of the process of manufacturing a semiconductor memory device according to Example 3, a variation of the implementation method. Figures 22A-22C are diagrams illustrating a part of the process of manufacturing a semiconductor memory device, as illustrated in Example 4 of the variation of the implementation method. Implementation

[0007] Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Furthermore, the present invention is not limited to the following embodiments. Also, the constituent elements in the following embodiments include constituent elements that are readily conceived by those skilled in the art or substantially the same constituent elements.

[0008] (Example of a semiconductor memory device) Figure 1 is a cross-sectional view showing a schematic configuration example of the semiconductor memory device 1 according to the embodiment. However, in Figure 1, the shaded areas have been omitted for ease of observation.

[0009] As shown in Figure 1, the semiconductor memory device 1 has an electrode film EL, a source line SL, and a plurality of word lines WL sequentially arranged from the bottom side of the paper. Furthermore, the semiconductor memory device 1 has a peripheral circuit CBA above the plurality of word lines WL, and the peripheral circuit CBA is disposed on the semiconductor substrate SB.

[0010] A source line SL is disposed on the electrode film EL, separated by an insulating layer 60. A plurality of plugs PG are disposed in the insulating layer 60, and the electrical conduction between the source line SL and the electrode film EL is maintained by the plugs PG. In this way, a source potential can be applied to the source line SL from the outside of the semiconductor memory device 1 through the electrode film EL and the plugs PG.

[0011] A plurality of word lines WL are stacked on the source line SL. A memory region MR is disposed in the center of the plurality of word lines WL, and contact regions ER are disposed at both ends of the plurality of word lines WL.

[0012] A plurality of pillars PL are disposed in the memory region MR, extending through the word line WL in the stacking direction. A plurality of memory cells are formed at the intersections of the pillars PL and the word line WL. Thus, the semiconductor memory device 1 is configured as, for example, a three-dimensional non-volatile memory formed by arranging memory cells in three dimensions in the memory region MR.

[0013] A plurality of contacts CC are configured in the contact area ER, each connected to a plurality of character lines WL. Furthermore, in this specification, the connection end of the contact CC to the character line WL is positioned on the lower side of the semiconductor memory device 1 in the extension direction of the contact CC.

[0014] Write and read voltages are applied from contact CC to memory cells contained in the memory region MR at the center of multiple word lines WL, with the word lines WL positioned at the same height as the memory cells. In this way, the word lines WL of the multi-layered stack are individually led out through these contacts CC.

[0015] Multiple character lines WL, posts PL, and contacts CC are covered by an insulating layer 50. The insulating layer 50 also extends around the multiple character lines WL.

[0016] The semiconductor substrate SB above the insulating layer 50 is, for example, a silicon substrate. Peripheral circuitry CBA, including transistors TR and wiring, is disposed on the surface of the semiconductor substrate SB. Various voltages applied to the memory cell from the contacts CC are controlled by the peripheral circuitry CBA, which is electrically connected to the contacts CC. Thus, the peripheral circuitry CBA controls the electrical operation of the memory cell.

[0017] The peripheral circuit CBA is covered by an insulating layer 40. The semiconductor memory device 1 is formed by bonding the insulating layer 40 with the insulating layer 50 covering the stacked body LM. The semiconductor memory device 1 is composed of a plurality of character lines WL, pillars PL and contacts CC, as well as the peripheral circuit CBA.

[0018] Next, using Figures 2A and 2B, a detailed configuration example of the semiconductor memory device 1 will be described. Figures 2A and 2B are diagrams showing an example of the configuration of the semiconductor memory device 1 according to the embodiment.

[0019] More specifically, Figure 2A is a cross-sectional view along the Y direction showing an example of the configuration of the memory region MR. Figure 2B is a cross-sectional view along the X direction showing an example of the configuration of the contact region ER. However, in Figures 2A and 2B, the structures below the insulating layer 60 and above the insulating layer 40 are omitted.

[0020] Furthermore, in this specification, both the X and Y directions refer to the directions along the face of the character line WL, and the X and Y directions are orthogonal to each other. Also, sometimes the direction in which the electrical leads out of the character line WL are drawn is referred to as the first direction, which is along the X direction. Also, sometimes the direction intersecting the first direction is referred to as the second direction, which is along the Y direction. However, since the semiconductor memory device 1 may contain manufacturing errors, the first and second directions may not be orthogonal.

[0021] As shown in Figure 2A, in the memory region MR, the source line SL has a multilayer structure, that is, the insulating layer 60 is sequentially stacked with, for example, the lower source line DSLa, the middle source line BSL and the upper source line DSLb.

[0022] The lower source line DSLa, the middle source line BSL, and the upper source line DSLb are, for example, polycrystalline silicon layers. Among them, at least the middle source line BSL can be a conductive polycrystalline silicon layer with diffused impurities.

[0023] As shown in Figure 2B, in the contact region ER, the source line SL has an intermediate insulating layer SCO between the lower source line DSLa and the upper source line DSLb, instead of having an intermediate insulating layer SCO within the intermediate source line BSL. This is because the contact region ER does not have a pillar PL that serves as the connection point for the source line SL. The intermediate insulating layer SCO is, for example, a silicon oxide layer. However, the source line SL can also have an intermediate source line BSL within the contact region ER.

[0024] A stacked layer LM is disposed on the source line SL. The stacked layer LM comprises stacked layers LMa and LMb, which are formed by alternately stacking multiple character lines WL and multiple insulating layers OL. The stacked layer LMa is disposed above the source line SL, and the stacked layer LMb is disposed on the stacked layer LMa.

[0025] In the layer below the bottommost word line WL of the multilayer LMa, separated by an insulating layer OL, one or more selectable gate lines SGS are arranged. In the examples of Figures 2A and 2B, the multilayer LMa has two selectable gate lines SGS0 and SGS1 sequentially from the top layer side. In the layer above the topmost word line WL of the multilayer LMb, separated by an insulating layer OL, one or more selectable gate lines SGD are arranged. In the examples of Figures 2A and 2B, the multilayer LMb has two selectable gate lines SGD0 and SGD1 sequentially from the top layer side.

[0026] However, the number of stacked layers of the character lines WL and the selected gate lines SGD and SGS in the stacked body LM is arbitrary.

[0027] The character lines WL and selector gate lines SGD and SGS, which are multiple conductive layers, are, for example, tungsten or molybdenum layers. The multiple insulating layers OL are, for example, silicon oxide layers.

[0028] The top insulating layer OL of each stacked layer LMa and LMb is, for example, thicker than other insulating layers OL in stacked layers LMa and LMb. The top insulating layer OL of stacked layer LMa is connected to the bottom word line WL of stacked layer LMb. Insulating layers 52 and 53 are sequentially arranged on the top insulating layer OL of stacked layer LMb. Insulating layers 52 and 53 constitute a part of the aforementioned insulating layer 50. The upper surface of insulating layer 53 is, for example, connected to the lower surface of insulating layer 40 on the CBA side of the peripheral circuit.

[0029] As shown in Figure 2A, the laminated volume LM is divided in the Y direction by a plurality of plate-shaped junctions LI.

[0030] That is, the plate-shaped contacts LI are arranged in the Y direction and extend along the stacking direction and the X direction of the laminate LM. Thus, the plate-shaped contacts LI extend continuously from one end of the laminate LM in the X direction to the other end within the laminate LM containing the memory region MR and the contact region ER.

[0031] In the memory region MR, the plate-shaped contact LI penetrates the laminate LM and the upper source line DSLb to reach the intermediate source line BSL. In the contact region ER, the plate-shaped contact LI penetrates the laminate LM and the upper source line DSLb to reach the intermediate insulating layer SCO.

[0032] Furthermore, the plate-shaped contact LI includes an insulating layer 55 and a conductive layer 25. The insulating layer 55 is, for example, a silicon oxide layer. The conductive layer 25 is, for example, a tungsten layer or a conductive polycrystalline silicon layer.

[0033] The insulating layer 55 covers the sidewalls of the plate-shaped contacts LI that face each other in the Y direction. The conductive layer 25 fills the inner side of the insulating layer 55. However, instead of the plate-shaped contacts LI, the plate-shaped member filled with the insulating layer can be inserted through the laminate LM and extended in the direction along the X direction, thereby dividing the laminate LM in the Y direction.

[0034] A plurality of separation layers SHE are disposed between adjacent plate-shaped contacts LI in the Y direction. These separation layers SHE are insulating layers 57 such as silicon oxide layers, penetrate the selector gate lines SGD0 and SGD1 of the laminate LMb, reach the insulating layer OL directly below the selector gate line SGD1, and extend in the memory region MR of the laminate LM in the direction along the X direction. With this configuration, the separation layers SHE selectively separate the selector gate lines SGD0 and SGD1 between the plate-shaped contacts LI in the Y direction.

[0035] A plurality of pillars PL are distributed in the memory region MR of the stacked matrix LM. These pillars PL penetrate the stacked matrix LM, the upper source line DSLb and the middle source line BSL, and reach the lower source line DSLa.

[0036] When viewed from the lamination direction of the laminate LM, a plurality of columns PL are arranged periodically, for example, in an alternating pattern. The cross-sectional shape of each column PL along the lamination direction of the laminate LM, that is, along the XY plane, has, for example, a circular, elliptical, or oval shape.

[0037] The pillar PL has pillars PLA and PLb. The pillar PLA extends from the uppermost insulating layer OL of the laminate LMa through the laminate LMa to reach the source line SL. The pillar PLb extends from the uppermost insulating layer OL of the laminate LMb through the laminate LMb to reach the uppermost insulating layer OL of the laminate LMa, and is connected to the upper end of the corresponding pillar PLA.

[0038] Each of the multiple pillars PL has: a memory layer ME extending along the stacking direction within the stacked body LM, a channel layer CN penetrating the stacked body LM and connected to the intermediate source line BSL, and a core layer CR that serves as the core material of the pillar PL.

[0039] The memory layer ME is disposed on the side of the pillar PL, except at the depth of the intermediate source line BSL. Furthermore, the memory layer ME is also disposed on the bottom surface of the pillar PL, reaching the depth of the lower source line DSLa. Moreover, the memory layer ME has a multi-layered structure, namely, starting from the outer periphery of the pillar PL, a barrier insulating layer, a charge storage layer, and a tunnel insulating layer (none shown) are sequentially stacked.

[0040] The channel layer CN penetrates the stack LM, the upper source line DSLb, and the intermediate source line BSL inside the memory layer ME, reaching the depth of the lower source line DSLa. That is, the channel layer CN is positioned on the side and bottom of the pillar PL via the memory layer ME. The core layer CR is filled further inside the channel layer CN.

[0041] A portion of the channel layer CN contacts the intermediate source line BSL on its side, thereby electrically connecting it to the source line SL containing the intermediate source line BSL. Furthermore, a capping layer CP is disposed at the upper end of the channel layer CN and is connected to the bit line BL via a plug CH disposed in the insulating layer 52. The bit line BL extends in the insulating layer 53 in the Y direction.

[0042] Furthermore, in the cross-section of Figure 2A, among the five posts PL between adjacent plate-shaped contacts LI in the Y direction, only one post PL is connected to the bit line BL via a plug CH. The other posts PL, located between the plate-shaped contacts LI, are at positions different from those in the cross-section of Figure 2A, and are connected to bit lines BL that are different from those in Figure 2A via plug CHs that are different from those in Figure 2A.

[0043] The memory layer ME includes a barrier insulating layer and a tunnel insulating layer, as well as a core layer CR, such as a silicon oxide layer. The charge storage layer of the memory layer ME is, for example, a silicon nitride layer. The channel layer CN is, for example, a polycrystalline silicon layer or an amorphous silicon layer, or other semiconductor layers.

[0044] With the above configuration, memory cells MC are formed on the side of the column PL, opposite to each character line WL. Data is written to and read from the memory cells MC by applying a specified voltage from the character lines WL.

[0045] Data from memory cell MC is read out to bit line BL connected to pillar PL. Bit line BL is connected to electrode pad PDb disposed on the surface of insulating layer 53. Electrode pad PDb is connected to electrode pad PDc, which is disposed on the surface of insulating layer 40 and electrically connected to peripheral circuit CBA. Thus, the data from memory cell MC read out to bit line BL is processed by peripheral circuit CBA.

[0046] Furthermore, using the above configuration, a selection gate STD is formed on the side of the pillar PL opposite to each selection gate line SGD. Also, a selection gate STS is formed on the side of the pillar PL opposite to each selection gate line SGS. By applying a specified voltage from the selection gate lines SGD and SGS, the selection gates STD and STS are switched on or off, causing the memory cell MC formed in the pillar PL to which these selection gates STD and STS belong to to be in a selected or non-selected state.

[0047] As shown in Figure 2B, a plurality of contacts CC and a plurality of columnar sections HR are configured in the contact area ER.

[0048] A portion of the plurality of contacts CC extends within the stacked body LMb along the stacking direction of the stacked body LM, and is connected to one or more select gate lines SGD or any of the plurality of character lines WL in the stacked body LMb.

[0049] A portion of the plurality of contacts CC extends within the stacked layers LMa and LMb along the stacking direction of the stacked layer LM, and is connected to any one of the plurality of character lines WL belonging to the stacked layer LMa. Furthermore, although not illustrated, another portion of the contacts CC extending within the stacked layers LMa and LMb is also connected to one or more select gate lines SGS of the stacked layer LMa.

[0050] The contacts CC have an insulating layer 56 covering the outer periphery of the contacts CC, and a conductive layer 26, such as a tungsten layer or a copper layer, filling the inner side of the insulating layer 56.

[0051] The conductive layer 26 of contact CC is connected to the upper wiring MX disposed in insulating layer 53 via plug V0 disposed in insulating layer 52. The upper wiring MX is electrically connected to the aforementioned peripheral circuit CBA (see Figure 1) via electrode pad PDb on the surface of insulating layer 53 and electrode pad PDc on the surface of insulating layer 40.

[0052] Furthermore, within the area sandwiched by the plate-shaped contacts LI, the aforementioned plurality of separation layers SHE extend in the memory region MR between the plate-shaped contacts LI in the direction along the X direction, and the portion of the contact region ER in which the plurality of contacts CC connected to the select gate line SGD are arranged also extends in the direction along the X direction.

[0053] In this way, the selective gate line SGD is sandwiched between plate-shaped contacts LI and separation layers SHE on both sides in the Y direction, or between two separation layers SHE, and its end in the X direction is selectively separated into a plurality of regions by separation layers SHE. Contact CC is connected to each of the plurality of regions of the selective gate line SGD separated by plate-shaped contacts LI and separation layers SHE.

[0054] With this configuration, the word lines WL and select gate lines SGD and SGS of each layer can be led out.

[0055] That is, with the above configuration, a specified voltage can be applied to the memory cell MC from the peripheral circuit CBA through the upper wiring MX, the contact CC and the character line WL, so that the memory cell MC can operate as a memory element.

[0056] Furthermore, a specified voltage can be applied to the select gate STD and STS from the peripheral circuit CBA via the upper wiring MX, contact CC, and select gate lines SGD and SGS, so that the memory cell MC is in a selected or non-selected state. At this time, the memory cell MC is in a selected or non-selected state in each region separated by the plate-shaped contact LI and the separation layer SHE.

[0057] In the contact area ER, which is provided for the configuration of a plurality of contacts CC, a plurality of columnar portions HR are distributed. These plurality of columnar portions HR penetrate the laminate LM, the upper source line DSLb and the intermediate insulating layer SCO to reach the lower source line DSLa.

[0058] When viewed from the lamination direction of the laminate LM, the plurality of columnar sections HR are arranged approximately periodically, for example, in a grid or staggered pattern. The reason for the approximately periodic arrangement of the plurality of columnar sections HR is that, in order to avoid interference with the plurality of junctions CC and plate junctions LI, the periodicity of the arrangement of the columnar sections HR is slightly disrupted around the plurality of junctions CC and plate junctions LI.

[0059] The cross-sectional shape of each columnar part HR along the XY plane has, for example, a circular, elliptical, or oblong shape.

[0060] Each columnar portion HR has a columnar portion HRa and a columnar portion HRb. The columnar portion HRa penetrates the uppermost insulating layer OLc of the laminate LMa and reaches the source line SL. The columnar portion HRb penetrates the uppermost insulating layer OLc of the laminate LMb and reaches the uppermost insulating layer OLc of the laminate LMa, and is connected to the upper end of the corresponding columnar portion HRa.

[0061] As described below, these columnar portions HR are dummy columns, serving to support the structure when the stacked body formed by the sacrificial layer and the insulating layer is formed into a stacked body LM, without contributing to the function of the semiconductor memory device 1. Therefore, the columnar portions HRa and HRb are each composed of a single insulating layer 54 such as a silicon oxide layer, and the configuration of the columnar portions HR does not have an electrical effect on other components.

[0062] Furthermore, at the same height position in the laminated body LM, the cross-sectional area of ​​the columnar portion HR along the XY plane can, for example, be greater than the cross-sectional area of ​​the column PL along the XY plane. Also, the distance between a plurality of columnar portions HR can, for example, be greater than the distance between a plurality of columns PL. In the XY plane, the density of columnar portions HR per unit area of ​​the character line WL in the laminated body LM can be lower than the density of columns PL per unit area of ​​the character line WL.

[0063] Thus, for example, by making the cross-sectional area of ​​the pillar PL smaller than that of the pillar portion HR and setting it to a narrow pitch, a plurality of memory cells MC can be formed at high density within a stacked matrix LM of a specified size, thereby increasing the memory capacity of the semiconductor memory device 1. On the other hand, since the pillar portion HR is specifically used to support the stacked matrix LM, it is not configured with a precision structure such as the pillar PL, which has a small cross-sectional area and a narrow pitch, thereby reducing the manufacturing burden of the semiconductor memory device 1.

[0064] (Manufacturing method of semiconductor memory device) Next, the manufacturing method of the semiconductor memory device 1 according to the embodiment will be described using Figures 3A to 17B. Figures 3A to 17B are diagrams illustrating a portion of the process of manufacturing the semiconductor memory device 1 according to the embodiment.

[0065] First, Figures 3A-6B show the formation of pillars PL in the subsequent configuration of the stacked matrix LM. Figures 3A-6B show cross-sections of the semiconductor memory device 1 during manufacturing along the Y direction, including the region that will subsequently become the memory region MR.

[0066] As shown in Figure 3A, a lower source line DSLa, an intermediate sacrificial layer SCN, and an upper source line DSLb are sequentially formed on the support substrate SS.

[0067] As the support substrate SS, a semiconductor substrate such as a silicon substrate, an insulating substrate such as a ceramic substrate, or a conductive substrate can be used. The aforementioned insulating layer 60 can also be formed on the upper surface side of the support substrate SS (see Figure 2A, etc.).

[0068] The intermediate sacrificial layer SCN is, for example, a silicon nitride layer, and is subsequently replaced by a polycrystalline silicon layer to become the intermediate source line BSL. Furthermore, although not shown in the figure, an intermediate insulating layer SCO is formed between the lower source line DSLa and the upper source line DSLb in the region that will subsequently become the contact region ER.

[0069] A multilayer structure LMsa is formed on the upper source line DSLb. This multilayer structure LMsa is formed by alternating layers of multiple insulating layers NL and multiple insulating layers OL. The insulating layer NL is, for example, a silicon nitride layer, which functions as a sacrificial layer. This sacrificial layer is then replaced by a conductive material to become the word line WL or the select gate line SGS.

[0070] As shown in Figure 3B, a plurality of memory vias MHa are formed, extending along the stacking direction within the stacked layer LMsa. These memory vias MHa penetrate the stacked layer LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa. These memory vias MHa will subsequently become part of the pillar PLA.

[0071] As shown in Figure 3C, the memory holes MHa are filled with sacrificial layers 27, such as amorphous silicon layers or CVD carbon layers. This forms pillars PLc, which are formed by filling multiple memory holes MHa with sacrificial layers 27.

[0072] Furthermore, in the region that will subsequently become the junction region ER, in parallel with the processing in Figures 3B and 3C, a sacrificial layer is filled into the through-hole of the laminate LMsa to form the structure that will subsequently become the columnar portion HRa.

[0073] As shown in Figure 4A, a stacked body LMsb is formed, which covers a stacked body LMsa. It is formed by alternating layers of multiple insulating layers NL and multiple insulating layers OL. The insulating layer NL of the stacked body LMsb functions as a sacrificial layer, which is subsequently replaced by a conductive layer to become the word line WL or the select gate line SGD.

[0074] As shown in Figure 4B, a plurality of memory vias MHb are formed, which penetrate the laminate LMsb and are respectively connected to a plurality of pillars PLc already formed within the laminate LMsa. The memory vias MHb will subsequently become part of the pillars PLb.

[0075] As shown in Figure 5A, the sacrificial layer 27 is removed from the pillar PLC at the bottom of the memory via MHb. This creates multiple memory vias MHa, which open at the bottom of the multiple memory vias MHb, and these multiple memory vias MHa penetrate the stacked layers LMsb, LMsa, the upper source line DSLb, and the intermediate sacrificial layer SCN to reach the lower source line DSLa.

[0076] Furthermore, when the sacrificial layer 27 filled in the column PLC is a CVD carbon layer or the like, the sacrificial layer 27 can be removed from the column PLC together when the masking pattern used to form the memory hole MHb in FIG4B is removed by ashing or the like using oxygen plasma.

[0077] Furthermore, in the region that will subsequently become the contact region ER, in parallel with the processing of Figures 4B to 5A, through holes are formed in the laminate LMsb, connecting it to the structure that will subsequently become the columnar portion HRa, and the sacrificial layer is removed. Also, for example, prior to the processing of Figure 5B below, an insulating layer 54 (see Figure 2B) is filled into the through holes of the laminates LMsb and LMsa to form the aforementioned columnar portion HR.

[0078] As shown in Figure 5B, a memory layer ME is formed on the sidewall of the memory via MH and the bottom surface exposed by the lower source line DSLa. The memory layer ME sequentially includes a barrier insulating layer, a charge storage layer, and a tunnel insulating layer (not shown) starting from the sidewall of the memory via MH. The memory layer ME is also formed on the upper surface of the stacked matrix LMsb.

[0079] Furthermore, within the memory aperture MH, a channel layer CNb and a core layer CR are sequentially formed, separated by a memory layer ME. This sequentially forms the memory layer ME and channel layer CN covering the sides and bottom of the memory aperture MH, and fills the center of the memory aperture MH with the core layer CR. On the upper surface of the laminate LMsb, a channel layer CN and a core layer CR are also sequentially formed, separated by a memory layer ME.

[0080] Then, the core layer CR, channel layer CN, and memory layer ME on the upper surface of the stacked matrix LMsb are removed in sequence. At this time, the core layer CR inside the memory hole MH is retracted, forming a depression at the upper end of the memory hole MH.

[0081] As shown in Figure 6A, a capping layer CP is formed at the recessed area at the upper end of the memory via MH. The capping layer CP is also formed on the upper surface of the laminate LMsb. The capping layer CP on the upper surface of the laminate LMsb is removed together with a portion of the uppermost insulating layer OL of the laminate LMsb.

[0082] As shown in Figure 6B, an additional layer is added to the top insulating layer OL of the laminate LMsb, which is thinned by CMP or similar methods. This forms a capping layer CP embedded in the top insulating layer OL, creating a pillar PL. However, at this point, the memory layer ME covers the entire sidewall of the pillar PL, and a portion of the sidewall of the channel layer CN is not exposed from the memory layer ME.

[0083] Subsequently, Figures 7A to 13C show the formation of contact holes CL, which will subsequently become contacts CC, in the multilayers LMsa and LMsb. Figures 7A to 13C show cross-sections of the semiconductor memory device 1 during manufacturing along the X direction, including the area that will subsequently become the contact region ER.

[0084] However, Figures 7A to 13C show, as an example, contact holes CLa to CLah that reach the depth positions of the eight insulating layers NL of the laminate LMs. Also, in Figures 7A to 13C, illustrations of the plurality of columnar portions HR are omitted.

[0085] As described below, a plurality of contact holes CL reaching different depths are formed by forming resist patterns multiple times, each time exposing different contact holes CL and processing them to different depths.

[0086] As shown in Figure 7A, a hard mask pattern 81 with a plurality of openings is formed on the upper surface of the laminate LMs. The hard mask pattern 81 is, for example, an inorganic layer that cannot be removed by combustion reactions such as ashing using oxygen plasma. The plurality of openings of the hard mask pattern 81 are, for example, pore shapes.

[0087] As shown in Figure 7B, the upper surface of the stacked material LMs exposed from the opening of the hard mask pattern 81 is etched to remove the uppermost insulating layer OL. This forms a plurality of contact holes CLh that penetrate the uppermost insulating layer OL and reach the insulating layer NL directly below it.

[0088] As shown in Figure 7C, a resist pattern 91 is formed, which covers part of the upper surface of the laminate LMs through a hard mask pattern 81, and has a plurality of openings. The resist pattern 91 is, for example, an organic layer such as a photoresist layer, which is photosensitive by extreme ultraviolet (EUV) light and can be removed by combustion reactions such as ashing using oxygen plasma, and is formed by spin coating or the like. Contact holes CLh are exposed from the openings of the resist pattern 91, for example, one is exposed every other opening.

[0089] As shown in Figure 8A, the contact hole CLh exposed from the opening of the resist pattern 91 is further etched, and a pair of insulating layers NL and OL are removed from the bottom surface of the contact hole CLh.

[0090] This forms a plurality of contact holes CLg that extend from the uppermost insulating layer OL through the laminate LMs to the second insulating layer OL, and from the uppermost insulating layer NL to the second insulating layer NL. The contact holes CLg are arranged every other contact hole CLh relative to the plurality of contact holes CLh covered by the resist pattern 91.

[0091] That is, in this stage, in the laminate LMs, a plurality of contact holes CLh and a plurality of contact holes CLg are formed alternately.

[0092] As shown in Figure 8B, the resist pattern 91 is removed by ashing using oxygen plasma or the like.

[0093] As shown in Figure 8C, a carbon-containing layer 101 is formed, which covers the upper surface of the laminated layers LMs through a hard mask pattern 81. The carbon-containing layer 101 is, for example, a photosensitive photoresist layer, similar to the aforementioned resist pattern 91, and is formed by a spin coating method or the like. However, since the carbon-containing layer 101 does not require microprocessability, a photoresist layer sensitive to medium ultraviolet light (MUV) or similar methods can be used as the carbon-containing layer 101.

[0094] The carbon-containing layer 101 also fills the plurality of contact holes CLh and CLg. At this time, at the position where it overlaps with the contact hole CLg in the vertical direction, the thickness of the carbon-containing layer 101 on the laminate LMs tends to be slightly thinner, and the contact hole CLg reaches a deeper depth in the laminate LMs than the contact hole CLh. This is because more carbon-containing layer 101 than contact hole CLh is required to fill the contact hole CLg.

[0095] As shown in Figure 9A, the carbon-containing layer 101 is exposed to MUV light and so on, so that it is exposed to light to a specified depth.

[0096] As shown in Figure 9B, the photosensitive portion of the carbon-containing layer 101 is removed by development. This results in the carbon-containing layer 101 being filled to a predetermined depth in each contact hole CLh and CLg. At this point, the upper surface of the carbon-containing layer 101 is preferably located at a depth approximately equal to the upper end of each contact hole CLh and CLg.

[0097] As shown in Figure 9C, a coating layer 71 is formed, which covers and fills the contact holes CLh and CLg containing the carbon layer 101. The coating layer 71 is, for example, an SOG (Spin-On Glass) layer formed by spin coating, and is formed on the entire upper surface of the laminate LMs, including the upper surface of the rigid mask pattern 81. In this case, the coating layer 71 is preferably formed with a density of 2.0 g / cm3 or less.

[0098] As shown in Figure 10A, for example, the carbon-containing layer 101 filling the contact holes CLh and CLg is removed through the coating layer 71 by a combustion reaction. Examples of combustion reactions include annealing at a specified temperature or plasma ashing.

[0099] As described above, the coating layer 71, due to its relatively low layer density, allows the sublimation gas from the carbon-containing layer 101 produced by the combustion reaction to pass through. Furthermore, when plasma ashing is used as the combustion reaction, the coating layer 71 also allows the ashing gas to pass through. In this case, gases commonly known as ashing gases, such as oxygen, water vapor, hydrogen, or NF3 gas, can be used. This allows the carbon-containing layer 101 to be removed through the coating layer 71.

[0100] As shown in Figure 10B, the entire surface of the coating layer 71 is etched back to remove it from the upper surface of the hard mask pattern 81. This leaves the coating layer 71 remaining within each contact hole CLh, CLg in a cap-like state, blocking the upper ends of these contact holes CLh, CLg. Furthermore, the thickness of the coating layer 71 is preferably, for example, around tens to hundreds of nm.

[0101] As shown in Figure 10C, a resist pattern 92 is formed, which covers part of the upper surface of the laminate LMs through the rigid mask pattern 81 and the coating layer 71, and has a plurality of openings. Furthermore, the resist pattern 92, like the resist pattern 91 mentioned above, is formed by a photoresist layer or the like that that is photosensitive by EUV light, and by a spin coating method or the like.

[0102] At this point, the upper ends of each contact hole CLh and CLg are blocked by the coating layer 71. Furthermore, although the layer density of the coating layer 71 is relatively low, liquid photoresist solvents, such as those obtained by dissolving the photoresist material, will not permeate through the coating layer 71. Therefore, the inflow of the photoresist layer into the contact holes CLh and CLg through the coating layer 71 can be suppressed. In this way, the resist pattern 92 covers a portion of the upper surface of the laminate LMs with a substantially uniform thickness.

[0103] The openings of the anti-corrosion pattern 92 are located in a group of adjacent contact holes CLh and CLg, for example, every other group, at a position that overlaps with the contact holes CLh and CLg in the vertical direction, and the coating 71 that blocks the contact holes CLh and CLg is exposed from these openings.

[0104] As shown in Figure 11A, the coating layer 71 on the upper ends of the contact holes CLh and CLg exposed from the opening of the resist pattern 92 is removed by plasma etching or the like. In this way, the contact holes CLh and CLg are exposed from the opening of the resist pattern 92.

[0105] As shown in Figure 11B, the contact holes CLh and CLg exposed from the opening of the resist pattern 92 are further etched, and for example, two pairs of insulating layers NL and OL are removed from the bottom surface of the contact holes CLh and CLg respectively.

[0106] In this way, a plurality of contact holes CLf are formed from the contact hole CLh that becomes the object of etching. These plurality of contact holes CLf penetrate the stacked layers LMs from the uppermost insulating layer OL to the third insulating layer OL, and from the uppermost insulating layer NL to the third insulating layer NL.

[0107] Furthermore, a plurality of contact holes CLe are formed from the contact hole CLg that becomes the object of etching. These plurality of contact holes CLe extend from the uppermost insulating layer OL through the stacked layers LMs up to the fourth insulating layer OL, and from the uppermost insulating layer NL to the fourth insulating layer NL.

[0108] Thus, through the processing up to this point, two sets of contact holes CLh~CLe are formed. These sets of contact holes CLh~CLe are arranged in the order of increasing depth of contact holes CLh~CLe in the laminate LMs.

[0109] As shown in Figure 11C, the resist pattern 92 is removed by ashing using oxygen plasma or the like. Furthermore, the coating layer 71 on the upper ends of the newly exposed contact holes CLh and CLg, which are exposed by removing the resist pattern 92, is removed by plasma etching or the like.

[0110] Subsequently, as described below, the same process as described above is performed repeatedly a specified number of times, such as forming a coating layer to block multiple contact holes CL, forming a resist pattern, and additional etching of the contact holes CL that open from the resist pattern.

[0111] As shown in Figure 12A, a carbon-containing layer 102 is formed, which covers the upper surface of the laminate LMs through a rigid mask pattern 81. The carbon-containing layer 102 is, for example, a photosensitive photoresist layer, similar to the carbon-containing layer 101 described above, and is formed by a spin coating method or the like.

[0112] The carbon-containing layer 102 also fills the plurality of contact holes CLh~CLe. At this time, as the depth of the contact holes CL increases, more carbon-containing layer 102 is filled, thus the thickness of the carbon-containing layer 102 above those contact holes CL becomes thinner. Because the overall depth of the contact holes CL increases, this thickness difference of the carbon-containing layer 102 becomes greater than the thickness difference of the carbon-containing layer 101 described above.

[0113] Then, MUV light is irradiated to expose the carbon-containing layer 102 to a predetermined depth. At this point, it is preferable to adjust various conditions according to the depth reached by the contact hole CL to keep the exposure depth of the carbon-containing layer 102, which has different thicknesses, approximately constant. For example, by forming a layer with low transmittance to the exposed light as the carbon-containing layer 102 and increasing the intensity of the exposed light, it is easier to make the exposure depth of the carbon-containing layer 102 uniform.

[0114] Furthermore, a reticle can also be used at this time, which has a pattern that is not transferred to the resist material and is below the resolution limit. That is, by setting the pattern coverage of the reticle area corresponding to the thicker part of the carbon-containing layer 102 to zero or low, and increasing the pattern coverage of the reticle area corresponding to the thinner part of the carbon-containing layer 102, it is easier to make the photosensitive depth of the carbon-containing layer 102 uniform.

[0115] As shown in Figure 12B, the photosensitive portion of the carbon-containing layer 102 is removed by development. This results in the carbon-containing layer 102 being filled to a predetermined depth within each contact hole CLh~CLe. At this point, by ensuring uniform photosensitive depth as described above, the upper surface of the carbon-containing layer 102 can be positioned at approximately the same depth from the upper end of each contact hole CLh~CLe.

[0116] As shown in Figure 12C, a coating layer 72 is formed, which covers the entire upper surface of the laminate LMs, including the contact holes CLh~CLe filled with carbon-containing layers 102 and the upper surface of the hard mask pattern 81. The coating layer 72 is, for example, an SOG layer formed by spin coating, similar to the coating layer 71 described above. Preferably, the coating layer 72 is formed with a density of 2.0 g / cm³ or less.

[0117] Furthermore, for example, through combustion reactions such as annealing or plasma ashing, the carbon-containing layer 102 filling the contact holes CLh~CLe can be removed by the coating layer 72. When plasma ashing is used as the combustion reaction, the ashing gas can also be a commonly known gas.

[0118] Then, the entire surface of the coating layer 72 is etched back to remove it from the upper surface of the hard mask pattern 81. In this way, the coating layer 72 remains as a cap covering the upper ends of each contact hole CLh~CLe. Furthermore, at this time, the thickness of the coating layer 72 is preferably, for example, around tens to hundreds of nm, similar to that of the coating layer 71 described above.

[0119] As shown in Figure 13A, a resist pattern 93 is formed. This resist pattern 93 covers part of the upper surface of the laminate LMs through the rigid mask pattern 81 and the coating layer 72, and has a plurality of openings. Furthermore, the resist pattern 93, like the resist patterns 91 and 92 mentioned above, is formed by a photoresist layer or the like that sensitive to EUV light, through a spin coating method or the like.

[0120] At this point, the upper ends of each contact hole CLh~CLe are blocked by the coating layer 72, thus preventing the photoresist layer from flowing into these contact holes CLh~CLe. In this way, the resist pattern 93 covers a portion of the upper surface of the laminate LMs with a substantially uniform thickness.

[0121] The openings of the anti-corrosion pattern 93 are located in the two sets of contact holes CLh~CLe, and are positioned at a position that overlaps with the one set of contact holes CLh~CLe in the vertical direction, so that the coating layer 72 blocking the contact holes CLh~CLe is exposed from the openings.

[0122] As shown in Figure 13B, the coating layer 72 on the upper ends of the contact holes CLh~CLe exposed from the opening of the resist pattern 93 is removed by plasma etching or the like. This exposes the contact holes CLh~CLe from the opening of the resist pattern 93.

[0123] As shown in Figure 13C, the contact holes CLh~CLe exposed from the opening of the resist pattern 93 are further etched, and for example, four pairs of insulating layers NL and OL are removed from the bottom surface of the contact holes CLh~CLe.

[0124] In this way, a contact hole CLd is formed from the contact hole CLh that becomes the object of etching. The contact hole CLd extends from the uppermost insulating layer OL through the stacked layers LMs to the fifth insulating layer OL, and from the uppermost insulating layer NL to the fifth insulating layer NL.

[0125] Furthermore, a contact hole CLc is formed from the contact hole CLg that becomes the object of etching. The contact hole CLc extends from the uppermost insulating layer OL through the stacked layers LMs to the sixth insulating layer OL, and from the uppermost insulating layer NL to the sixth insulating layer NL.

[0126] Furthermore, a contact hole CLb is formed from the contact hole CLf that becomes the object of etching. The contact hole CLb extends from the uppermost insulating layer OL through the stacked layers LMs to the 7th insulating layer OL, and from the uppermost insulating layer NL to the 7th insulating layer NL.

[0127] Furthermore, a contact hole CLa is formed from the contact hole CLa that becomes the object of etching. The contact hole CLa extends from the uppermost insulating layer OL through the stacked layers LMs to the 8th insulating layer OL, and from the uppermost insulating layer NL to the 8th insulating layer NL.

[0128] In this way, a plurality of contact holes CLh~CLa are formed, and the depth of these plurality of contact holes CLh~CLa in the laminate LMs increases sequentially, reaching the 8 insulating layers NL in the laminate LMs respectively.

[0129] Then, the resist pattern 93 is removed by ashing using oxygen plasma or the like. Furthermore, the hard mask pattern 81 and the residual coating layer 72 in some of the contact holes CLh~CLe are removed by plasma etching or the like.

[0130] Furthermore, a sacrificial layer such as an amorphous silicon layer or a CVD carbon layer is filled into the contact holes CLh~CLe. In subsequent steps, an insulating layer 56 and a conductive layer 26 (see Figure 2B, etc.) are formed to form a plurality of contacts CC.

[0131] Subsequently, Figures 14A to 17B illustrate the formation of the intermediate source line BSL from the intermediate sacrificial layer SCN of the source line SL, and the formation of the word line WL from the insulating layer NL of the stacked layers LMsa and LMsb. Similar to Figures 3A to 6b above, Figures 14A to 17B show cross-sections of the semiconductor memory device 1 during manufacturing along the Y direction, including the region that will subsequently become the memory region MR.

[0132] As shown in Figure 14A, a slit ST is formed, which penetrates the stacked layers LMsb and LMsa, the upper source line DSLb, and reaches the intermediate sacrificial layer SCN. Furthermore, an insulating layer 55s is formed on the opposite sidewalls of the slit ST in the Y direction. The slit ST also extends in the X direction within the stacked layers LMsa and LMsb.

[0133] As shown in Figure 14B, a removal solution, such as hot phosphoric acid, for removing the intermediate sacrificial layer SCN, flows in through the slit ST protected by the insulating layer 55s on the sidewall, thereby removing the intermediate sacrificial layer SCN sandwiched between the lower source line DSLa and the upper source line DSLb.

[0134] This forms an interstitial layer GPs between the lower source line DSLa and the upper source line DSLb. Furthermore, a portion of the memory layer ME on the outer periphery of the pillar PL is exposed within the interstitial layer GPs. At this time, because the sidewalls of the slit ST are protected by the insulating layer 55s, it is even possible to prevent the removal of the insulating layer NL within the stacked layers LMsa and LMsb.

[0135] As shown in Figure 15A, the liquid is appropriately directed into the interstitial layers GPs through the slit ST, sequentially removing the barrier insulating layer, charge accumulation layer, and tunnel insulating layer (not shown) of the memory layer ME exposed within the interstitial layers GPs. This removes the memory layer ME from a portion of the sidewall of the pillar PL, exposing a portion of the inner channel layer CN within the interstitial layers GPs.

[0136] As shown in Figure 15B, a raw material gas, such as amorphous silicon, is injected through a slit ST protected by an insulating layer 55s on the sidewall, and the interstitial layer GPs is filled with amorphous silicon. Furthermore, the support substrate SS is heated to polycrystalline the amorphous silicon filling the interstitial layer GPs, thereby forming an intermediate source line BSL containing polycrystalline silicon.

[0137] In this way, a portion of the channel layer CN of the pillar PL is connected to the source line SL on the side via the intermediate source line BSL.

[0138] Furthermore, although not illustrated, the aforementioned slit ST will subsequently become an extension of the contact area ER, with the lower end of the slit ST reaching the intermediate insulating layer SCO sandwiched between the lower source line DSLa and the upper source line DSLb. Therefore, the intermediate insulating layer SCO will not be affected by the processing described in Figures 14A to 15B, and will remain even after the processing described in Figures 14A to 15B.

[0139] As shown in Figure 16A, the insulating layer on the sidewall of the slit ST is removed for 55 seconds.

[0140] As shown in Figure 16B, a removal liquid, such as hot phosphoric acid, used to remove the insulating layer NL, flows into the interior of the laminates LMsa and LMsb through the slit ST where the insulating layer 55s has been removed, thereby removing the insulating layer NL from the laminates LMsa and LMsb. This forms the laminates LMga and LMgb, which have a plurality of gap layers GP formed by removing the insulating layer NL between the insulating layers OL.

[0141] The laminates LMga and LMgb, comprising a plurality of interstitial layers GP, are brittle structures. A plurality of pillars PL support this brittle laminate LMga and LMgb. Furthermore, although not illustrated, at the junction region ER, the aforementioned pillars HR (see Figure 2B, etc.) support the brittle laminate LMga and LMgb as described above. This suppresses bending of the residual insulating layer OL within the laminates LMga and LMgb, or deformation or collapse of the laminates LMga and LMgb.

[0142] As shown in Figure 17A, a raw material gas containing a conductive material, such as tungsten or molybdenum, is injected into the laminates LMga and LMgb through the slit ST. The conductive material fills the interstitial layer GP of the laminates LMga and LMgb to form multiple character lines WL, etc. In this way, a laminate LM is formed, which comprises laminates LMa and LMb formed by alternating layers of multiple character lines WL and multiple insulating layers OL.

[0143] As mentioned above, the process of forming the intermediate source line BSL from the intermediate sacrificial layer SCN and the process of forming the word line WL from the insulating layer NL are also called replacement processes.

[0144] As shown in Figure 17B, a conductive layer 25 is filled within the slit ST through an insulating layer 55 to form a plate-shaped contact LI. Furthermore, a groove is formed that penetrates one or more conductive layers, including the uppermost conductive layer of the laminate LMb. A separation layer SHE is formed by filling the groove with an insulating layer 57, which divides the conductive layers into a pattern of selectable gate lines SGD.

[0145] Then, although not shown in the figure, after removing the sacrificial layer from the plurality of contact holes CL (see Figure 13C, etc.) already formed in the contact area ER, the conductive layer 26 is filled in the contact holes CL through the insulating layer 56 to form a plurality of contacts CC respectively connected to a plurality of character lines WL and select gate lines SGD, SGS.

[0146] Furthermore, after forming the insulating layer 52 covering the stacked body LM, a plug CH is formed. The plug CH penetrates the uppermost insulating layer OL and the insulating layer 52 of the stacked body LM and is connected to the capping layer CP at the upper end of the pillar PL. Furthermore, an insulating layer 53 covering the insulating layer 52 is formed, and a bit line BL connected to each plug CH is formed in the insulating layer 53.

[0147] Furthermore, in parallel with this, a plug V0 is formed, which penetrates the insulating layer 52 and is connected to the upper end of the contact CC. Also, an upper wiring MX connected to each plug V0 is formed in the insulating layer 53.

[0148] Furthermore, for example, a double-track metal inlay method can be used to form the plug CH and bit line BL, and the plug V0 and upper layer wiring MX together.

[0149] Furthermore, on a semiconductor substrate SB formed separately from the support substrate SS on which the stacked body LM is formed, a peripheral circuit CBA is formed and covered by an insulating layer 40. In the insulating layer 40, contacts, vias, wirings, etc., that lead the peripheral circuit CBA to the surface of the insulating layer 40 are formed and connected to electrode pads, etc., formed on the upper surface of the insulating layer 40.

[0150] Next, the support substrate SS and the semiconductor substrate SB are bonded together using their respective insulating layers 50 and 40, and the electrode pads in the insulating layers 50 and 40 are connected. Then, the support substrate SS is removed to expose the source line SL, and it is connected to the electrode film EL via the insulating layer 60 with the plug PG formed thereon.

[0151] In this way, a semiconductor memory device 1 according to the embodiment is manufactured.

[0152] (Comparative Example) In semiconductor memory devices such as three-dimensional non-volatile memory, a plurality of contacts are sometimes formed. These contacts pass through a multilayer formed by stacking multiple word lines, and are respectively connected to each word line. The plurality of contacts can be obtained by forming resist patterns multiple times to form a plurality of contact holes with different depths.

[0153] However, if a resist pattern is formed on the contact holes during the formation of multiple contact holes, the contact holes will also be filled with resist material. In this case, since the amount of resist material varies depending on the depth of the contact holes, the thickness of the resist pattern may be uneven. Figures 18A-18C illustrate this situation.

[0154] Figures 18A-18C are part of the procedure for forming the contact hole CL in the semiconductor memory device of the comparative example.

[0155] Figure 18A shows the formation of photoresist layers 93x on contact holes CLh~CLe with different depths of penetration as shown in Figure 11C of the above embodiment. As shown in Figure 18A, the depths of penetration of contact holes CLh~CLe increase sequentially, and correspondingly, the thickness of the photoresist layers 93x formed on these contact holes CLh~CLe gradually decreases.

[0156] As shown in Figure 18B, in order to process a portion of a plurality of contact holes CLh~CLe, a photoresist layer 93x is patterned by exposure and development to form a resist pattern 93p with openings on a portion of the contact holes CLh~CLe. However, due to the uneven thickness of the photoresist layer 93x, the exposure state of the resist pattern 93p will also be uneven according to the layer thickness, making it difficult to form openings with equal opening areas on these contact holes CLh~CLe.

[0157] As shown in Figure 18C, in order to perform additional etching on the contact holes CLh~CLe exposed from the opening of the resist pattern 93p, it is also necessary to remove the photoresist layer 93x filling the contact holes CLh~CLe. At this time, the overall thickness of the resist pattern 93p is reduced, which may result in insufficient protection of the parts other than the etched objects during the subsequent additional etching of the contact holes CLh~CLe.

[0158] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, a carbon-containing layer 102 is filled into a plurality of contact holes CLh~CLe, such that its upper surface is located at a depth specified from the upper end of each of the plurality of contact holes CLh~CLe. Furthermore, a coating layer 72 is formed, which covers the upper surface of the carbon-containing layer 102 in each of the plurality of contact holes CLh~CLe, and the carbon-containing layer 102 is removed through the coating layer 72.

[0159] Thus, by forming a cap-like coating 72 that blocks the upper ends of the plurality of contact holes CLh~CLe, the flow of resist material into the contact holes CLh~CLe during the formation of the resist pattern 93 can be suppressed. This suppresses uneven thickness of the resist pattern 93 on the plurality of contact holes CLh~CLe at different depths. Furthermore, it allows for alignment of the focal points of each opening of the resist pattern 93, resulting in a substantially uniform opening area.

[0160] Table 1 below shows an example of the focal offset value during photoresist layer exposure in the comparative example and the embodiment in which the above-described embodiments are applied to a sample substrate. The focal offset value is the difference between the focal value at which the opening area of ​​the resist pattern becomes extremely large or extremely small, and the resist pattern is formed in an area where no contact hole is formed, i.e., a position where there is no concern about resist material flowing into the contact hole.

[0161] [Table 1] Example Comparative example Cont. Non-forming region ±0.00 μm ±0.00 μm Shallow hole Cont. area ±0.00 μm +0.12 μm Deep Hole Cont. Area ±0.00 μm +0.21 μm

[0162] In the regions shown in Table 1 above—those without contact holes, those with contact holes of shallow depth (shallow hole regions), and those with contact holes of greater depth (deep hole regions)—the thickness of the photoresist layer is uneven, resulting in uneven focus shift values ​​during exposure. Therefore, there is a risk of uneven areas at multiple openings, or that some of these openings may not be open at all. On the other hand, in the embodiment, since the unevenness of the photoresist layer thickness is suppressed, the focus shift values ​​are all equal in all of the aforementioned regions.

[0163] Furthermore, according to the configuration of the above embodiment, since the carbon-containing layer 102 is removed after forming the cap-shaped covering layer 72 that blocks the plurality of contact holes CLh~CLe, it is not necessary to remove the carbon-containing layer 102 and the like within the contact holes CLh~CLe after forming the resist pattern 93, thus suppressing the reduction of the resist pattern 93's thickness. This allows for more reliable protection of the portions other than the etched objects when additional etching is performed on the contact holes CLh~CLe.

[0164] According to the manufacturing method of the semiconductor memory device 1 according to the embodiment, the coating layer 72 contains a material that allows sublimation gas from the carbon-containing layer 102 generated by the combustion reaction to pass through, while preventing the photoresist solvent, which is the raw material for the resist pattern 93, from passing through. This allows the carbon-containing layer 102 within the contact holes CLh~CLe to be removed through the coating layer 72 by means of annealing or plasma ashing. Furthermore, even if the resist pattern 93 is subsequently formed on the coating layer 72, the inflow of liquid photoresist solvents into the contact holes CLh~CLe can be prevented.

[0165] According to the manufacturing method of the semiconductor memory device 1 according to the embodiment, the density of the coating layer 72 is 2.0 g / cm3 or less. Thus, since the coating layer 72 has a relatively low density, the carbon-containing layer 102 in the contact holes CLh~CLe can be removed through the coating layer 72.

[0166] According to the manufacturing method of the semiconductor memory device 1 in the embodiment, the coating layer 72 is an SOG layer. The SOG layer is, for example, a layer with low layer density formed by spin coating or the like. In this way, the carbon-containing layer 102 in the contact holes CLh~CLe can be removed through the coating layer 72.

[0167] According to the manufacturing method of the semiconductor memory device 1 of the embodiment, a photoresist layer is formed as a carbon-containing layer 102, and the photoresist layer is exposed to light to a predetermined depth, and the exposed portion of the photoresist layer is removed. In this way, the upper surface of the carbon-containing layer 102 can be easily moved back to a predetermined depth position from the upper end of each of the plurality of contact holes CLh~CLe.

[0168] Furthermore, since precise control, such as patterning the resist pattern 93, is not required, even if the thickness of the carbon layer 102 on the contact holes CLh~CLe is uneven, it is easy to make the height position of the upper surface of the carbon layer 102 that has receded due to photosensitive uniform.

[0169] (Variation Example 1) Next, the method for forming the contact hole CL in the semiconductor memory device of Variation 1 of Embodiment 1 will be described using Figures 19A to 19C. The difference between the semiconductor memory device of Variation 1 and the above embodiment is that the carbon-containing layer is surface-treated before forming the coating layer.

[0170] Figures 19A-19C are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to Embodiment 1. In Figures 19A-19C, the following explanation illustrates the surface treatment of the carbon-containing layer 102 in the above embodiment. That is, Figures 19A-19C correspond to Figures 12A and 12B of the above embodiment. However, in the multiple steps of forming the contact hole CL, surface treatment can be performed each time the carbon-containing layer is formed.

[0171] Furthermore, in Figures 19A to 19C, sometimes the same symbols are used to mark the same components as in the embodiments, and their descriptions are omitted.

[0172] As shown in Figure 19A, a plurality of contact holes CLh~CLe are formed in the laminate LMs. Furthermore, a carbon-containing layer 102 covering the contact holes CLh~CLe is formed, for example, by spin coating.

[0173] As shown in Figure 19B, the carbon-containing layer 102 is exposed and developed to remove the photosensitive portion of the carbon-containing layer 102.

[0174] Here, when the SOG layer or other coating layer 72 is formed by spin coating or the like, the solvent obtained by dissolving the raw material of the SOG layer, namely the SOG solvent, is coated onto the carbon-containing layer 102, which is also formed by spin coating or the like. At this time, the carbon-containing layer 102 may be partially dissolved by the SOG solvent.

[0175] Therefore, in Variation 1, the surface treatment of the carbon-containing layer 102 is performed as described below.

[0176] As shown in Figure 19C, a carbon-containing layer 102t with a hardened upper surface is formed by surface treatment of the carbon-containing layer 102. Methods for surface treatment of the carbon-containing layer 102 may include, for example, irradiating the upper surface of the carbon-containing layer 102 with ultraviolet light, performing plasma treatment by reactive ion etching (RIE) using argon, oxygen, or carbon fluoride gas, or doping with specified elements such as argon or silicon.

[0177] Through this surface treatment, the CH bonds in the resin material, such as the photoresist layer constituting the carbon-containing layer 102, break on the surface above the carbon-containing layer 102, thus transforming it into a carbon-like layer. That is, the carbonization of the resin material surface constituting the carbon-containing layer 102 progresses as described above, resulting in hardening of the surface above the carbon-containing layer 102. This makes the surface above the carbon-containing layer 102 difficult to dissolve in solvents such as SOG.

[0178] Subsequently, similar to the above embodiment, a coating layer 72 is formed on the carbon-containing layer 102t hardened on the upper surface, and the semiconductor memory device is manufactured by performing the processing after FIG13A of the above embodiment.

[0179] According to the manufacturing method of the semiconductor memory device of Variation 1, the upper surface of the carbon-containing layer 102 located at a predetermined depth from the upper end of each of the plurality of contact holes CLh~CLe is hardened. This prevents the carbon-containing layer 102t with the hardened upper surface from dissolving in the SOG solvent when a SOG layer, such as a coating layer 72, is subsequently formed by spin coating or similar methods.

[0180] According to the method for manufacturing a semiconductor memory device according to Variation 1, hardening the surface above the carbon-containing layer 102 includes: irradiating the surface above the carbon-containing layer 102 with ultraviolet light, performing plasma treatment, or doping with at least one of a specified element. This allows the photoresist layer constituting the carbon-containing layer 102 to deteriorate and become less soluble.

[0181] According to the manufacturing method of the semiconductor memory device of Variation 1, the same effects as the manufacturing method of the semiconductor memory device 1 of the above embodiment can be achieved.

[0182] Furthermore, in the above-described variation 1, surface treatment is performed to harden the surface of the carbon-containing layer 102, thereby making the surface of the carbon-containing layer 102 less soluble. However, the method for making the carbon-containing layer 102 less soluble is not limited to the above-described surface treatment. For example, a highly cross-linked resin material can also be used as the carbon-containing layer 102 to make it less soluble.

[0183] However, highly cross-linked resin materials must be formed at high temperatures, which makes the carbon-containing layer 102 in the contact holes CLh~CLe prone to shrinkage. Therefore, when using a highly cross-linked resin material as the carbon-containing layer 102, it is preferable to control the amount of filling into the contact holes CLh~CLe based on the shrinkage during the formation of the carbon-containing layer 102.

[0184] (Variation Example 2) Next, the method for forming the contact hole CL in the semiconductor memory device of Variation Example 2 of Embodiment 2 will be described using Figures 20A to 20C. The difference between the semiconductor memory device of Variation Example 2 and the above embodiment is that a CVD-SiO layer is formed as the coating layer instead of an SOG layer.

[0185] Figures 20A-20C are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to Embodiment Variation 2. In Figures 20A-20C, the following explanation illustrates the case where the coating layer 72a of Embodiment Variation 2 is formed on the carbon-containing layer 102 of the above-described embodiment. That is, Figures 20A-20C correspond to Figures 12A-12C of the above-described embodiment. However, in the multiple steps of forming the contact hole CL, a CVD-SiO layer can be used each time the coating layer is formed.

[0186] Furthermore, in Figures 20A to 20C, sometimes the same symbols are used to mark the same components as in the embodiments, and their descriptions are omitted.

[0187] As shown in Figure 20A, a plurality of contact holes CLh~CLe are formed in the laminate LMs. Furthermore, a carbon-containing layer 102 covering the contact holes CLh~CLe is formed, for example, by spin coating.

[0188] As shown in Figure 20B, the carbon-containing layer 102 is exposed and developed to remove the photosensitive portion of the carbon-containing layer 102.

[0189] As shown in Figure 20C, a coating layer 72a is formed, which covers the entire upper surface of the stacked body LMs, including the contact holes CLh~CLe filled with the carbon-containing layer 102 and the upper surface of the hard mask pattern 81. The coating layer 72a is, for example, a SiO layer formed by chemical vapor deposition (CVD). Furthermore, when using this CVD method, the coating layer 72a is formed with a substantially uniform layer thickness on the upper surface of the carbon-containing layer 102, as well as the sidewalls and upper surface of the hard mask pattern 81.

[0190] Furthermore, although CVD-SiO layers are denser than SOG layers, even when using CVD-SiO layers as the coating layer 72a, it is still preferable to form the coating layer with a layer density of 2.0 g / cm3 or less. Also, the coating layer 72a is preferably formed such that the entire surface is etched back in subsequent steps, and at the stage where it is processed into a cap shape that blocks each contact hole CLh~CLe, it has a layer thickness of approximately tens of nm.

[0191] By constructing the coating layer 72a as described above, even in the configuration of Variation Example 2, annealing or plasma ashing can be used to remove the carbon-containing layer 102 through the coating layer 72a.

[0192] Furthermore, in order to prevent the carbon-containing layer 102 filling the contact holes CLh~CLe from deteriorating, it is preferable to use a low-temperature CVD method to form the coating layer 72a. Moreover, by using atomic layer deposition (ALD) or similar methods, the coating layer 72a can be formed more precisely. Atomic layer deposition is a type of CVD method.

[0193] Subsequently, similar to the above embodiment, the carbon-containing layer 102 is removed through the coating layer 72a, and the semiconductor memory device is manufactured by performing the processing after FIG13A of the above embodiment.

[0194] According to the manufacturing method of the semiconductor memory device in Variation 2, the coating layer 72a is a CVD-SiO layer. This allows the coating layer 72a to be formed on the carbon-containing layer 102 without concern about the dissolution of the carbon-containing layer 102.

[0195] According to the manufacturing method of the semiconductor memory device in Variation 2, the same effects as the manufacturing method of the semiconductor memory device 1 in the above embodiment can be achieved.

[0196] (Variation Example 3) Next, the method for forming the contact hole CL in the semiconductor memory device of Variation 3 of Embodiment 3 will be described using Figures 21A to 21C. The difference between the semiconductor memory device of Variation 3 and the above-described embodiment is that a CVD-SiO layer is formed before forming a coating layer such as an SOG layer.

[0197] Figures 21A-21C are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to Embodiment Variation 2. In Figures 21A-21C, the following explanation illustrates the case where a coating layer 72b, serving as an SOG layer, is formed on the carbon-containing layer 102 of the above embodiment, with a coating layer 72a serving as a CVD-SiO layer as a buffer. That is, Figures 21A-21C show the processing following Figures 20A-20C of Embodiment 2. However, in the multiple steps of forming the contact hole CL, a CVD-SiO layer can be inserted each time a coating layer such as an SOG layer is formed.

[0198] As described above, the coating layer 72a formed using the CVD method has a generally uniform thickness. Therefore, compared to the coating layer 72 formed using methods such as spin coating, the surface of the coating layer 72a is prone to unevenness due to the influence of the hard mask pattern 81. Therefore, as shown below, an SOG layer coating layer 72b is formed overlapping the CVD-SiO layer coating layer 72a.

[0199] As shown in FIG21A, a coating layer 72a of the above-described variation 2 is formed on the upper end of a plurality of contact holes CLh~CLe. The carbon-containing layer 102 inside the contact holes CLh~CLe is removed through the coating layer 72a by means of annealing or plasma ashing.

[0200] As shown in Figure 21B, a coating layer 72b is further formed on the coating layer 72a covering the contact holes CLh~CLe. Since the coating layer 72b is an SOG layer formed by spin coating or the like, the influence of the unevenness of the hard mask pattern 81 is mitigated by forming the coating layer 72b overlapping with the coating layer 72a.

[0201] As shown in Figure 21C, by etching back the entire surface of the coating layers 72a and 72b, the coating layers 72a and 72b on the hard mask pattern 81 are removed, resulting in coating layers 72a and 72b that cover the contact holes CLh to CLe in a cap-like manner. This yields coating layers 72a and 72b with a flatter overall surface.

[0202] According to the manufacturing method of the semiconductor memory device of Variation 2, a coating layer 72a is formed covering the upper surface of the carbon-containing layer 102, the carbon-containing layer 102 being located at a depth specified from the upper end of each of the plurality of contact holes CLh~CLe. Furthermore, a coating layer 72b is formed covering the plurality of contact holes CLh~CLe through the coating layer 72a.

[0203] Thus, by introducing a coating layer 72a, such as a CVD-SiO layer, a coating layer 72b can be formed on the carbon-containing layer 102 without worrying about the dissolution of the carbon-containing layer 102. Furthermore, by covering the contact holes CLh~CLe with the coating layer 72b, such as an SOG layer, through the coating layer 72a, the overall flatness of the coating layers 72a and 72b can be improved.

[0204] According to the manufacturing method of the semiconductor memory device in Variation 3, the same effects as the manufacturing method of the semiconductor memory device 1 in the above embodiment can be achieved.

[0205] (Variation Example 4) Next, the method for forming the contact hole CL in the semiconductor memory device of Variation Example 4 of Embodiment 4 will be described using Figures 22A to 22C. The difference between the semiconductor memory device of Variation Example 4 and the above-described embodiment is that a carbon-containing layer, such as a carbon layer, is formed instead of a photoresist layer.

[0206] Figures 22A-22C are diagrams illustrating a portion of the process of manufacturing a semiconductor memory device according to Embodiment 4. In Figures 22A-22C, the following explanation illustrates a case where a carbon-containing layer 103 is formed instead of the carbon-containing layer 102 in the above-described embodiment. That is, Figures 22A-22C correspond to Figures 12A-12C of the above-described embodiment. However, in the repeated steps of forming the contact hole CL, a carbon layer can be used each time the carbon-containing layer is formed.

[0207] Furthermore, in Figures 22A to 22C, sometimes the same symbols are used to mark the same components as in the embodiments, and their descriptions are omitted.

[0208] As shown in Figure 22A, a plurality of contact holes CLh~CLe are formed in the laminate LMs. Furthermore, a carbon-containing layer 103 is formed covering these contact holes CLh~CLe. The carbon-containing layer 103 is a carbon layer with carbon as its main component and can be formed by spin coating or CVD.

[0209] Unlike photoresist layers, carbon layers are not photosensitive. However, like photoresist layers, carbon layers can be removed through combustion reactions such as annealing or plasma ashing.

[0210] As shown in Figure 22B, the surface of the carbon-containing layer 103 is removed by methods such as chemical mechanical polishing (CMP). This results in the carbon-containing layer 103 being filled to a predetermined depth in each contact hole CLh~CLe.

[0211] Similarly, the upper surface of the carbon-containing layer 103 is preferably at a depth approximately equal to the upper end of each contact hole CLh~CLe. However, when the carbon-containing layer 103 is removed using methods such as CMP, the upper surface of the carbon-containing layer 103 sometimes forms a shape known as a dish-shaped depression, that is, for example, the central portion of a plurality of contact holes CLh~CLe arranged in the X direction is slightly recessed than the vicinity of the two ends. This is because the grinding rate of the central portion of the plurality of contact holes CLh~CLe tends to be slightly faster than the grinding rate near the two ends.

[0212] As shown in Figure 22C, a coating layer 73 is formed, which covers the entire upper surface of the laminate LMs, including the contact holes CLh~CLe filled with carbon-containing layers 103 and the upper surface of the hard mask pattern 81. Alternatively, the coating layer 73 can be an SOG layer, for example, applied using a spin coating method. This allows the outermost surface of the coating layer 73 to be substantially flat even if the height of the upper surface of the carbon-containing layer 103 within the contact holes CLh~CLe is slightly inconsistent due to disc-shaped recesses, etc.

[0213] Furthermore, the carbon-containing layer 103 is removed through the coating layer 73 by means of annealing or plasma ashing. Then, the entire surface of the coating layer 73 covering the entire upper surface of the overlay body LMs is etched back to obtain the coating layer 73 that covers the upper ends of the contact holes CLh~CLe in a cap-like manner.

[0214] Subsequently, the processing described in Figure 13A of the above embodiment is performed to manufacture a semiconductor memory device.

[0215] (Other examples of variations) In the above-described embodiments, during the repeated steps of forming the contact hole CL, the upper end of the contact hole CL is pre-sealed with a coating layer in a cap-like manner each time the resist pattern is formed. However, the above-described embodiments can also be applied only to the latter half of the repeated steps of forming the contact hole CL. In this latter half of the steps, the depth of the contact hole CL increases, and the thickness difference of the resist pattern is more likely to exceed the allowable value.

[0216] Furthermore, in the above embodiments and variations 1 to 4, for example, the contact holes CL are arranged in such a way that the depth reaches an increasing number of times in the X direction. However, the arrangement order of the contact holes CL is not limited to this. Also, the processing order of the contact holes CL is not limited to the examples in the above embodiments, and various methods can be used. By applying the configuration of the above embodiments, it is possible to form a resist pattern with a substantially uniform layer thickness on contact holes of different depths, regardless of the arrangement order and processing order of the contact holes.

[0217] Furthermore, in the above embodiments and variations 1 to 4, when additional processing is performed on the contact holes, a resist pattern such as a photoresist layer is used as a mask. In this case, the photoresist layer used as the mask can be either positive or negative. Also, when forming the resist pattern, a bottom anti-reflective coating (BARC) layer can be placed, or a multi-layer mask structure composed of a carbon layer / SOG layer / photoresist layer can be used as the mask pattern. By applying the above embodiments and their configurations, as described above, a resist pattern with a substantially uniform layer thickness can be formed on contact holes reaching different depths without being affected by the type or shape of the mask pattern.

[0218] Furthermore, in the above embodiments and variations 1 to 4, when a photoresist layer or the like is used to form a resist pattern, exposure is performed using EUV or the like. However, the exposure of the resist pattern and the exposure method are not limited to the above examples. For example, MUV, or excimer laser light such as KrF or ArF can also be used. When using ArF excimer laser light, dry exposure or immersion exposure methods can be used. Even when a photoresist layer is used as a carbon-containing layer as in the above embodiments and variations 1 to 3, exposure is not limited to MUV, and the type of light and exposure type can be appropriately selected.

[0219] Furthermore, in the above embodiments and variations 1 to 4, the contact regions ER, etc., are disposed at both ends of the laminate LM in the X direction. However, the placement of the contact regions in the laminate LM is not limited to this. The contact regions may also be disposed, for example, at the central part of the laminate LM. In this case, for example, memory regions MR may be disposed at both ends of the laminate LM.

[0220] Furthermore, in the above embodiments and variations 1 to 4, the pillar PL is connected to the source line SL on the side of the channel layer CN, but it is not limited to this. For example, the pillar can also be constructed by removing the memory layer at the bottom of the pillar and connecting it to the source line at the lower end of the channel layer.

[0221] Furthermore, in the above embodiments and variations 1 to 4, the insulating layers NL and OL are laminated in two stages, resulting in a laminate LM with a two-layer structure comprising laminates LMa and LMb. However, the laminate may also have a single-layer structure, or it may have a structure with three or more layers. By continuously increasing the number of layers, the number of laminates for the character line WL can be further increased.

[0222] Several embodiments of the present invention have been described, but these embodiments are provided as examples and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other forms and can be omitted, substituted, or modified in various ways without departing from the spirit of the invention. These embodiments and their variations are included in the scope or spirit of the invention, and are included within the scope of the invention described in the claims and their equivalents.

[0223] 1: Semiconductor memory devices 25: Conductive layer 26: Conductive layer 27: Sacrificial Layer 40: Insulation layer 50: Insulation layer 52: Insulation layer 53: Insulation layer 54: Insulation layer 55: Insulation layer 55s: Insulation layer 56: Insulation layer 57: Insulation layer 60: Insulation layer 71, 72, 72a, 72b, 73: Overlying layer 81: Hard mask pattern 91~93: Anti-corrosion patterns 93x: Photoresist layer 93p: Anti-corrosion pattern 101, 102, 102t, 103: Carbon-containing layers BL: Bitline BSL: Intermediate Source Line CBA: Peripheral Circuits CC: Contact CL, CLa~CLh: Contact holes CP: cap layer CN: Channel Layer CR: Core Layer DSLa: Lower source line DSLb: Upper source line EL: Electrode film ER: Contact Area GP: Interstitial layer GPs: interstitial layer HR: columnar portion HRa: columnar portion HRb: columnar portion LM, LMa, LMb, LMga, LMgb, LMsa, LMsb: laminated body LMs: stacked volumes LI: plate contact MC: Memory Cell ME: Memory Layer MR: Memory Region MHa: Memory Hole MHb: Memory Hole MX: Upper layer wiring NL,OL: Insulation layer PL, PLA, PLB: Columns PLC: Column PDb: Electrode pad PDc: Electrode pad PL: Column PG: Plug SB: Semiconductor substrate SGD, SGS: Selecting the gate wire SGD0: Select gate line SGD1: Select gate line SGS0: Select Gate Line SGS1: Select Gate Line STD, STS: Select gate SS: Support substrate ST: Slit SL: Source Line SCN: Intermediate Sacrificial Layer SHE: Separation layer TR: Transistor WL: Character Line

Claims

1. A method for manufacturing a semiconductor memory device, comprising: forming a multilayer body, the multilayer body being formed by alternating layers of a plurality of first insulating layers and a plurality of second insulating layers; forming a plurality of holes extending along the stacking direction of the multilayer body and reaching different depths; filling the plurality of holes with a carbon-containing layer such that each hole has an upper surface at a predetermined depth from its upper end; forming a coating layer covering the upper surface of the carbon-containing layer in each of the plurality of holes; removing the carbon-containing layer through the coating layer; and forming a resist pattern covering a portion of the plurality of holes blocked by the coating layer and having an opening for exposing another portion of the plurality of holes. The coating layer that blocks the opening of the plurality of holes exposed in the above-mentioned anti-corrosion pattern is removed, and the other part of the plurality of holes is further processed to increase the depth of the other part of the plurality of holes.

2. The method for manufacturing a semiconductor memory device as claimed in claim 1, wherein the carbon-containing layer is removed by a combustion reaction, and the coating layer comprises a material that allows the sublimation gas of the carbon-containing layer generated by the combustion reaction to pass through, but does not allow the photoresist solvent, which is the raw material for the resist pattern, to pass through.

3. The method for manufacturing a semiconductor memory device as claimed in claim 2, wherein the density of the aforementioned coating layer is 2.0 g / cm3 or less.

4. The method for manufacturing a semiconductor memory device as claimed in claim 2, wherein the coating layer is an SOG layer or a CVD-SiO layer.

5. A method for manufacturing a semiconductor memory device as claimed in claim 1, wherein filling the plurality of holes with the carbon-containing layer comprises: A carbon-containing layer is formed covering the plurality of holes, and the carbon-containing layer is filled into the plurality of holes; and the thickness of the carbon-containing layer covering the plurality of holes is reduced, such that the upper surface of the carbon-containing layer is retracted to a position at a predetermined depth from the upper end of each of the plurality of holes.

6. The method for manufacturing a semiconductor memory device as claimed in claim 5, wherein retracting the aforementioned upper surface of the carbon-containing layer comprises: A photoresist layer is formed as the aforementioned carbon-containing layer, and the photosensitive portion of the photoresist layer is removed by exposing the photoresist layer to a predetermined depth.

7. The method for manufacturing a semiconductor memory device as claimed in claim 6, wherein forming the aforementioned coating layer includes: A CVD-SiO layer is formed covering the upper surface of the photoresist layer, the photoresist layer being located at a predetermined depth from the upper end of each of the plurality of holes; and an SOG layer is formed as the coating layer, the coating layer covering the plurality of holes through the CVD-SiO layer.

8. The method for manufacturing a semiconductor memory device as claimed in claim 6, wherein forming the aforementioned coating layer includes: The photoresist layer is hardened at a predetermined depth from the upper end of each of the plurality of holes; and an SOG layer is formed as the coating layer, which covers the hardened upper surface of the carbon-containing layer.

9. The method for manufacturing a semiconductor memory device as claimed in claim 8, wherein hardening the upper surface of the photoresist layer comprises: The photoresist layer is subjected to ultraviolet light, plasma treatment, or doping with a specified element, or at least one of these methods.

10. The method for manufacturing a semiconductor memory device as claimed in claim 4, wherein retracting the aforementioned upper surface of the carbon-containing layer comprises: A carbon layer is formed as the aforementioned carbon-containing layer, and the aforementioned carbon layer is etched back to a specified depth.

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