Electronic device

Abstract

This disclosure provides an electronic device. The electronic device includes an adjustable element, a first power supply circuit, and a second power supply circuit. The first power supply circuit and the second power supply circuit are electrically connected to the adjustable element. The first power supply circuit drives the adjustable element during a first time period. The second power supply circuit drives the adjustable element during a second time period.

Description

Technical Field

[0001] The present disclosure relates to an electronic device, and more particularly to an electronic device having an adjustable element. Prior Art

[0002] Generally, electronic devices use a driver element to drive electronic components. The driver element provides driving power to electronic components (such as pixel circuits or adjustable elements). However, over extended periods of operation, driver elements can degrade. The abnormal driving power provided by the degraded driver element can reduce the stability of the electronic components during operation. Therefore, reducing the potential for driver element degradation and improving the stability of electronic components during operation is a key research topic for those skilled in the art. Summary of the Invention

[0003] The present disclosure provides an electronic device capable of improving the stability of electronic components during long-term operation.

[0004] The electronic device disclosed herein includes an adjustable element, a first power supply circuit, and a second power supply circuit. The first power supply circuit and the second power supply circuit are electrically connected to the adjustable element. The first power supply circuit drives the adjustable element during a first time period. The second power supply circuit drives the adjustable element during a second time period.

[0005] Based on the above, the first and second power supply circuits use a time-sharing method to drive the adjustable element. The first and second power supply circuits can alternately rest. This reduces the likelihood of degradation of the first and second power supply circuits during long-term operation, thereby improving the stability of the electronic device during operation.

[0006] To make the above features and advantages of the present disclosure more clearly understood, embodiments are given below and described in detail with reference to the accompanying drawings. Simple diagram description

[0007] FIG1 is a schematic diagram of an electronic device according to a first embodiment of the present disclosure. FIG. 2 is a schematic diagram of an electronic device according to a second embodiment of the present disclosure. FIG3 is a circuit diagram of an electronic device according to a second embodiment of the present disclosure. FIG. 4 is a timing diagram according to the second embodiment of the present disclosure. FIG. 5 is a schematic diagram of an electronic device according to a third embodiment of the present disclosure. FIG6 is a circuit diagram of an electronic device according to a third embodiment of the present disclosure. FIG. 7 is a timing diagram according to FIG. 6 . FIG. 8 is a layout diagram of a substrate of an electronic device according to an embodiment of the present disclosure. Implementation Method

[0008] The present disclosure can be understood by referring to the following detailed description in conjunction with the accompanying drawings, as described below. It should be noted that for the purposes of clarity and ease of understanding, the various figures of the present disclosure depict portions of electronic devices, and some elements in each figure may not be drawn to scale. Furthermore, the number and size of each device depicted in the figures are for illustrative purposes only and are not intended to limit the scope of the present disclosure.

[0009] Certain terms are used throughout the description and in the following claims to refer to specific components. As those skilled in the art will appreciate, electronic device manufacturers may refer to components by different names. This document does not intend to distinguish between components that differ in name but not function. In the following description and in the claims, the terms "include," "comprises," and "have" are used in an open-ended manner and, therefore, should be interpreted to mean "including, but not limited to..." Therefore, when the terms "include," "comprising," and / or "having" are used in the description of the present disclosure, they will indicate the presence of corresponding features, regions, steps, operations, and / or elements, but are not limited to the presence of one or more corresponding features, regions, steps, operations, and / or elements.

[0010] It should be understood that when an element is referred to as being “coupled to,” “connected to,” or “connected to” another element, the element may be directly connected to the other element and an electrical connection may be directly established, or an intermediate element may exist between the elements for relaying the electrical connection (indirect electrical connection). In contrast, when an element is referred to as being “directly coupled to,” “directly connected to,” or “directly connected to” another element, there are no intermediate elements.

[0011] Although terms such as first, second, and third may be used to describe various components, these components are not limited by these terms. These terms are used solely to distinguish components from other components in the specification. Claims may not use the same terms, but instead may use terms such as first, second, and third relative to the order in which the components are described. Therefore, in the following description, the first component may be the second component in a claim.

[0012] The electronic devices disclosed herein may include, but are not limited to, display devices, antenna devices, sensing devices, light-emitting devices, touch displays, curved displays, or free-form displays. The electronic devices may include bendable or flexible electronic devices. The electronic devices may, for example, include, but are not limited to, liquid crystal, light-emitting diodes, quantum dots (QDs), fluorescence, phosphors, other suitable display media, or combinations thereof. Light-emitting diodes may, for example, include, but are not limited to, organic light-emitting diodes (OLEDs), sub-millimeter light-emitting diodes (mini LEDs), micro LEDs, or quantum dot LEDs (including QLEDs and QDLEDs), or other suitable materials or combinations thereof. The display device may, for example, include, but is not limited to, a tiled display device. The antenna device may, for example, be a liquid crystal antenna or a varactor antenna, but is not limited to such. The antenna device may, for example, include an antenna splicing device, but is not limited thereto. It should be noted that the electronic device may be any combination or permutation of the aforementioned, but is not limited thereto. Furthermore, the electronic device may have a rectangular, circular, polygonal shape, a shape with curved edges, or other suitable shapes. The electronic device may have peripheral systems such as a drive system, a control system, a light source system, etc. to support the display device, antenna device, or splicing device, but the present disclosure is not limited thereto. The sensing device may include a camera, an infrared sensor, or a fingerprint sensor, etc., but the present disclosure is not limited thereto. In some embodiments, the sensing device may also include a flash, an infrared (IR) light source, other sensors, electronic components, or a combination thereof, but is not limited thereto.

[0013] In this disclosure, embodiments use the term "pixel" or "pixel unit" to describe a specific area containing at least one functional circuit for at least one specific function. The area of a "pixel" depends on the unit used to provide the specific function. Adjacent pixels may share the same components or conductors, but may also include their own specific components. For example, adjacent pixels may share the same scan line or data line, but pixels may also have their own transistors or capacitors.

[0014] It should be noted that the technical features in the different embodiments described below may be replaced, recombined, or mixed with each other to constitute another embodiment without departing from the spirit of the present disclosure.

[0015] Please refer to Figure 1, which is a schematic diagram of an electronic device according to a first embodiment of the present disclosure. In this embodiment, the electronic device 100 includes a tunable element EE and first through nth power supply circuits 110_1, 110_n, 110_n. The first power supply circuit 110_1 is electrically connected to the tunable element EE. The first power supply circuit 110_1 can drive the tunable element EE during a first time period. The second power supply circuit 110_2 is electrically connected to the tunable element EE. The second power supply circuit 110_2 can drive the tunable element EE during a second time period. Similarly, the power supply circuit 110_n can drive the tunable element EE during the nth time period. In other words, the first through nth power supply circuits 110_1, 110_n drive the tunable element EE in different time periods using a time-sharing method. In some embodiments, the power supply circuit can be a driver circuit.

[0016] According to some embodiments, the first through nth power supply circuits 110_1 through 110_n utilize a time-sharing mechanism to drive the adjustable element. These circuits can alternately rest. This reduces the likelihood of degradation of the first through nth power supply circuits 110_1 through 110_n during prolonged operation, thereby improving the stability of the first through nth power supply circuits 110_1 through 110_n and the adjustable element EE during prolonged operation.

[0017] The number of power supply circuits disclosed herein can be multiple and is not limited to this embodiment.

[0018] In this embodiment, the first to nth power supply circuits 110_1 to 110_n each receive the same high reference voltage VDD. According to some embodiments, the first time period and the second time period do not overlap. According to some embodiments, the first to nth time periods do not overlap with each other.

[0019] In this embodiment, the electronic device 100 is applicable to the field of wireless transmission. For example, the electronic device 100 is applicable to an antenna device. The adjustable element EE may be a communication element, such as a varactor or a radio frequency radiation element. According to some embodiments, a specific parameter (e.g., a physical parameter) of the adjustable element may be adjusted based on an applied signal. The specific parameter may include, for example, capacitance, inductance, resistance, dielectric constant, or a combination thereof.

[0020] According to some embodiments, as shown in FIG8 , an electronic device 100 may include a substrate 80 , which includes an active region 80A and a peripheral region 80B. The peripheral region 80B is adjacent to the active region 80A. For example, the active region 80A may be located in the center of the substrate 80 , while the peripheral region 80B may be located at an edge of the substrate 80 (this disclosure is not limited to this). Specifically, the peripheral region 80B may be closer to the side edge 800S of the substrate 80 than the active region 80A. The active region 80A may be a region for transmitting and receiving electromagnetic waves. According to some embodiments, an adjustable element EE may be disposed on the substrate 80 within the active region 80A. For example, as shown in FIG8 , a plurality of adjustable elements EE may be disposed within the active region 80A of the substrate 80. According to some embodiments, the first power supply circuit 110_1 to the nth power supply circuit 110_n may be disposed within the active region 80A. According to other embodiments, the first to nth power supply circuits 110_1 to 110_n may be disposed within the peripheral area 80B. According to some embodiments, the substrate 80 may be a rigid substrate or a flexible substrate. For example, a rigid substrate may be glass, and a flexible substrate may be plastic or polymer, but the present disclosure is not limited thereto.

[0021] In addition, in this embodiment, as shown in FIG. 1 , the electronic device 100 further includes a selection circuit 120 and a storage capacitor Cst. The selection circuit 120 is electrically connected to the data line DL. The selection circuit 120 receives a data voltage Vdata from the data line DL and provides the data voltage Vdata to the first power supply circuit 110_1 through the nth power supply circuit 110_n. The storage capacitor Cst is coupled between the selection circuit 120 and the low reference voltage VSS. The capacitor Cst is used to maintain the voltage value of the data voltage Vdata.

[0022] Taking this embodiment as an example, the data voltage Vdata can be used to change the electronic characteristics of the adjustable element EE. In addition, the data voltage Vdata can be used to compensate for the operations of the first power supply circuit 110_1 to the nth power supply circuit 110_n.

[0023] Please refer to FIG. 2 , which is a schematic diagram of an electronic device according to a second embodiment of the present disclosure. In this embodiment, electronic device 200 includes an adjustable element EE, first through nth power supply circuits 210_1 through 210_n, a selection circuit 220, and a storage capacitor Cst. The first through nth power supply circuits 210_1 through 210_n utilize a time-sharing mechanism to drive the adjustable element EE during different time periods.

[0024] The first power supply circuit 210_1 includes a compensation circuit 211_1. The second power supply circuit 210_2 includes a compensation circuit 211_2. Similarly, the nth power supply circuit 210_n includes a compensation circuit 211_n. In this embodiment, the compensation circuits 211_1-211_n can each use the data voltage Vdata to compensate the corresponding power supply circuit. For example, the first compensation circuit 211_1 can use the data voltage Vdata to compensate the first power supply circuit 210_1.

[0025] The first power supply circuit 210_1 also includes a source follower circuit 212_1. The compensation circuit 211_1 can use the data voltage Vdata to compensate the source follower circuit 212_1. For example, the source follower circuit 212_1 uses the high reference voltage VDD to provide driving power (e.g., driving current or driving voltage) to drive the adjustable element EE. However, due to differences in the manufacturing process or operating environment conditions (e.g., temperature and humidity) of the adjustable element EE, the adjustable element EE may experience leakage current during operation. This leakage current of the adjustable element EE can affect the driving power provided by the source follower circuit 212_1. Therefore, the compensation circuit 211_1 can use the data voltage Vdata to compensate for the driving power (e.g., driving current or driving voltage) provided by the source follower circuit 212_1.

[0026] Similarly, the second power supply circuit 210_2 further includes a source follower circuit 212_2. The compensation circuit 211_2 can use the data voltage Vdata to compensate the source follower circuit 212_2. The power supply circuit 210_n further includes a source follower circuit 212_n. The compensation circuit 211_n can use the data voltage Vdata to compensate the source follower circuit 212_n.

[0027] As shown in FIG2 , in this embodiment, the selection circuit 220 may be electrically connected to at least one, some, or all of the power supply circuits 210_1 to 210_n. For example, the selection circuit 220 is electrically connected to the compensation circuits 211_1 to 211_n. The selection circuit 220 provides a data voltage Vdata based on the voltage value of a select signal SS and provides the data voltage Vdata to the compensation circuits 211_1 to 211_n. The selection circuit 220 may include a scan transistor TS. A first terminal of the scan transistor TS is electrically connected to the data line DL to receive the data voltage Vdata. A second terminal of the scan transistor TS is electrically connected to the compensation circuits 211_1 to 211_n. The control terminal GS of the scan transistor TS receives the select signal SS. The scan transistor TS is turned off in response to a low voltage value of the select signal SS. Consequently, the scan transistor TS stops transmitting the data voltage Vdata. The scan transistor TS is turned on in response to a high voltage value of the select signal SS. Therefore, the scan transistor TS can transmit the data voltage Vdata on the data line DL to the compensation circuits 211_1 to 211_n. According to some embodiments, the selection circuit 220 can be disposed in the active region 80A of the substrate 80, and the first to nth power supply circuits 210_1 to 210_n can be disposed in the active region 80A.

[0028] As shown in Figure 2, according to some embodiments, the selection circuit 220 can be configured to provide a data voltage Vdata based on the voltage value of a selection signal SS, and provide the data voltage Vdata to the first power supply circuit and the second power supply circuit. Specifically, the selection circuit 220 can receive the selection signal SS during its on-time, which can be referred to as a scan time. The same scan time can be divided into multiple time periods, for example, a first time period, a second time period, and so on to an nth time period. That is, for example, the scan time can include a first time period and a second time period. The first time period and the second time period can be non-overlapping. According to some embodiments, the first through nth time periods can be non-overlapping.

[0029] In this embodiment, the scanning transistor TS can be implemented as an N-type transistor. For example, the scanning transistor TS is an N-type thin-film transistor or an NMOS transistor. In other embodiments, the scanning transistor TS can be implemented as a P-type transistor. In these embodiments, the scanning transistor TS is turned off based on the high or low voltage values of the select signal SS and turned on based on the low voltage value of the select signal SS. In this specification, for simplicity, the transistor system is illustrated using an N-type transistor, but the present invention is not limited to this. P-type transistors can also be used as the transistor, which will not be discussed in detail here.

[0030] For further explanation, please refer to Figures 3 and 4 simultaneously. Figure 3 is a circuit diagram of an electronic device according to the second embodiment of the present disclosure. Figure 4 is a timing diagram according to the second embodiment of the present disclosure. In this embodiment, the control signals VG1-VGn may have positive pulses during different time periods TT1-TTn. For example, the scan transistor TS is turned on based on the high voltage value of the select signal SS. The control signal VG1 has a positive pulse during time period TT1. The control signal VG2 has a positive pulse during time period TT2. The control signal VG3 has a positive pulse during time period TT3. Similarly, the control signal VGn has a positive pulse during time period TTn. The above time periods TT1-TTn may be adjacent to each other and do not overlap. Therefore, based on the control signals VG1-VGn, the source follower circuits 212_1-212_n sequentially provide substantially the same driving power during different time periods TT1-TTn. In this embodiment, the source follower circuit 212_1 is electrically connected to the first node ND1. In other words, the source follower circuit 212_1 is electrically connected to the adjustable element EE via the first node ND1. The source follower circuit 212_1 includes a control terminal. The voltage at the first node ND1 can follow the voltage at the control terminal of the source follower circuit 212_1 and be provided to the adjustable element EE. The source follower circuit 212_1 is implemented by a power transistor T1-1. A first terminal of the power transistor T1-1 receives a high reference voltage VDD. A second terminal of the power transistor T1-1 is electrically connected to the first node ND1. A control terminal of the power transistor T1-1 receives a control signal VG1. The power transistor T1-1 can be implemented by an N-type transistor. For example, the power transistor T1-1 is an N-type thin-film transistor or an NMOS transistor. Therefore, the voltage at the first node ND1 can follow the voltage value of the control signal VG1. In other embodiments, the power transistor T1-1 can be a P-type transistor, which will not be described here. According to some embodiments, the time period TT1 and the time period TT2 may partially overlap, that is, the pulse of the control signal VG1 and the pulse of the control signal VG2 may partially overlap.

[0031] As shown in FIG3 , the compensation circuit 211_1 includes a compensation transistor T2-1. A first terminal of the compensation transistor T2-1 and a control terminal of the compensation transistor T2-1 are electrically connected to a second terminal of the scan transistor TS. A second terminal of the compensation transistor T2-1 is electrically connected to a first node ND1. The compensation transistor T2-1 is electrically connected between the second terminal of the scan transistor TS and the first node ND1 in a diode connection. A first terminal of the scan transistor TS is electrically connected to a data line DL to receive a data voltage Vdata.

[0032] For example, the adjustable element EE may experience leakage current during operation. The voltage at the first node ND1 may be lower than the designed voltage. Once the voltage at the first node ND1 is reduced, the voltage difference between the first terminal and the second terminal of the power transistor T1-1 increases, thereby increasing the voltage stress of the power transistor T1-1. In this embodiment, the compensation circuit 211_1 uses the data voltage Vdata to compensate for the voltage at the first node ND1 during the first time period, thereby bringing the voltage at the first node ND1 to the designed voltage. The voltage difference between the first terminal and the second terminal of the power transistor T1-1 does not increase. Therefore, the voltage stress of the power transistor T1-1 does not increase.

[0033] In this embodiment, a source follower circuit 212_2 in the second power supply circuit 210_2 is electrically connected to the adjustable element EE via a second node ND2. The source follower circuit 212_2 includes a control terminal. The voltage at the second node ND2 can follow the voltage at the control terminal of the source follower circuit 212_2 and be provided to the adjustable element EE. The source follower circuit 212_2 is implemented by a power transistor T1-2. A first terminal of the power transistor T1-2 receives a high reference voltage VDD. A second terminal of the power transistor T1-2 is electrically connected to the second node ND2. A control terminal of the power transistor T1-2 receives a control signal VG2. The power transistor T1-2 can be implemented by an N-type transistor. For example, the power transistor T1-2 is an N-type thin-film transistor or an NMOS transistor. Therefore, the voltage at the second node ND2 can follow the voltage value of the control signal VG2.

[0034] The compensation circuit 211_2 includes a compensation transistor T2-2. A first terminal of the compensation transistor T2-2 and a control terminal of the compensation transistor T2-2 are electrically connected to the second terminal of the scan transistor TS. A second terminal of the compensation transistor T2-2 is electrically connected to the second node ND2. In this embodiment, the compensation circuit 211_2 uses the data voltage Vdata to compensate for the voltage at the second node ND2 during the second time period, thereby bringing the voltage at the second node ND2 to the designed voltage value. Therefore, the voltage stress of the power transistor T1-2 is not increased.

[0035] In this embodiment, a source follower circuit 212_n in the nth power supply circuit 210_n is electrically connected to the adjustable element EE via the nth node NDn. The source follower circuit 212_n includes a control terminal. The voltage at the nth node NDn can follow the voltage at the control terminal of the source follower circuit 212_n and be provided to the adjustable element EE. The source follower circuit 212_n is implemented by a power transistor T1-n. A first terminal of the power transistor T1-n receives a high reference voltage VDD. A second terminal of the power transistor T1-n is electrically connected to the nth node NDn. A control terminal of the power transistor T1-n receives a control signal VGn. The power transistor T1-n can be implemented by an N-type transistor. For example, the power transistor T1-n is an N-type thin film transistor or an NMOS transistor. Therefore, the voltage at the nth node NDn can follow the voltage value of the control signal VGn.

[0036] The compensation circuit 211_n includes a compensation transistor T2-n. A first terminal and a control terminal of the compensation transistor T2-n are electrically connected to the second terminal of the scan transistor TS. A second terminal of the compensation transistor T2-n is electrically connected to the nth node NDn. In this embodiment, the compensation circuit 211_n uses the data voltage Vdata to compensate for the voltage at the nth node NDn during the nth time period, thereby bringing the voltage at the nth node NDn to the designed voltage value. Therefore, the voltage stress of the power transistor T1-n is not increased.

[0037] Please refer to Figure 5, which is a schematic diagram of an electronic device according to a third embodiment of the present disclosure. In this embodiment, the electronic device 300 includes an adjustable element EE, power supply circuits 310_1-310_n, a compensation circuit 320, and a selection circuit 330. The compensation circuit 320 is electrically connected between the first power supply circuit 310_1 and the adjustable element EE. The first power supply circuit 310_1 can provide a first drive current ID1 during a first time period. The second power supply circuit 310_2 can provide a second drive current ID2 during a second time period. The nth power supply circuit 310_n can provide an nth drive current IDn during an nth time period. The first through nth drive currents ID1 through IDn can be provided to the adjustable element EE in a time-sharing manner.

[0038] In this embodiment, the compensation circuit 320 is electrically connected to the first to nth power supply circuits 310_1 to 310_n, the selection circuit 330, and the adjustable element EE. During different time periods, one of the first to nth drive currents ID1 to IDn can flow through the adjustable element EE via the compensation circuit 320. Therefore, the compensation circuit 320 can receive one of the first to nth drive currents ID1 to IDn during different time periods. In this embodiment, during a first time period, the compensation circuit 320 receives the first drive current ID1 and compensates for the first drive current ID1 flowing through the adjustable element EE. The compensation circuit 320 receives the first drive current ID1 and compensates for the first drive current ID1 flowing through the adjustable element EE. During a second time period, the compensation circuit 320 receives the second drive current ID2 and compensates for the second drive current ID2 flowing through the adjustable element EE. The compensation circuit 320 receives the second drive current ID2 and compensates for the second drive current ID2 flowing through the adjustable element EE, and so on.

[0039] In this embodiment, the selection circuit 330 is electrically connected to the data line DL. The selection circuit 330 receives a data voltage Vdata from the data line DL. The compensation circuit 320 compensates the first through nth driving currents ID1 through IDn based on the data voltage Vdata. This compensates the first through nth driving currents ID1 through IDn so that their values are substantially equal to the driving current of the adjustable element EE when no leakage current occurs. According to some embodiments, the selection circuit 330 and the compensation circuit 320 may be disposed within the active region 80A of the substrate 80, and the first through nth power supply circuits 310_1 through 310_n may be disposed within the peripheral region 80B.

[0040] Please refer to Figure 6, which is a circuit diagram of an electronic device according to a third embodiment of the present disclosure. In this embodiment, a first power supply circuit 310_1 includes a power supply transistor T1-1, and a second power supply circuit 310_2 includes a power supply transistor T1-2. The first power supply circuit 310_1 is electrically connected to the compensation circuit 320 and configured to provide a first drive current ID1 during a first time period. The second power supply circuit 310_2 is electrically connected to the compensation circuit 320 and configured to provide a second drive current ID2 during a second time period. A first terminal of the power supply transistor T1-1 receives a high reference voltage VDD. A second terminal of the power supply transistor T1-1 is electrically connected to the compensation circuit 320. A control terminal of the power supply transistor T1-1 receives a control signal VG1. During the first time period, the power supply transistor T1-1 can provide the first drive current ID1 based on the control signal VG1. The second power supply circuit 310_2 includes a power supply transistor T1-2. A first terminal of the power supply transistor T1-2 receives the high reference voltage VDD. The second terminal of the power supply transistor T1-2 is electrically connected to the compensation circuit 320. The control terminal of the power supply transistor T1-2 receives a control signal VG2. The power supply transistor T1-2 can provide a second drive current ID2 in a second time period based on the control signal VG2. Similarly, the nth power supply circuit 310_n includes a power supply transistor T1-n. The first terminal of the power supply transistor T1-n receives a high reference voltage VDD. The second terminal of the power supply transistor T1-n is electrically connected to the compensation circuit 320. The control terminal of the power supply transistor T1-n receives a control signal VGn. The power supply transistor T1-n can provide an nth drive current IDn in the nth time period based on the control signal VGn.

[0041] The selection circuit 330 includes a scan transistor TS. A first terminal of the scan transistor TS is electrically connected to the data line DL to receive the data voltage Vdata. A second terminal of the scan transistor TS is electrically connected to the compensation circuit 320. A control terminal of the scan transistor TS receives a selection signal SS.

[0042] According to some embodiments, as shown in FIG6 , the compensation circuit 320 may include a bias transistor TB, a compensation transistor TC, a drive transistor TD, a reset transistor TR, and a storage capacitor Cst. A first terminal of the bias transistor TB is electrically connected to the first to nth power supply circuits 310_1 to 310_n. A second terminal of the bias transistor TB is electrically connected to the first terminal of the drive transistor TD. A control terminal of the bias transistor TB receives a bias signal SB. A second terminal of the drive transistor TD is electrically connected to the selection circuit 330 and the adjustable element EE via a node N1. A first terminal of the compensation transistor TC is electrically connected to the second terminal of the bias transistor TB. A second terminal of the compensation transistor TC is electrically connected to the control terminal of the drive transistor TD. The control terminal of the compensation transistor TC receives a selection signal SS. The storage capacitor Cst is electrically connected to the first terminal of the bias transistor TB and the control terminal of the drive transistor TD. A first terminal of the reset transistor TR is electrically connected to the first terminal of the bias transistor TB. A second terminal of the reset transistor TR is electrically connected to the control terminal of the drive transistor TD. The control terminal of the reset transistor TR receives a reset signal SR.

[0043] In this embodiment, the bias transistor TB, the compensation transistor TC, the drive transistor TD, and the reset transistor TR can each be implemented by an N-type transistor. For example, the bias transistor TB, the compensation transistor TC, the drive transistor TD, and the reset transistor TR can each be an N-type thin film transistor or an NMOS transistor.

[0044] Please refer to Figures 6 and 7 simultaneously. Figure 7 is a timing diagram based on Figure 6. The timing in this embodiment is the timing when the power supply transistors T1-1 to T1-n are turned on in a time-sharing manner. The voltage Vd at the first terminal of the driver transistor TD is at the reference high voltage VDD during the previous bias period PB before time t1. During the reset period PR from time t2 to time t3, the reset transistor TR is turned on by the high voltage reset signal SR. The bias signal SB and the select signal SS are at low voltage levels. Therefore, the bias transistor TB, the scan transistor TS, and the compensation transistor TC are turned off. The control terminal of the driver transistor TD receives the reference high voltage VDD. Furthermore, the voltage Vd at the first terminal of the driver transistor TD can be maintained in an operating state. During the reset period PR from time t2 to time t3, the voltage Vg at the control terminal of the driver transistor TD and the voltage Vd at the first terminal of the driver transistor TD are substantially equal to the reference high voltage VDD.

[0045] During scan period PS from time t4 to time t5, bias transistor TB is turned off in response to bias signal SB having a low voltage level. Scan transistor TS and compensation transistor TC are turned on in response to select signal SS having a high voltage level, causing drive transistor TD to operate in a diode connection. Furthermore, data line DL can provide data voltage Vdata to the control terminal of drive transistor TD via scan transistor TS, drive transistor TD, and compensation transistor TC. Therefore, voltage Vg at the control terminal of drive transistor TD can be Vdata + |Vth|. Vth is the threshold voltage of drive transistor TD. Voltage Vd at the first terminal of drive transistor TD is also Vdata + |Vth|. Furthermore, voltage Vs at the second terminal of drive transistor TD is data voltage Vdata.

[0046] During a bias period PB from time t6 to time t7, bias transistor TB is turned on in response to bias signal SB having a high voltage level. Scan transistor TS and compensation transistor TC are turned off in response to select signal SS having a low voltage level. Because bias transistor TB is turned on, voltage Vd at the first terminal of driver transistor TD is the high reference voltage VDD. Voltage Vg at the control terminal of driver transistor TD is maintained at a voltage of Vdata + |Vth|. Voltage Vs at the second terminal of driver transistor TD can be data voltage Vdata. Simultaneously, adjustable element EE is operating in an operating state, and the second terminal of driver transistor TD provides a received drive current to adjustable element EE in response to operating voltage VDD.

[0047] When leakage current occurs in the adjustable element EE, the voltage at node N1 may drop. The voltage Vs at the second terminal of the driver transistor TD may also drop. According to some embodiments, since the voltage Vg at the control terminal of the driver transistor TD may be Vdata+|Vth|, and the voltage Vs at the second terminal of the driver transistor TD is the data voltage Vdata, the driver transistor TD can provide a fixed drive current SC (i.e., one of the compensated first to nth drive currents ID1 to IDn) to the adjustable element EE based on a fixed voltage difference between the control terminal of the driver transistor TD and the second terminal of the driver transistor TD. Furthermore, the voltage Vs at the second terminal of the driver transistor TD can compensate for voltage loss caused by leakage current in the adjustable element EE.

[0048] In summary, the electronic device disclosed herein includes a first power supply circuit and a second power supply circuit electrically connected to an adjustable element. The first power supply circuit can drive the adjustable element during a first time period, and the second power supply circuit can drive the same adjustable element during a second time period. In this manner, the first and second power supply circuits drive the adjustable element in a time-sharing manner. The first and second power supply circuits can alternately rest. This reduces the likelihood of degradation of the first and second power supply circuits during long-term operation, thereby improving the operational stability of the electronic element. According to some embodiments, the electronic device disclosed herein can also compensate for leakage current in the adjustable element.

[0049] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present disclosure.

[0050] 100, 200, 300: Electronic devices 110_1, 210_1, 310_1: first power supply circuit 110_2, 210_2, 310_2: second power supply circuit 110_n, 210_n, 310_n: nth power supply circuit 120, 220, 330: Select circuit 210_3: Third power supply circuit 211_1~211_n, 320: compensation circuit 212_2~212_n: Source follower circuit 80:Substrate 800S: Side 80A: Active area 80B: surrounding areas Cst: Storage capacitor DL: data line EE: Adjustable Element GS: control terminal of scanning transistor ID1: First drive current ID2: Second driving current IDn: nth driving current N1: Node ND1: First Node ND2: Second Node ND3: Third Node NDn: nth node PB: Bias period PR: Reset Period PS: Scan cycle SB: Bias signal SC: driving current SS: Select signal SR: Reset signal t: time t1~t7: time points T1-1~T1-n、TD: power supply transistor T2-1~T2-n: Compensation transistor TB: Bias transistor TC: Compensation transistor TD: driver transistor TR: Reset transistor TS: Scanning Transistor TT1~TTn: time period V: voltage Vdata: data voltage Vd: voltage at the first terminal of the driver transistor VDD: High reference voltage Vg: The voltage at the control terminal of the driver transistor VG1~VGn: control signal Vs: The voltage at the second terminal of the driving transistor VSS: Low reference voltage Vth: threshold voltage

Claims

1. An electronic device comprising: Adjustable components; A first power supply circuit is electrically connected to the adjustable element; The second power supply circuit is electrically connected to the adjustable element; The system includes a selection circuit configured to provide a data voltage based on the voltage value of a selection signal and to provide the data voltage to the first power supply circuit and the second power supply circuit. The first power supply circuit drives the adjustable element in a first time period, and the second power supply circuit drives the adjustable element in a second time period. The first power supply circuit includes a first source follower circuit electrically connected to a first node, the first source follower circuit including a control terminal. In the first time period, the voltage of the first node is provided to the adjustable element following the voltage of the control terminal. The selection circuit is activated during a scan time, the scan time including the first time period and the second time period.

2. The electronic device as claimed in claim 1, further comprising: A compensation circuit that uses data voltage to compensate the first source follower circuit of the first power supply circuit.

3. The electronic device of claim 1, wherein the electronic device includes a substrate, the substrate including an active region and a peripheral region adjacent to the active region, wherein the first power supply circuit and the second power supply circuit are disposed within the active region.

4. The electronic device as claimed in claim 1, wherein the first time period and the second time period do not overlap.

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