Trench type power semiconductor devices with gate protrusion structures and their preparation methods

Abstract

This invention discloses a trench-type power semiconductor device with a gate protrusion structure and its fabrication method. The fabrication method includes: depositing an epitaxial layer on a silicon substrate; sequentially fabricating a silicon dioxide pad layer, a first mask layer, and a second mask layer on the epitaxial layer; etching to form a gate trench; forming a gate oxide layer; depositing gate polysilicon; removing the gate polysilicon from the surface of the first mask layer by chemical mechanical polishing; etching to remove the first mask layer and adjusting the morphology of the gate polysilicon on the silicon plateau region; forming a body region and a source region by ion implantation; and fabricating source region contact holes and tungsten plugs. In this invention, the gate protrusion structure is formed during the fabrication of the trench-type power semiconductor device, which solves the problem of increased channel leakage current after polysilicon etching. Furthermore, by increasing the cross-sectional area of ​​the gate polysilicon, the gate resistance is reduced, improving the switching speed and linearity capability, and optimizing the device performance.

Description

Technical Field

[0001] This work belongs to the field of power device semiconductors, and in particular relates to a trench-type power semiconductor device with a gate protrusion structure and its fabrication method. Prior Technology

[0002] Due to the growing emphasis on environmental protection across society, power devices, with their energy-saving characteristics, are playing an increasingly prominent role in electronic power applications. Market demand drives power device manufacturers to continuously iterate and launch new devices with even lower power consumption. The traditional manufacturing method for trench-type gate power devices is as follows: first, an epitaxial layer is grown on a silicon substrate; then, trenches are formed on the epitaxial layer; subsequently, a gate oxide layer is formed; then, polysilicon gate is formed; next, the body and source regions are fabricated; then, a dielectric layer is formed and contact holes and tungsten plugs are prepared; subsequently, circuit connections are formed; finally, a passivation layer is formed.

[0003] However, the above manufacturing method brings the following problems: 1. Due to the thin gate oxide layer, low turn-on threshold devices cannot use chemical mechanical polishing to planarize the gate polysilicon, and must use dry plasma etching to process the gate polysilicon. To avoid the residue of ridge polysilicon, plasma etching needs to ensure a certain degree of over-etching, which leads to a deep depression at the top of the trench gate polysilicon. This depression exposes the channel sidewalls and increases the impact of subsequent source implantation on channel doping. Reducing the on-resistance requires miniaturizing the channel length, but short channels will make the above effects more severe, increasing channel leakage current and making mass production impossible; 2. The over-etching of the gate polysilicon leading to the depression at the top of the polysilicon increases the gate resistance, affecting the device's turn-on speed and linear current capability. Therefore, the manufacturing method of traditional trench gate power devices needs to be improved. Summary of the Invention

[0004] In view of the shortcomings of the prior art, the technical problem to be solved by this invention is to provide a trench power semiconductor device with a gate protrusion structure and a method for fabricating the same.

[0005] To solve the above-mentioned technical problems, this work provides the following technical solution: A trench-type power semiconductor device with a gate protrusion structure and its fabrication method include the following steps: S1. Deposit an epitaxial layer on a silicon substrate; S2. Sequentially prepare a silicon dioxide pad layer, a first mask layer, and a second mask layer on the epitaxial layer; S3. Etch gate trench patterns on the second mask layer, the first mask layer, and the silicon dioxide pad layer, and etch gate trenches on the epitaxial layer; S4. A gate oxide layer is formed on the trench wall of the gate trench; S5. Deposit gate polysilicon, which fills the gate trench; S6. Remove the gate polysilicon from the surface of the first mask layer by chemical mechanical polishing; S7. The first mask layer is removed by wet etching, and the morphology of the gate polysilicon on the silicon plateau region is adjusted by dry etching; S8. Formation of the body region and source region via ion implantation; S9. Prepare source region contact holes and tungsten plugs; S10. Complete the subsequent fabrication process of the trench power semiconductor device.

[0006] A trench-type power semiconductor device with a gate protrusion structure and its fabrication method are disclosed. The device is fabricated using the trench-type power semiconductor device with a gate protrusion structure and its fabrication method.

[0007] In this invention, a gate protrusion structure is formed during the fabrication of trench-type power semiconductor devices. This avoids the excessive sensitivity of the polysilicon gate etching process window of short-channel devices to channel doping. It solves the problem that the gate etch-back depth after polysilicon etching causes source region implanted ions to affect the channel from the gate sidewall, thereby increasing channel leakage current. This allows power devices with smaller on-resistance to be mass-produced smoothly. Furthermore, by increasing the cross-sectional area of ​​the polysilicon gate, the gate resistance is reduced, the switching speed and linearity capability are improved, and the device performance is optimized. Simple Explanation of the Diagram

[0008] Figure 1 is a flowchart of an embodiment of the fabrication method of a trench-type power semiconductor device with a gate protrusion structure according to the present invention; Figure 2 is a schematic diagram of the structure after a hard mask is formed on the epitaxial layer; Figure 3 is a schematic diagram of the structure after the gate trench pattern is etched on the hard mask; Figure 4 is a schematic diagram of the structure after etching to form the gate trench; Figure 5 is a schematic diagram of the structure after etching to remove the second mask layer; Figure 6 is a schematic diagram of the structure after the growth of the sacrificial oxide layer; Figure 7 is a schematic diagram of the structure after etching to remove the sacrificial oxide layer; Figure 8 is a schematic diagram of the structure after the growth of the gate oxide layer; Figure 9 is a schematic diagram of the structure after the polysilicon gate electrode is deposited; Figure 10 is a schematic diagram of the structure after the gate polysilicon on the surface of the first mask layer is removed by chemical mechanical polishing; Figure 11 is a schematic diagram of the structure after removing the first mask layer; Figure 12 is a schematic diagram of the structure after adjusting the morphology of the gate polysilicon on the silicon plateau region; Figure 13 is a schematic diagram of the structure after the impurity formation region is implanted; Figure 14 is a schematic diagram of the structure after the formation of the source region and the silicon dioxide dielectric layer; Figure 15 is a schematic diagram of the structure after the source region contact hole is formed; Figure 16 is a schematic diagram of the structure after the formation of the ohmic contact region and the initiation of impurities through thermal annealing. Implementation

[0009] Please refer to Figure 1, which is a flowchart of an embodiment of the fabrication method for a trench power semiconductor device with a gate protrusion structure according to this invention. The fabrication method for the trench power semiconductor device with a gate protrusion structure in this embodiment includes the following steps: S1. Deposit one or more epitaxial layers 2 on a silicon substrate 1. The epitaxial layer 2 is generally formed by chemical vapor deposition. The epitaxial layer 2 is doped with trivalent elements (e.g., boron) or pentavalent elements (e.g., arsenic, phosphorus) depending on the device polarity. The thickness of the epitaxial layer 2 is determined according to the operating voltage, or it is an epitaxial layer 2 with a multilayer structure.

[0010] S2. Referring to Figure 2, a silicon dioxide pad layer 3, a first mask layer 4, and a second mask layer 5 are sequentially fabricated on the epitaxial layer 2. It should be noted that Figures 2 to 16 are schematic diagrams of relevant regions within a single cell structure during device fabrication, not complete structural diagrams. The silicon dioxide pad layer 3, the first mask layer 4, and the second mask layer 5 form a hard mask. In this embodiment, the material of the first mask layer 4 is silicon nitride, and the material of the second mask layer 5 is silicon dioxide, thus forming a multilayer composite structure of silicon dioxide-silicon nitride-silicon dioxide insulating masks. Both silicon dioxide and silicon nitride can be prepared using chemical vapor deposition (CVD).

[0011] S3. The gate trench 6 pattern is etched on the hard mask (i.e., the second mask layer 5, the first mask layer 4, and the silicon dioxide pad layer 3), and the gate trench 6 is formed on the epitaxial layer 2. This step may include the following sub-steps: S310. Photoresist is covered on the second mask layer 5, and the pattern of the gate trench 6 is exposed on the photoresist through the mask.

[0012] S320. Referring to Figures 3 and 4, the second mask layer 5, the first mask layer 4, and the silicon dioxide pad layer 3 are dry-etched using a photoresist pattern to form a mask pattern. Then, the gate trench 6 is formed on the epitaxial layer 2 by dry etching using the mask pattern. The gate trench 6 includes cell gate trenches, gate interconnect trenches, and other wafer functional structures.

[0013] S330. Referring to Figure 5, the photoresist and the second mask layer 5 are removed by wet etching, and wet cleaning is performed before the sacrificial oxide layer 7 is grown. Since the silicon dioxide pad layer 3 and the second mask layer 5 in this embodiment are both made of silicon dioxide, a portion of the second mask layer 5 will also be removed during the wet etching process.

[0014] S4. Form a gate oxide layer 8 on the trench wall of the gate trench 6. This step may include the following sub-steps: S410, Referring to Figure 6, a silicon dioxide layer 7 is grown on the trench wall of the gate trench 6 using a thermal oxidation process; the thickness of the sacrificial oxide layer 7 is generally 5nm~50nm. By forming the sacrificial oxide layer 7, the cell trench and gate interconnect trench can be rounded and plasma damage repaired using the thermal oxidation process.

[0015] S420, Please refer to Figure 7, use wet etching to remove the sacrificial oxide layer 7.

[0016] S430. Please refer to Figure 8. A gate oxide layer 8 is grown on the trench wall of the gate trench 6 using a thermal oxidation process. The thickness of the grown gate oxide layer 8 is determined according to the requirements of device performance. The thickness of the gate oxide layer 8 is generally 5nm~50nm.

[0017] S5. Please refer to Figure 9. The gate polysilicon 9 is oxidized by low-pressure chemical vapor deposition. The gate polysilicon 9 needs to fill the gate trench 6. The thickness depends on the actual trench depth.

[0018] S6. Please refer to Figure 10. The gate polysilicon 9 on the surface of the first mask layer 4 is removed by chemical mechanical polishing. Since the stop position of chemical mechanical polishing cannot be set very precisely, in the actual process, after polishing to the surface of the first mask layer 4, a further portion will be polished downwards.

[0019] S7. Referring to Figure 11, the first mask layer 4 is removed by wet etching. At this time, a raised gate polysilicon 9 structure, namely the gate protrusion structure 10, is left on the surface of the gate trench 6. Referring to Figure 12, the morphology of the gate polysilicon 9 on the silicon plateau region is then adjusted by dry etching. This mainly involves removing the gate polysilicon 9 that extends laterally from the gate trench 6 to the silicon plateau region to avoid affecting subsequent ion implantation, and adjusting the gate resistance. Of course, it is not necessary to remove all the gate polysilicon 9 that extends laterally from the gate trench 6 to the silicon plateau region. A small amount of gate polysilicon 9 can remain in the area of ​​the silicon plateau region that does not affect the implantation of the body region 11.

[0020] S8. Form the body region 11 and the source region 12 by ion implantation. This step may include the following sub-steps: S810, Please refer to Figure 13. An impurity region 11 is formed on the upper surface of the epitaxial layer 2 by ion implantation. The impurity is a trivalent or pentavalent element, and the specific type is determined according to the polarity of the device.

[0021] S820: The impurities in the body region 11 are activated by a thermal process. At this time, the exposed gate polysilicon 9 surface will also be oxidized to form silicon dioxide. Therefore, in this S7 step, the remaining small amount of gate polysilicon 9 on the silicon platform region will be oxidized to form silicon dioxide.

[0022] S830. Referring to Figure 14, a source region 12 is formed on the upper surface of the body region 11 by ion implantation of impurities. The ion-implanted impurities can be pentavalent or trivalent elements. The impurities implanted in the source region 12 are opposite to those implanted in the body region 11. That is, when the impurity implanted in the body region 11 is a trivalent element, the impurity implanted in the source region 12 is a pentavalent element; when the impurity implanted in the body region 11 is a pentavalent element, the impurity implanted in the source region 12 is a trivalent element.

[0023] S840, the impurities in the source region 12 are activated by a thermal process to obtain a cellular structure.

[0024] S850, Please refer to Figure 14. A silicon dioxide dielectric layer 13 is formed on the epitaxial layer 2 by chemical vapor deposition.

[0025] S9. Prepare the source region 12 contact hole 14 and tungsten plug. This step may include the following sub-steps: S910. Referring to Figure 15, the source region 12 contact hole 14 pattern is defined using photoresist, and the silicon dioxide dielectric layer 13 and epitaxial layer 2 are formed by dry etching.

[0026] S920. Referring to Figure 16, a high concentration of impurities is doped into the bottom of the contact hole 14 of the source region 12 by ion implantation, forming an ohmic contact region 15 at the bottom of the contact hole 14 of the source region 12. In this step, the polarity of the impurity element implanted by ion implantation should be opposite to the polarity of the element implanted in the source region 12.

[0027] S930, please continue to refer to Figure 16, start impurities through rapid thermal annealing.

[0028] S940. Tungsten metal (not shown in the figure) is deposited in the contact hole 14 of the source region 12 using a tungsten plug process. Before depositing the tungsten metal, a metal and nitride can be deposited as a protective layer for the contact hole 14 using a physical vapor deposition process. Silicon is then formed using rapid thermal degradation; the metal can be one or more of titanium, cobalt, and tantalum.

[0029] S950: Remove the tungsten metal outside the contact hole 14 of the source region 12 by dry etching, and form a tungsten plug in the contact hole 14.

[0030] S10. Complete the subsequent fabrication process of the trench-type power semiconductor device. The subsequent fabrication process generally includes: depositing an aluminum-copper compound on top of the tungsten plug using physical vapor deposition, and forming the circuit using photolithography and dry etching. A passivation layer is deposited and etched away using photolithography; this passivation layer generally includes silicon nitride or silicon dioxide, followed by alloy annealing, etc. The subsequent fabrication processes after the formation of the tungsten plug are all existing technologies and will not be described in detail here. After completing the above subsequent fabrication processes, a trench-type power semiconductor device with a gate protrusion structure 10 is obtained.

[0031] The trench-type power semiconductor device obtained by the method in this embodiment has a gate protrusion structure 10, which avoids the excessive sensitivity of the polysilicon gate etching process window to channel doping in short-channel devices. It also solves the problem that the gate etch-back depth after polysilicon etching causes ions implanted from the source region 12 to affect the channel from the gate sidewall, thereby increasing channel leakage current. This allows for the successful mass production of power devices with lower on-resistance. Furthermore, forming the gate protrusion structure 10 increases the cross-sectional area of ​​the gate polysilicon 9, reduces gate resistance, improves switching speed and linearity, and optimizes device performance.

[0032] This invention also discloses a trench power semiconductor device with a gate protrusion structure, which can be prepared by the trench power semiconductor device preparation method with a gate protrusion structure in any of the preceding embodiments.

[0033] 1: Silicon substrate 2: Epitaxial layer 3: Silicon dioxide padding 4: First mask layer 5: Second mask layer 6: Gate trench 7: Sacrificial oxide layer 8: Gate oxide layer 9: Gate polysilicon 10: Gate protrusion structure 11: Body area 12: Source Region 13: Silicon dioxide dielectric layer 14: Contact Hole 15: Ohmic contact area

Claims

1. A method for fabricating a trench-type power semiconductor device with a gate protrusion structure, wherein, The steps include: S1, depositing an epitaxial layer on a silicon substrate; S2. Sequentially prepare a silicon dioxide pad layer, a first mask layer, and a second mask layer on the epitaxial layer; S3. Etch gate trench patterns on the second mask layer, the first mask layer, and the silicon dioxide pad layer, and etch gate trenches on the epitaxial layer; S4. Form a gate oxide layer on the trench walls; S5. Deposit gate polycrystalline silicon, which fills the gate trenches; S6. Remove the gate polycrystalline silicon from the surface of the first mask layer by chemical mechanical polishing; S7. Remove the first mask layer by wet etching and adjust the gate polycrystalline silicon morphology on the silicon plateau region by dry etching; S8. Form the body region and source region by ion implantation; S9. Prepare the source region contact hole and tungsten plug; S10. Complete the subsequent fabrication process of the trench power semiconductor device.

2. The method for fabricating a trench power semiconductor device with a gate protrusion structure as described in claim 1, wherein, The epitaxial layer is formed by chemical vapor deposition and is doped with trivalent or pentavalent elements.

3. The method for fabricating a trench power semiconductor device with a gate protrusion structure as described in claim 1, wherein, The first mask layer is made of silicon nitride, and the second mask layer is made of silicon dioxide.

4. A method for fabricating a trench-type power semiconductor device with a gate protrusion structure as described in any of claims 1-3, wherein, Step S3 includes the following sub-steps: S310, covering the second mask layer with photoresist, and exposing the gate trench pattern on the photoresist through the mask; S320, using the photoresist pattern to dry etch the second mask layer, the first mask layer, and the silicon dioxide pad layer to form a mask pattern, and using the mask pattern to dry etch the gate trench on the epitaxial layer; S330, removing the photoresist and the second mask layer by wet etching, and performing wet cleaning.

5. The method for fabricating a trench power semiconductor device with a gate protrusion structure as described in claim 4, wherein, The gate trench includes cell gate trenches and gate interconnection trenches.

6. The method for fabricating a trench power semiconductor device with a gate protrusion structure as described in claim 4, wherein, The S4 step includes the following sub-steps: S410, growing a silicon dioxide layer as a sacrificial oxide layer on the wall of the gate trench; S420, removing the sacrificial oxide layer by wet etching; S430, growing a gate oxide layer on the wall of the gate trench by thermal oxidation.

7. The method for fabricating a trench power semiconductor device with a gate protrusion structure as described in claim 6, wherein, The thickness of the sacrificial oxide layer is 5nm~50nm; the thickness of the gate oxide layer is 5nm~50nm.

8. The method for fabricating a trench power semiconductor device with a gate protrusion structure as described in claim 6, wherein, Step S8 includes the following sub-steps: S810, forming a bulk region on the upper surface of the epitaxial layer by ion implantation of impurities; S820, activating the impurities in the bulk region by thermal process; S830, forming a source region on the upper surface of the bulk region by ion implantation of impurities; S840, activating the impurities in the source region by thermal process to obtain a cellular structure; S850, forming a silicon dioxide dielectric layer on the epitaxial layer by chemical vapor deposition.

9. A method for fabricating a trench power semiconductor device with a gate protrusion structure as described in claim 8, wherein: S910. Define the source region contact hole pattern using photoresist, and form the source region contact hole by dry etching the silicon dioxide dielectric layer and the epitaxial layer; S920. Dope the bottom of the source region contact hole with a high concentration of impurities by ion implantation to form an ohmic contact region at the bottom of the source region contact hole; S930. Initiate the impurities by rapid thermal annealing; S940. Deposit metallic tungsten in the source region contact hole using a tungsten plug process; S950. Remove the metallic tungsten outside the source region contact hole by dry etching to form a tungsten plug in the contact hole.

10. A trench-type power semiconductor device with a gate protrusion structure, wherein, The device is prepared using the trench power semiconductor device fabrication method with gate protrusion structure as described in any one of claims 1 to 9.

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