Apparatus and method for stress testing

Abstract

A first voltage source is coupled to a first terminal of the test transistor. A first terminal of a probe circuit is coupled to the first terminal of the test transistor. A second terminal of the probe circuit is coupled to a second terminal of the test transistor. A third terminal of the probe circuit is coupled to a control terminal of the test transistor. A first terminal of a first resistor is coupled to a second terminal of the test transistor. A second terminal of the first resistor is coupled to a second voltage source. A first input terminal of an amplifier is coupled to a third voltage source. A second input terminal of the amplifier is coupled to the first terminal of the first resistor. The output terminal of the amplifier is coupled to the control terminal of the test transistor.

Description

[Technical Field]

[0001] None. [Previous Technology]

[0002] Modern integrated wafers contain millions or billions of semiconductor devices formed on a semiconductor substrate (such as silicon). Silicon-based semiconductor devices (such as transistors and photodiodes) have been the standard in the semiconductor industry for the past four decades. However, semiconductor devices based on alternative materials are receiving increasing attention. For example, semiconductor devices based on III-N semiconductors (such as gallium nitride (GaN)) are widely used in high-power applications, optoelectronic applications, and high-temperature applications. [Summary of the Invention]

[0003] None.

Implementation Method

[0005] The following disclosure provides many different embodiments or instances for implementing different features of the provided object. Specific examples of components and arrangements described below are used to simplify the embodiments of this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of forming a first feature above or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which an additional feature is formed between the first and second features such that the first and second features do not need to be in direct contact. Furthermore, the embodiments of this disclosure may repeat element symbols or letters in various instances. This repetition is for simplicity and clarity and does not in itself specify a relationship between the various embodiments or configurations discussed.

[0006] Furthermore, for ease of description, spatial relative terms such as "below," "under," "below," "above," and "above" may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. In addition to the orientations shown in the figures, the spatial relative terms are intended to cover different orientations of the device in use or operation. The device may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive terms used herein may be interpreted accordingly.

[0007] During the fabrication of integrated wafers, defects may form within the wafer's layers or along its surface. For example, in the fabrication of gallium nitride (GaN) high electron mobility transistors (HEMTs), crystal defects (e.g., vacancies, grain boundaries, edge dislocations, screw dislocations, mixed dislocations, etc.) may appear within the transistor's layers or along its surface. These defects can affect the transistor's performance and reliability. For example, over time, these defects can affect linear drain current degradation, current leakage, on-resistance, threshold voltage, etc. Therefore, many integrated wafers undergo stress testing after fabrication to ensure that the wafer's reliability and performance meet certain requirements before it is considered acceptable.

[0008] Some stress tests involve applying electrical and thermal stress to a test transistor over a set time period and determining how device performance changes due to the stress test. First, the initial performance of the test transistor is measured before stress is applied. Then, the stress test is performed. For example, a high-temperature reverse bias (HTRB) stress test involves heating the test transistor to a high temperature (e.g., greater than 100 degrees Celsius) while simultaneously applying a large voltage (e.g., greater than 100 volts) to the test transistor. The test transistor is switched on (e.g., a voltage is applied to the control terminal of the test transistor) to allow current to flow through it. The high voltage and high temperature are maintained for a period of time to maintain stress on the test transistor. The stress test is ended by removing the high voltage and high temperature from the transistor. Next, the final performance of the test transistor is measured after the stress test. Finally, the difference between the initial and final performance of the test transistor is determined.

[0009] The challenge of this stress test is that as the temperature of the test transistor increases, its on-resistance may increase, thus potentially reducing the current flowing through the transistor during the stress test. Therefore, it may be necessary to increase the duration of the stress test. Increasing the duration of the stress test may increase testing costs and potentially slow down wafer production.

[0010] In various embodiments of this disclosure, the voltage at the transistor control terminal is adjusted throughout the stress test so that the current flowing through the transistor remains substantially constant throughout the stress test (although the on-resistance changes during the stress test). By maintaining a constant current flowing through the test transistor throughout the stress test, the duration of the stress test can be reduced. Therefore, testing costs can be reduced and wafer yield can be increased.

[0011] Figure 1 illustrates a circuit diagram 100 of some embodiments of an apparatus for stress testing a test transistor 102. Figure 2 illustrates a schematic diagram of some embodiments of the performance of the apparatus of Figure 1.

[0012] Referring to Figure 1, the device includes a first voltage source 104, a second voltage source 106, a third voltage source 108, a probe circuit 110, a first resistor 112, an amplifier 114, a heater 118, and a heater power supply 120. In some embodiments, the second voltage source 106 is ground 122 or coupled to ground 122.

[0013] The test transistor 102 has a first terminal 102a, a second terminal 102b, and a control terminal 102c. The first voltage source 104 has an output terminal 104a coupled to the first terminal 102a of the test transistor 102. The first resistor 112 has a first terminal 112a coupled to the second terminal 102b of the test transistor 102. The second voltage source 106 has an output terminal 106a coupled to the second terminal 112b of the first resistor 112. The amplifier 114 has a first input terminal 114a (e.g., a reference terminal), a second input terminal 114b (e.g., a feedback terminal), and an output terminal 114c. The third voltage source 108 has an output terminal 108a coupled to the first input terminal 114a of the amplifier 114. The second input terminal 114b of the amplifier 114 is coupled to the first terminal 112a of the first resistor 112 (and the second terminal 102b of the test transistor 102). The probe circuit 110 has a first terminal 110a coupled to a first terminal 102a of the test transistor 102, a second terminal 110b coupled to a second terminal 102b of the test transistor 102, and a third terminal 110c coupled to a control terminal 102c of the test transistor 102. In some embodiments, the probe circuit 110 has a fourth terminal (not shown) coupled to a block or body terminal (not shown) of the test transistor 102. A heater 118 is located near the test transistor 102. The heater 118 is coupled to a heater power supply 120.

[0014] To perform stress testing (e.g., HTRB testing) on ​​the test transistor 102 under thermal and electrical stress, a heater 118 heats the test transistor 102. A first voltage source 104 provides a stress voltage Vstress to the first terminal 102a of the test transistor 102, a second voltage source 106 provides a reference voltage Vref to the second terminal 112b of the first resistor 112, and a third voltage source 108 provides a control voltage Vctrl to the first input terminal 114a of the amplifier 114. The amplifier 114 receives a feedback voltage Vfb (e.g., the voltage across the first resistor 112) at the second input terminal 114b. Amplifier 114 increases the amplifier voltage Vamp by an order of magnitude, causing test transistor 102 to conduct and transfer the stress current Istress from the first terminal 102a to the second terminal 102b. Amplifier 114 also adjusts the amplifier voltage Vamp by an order of magnitude such that the feedback voltage Vfb (at the second input terminal 114b) is approximately equal to the control voltage Vctrl (at the first input terminal 114a), as shown in Figure 2. For example, adjusting the amplifier voltage Vamp by amplifier 114 increases the current through test transistor 102 and the first resistor 112, thereby increasing the voltage across the first resistor 112 (feedback voltage Vfb), at least until the voltage across the first resistor 112 (feedback voltage Vfb) equals the control voltage Vctrl, as shown in Figure 2.

[0015] In some cases, when subjected to thermal and electrical stress, the characteristics of the test transistor 102 may change with increasing temperature TEMP (e.g., the on-resistance Ron of the test transistor 102 increases), as shown in Figure 2. However, since the control voltage Vctrl from the third voltage source 108 to the first input terminal 114a is constant, and since the amplifier 114 adjusts the amplifier voltage Vamp to make the feedback voltage Vfb at the second input terminal 114b equal to the control voltage Vctrl at the first input terminal 114a, the feedback voltage Vfb at the second input terminal 114b (e.g., the voltage across the first resistor 112) is approximately constant, as shown in Figure 2. Therefore, the current through the first resistor 112 is approximately constant, and thus the stress current Istress through the test transistor 102 is approximately constant, even though the characteristics of the test transistor 102 may change under stress (e.g., the on-resistance increases), as shown in Figure 2.

[0016] Since the current through the test transistor 102 remains substantially constant throughout the stress test, the duration of the stress test (Ttest) can be reduced (e.g., from approximately 500 hours to approximately 10 minutes). For example, by maintaining a constant current throughout the stress test, charge carrier injection into defects within the test transistor 102 (e.g., hot carrier injection) can be induced more quickly, and the performance degradation of the test transistor 102 (e.g., on-resistance, linear drain current, threshold voltage, leakage, etc.) can be induced more quickly. Therefore, the reliability and performance of the device can be tested in a shorter time. By reducing the duration of the stress test, testing costs can be reduced and wafer yield can be increased.

[0017] Figure 3 illustrates a flowchart 300 of some embodiments of a method for stress testing a test transistor 102. Although the method in Figure 3 is described below as a series of actions or events, it should be understood that the order of these actions or events should not be construed as limiting. For example, some actions may occur in a different order and / or simultaneously with other actions or events other than those described and / or illustrated herein. Furthermore, not all illustrated actions require the implementation of one or more of the states or embodiments described herein. In addition, one or more actions described herein may be performed in one or more separate actions and / or stages.

[0018] In block 302, the initial performance of the test transistor is measured. For example, a normal operating voltage is applied to the first terminal 102a and the control terminal 102c of the test transistor 102, while the test transistor 102 is maintained at room temperature, and the performance of the test transistor is measured by probe circuit 110 (e.g., linear drain current, on-resistance, gate-source leakage, drain-source leakage, gate-body leakage, etc.). For example, the probe circuit measures the voltage at the first terminal 102a, the second terminal 102b, and the control terminal 102c of the test transistor 102, and measures the current through the test transistor 102 (e.g., from terminal 102a to terminal 102b, from terminal 102c to terminal 102b, from terminal 102c to terminal 102a, from terminal 102c to body, etc.).

[0019] In block 304, a stress voltage is applied to the first terminal of the test transistor, and an amplifier voltage is applied to the control terminal of the test transistor to cause a stress current to flow through the test transistor. For example, a first voltage source 104 provides a stress voltage Vstress (e.g., a range of 300 to 800 volts, 400 to 700 volts, or other suitable range) to the first terminal 102a of the test transistor 102 during a first time period Ttest. This stress voltage Vstress is much higher than the normal operating voltage. In addition, a third voltage source 108 provides a control voltage Vctrl (e.g., a range of 0.1 to 20 volts, 1 to 15 volts, 5 to 10 volts, or other suitable range) to the first input terminal 114a of the amplifier 114 during the first time period Ttest. Furthermore, amplifier 114 provides amplifier voltage Vamp to control terminal 102c of test transistor 102 during the first time period Ttest. Therefore, stress current Istress flows between the first terminal 102a and the second terminal 102b of test transistor 102 during the first time period Ttest.

[0020] In block 306, the temperature of the test transistor is increased and maintained at the increased temperature. For example, heater 118 heats the test transistor 102 from a first temperature (e.g., room temperature) to a test temperature (e.g., a range of 100 to 175 degrees Celsius, a range of 100 to 150 degrees Celsius, a range of 125 to 150 degrees Celsius, or other suitable range), and Ttest maintains the test transistor 102 at the test temperature for a first time period.

[0021] In block 308, the amplifier voltage at the control terminal of the test transistor is adjusted to maintain the stress current through the test transistor. For example, in some cases, increasing the temperature TEMP of the test transistor 102 will increase the on-resistance Ron of the test transistor 102. Furthermore, amplifier 114 increases the amplifier voltage Vamp supplied to the control terminal 102c of the test transistor 102 in response to the increase in the on-resistance Ron of the test transistor 102, to maintain the current level of the stress current Istress through the test transistor 102, regardless of whether the on-resistance Ron increases.

[0022] In block 310, the final performance of the test transistor is measured. For example, after the electrical and thermal stresses are removed from the test transistor 102, a normal operating voltage is applied to the first terminal 102a and the control terminal 102c of the test transistor 102, while the test transistor 102 is maintained at room temperature, and the performance of the test transistor is measured by probe circuit 110 (e.g., linear drain current, on-resistance, gate-source leakage, drain-source leakage, gate-body leakage, etc.). For example, the probe circuit measures the voltage at the first terminal 102a, the second terminal 102b, and the control terminal 102c of the test transistor 102, and measures the current through the test transistor 102 (e.g., from terminal 102a to terminal 102b, from terminal 102c to terminal 102b, from terminal 102c to terminal 102a, from terminal 102c to body, etc.).

[0023] In block 312, the difference between the initial and final performance of the test transistor is determined. For example, the difference between the initial linear drain current and the final linear drain current of the test transistor 102 is determined to determine linear drain current degradation caused by stress testing. Furthermore, the difference between the initial and final on-resistance, the difference between the initial and final leakage, and the difference between the initial and final threshold voltage are determined, etc. In some embodiments, the performance of the test transistor 102 is measured and monitored during stress testing, in addition to the initial and final measurements.

[0024] Figure 4 illustrates a circuit diagram 400 of some embodiments of the device in Figure 1, wherein the probe circuit 110, the first resistor 112 and the amplifier 114 are integrated on the integrated chip 402.

[0025] The first terminal 110a of the probe circuit 110 is coupled to the first terminal 402a of the integrated chip 402. The first terminal 402a is coupled to the output terminal 104a of the first voltage source 104 and the first terminal 102a of the test transistor 102. The second terminal 110b of the probe circuit 110, the first terminal 112a of the first resistor 112, and the second input terminal 114b of the amplifier 114 are coupled to the second terminal 402b of the integrated chip 402. The second terminal 402b is coupled to the second terminal 102b of the test transistor 102. The third terminal 110c of the probe circuit 110 and the output terminal 114c of the amplifier 114 are coupled to the third terminal 402c of the integrated chip 402. The third terminal 402c is coupled to the control terminal 102c of the test transistor 102. The second terminal 112b of the first resistor 112 is coupled to the fourth terminal 402d of the integrated chip 402. The fourth terminal 402d is coupled to the output terminal 106a of the second voltage source 106 (e.g., ground 122). The first input terminal 114a of the amplifier 114 is coupled to the fifth terminal 402e of the integrated chip. The fifth terminal 402e is coupled to the output terminal 108a of the third voltage source 108.

[0026] In some embodiments, the apparatus further includes a control circuit 406. The control circuit 406 is coupled to a first voltage source 104 and a third voltage source 108, and controls the voltage levels output by the first voltage source 104 and the third voltage source 108. For example, a first terminal 406a of the control circuit 406 is coupled to a control terminal 104b of the first voltage source 104. The stress voltage Vstress provided by the first voltage source 104 to the first terminal 102a of the test transistor 102 can be adjusted by the control circuit 406 to tune the electrical stress between the first terminal 102a and the second terminal 102b of the test transistor 102. For example, in some embodiments, the control circuit 406 controls the first voltage source 104 to provide a 500-volt voltage to the first terminal 102a of the test transistor 102. In other embodiments, the control circuit 406 controls the first voltage source 104 to provide a 520-volt voltage to the first terminal 102a of the test transistor 102. In other embodiments, control circuit 406 controls a first voltage source to provide a 650-volt voltage or other suitable voltage to the first terminal 102a of test transistor 102.

[0027] Furthermore, the second terminal 406b of the control circuit 406 is coupled to the control terminal 108b of the third voltage source 108. The control voltage Vctrl provided by the third voltage source 108 to the first input terminal 114a of the amplifier 114 can be adjusted by the control circuit 406 to tune the stress current Istress through the test transistor 102 (thereby tuning the stress test duration). For example, in some embodiments, the control circuit 406 controls the third voltage source 108 to provide a 5-volt voltage to the first input terminal 114a of the amplifier 114. In some such embodiments, the resistance of the first resistor is 1000 ohms, so the stress current through the test transistor 102 is about 5 mA. In some such embodiments, the stress time (e.g., the amount of time the stress current passes through the test transistor 102 when the test transistor 102 is at the test temperature) is 10 minutes.

[0028] In other embodiments, control circuitry 406 controls a third voltage source 108 to provide a 7.5-volt voltage to the first input terminal 114a of amplifier 114. In some such embodiments, the resistance of the first resistor is 1000 ohms, so the stress current through the test transistor 102 is approximately 7.5 mA. In some such embodiments, the stress time is 7.5 minutes.

[0029] In other embodiments, control circuitry 406 controls a third voltage source 108 to supply 10 volts or other suitable voltage to the first input terminal 114a of amplifier 114. In some such embodiments, the resistance of the first resistor is 1000 ohms, so the stress current through the test transistor 102 is approximately 10 mA. In some such embodiments, the stress time is 5 minutes.

[0030] In some embodiments, control circuitry 406 is coupled to heater 118 (e.g., a third terminal 406c of control circuitry 406 is coupled to control terminal 118a of heater 118) and controls heater 118 to maintain the temperature of test transistor 102. Control circuitry 406 can adjust the temperature of test transistor 102 to tune the thermal stress applied to test transistor 102. For example, in some embodiments, control circuitry 406 controls heater 118 to heat test transistor 102 to 100 degrees Celsius. In other embodiments, control circuitry 406 controls heater 118 to heat test transistor 102 to 125 degrees Celsius. In other embodiments, control circuitry 406 controls heater 118 to heat test transistor 102 to 150 degrees Celsius or other suitable temperature.

[0031] In some systems, stress testing is accelerated (and the duration of stress testing is reduced) by increasing the thermal stress on the test transistor 102 (e.g., increasing the temperature of the test transistor 102). However, increasing the thermal stress may increase the power consumption of the test. By using a constant current to accelerate the stress test (rather than increasing the temperature during the test) as described in various embodiments of this disclosure, the temperature of the test transistor can be reduced. Therefore, the power consumption of the stress test can be reduced.

[0032] In some embodiments, the apparatus further includes a computing circuit 408 coupled to the probe circuit 110. For example, the probe circuit 110 has an output terminal 110d, which is coupled to an input terminal 408a of the computing circuit 408 via a sixth terminal 402f of the integrated wafer 402. The computing circuit 408 receives measurements (e.g., current measurements, voltage measurements, etc.) performed by the probe circuit and calculates the performance of the test transistor 102 (e.g., on-resistance, leakage, threshold voltage, linear drain current, etc.) based on the measurements from the probe circuit 110. Furthermore, the computing circuit 408 determines the difference between measurements performed before and after the stress test. Therefore, the computing circuit 408 can determine the performance and reliability degradation of the test transistor 102.

[0033] In some embodiments, the first resistor 112 is a variable resistor with a control terminal 112c. The control terminal 112c is coupled to a terminal 406d of the control circuit 406 via a terminal 402g of the integrated wafer 402. The resistance of the first resistor 112 can be adjusted to further tune the stress current Istress through the test transistor (and thus further tune the stress time). For example, in some embodiments, the control circuit 406 controls the first resistor 112 to have a resistance of 500 ohms. In some such embodiments, the voltage at the first input terminal 114a of the amplifier 114 is 5 volts, so the stress current through the test transistor 102 is about 10 mA. In some such embodiments, the stress time is 5 minutes.

[0034] In other embodiments, the control circuit 406 controls the first resistor 112 to have a resistance of 1000 ohms. In some such embodiments, the voltage at the first input terminal 114a of the amplifier 114 is 5 volts, so the stress current through the test transistor 102 is about 5 mA. In some such embodiments, the stress time is 10 minutes.

[0035] In other embodiments, the control circuit 406 controls the first resistor 112 to have a resistance of 2000 ohms. In some such embodiments, the voltage at the first input terminal 114a of the amplifier 114 is 5 volts, so the stress current through the test transistor 102 is approximately 2.5 mA. In some such embodiments, the stress time is 20 minutes.

[0036] Figure 5 is a cross-sectional view 500 illustrating some embodiments of the apparatus in Figure 4.

[0037] In some embodiments, test transistor 102 is located on test wafer 502. Other transistors 506 and 508 are located on test wafer 502 and spaced apart from test transistor 102. In some embodiments, integrated wafer 402 is referred to as probe card wafer and is disposed on probe card 518. Test wafer 502 is disposed on wafer holder 504 within test chamber 520. Heater 118 is located in test chamber 520 and heats test chamber 520. In some embodiments, probe card 518 including integrated wafer 402 is located in test chamber 520.

[0038] In some embodiments, a first probe 510 extends from a probe card 518 to a test transistor 102 and electrically couples an end 402a of an integrated wafer 402 to a first end 102a of the test transistor 102. For example, the first probe 510 extends from a first connection (not shown) on the probe card 518 (coupled to an end 402a of the integrated wafer 402) to a first conductive pad 526 on the test wafer 502 (coupled to the first end 102a of the test transistor 102). A second probe 512 extends from the probe card 518 to the test transistor 102 and electrically couples an end 402b of the integrated wafer 402 to a second end 102b of the test transistor 102. For example, the second probe 512 extends from a second connection (not shown) on the probe card 518 (coupled to an end 402b of the integrated wafer 402) to a second conductive pad 528 on the test wafer 502 (coupled to the second end 102b of the test transistor 102). The third probe 514 extends from the probe card 518 to the test transistor 102 and electrically couples end 402c of the integrated wafer 402 to the control terminal 102c of the test transistor. For example, the third probe 514 extends from a third connection (not shown) on the probe card 518 (coupled to end 402c of the integrated wafer 402) to a third conductive pad 530 on the test wafer 502 (coupled to the control terminal 102c of the test transistor 102).

[0039] In some embodiments, a first voltage source 104, a second voltage source 106, a third voltage source 108, a heater power supply 120, a control circuit 406, and a computing circuit 408 are disposed within a test apparatus 516. The test apparatus 516 is coupled to a probe card 518 via an external wiring 522. For example, the external wiring 522 couples a first terminal 402a of an integrated chip 402 to the first voltage source 104, a fourth terminal 402d of an integrated chip 402 to a second voltage source 106 (e.g., ground 122), a fifth terminal 402e of an integrated chip 402 to the third voltage source 108, and a sixth terminal 402f of an integrated chip 402 to the computing circuit 408. The test apparatus 516 is coupled to a heater 118 via an external wiring 524. For example, external wiring 524 couples heater power supply 120 to heater 118 and couples terminal 406c of control circuit 406 to terminal 118a of heater 118.

[0040] By integrating the first resistor 112 and amplifier 114 into the probe card 518, stress testing of the test transistor 102 can be performed on the test wafer 502. Therefore, parasitic resistance, parasitic inductance, and parasitic capacitance caused by packaging the test transistor 102 can be avoided during testing. Consequently, the test results have higher precision and accuracy. Furthermore, stress testing of the test transistor 102 on the test wafer 502 can increase the speed of the wafer manufacturing process, thereby increasing wafer yield. In addition, the number of sacrificial wafers can be reduced, further increasing wafer yield.

[0041] In some embodiments, the first resistor 112 and amplifier 114 are integrated into the test wafer 502. For example, the first resistor 112 and amplifier 114 are formed on the test wafer 502 and coupled to the test transistor 102 via on-wafer interconnects.

[0042] In some embodiments, the test wafer 502 is diced, the test transistor 102 is packaged, the test transistor package is disposed on an evaluation board, and stress testing is performed on the packaged test transistor 102 on the evaluation board. In some embodiments, the package-level test is performed in addition to wafer-level testing. In some embodiments, the package-level test is an alternative to wafer-level testing.

[0043] Figure 6 illustrates a flowchart 600 of some embodiments of the process flow for fabricating test transistors.

[0044] In block 602, a wafer is manufactured. For example, a plurality of transistors are formed on the wafer.

[0045] In block 604, the wafer is probed to test the transistors on the wafer to ensure that the transistors are functioning properly. Additionally, stress testing is performed on the transistors on the wafer. In some embodiments, the probe and wafer-level stress testing take approximately one week. For example, in some embodiments, the probe takes approximately one week, and the stress test takes approximately 10 minutes.

[0046] In block 606, the wafer is diced and the die is packaged. In some embodiments, dicing and packaging take approximately 3 weeks.

[0047] Figure 6 further illustrates a flowchart 650 of another embodiment of the process flow for testing transistors.

[0048] In block 652, wafers are manufactured.

[0049] In block 654, the wafer is probed to test the transistors on the wafer to ensure that the transistors are working properly.

[0050] In block 656, the wafer is cut and the die is packaged.

[0051] In block 658, stress testing is performed on the transistor. For example, stress testing is performed on a package including the transistor on an evaluation board. In some embodiments, the package-level stress test takes approximately 10 minutes.

[0052] Figure 7 illustrates a circuit diagram 700 of some embodiments of the apparatus of Figure 4, wherein a first function generator circuit 702 is coupled between a third voltage source 108 and an amplifier 114.

[0053] The first function generator circuit 702 has a first input terminal 702a coupled to the output terminal 108a of the third voltage source 108, a second input terminal 702b coupled to the terminal 406e of the control circuit 406, and an output terminal 702c coupled to the first input terminal 114a of the amplifier 114 (via the terminal 402e of the integrated chip 402).

[0054] The first function generator circuit 702 receives a control voltage from the third voltage source 108 and an input signal from the control circuit 406, and outputs a control signal to the first input terminal 114a of the amplifier 114 based on the voltage from the third voltage source 108 and the input signal from the control circuit 406. In some embodiments, the control signal is a square wave, the maximum voltage of which is set by the third voltage source 108, and the frequency and duty cycle are set by the control circuit 406. For example, in some embodiments, the control signal is a square wave signal with a peak voltage of 1 to 15 volts or other suitable voltage, a frequency of 1000 Hz to 100 million Hz or other suitable frequency, and a duty cycle of 1% to 50% or other suitable duty cycle. In other embodiments, the control signal is a step signal that steps from a first voltage to a second voltage, a third voltage, and so on. In other embodiments, the control signal is a ramp signal or other suitable signal.

[0055] In some embodiments, the apparatus further includes a second function generator circuit 704. The second function generator circuit 704 has a first input terminal 704a coupled to the output terminal 104a of the first voltage source 104, a second input terminal 704b coupled to the terminal 406f of the control circuit 406, and an output terminal 704c coupled to the first terminal 102a of the test transistor 102.

[0056] The second function generator circuit 704 receives a voltage from the first voltage source 104 and an input signal from the control circuit 406, and outputs a stress signal to the first terminal 102a of the test transistor 102 based on the voltage from the first voltage source 104 and the input signal from the control circuit 406. In some embodiments, the stress signal is a square wave, the maximum voltage of which is set by the first voltage source 104, and the frequency and operating period are set by the control circuit 406. In other embodiments, the stress signal is a step signal. For example, in some embodiments, the stress signal steps from 0 volts to 400 volts in 25-volt steps. In other embodiments, the stress signal steps from 0 volts to 600 volts or other suitable voltages in 50-volt steps or other suitable steps. In some embodiments, the stress signal is a square wave signal with a peak voltage of 400 to 600 volts or other suitable voltage, a frequency of 1000 Hz to 100 million Hz or other suitable frequency, and a duty cycle of 1% to 50% or other suitable duty cycles. In some embodiments, the stress signal is a ramp signal or other suitable signal.

[0057] In some embodiments, in addition to or alternatively to the HTRB stress test, the test transistor 102 is subjected to a high temperature operation life (HTOL) test, wherein the temperature of the test transistor 102 is raised to a test temperature in the range of 125 degrees Celsius to 175 degrees Celsius or other suitable temperature, the frequency of the control signal is 1000 Hz to 100 million Hz or other suitable frequency, the duty cycle of the control signal is 1% to 50% of the duty cycle, the stress output of the stress voltage at the first voltage source 104 is 40 volts to 1200 volts, and leakage of the test transistor 102 is measured. For example, leakage is measured before and after the application of HTOL stress, and the difference between the initial leakage and the final leakage is determined.

[0058] In some embodiments, in addition to or alternatively to HTRB stress testing and / or HTOL testing, the test transistor 102 is subjected to a high temperature current collapse (HTCC) test, wherein the temperature of the test transistor is raised to a test temperature or other suitable temperature in the range of 125 degrees Celsius to 175 degrees Celsius, the control signal is a pulse signal with a pulse duration of 1 microsecond to 1 second or other suitable pulse duration, the control signal is periodic with a period range of 1 millisecond to 1 second or other suitable time period, and the on-resistance of the test transistor 102 is measured before and after the HTCC test.

[0059] In some embodiments, in addition to stress testing, HTOL testing and / or HTCC testing, or alternatively, the test transistor is subjected to room temperature current collapse (RTCC) testing, wherein the temperature of the test transistor 102 is set to room temperature (e.g., 25 degrees Celsius), the control signal is a pulse signal with a pulse duration of 1 microsecond to 1 second or other suitable pulse duration, the control signal is periodic with a period range of 1 millisecond to 1 second or other suitable time period, and the on-resistance of the test transistor 102 is measured before and after the RTCC test.

[0060] Figure 8 illustrates a circuit diagram 800 of some embodiments of the device of Figure 7, wherein the device further includes a second resistor 802, a third resistor 804 and a fourth resistor 806.

[0061] The second resistor 802 has a first terminal 802a, coupled to the second terminal 102b of the test transistor 102 via terminal 402b of the integrated chip 402. The second resistor 802 has a second terminal 802b, coupled to the first terminal 112a of the first resistor 112 and the second input terminal 114b of the amplifier 114. The third resistor 804 has a first terminal 804a, coupled to the output terminal 702c of the first function generator circuit 702 and / or the output terminal 108a of the third voltage source 108 via terminal 402e of the integrated chip 402. The third resistor 804 has a second terminal 804b, coupled to the first input terminal 114a of the amplifier 114. The fourth resistor 806 has a first terminal 806a, coupled to the second terminal 804b of the third resistor 804 and the first input terminal 114a of the amplifier 114. The fourth resistor 806 has a second terminal 806b, which is coupled to a second voltage source 106 (e.g., ground 122) via a terminal 402d of the integrated wafer 402. In some embodiments, resistors 112, 802, 804, 806 and amplifier 114 are integrated into a test wafer (e.g., 502 in Figure 5) and coupled via on-wafer interconnects.

[0062] The first resistor 112 and the second resistor 802 form a first voltage divider, which provides a portion of the voltage at the second terminal 102b of the test transistor 102 to the second input terminal 114b of the amplifier 114. The third resistor 804 and the fourth resistor 806 form a second voltage divider, which provides a portion of the voltage from the third voltage source 108 to the first input terminal 114a of the amplifier 114.

[0063] The second resistor 802 and the third resistor 804 have a first temperature coefficient. The first resistor 112 and the fourth resistor 806 have a second temperature coefficient, which is smaller in magnitude than the first temperature coefficient. The second temperature coefficient is of a relatively low magnitude, causing the resistance of the first resistor 112 and the resistance of the fourth resistor 806 to remain essentially stable within a certain temperature range. The first temperature coefficient is of a relatively high magnitude, causing the resistance of the second resistor 802 and the resistance of the third resistor 804 to change with temperature. For example, when the temperature of resistors 112, 802, 804, and 806 increases from the first temperature to the second temperature during a stress test, the resistance of the first resistor 112 and the resistance of the fourth resistor 806 remain approximately unchanged, while the resistance of the second resistor 802 and the resistance of the third resistor 804 changes from the first resistance to the second resistance.

[0064] Since the changes in resistance of the second resistor 802 and the third resistor 804 are approximately the same, the amplifier voltage Vamp output at the output terminal 114c of the amplifier 114 remains approximately constant. Therefore, the effect of temperature on the output of the amplifier 114 can be reduced, thereby making the performance of the entire device less dependent on temperature.

[0065] In some embodiments, the first resistor 112 and the fourth resistor 806 are silicon chromium (SiCr) thin film resistors (TFR), while the second resistor 802 and the third resistor 804 are gallium nitride (GaN) two-dimensional electron gas (2DEG) resistors.

[0066] Figure 9 illustrates a cross-sectional view 900 of some embodiments of the test transistor 102.

[0067] In some embodiments, the test transistor 102 is a gallium nitride (GaN) high electron mobility transistor (HEMT). The test transistor 102 is formed along the semiconductor substrate 902. A nucleation layer 904 is located above the semiconductor substrate 902. A buffer layer 906 is located above the nucleation layer 904. A superlattice layer 908 is located above the buffer layer 906. A channel layer 910 is located above the superlattice layer 908. A barrier layer 912 is located above the channel layer 910. In some embodiments, a two-dimensional electrode gas layer 930 is located within the channel layer 910, along the interface between the channel layer 910 and the barrier layer 912.

[0068] The first source / drain structure 914 and the second source / drain structure 916 are laterally spaced above the barrier layer 912. A gate structure 918 is located above the barrier layer 912 and between the source / drain structures 914 and 916. In some embodiments, a capping layer 920 is located between the gate structure 918 and the barrier layer 912. The source / drain structure may refer individually or collectively to either the source or the drain, depending on the context.

[0069] Dielectric structure 922 is located above source / drain structures 914, 916 and gate structure 918. In some embodiments, field plate 924 extends from above the first source / drain structure 914 to above the gate structure 918. Interconnect 926 extends from field plate 924 to the first source / drain structure 914.

[0070] In some embodiments, during the fabrication of the test transistor 102, defects 928 (e.g., crystal defects such as vacancies, grain boundaries, edge dislocations, screw dislocations, mixed dislocations, grooves, pits, etc.) are formed along the buffer layer 906. Furthermore, in some embodiments, during the fabrication of the test transistor 102, defects 932 are formed along the surface of the barrier layer 912.

[0071] In some embodiments, the semiconductor substrate 902 comprises silicon or other suitable materials. In some embodiments, the nucleation layer 904 comprises aluminum nitride or other suitable materials. In some embodiments, the buffer layer 906 comprises aluminum gallium nitride or other suitable materials with graded aluminum and gallium concentrations. In some embodiments, the superlattice layer 908 comprises gallium nitride or other suitable materials. In some embodiments, the channel layer 910 comprises gallium nitride or other suitable materials. In some embodiments, the barrier layer 912 comprises aluminum gallium nitride or other suitable materials. In some embodiments, the capping layer 920 comprises gallium nitride or other materials. In some embodiments, the source / drain structures 914, 916, the gate structure 918, the field plate 924, and / or the interconnect 926 comprise copper, tungsten, titanium, aluminum, nickel, gold, or other suitable materials. In some embodiments, the dielectric structure 922 comprises silicon dioxide, silicon nitride, or other suitable materials.

[0072] Therefore, in some embodiments, this disclosure relates to an apparatus including a first voltage source, a second voltage source, and a third voltage source, a probe circuit, a first resistor, and an amplifier. The first voltage source is coupled to a first terminal of a test transistor. The probe circuit has a first terminal, a second terminal, and a third terminal. The first terminal of the probe circuit is coupled to the first terminal of the test transistor. The second terminal of the probe circuit is coupled to the second terminal of the test transistor. The third terminal of the probe circuit is coupled to a control terminal of the test transistor. The first resistor has a first terminal and a second terminal. The first terminal of the first resistor is coupled to the second terminal of the test transistor. The second terminal of the first resistor is coupled to the second voltage source. The amplifier has a first input terminal, a second input terminal, and an output terminal. The first input terminal is coupled to the third voltage source. The second input terminal is coupled to the first terminal of the first resistor. The output terminal is coupled to the control terminal of the test transistor. In some embodiments, the first resistor has a control terminal, and the apparatus further includes a control circuit having a first output terminal coupled to the control terminal of the first resistor. In some embodiments, the first voltage source has a control terminal coupled to the second output terminal of the control circuit; and the third voltage source has a control terminal coupled to the third output terminal of the control circuit. In some embodiments, the device includes a first signal generator circuit coupled between a third voltage source and a first input terminal of an amplifier. In some embodiments, the device includes a second signal generator circuit coupled between a first voltage source and a first terminal of a test transistor. In some embodiments, the device includes a voltage divider circuit coupled between a third voltage source and a first input terminal of an amplifier, wherein the voltage divider circuit has a first terminal coupled to the third voltage source, a second terminal coupled to the first input terminal of the amplifier, and a third terminal coupled to a second voltage source. In some embodiments, the device includes a second resistor having a first terminal and a second terminal; the first terminal of the second resistor is coupled to the second terminal of the test transistor; and the second terminal of the second resistor is coupled to the second input terminal of the amplifier and the first terminal of the first resistor. In some embodiments, the voltage divider circuit includes a third resistor and a fourth resistor; the first terminal of the third resistor is coupled to the third voltage source; the second terminals of the third resistor and the first terminals of the fourth resistor are coupled to the first input terminal of the amplifier; and the second terminal of the fourth resistor is coupled to the second voltage source. In some embodiments, the first resistor and the third resistor have a first temperature coefficient, and the second resistor and the fourth resistor have a second temperature coefficient, which is different from the first temperature coefficient. In some embodiments, the first resistor and the third resistor have a first resistance, and the second resistor and the fourth resistor have a second resistance, which is different from the first resistor.In some embodiments, a first resistor and an amplifier are located on an integrated wafer, and a test transistor is located on a test wafer separate from the integrated wafer. The apparatus includes: a first wafer probe extending from the integrated wafer to the test wafer and coupling a first voltage source and a first terminal of a probe circuit to a first terminal of the test transistor; a second wafer probe extending from the integrated wafer to the test wafer and coupling a first terminal of the first resistor, a second input terminal of the amplifier, and a second terminal of the probe circuit to a second terminal of the test transistor; and a third wafer probe extending from the integrated wafer to the test wafer and coupling an output terminal of the amplifier and a third terminal of the probe circuit to a control terminal of the test transistor. In some embodiments, the apparatus includes: a test chamber in which the integrated wafer and the test wafer are disposed; and a heater located in the test chamber. In some embodiments, the first resistor, the amplifier, and the test transistor are located on the integrated wafer.

[0073] In other embodiments, this disclosure relates to an apparatus including a first voltage source, a second voltage source, a third voltage source, a probe circuit, a first resistor, and an amplifier. The first voltage source is coupled to a first terminal of a test transistor and is used to provide a stress voltage to the first terminal of the test transistor. The probe circuit is coupled to the first terminal of the test transistor, a second terminal of the test transistor, and a control terminal of the test transistor. The probe circuit is used to measure the voltage across the test transistor and the current flowing through the test transistor. The first resistor is coupled between the second terminal of the test transistor and the second voltage source. The amplifier is coupled to the test transistor and the first resistor. The amplifier is used to receive a control voltage from the third voltage source and, based on the voltage across the first resistor and the control voltage, provide an amplifier voltage to the control terminal of the test transistor to allow a current with a test current level to flow through the test transistor. The amplifier is used to adjust the amplifier voltage to maintain the test current level flowing through the test transistor. In some embodiments, the device includes a signal generator for generating a control signal based on a control voltage, frequency, and duty cycle, and for providing the control signal to an amplifier; the amplifier is used to provide an amplifier voltage to a control terminal of a test transistor based on the control signal. In some embodiments, the device includes a control circuit for adjusting the resistance of a first resistor, adjusting the control voltage, and adjusting the stress voltage. In some embodiments, the device includes a first voltage divider circuit coupled to a third voltage source and an amplifier, and for adjusting the control voltage based on the temperature of the first voltage divider circuit; and a second voltage divider circuit including a first resistor, the second voltage divider circuit being coupled to the test transistor and the amplifier, and for adjusting the voltage across the first resistor based on the temperature of the second voltage divider circuit.

[0074] In other embodiments, this disclosure relates to a method comprising the steps of: measuring the initial performance of a test transistor before a first time period. The method comprises the steps of: after measuring the initial performance of the test transistor, applying a first voltage to a control terminal of the test transistor to cause a first current to flow through the test transistor during the first time period. The method comprises the steps of: raising the temperature of the test transistor from a first temperature to a second temperature, and maintaining the temperature of the test transistor at the second temperature during the first time period. The method comprises the steps of: adjusting the first voltage during the first time period in response to the temperature increase of the test transistor to maintain the first current flowing through the test transistor during the first time period. The method comprises the steps of: measuring the final performance of the test transistor after the first time period. The method comprises the steps of: determining the difference between the initial performance of the test transistor and the final performance of the test transistor. In some embodiments, the method comprises the steps of: adjusting the resistance between a second terminal of the test transistor and ground to adjust the magnitude of the first current. In some embodiments, the method comprises the steps of: adjusting the first voltage to adjust the magnitude of the first current. In some embodiments, the method comprises the steps of: oscillating the first voltage according to a frequency and a duty cycle.

[0075] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various embodiments disclosed herein. Those skilled in the art should understand that the embodiments disclosed herein can be readily used as the basis for designing or modifying other processes and structures to achieve the same purposes and / or advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructions do not depart from the spirit and scope of the embodiments disclosed herein, and that various changes, substitutions, and modifications can be made to these equivalent constructions without departing from the spirit and scope of the embodiments disclosed herein. [Simplified Explanation of the Diagram]

[0004] The various embodiments of this disclosure can be best understood in conjunction with the accompanying drawings and the following detailed description. Note that, according to standard industry practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Figure 1 illustrates a circuit diagram of some embodiments of an apparatus for stress testing a test transistor. Figure 2 illustrates a schematic diagram of some embodiments of the performance of the apparatus of Figure 1. Figure 3 illustrates a flowchart of some embodiments of a method for stress testing a test transistor. Figure 4 illustrates a circuit diagram of other embodiments of the apparatus of Figure 1. Figure 5 illustrates a cross-sectional view of some embodiments of the apparatus of Figure 4. Figure 6 illustrates a flowchart of some embodiments of a process flow for manufacturing a test transistor. Figure 7 illustrates a circuit diagram of other embodiments of the apparatus of Figure 4. Figure 8 illustrates a circuit diagram of other embodiments of the apparatus of Figure 7. Figure 9 illustrates a cross-sectional view of some embodiments of a test transistor. [Biomaterial Storage]

[0077] Domestic storage information (please note in order of storage institution, date, and number): None. International storage information (please note in order of storage country, institution, date, and number): None.

Claims

1. A stress testing apparatus, comprising: a first voltage source, a second voltage source, and a third voltage source, the first voltage source being coupled to a first terminal of a test transistor; a probe circuit having a first terminal, a second terminal, and a third terminal, the first terminal of the probe circuit being coupled to the first terminal of the test transistor, the second terminal of the probe circuit being coupled to a second terminal of the test transistor, and the third terminal of the probe circuit being coupled to a control terminal of the test transistor; a first resistor having a first terminal and a second terminal, the first terminal of the first resistor being coupled to the second terminal of the test transistor, and the second terminal of the first resistor being coupled to the second voltage source; and an amplifier having a first input terminal, a second input terminal, and an output terminal, the first input terminal of the amplifier being coupled to the third voltage source, the second input terminal of the amplifier being coupled to the first terminal of the first resistor, and the output terminal of the amplifier being coupled to the control terminal of the test transistor.

2. The apparatus of claim 1, wherein the first resistor has a control terminal, the apparatus further comprising: a control circuit having a first output terminal coupled to the control terminal of the first resistor, wherein the first voltage source has a control terminal coupled to a second output terminal of the control circuit, and wherein the third voltage source has a control terminal coupled to a third output terminal of the control circuit.

3. The apparatus of claim 1, further comprising: a first signal generator circuit coupled between the third voltage source and the first input terminal of the amplifier; and a second signal generator circuit coupled between the first voltage source and the first terminal of the test transistor.

4. The apparatus of claim 1, further comprising: a voltage divider circuit coupled between the third voltage source and the first input terminal of the amplifier, the voltage divider circuit having a first terminal coupled to the third voltage source, a second terminal coupled to the first input terminal of the amplifier, and a third terminal coupled to the second voltage source; and a second resistor having a first terminal and a second terminal, the first terminal of the second resistor coupled to the second terminal of the test transistor, the second terminal of the second resistor coupled to the second input terminal of the amplifier and the first terminal of the first resistor, wherein the voltage divider circuit includes a third resistor and a fourth resistor, a first terminal of the third resistor coupled to the third voltage source, a second terminal of the third resistor and a first terminal of the fourth resistor coupled to the first input terminal of the amplifier, and a second terminal of the fourth resistor coupled to the second voltage source.

5. The apparatus of claim 4, wherein the first resistor and the third resistor have a first temperature coefficient, and wherein the second resistor and the fourth resistor have a second temperature coefficient, the second temperature coefficient being different from the first temperature coefficient.

6. The apparatus of claim 1, wherein the first resistor is located on an integrated wafer, the amplifier is located on the integrated wafer, and the test transistor is located on a test wafer separate from the integrated wafer, the apparatus further comprising: a first wafer probe extending from the integrated wafer to the test wafer and coupling the first voltage source and a first terminal of the probe circuit to the first terminal of the test transistor; a second wafer probe extending from the integrated wafer to the test wafer and coupling the first terminal of the first resistor, the second input terminal of the amplifier, and the second terminal of the probe circuit to the second terminal of the test transistor; a third wafer probe extending from the integrated wafer to the test wafer and coupling the output terminal of the amplifier and the third terminal of the probe circuit to the control terminal of the test transistor; a test chamber in which the integrated wafer and the test wafer are disposed; and a heater located in the test chamber.

7. A stress testing apparatus, comprising: a first voltage source, a second voltage source, and a third voltage source, the first voltage source being coupled to a first terminal of a test transistor and used to provide a stress voltage to the first terminal of the test transistor; a probe circuit coupled to the first terminal of the test transistor, a second terminal of the test transistor, and a control terminal of the test transistor, the probe circuit being used to measure a voltage across the test transistor and a current flowing through the test transistor; a first resistor coupled between the second terminal of the test transistor and the second voltage source; and an amplifier coupled to the test transistor and the first resistor, the amplifier being used to receive a control voltage from the third voltage source, and to provide an amplifier voltage to the control terminal of the test transistor based on a voltage across the first resistor and the control voltage, so that a current having a test current level flows through the test transistor, the amplifier being used to adjust the amplifier voltage to maintain the test current level flowing through the test transistor.

8. The apparatus of claim 7, further comprising: a signal generator for generating a control signal based on the control voltage, a frequency and a duty cycle, and for providing the control signal to the amplifier, wherein the amplifier provides an amplifier voltage to the control terminal of the test transistor based on the control signal.

9. The apparatus of claim 7, further comprising: a control circuit for adjusting a resistance of the first resistor, adjusting the control voltage, and adjusting the stress voltage.

10. A method for stress testing, comprising the steps of: measuring an initial performance of a test transistor before a first time period; after measuring the initial performance of the test transistor, applying a first voltage to a control terminal of the test transistor to cause a first current to flow through the test transistor during the first time period; raising a temperature of the test transistor from a first temperature to a second temperature, and maintaining the temperature of the test transistor at the second temperature during the first time period; adjusting the first voltage during the first time period in response to the temperature increase of the test transistor to maintain the first current flowing through the test transistor during the first time period; measuring a final performance of the test transistor after the first time period; and determining a difference between the initial performance of the test transistor and the final performance of the test transistor.

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