Semiconductor structure and methods of formation

Abstract

A semiconductor structure includes a first semiconductor die and a second semiconductor die. The first semiconductor die includes a first semiconductor device, and the second semiconductor die includes a second semiconductor device. The first semiconductor device includes a first cavity, a first microelectromechanical system (MEMS) structure within the first cavity, and a first sealing structure surrounding the first cavity and between a first semiconductor layer and a second semiconductor layer of the first semiconductor device. The second semiconductor device includes a second cavity, a second MEMS structure within the second cavity, and a second sealing structure surrounding the second cavity and between a first semiconductor layer and a second semiconductor layer of the second semiconductor device. The first sealing structure has a lateral dimension relative to the first cavity that is larger than the lateral dimension of the second sealing structure relative to the second cavity.

Description

Prior Technology

[0001] Integrated circuits can be fabricated on semiconductor wafers. Semiconductor wafers can be stacked or bonded together to form what are known as three-dimensional integrated circuits. Some semiconductor wafers include micro-electromechanical-system (MEMS) devices, which involve processes for forming microstructures on the micrometer scale (one millionth of a meter). MEMS devices can be built on silicon wafers and implemented in thin films of material. MEMS applications include inertial sensing applications, such as motion sensors, accelerometers, and gyroscopes. Other MEMS applications include optical applications (such as movable mirrors) and radio frequency (RF) applications (such as RF switches and resonators). Simple Explanation of the Diagram

[0002] The best understanding of this disclosure will be achieved by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, according to industry standard practice, the various features are not drawn to scale. In fact, the dimensions of the various features may be arbitrarily increased or decreased for clarity of explanation. Figures 1A to 1C are diagrams of exemplary semiconductor devices described herein. Figures 2A to 2G are diagrams of exemplary embodiments of the joining structure described herein. Figures 3A to 3D are figures of exemplary embodiments of the cavity structure described herein. Figures 4A to 4C are diagrams of the exemplary semiconductor devices described herein. Figure 5 is a diagram of an exemplary embodiment of the semiconductor structure described herein. Figures 6A to 6F are diagrams of exemplary embodiments of forming a first wafer of the semiconductor device described herein. Figures 7A to 7C are diagrams of exemplary embodiments of forming a second wafer of the semiconductor device described herein. Figures 8A and 8B are diagrams of exemplary embodiments of the bonding and dicing of wafers using the semiconductor device described herein. Figure 9 shows the relationship between the quality factor and pressure changes described in this paper. Figure 10 is a graph of the quality factor differences described in this article. Figure 11 is a flowchart of an exemplary process related to forming the semiconductor structure described herein. Implementation

[0003] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and arrangements are described below to simplify this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, the following description of a first feature formed on or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features, thereby preventing direct contact between the first and second features. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. Such repetition is for the purpose of brevity and clarity and is not intended to indicate any relationship between the various embodiments and / or configurations discussed.

[0004] Furthermore, for ease of explanation, spatially relative terms such as "beneath," "below," "lower," "above," "upper," and similar expressions may be used herein to describe the relationship between one device or feature shown in the figures and another device or feature. These spatially relative terms are intended to encompass not only the orientation shown in the figures but also different orientations of the device during use or operation. The device may have other orientations (rotated 90 degrees or in other orientations), and the spatially relative descriptions used herein will be interpreted accordingly.

[0005] MEMS devices may include multiple devices or wafers bonded together to form a MEMS device. For example, a MEMS device may include: a circuit wafer (e.g., a complementary metal oxide semiconductor (CMOS) wafer) including circuitry for the MEMS device; a device wafer including levitation mechanical components used as actuators in the MEMS device; and a cavity (or cap) wafer for sealing mechanical components within a cavity or microcavity. The circuit wafer, device wafer, and / or cap wafer may be bonded together using eutectic bonding and / or fusion bonding processes. Eutectic bonding is a wafer bonding technique that forms a eutectic system between the materials of the MEMS device by heating the wafer. The eutectic system typically includes silicon or germanium and a metal (e.g., gold or aluminum). Due to the formation of the eutectic system, the two materials diffuse into each other and form a bond at the eutectic point. Fused bonding is a wafer bonding technique for joining silicon (Si) with silicon (Si), silicon (Si) with silicon oxide (e.g., SiOx, such as SiO2), or silicon oxide with silicon oxide (e.g., SiO2 with SiO2).

[0006] Devices (such as MEMS resonators, MEMS accelerometers, and MEMS gyroscopes) operate optimally in a vacuum environment. In a vacuum environment, the device can be hermetically sealed within a cavity (e.g., a micro-chamber) under vacuum conditions. This hermetically sealed seal can fail due to factors such as process anomalies and / or defects. Sealing tests can be used to test the seal and ensure its integrity. Sealing tests can be performed by detecting pressure changes within the cavity. Pressure-sensitive devices within the cavity (e.g., resonators, Pirani gauges) can be used as sensors to detect these pressure changes.

[0007] Variations in cavity pressure can negatively impact the performance of MEMS devices. For example, the quality factor (Q) of a MEMS device (such as a resonator) depends on the vacuum pressure within its cavity. The quality factor of a resonator corresponds to the ratio of the initial energy stored in the resonator to the energy lost during one oscillation cycle. As the vacuum pressure (e.g., negative pressure) decreases (e.g., equal to the ambient pressure outside the cavity), the damping of the resonator increases, resulting in greater energy loss per oscillation (and thus a lower quality factor).

[0008] The pressure inside the cavity can vary depending on various factors, such as outgassing and / or gas leakage. "Outgassing" refers to the outflow of gas that may be trapped within the thin film material in the cavity during manufacturing processes (e.g., deposition processes). "Gas leakage" refers to gas flowing into the cavity from the outside, for example, due to negative pressure or vacuum within the cavity. The width of the sealing structure around the cavity (e.g., a sealing ring) can be large enough to allow sufficient time for gas to diffuse into the cavity, allowing the MEMS device to operate unimpeded. However, if a gas leakage path occurs through the sealing structure, the amount of leakage may be too small to be detected within a given time period due to the width of the sealing structure. For example, because gas diffusion occurs over time, after a certain period, leakage will begin to change the pressure in the cavity, thereby altering the quality factor of the MEMS device. However, because the amount of leakage over time is small, the change in the quality factor over time may not be large enough to detect the leakage, as the increase in damping on the MEMS device over time may be small. Because the leak went undetected, it may reduce the vacuum quality in the cavity, thereby reducing the sensitivity of the MEMS device, reducing the accuracy of the MEMS device, and / or causing the MEMS device to malfunction.

[0009] In some cases, MEMS devices can utilize greater environmental stress conditions, resulting in more gas leakage, which can then be used to detect process defects. However, excessive environmental stress on MEMS devices can alter their operation and / or degrade their performance.

[0010] In some embodiments described herein, product dies, including MEMS devices, are fabricated on a wafer together with one or more process control monitoring (PCM) dies. The width of the sealing structure surrounding the cavities in the one or more PCM dies on the wafer is controlled such that the cavities of the PCM dies are more susceptible to gas leakage than the cavities of the product dies. Higher sensitivity to gas leakage means a greater amount of gas leaking from the cavities in the PCM dies can be detected during testing when process variations or defects occur on the wafer. Specifically, the width of the sealing structure allows for the measurement of changes in the cavity pressure of the PCM dies between a first time and a second time. Changes in cavity pressure can cause a larger change in the quality factor (Q) of the PCM dies than in the product dies, making leaks in the PCM dies easier to detect without subjecting the product dies to destructive stress. The sealing structure can have different design variations in its shape and the location of the controlled width. The number of PCM dies and product dies on the wafer can also differ.

[0011] Figures 1A to 1C are diagrams of an exemplary semiconductor device 100 described herein. Semiconductor device 100 may be a MEMS device, such as a MEMS resonator, MEMS accelerometer, MEMS gyroscope, and other examples. As shown in Figure 1, semiconductor device 100 may include a device wafer 102. Device wafer 102 may be a complementary metal oxide semiconductor (CMOS) wafer, which includes semiconductor elements such as transistors, inductors, capacitors, and / or resistors, and includes integrated circuits and / or interconnect metallization layers of semiconductor device 100. Device wafer may include a substrate of semiconductor device 100. The substrate may correspond to a portion of device wafer 102 and may include a silicon (Si) substrate, a substrate formed of a material including silicon, a group V compound semiconductor material substrate such as gallium arsenide (GaAs), a silicon-on-insulator (SOI) substrate, or other types of substrates.

[0012] In the semiconductor device 100, an interconnect layer 104 is formed on the device wafer 102 in the z-direction. The interconnect layer 104 may include one or more dielectric layers, such as silicon nitride (SixNy), oxides (e.g., silicon oxide (SiOx) and / or another oxide material), and / or another type of dielectric material. The interconnect layer 104 may also include one or more interlayer dielectric (ILD) layers, one or more etch stop layers (ESL), and / or another type of dielectric layer.

[0013] Each ILD layer may comprise a low-k oxide material, such as silica (SiOx) or undoped silicate glass (USG). Additionally and / or alternatively, each ILD layer may comprise boron-containing silicate glass (BSG), fluorine-containing silicate glass (FSG), tetraethyl orthosilicate (TEOS), hydrogen silsesquioxane (HSQ), and / or other suitable dielectric materials. In some embodiments, the ILD layer comprises an extremely low dielectric constant (ELK) dielectric material with a dielectric constant less than about 2.5. Examples of ELK dielectric materials include carbon-doped silicon oxide (C-SiOx), amorphous fluorinated carbon (a-CxFy), parylene, bis-benzocyclobutene (BCB), polytetrafluoroethylene (PTFE), silicon oxycarbide (SiOC) polymers, porous HSQ, porous methyl silsesquioxane (MSQ), porous polyarylether (PAE), and / or porous silicon oxide (SiOx).

[0014] Each ESL may include silicon nitride (SixNy), silicon carbide (SiC), silicon oxynitride (SiON), and / or other suitable dielectric materials. In some embodiments, the ILD layer and the ESL include different dielectric materials to provide etch selectivity, thereby enabling the formation of various structures in the interconnect layer 104. For example, the ILD layer may each include a low-dielectric-constant dielectric material (e.g., USG), and the ESL may each include a high-dielectric-constant dielectric material (e.g., silicon nitride (SixNy) or silicon carbide (SiC)). Additionally and / or alternatively, two or more ESLs may include different materials. For example, one or more first ESLs may include silicon nitride (SixNy), and one or more second ESLs may include silicon carbide (SiC).

[0015] The interconnect layer 104 includes multiple conductive structures arranged in multiple layers. These conductive structures can be electrically and / or physically coupled to one or more integrated circuit devices and / or one or more MEMS devices. The conductive structures provide electrical wiring so that signals and / or power can be delivered to or from the integrated circuit devices and / or MEMS devices.

[0016] The interconnect layer 104 may include a metallization structure 106 and an interconnect structure 108. The metallization structure 106 may include trenches, metallization layers, conductive traces, and / or combinations of other types of conductive structures. The interconnect structure 108 may include vias, interconnects, and / or combinations of other types of conductive structures. The metallization structure 106 and the interconnect structure 108 may include one or more electrically conductive materials, such as tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), aluminum (Al), copper (Cu), gold (Au), and / or combinations thereof, as well as other examples of electrically conductive materials. In some embodiments, one or more padding layers are included between the dielectric layer of the interconnect layer 104 and the metallization structure 106, and / or between the dielectric layer of the interconnect layer 104 and the interconnect structure 108. The one or more padding layers may include barrier pads, adhesive pads, and / or other types of pads. Examples of materials used for one or more backing layers include tantalum nitride (TaN) and / or titanium nitride (TiN), etc.

[0017] The interconnect layer 104 may also include one or more test pads 110, which can be used in conjunction with integrated circuit device and / or MEMS device testing (e.g., circuit probe (CP) testing and / or wafer acceptance testing (WAT)). The test pads 110 may include conductive materials such as aluminum (Al), copper (Cu), aluminum-copper (AlCu), tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), gold (Au), or other suitable conductive materials. In some embodiments, the peripheral region (including the test pads 110) is contained within a diced region of the device wafer 102. In this case, the peripheral region may be removed (e.g., diced, sawed) from the semiconductor die before it is incorporated into the semiconductor die package.

[0018] In some embodiments, the semiconductor layer 112 is added to the device wafer 102 by fusion bonding the semiconductor substrate to the top surface of the interconnect layer 104. The semiconductor substrate may include a silicon (Si) substrate, a substrate formed of a material including silicon, a group V compound semiconductor material substrate such as gallium arsenide (GaAs), or other types of substrates.

[0019] One or more contact structures 114 (e.g., through-silicon vias, TSVs) are formed through the semiconductor layer 112 to contact one or more interconnect structures 108 of the interconnect layer 104. The contact structures 114 may include conductive materials such as aluminum (Al), copper (Cu), aluminum-copper (AlCu), tungsten (W), cobalt (Co), ruthenium (Ru), titanium (Ti), gold (Au), or other suitable conductive materials. The contact structures 114 can be used to provide electrical wiring so that signals and / or power can be supplied to and / or supplied from integrated circuit devices and / or MEMS devices. For example, one or more MEMS structures 116 (e.g., movable MEMS structures) may be formed in the semiconductor layer 112, which can be used as MEMS actuators (e.g., MEMS devices) of the semiconductor device 100. One or more MEMS structures 116 may be formed by etching portions of the semiconductor layer 112 to form elongated members, which are suspended above the interconnect layer 104 by lateral connection to one side of the semiconductor layer 112 of the device wafer 102. In this way, the MEMS structure 116 is allowed to move or displace to function as a vibrating mass, a flexible string or coil, a parallel plate for capacitive sensing, or other types of actuators to perform functions in resonators, sensors, gyroscopes, accelerometers, and / or other types of MEMS devices.

[0020] As shown in Figure 1A, the top cover wafer 118 is bonded to the device wafer 102 via a semiconductor layer 112. The top cover wafer 118 is bonded to the semiconductor layer 112 via a bonding structure 124 (e.g., a sealing structure), the bonding structure 124 comprising a stacked arrangement of a first bonding layer 120 and a second bonding layer 122. In some embodiments, the first bonding layer 120 comprises a metal (e.g., aluminum or gold) and the second bonding layer 122 comprises a semiconductor material (e.g., germanium or silicon). The top cover wafer 118 may comprise a substrate formed from a silicon wafer or another type of wafer used in semiconductor processing, which can be etched and has mechanical strength and material composition to form a cavity 126 in the top cover wafer 118.

[0021] In some embodiments, eutectic bonding is used to bond the top cover wafer 118 to the semiconductor layer 112. In this case, the first bonding layer 120 and the second bonding layer 122 diffuse into each other and bond at the eutectic point. Due to the formation of the eutectic system, there may be no identifiable interface between the bonded first bonding layer 120 and the second bonding layer 122. The eutectic bonding structure 124 can form a hermetically sealed seal between the top cover wafer 118 and the semiconductor layer 112 of the device wafer 102. The eutectic bonds between the semiconductor layer 112 and the top cover wafer 118, and the fused bonds between the interconnect layer 104 and the semiconductor layer 112, form a cavity 126 in which one or more MEMS structures 116 are hermetically sealed. The cavity 126 allows one or more MEMS structures 116 to move or be driven freely and prevents foreign objects and other contaminants from damaging the MEMS structures 116. The cavity 126 may be a sealed microcavity in which a vacuum is formed to prevent the cavity 126 from venting and gas leakage into the cavity 126. The cavity 126 may be composed of a device wafer 102 and a top cover wafer 118, which can surround one or more MEMS structures 116 in the cavity 126.

[0022] As explained in more detail here, the bonding structure 124 is formed around the cavity 126 to surround the cavity 126 and to act as a sealing structure to hermetically seal the cavity 126 between the top cover wafer 118 and the semiconductor layer 112.

[0023] The number and arrangement of structures, layers, and / or similar elements shown in Figure 1A are provided as examples only. In practice, MEMS structures may include additional structures and / or layers, fewer structures and / or layers, different structures and / or layers, or structures and / or layers with different arrangements, that are different from those shown in Figure 1A.

[0024] Furthermore, although FIG. 1A shows a single semiconductor device 100, multiple semiconductor devices 100, including various cavities 126 and their corresponding bonding structures 124, can be formed on a device wafer 102. For example, the device wafer 102 may include corresponding MEMS structures 116 formed in different portions of the semiconductor layer 112 and may be bonded to different portions of the top cover wafer 118, each including cavities 126 arranged around the respective MEMS structure 116. In other words, multiple semiconductor devices 100 with the same or similar configuration as the semiconductor device 100 shown in FIG. 1A can be formed on the device wafer 102 and on both the device wafer 102 and the top cover wafer 118.

[0025] Figure 1B is a first top view 128 of the semiconductor device 100, showing a top cover wafer 118, the device wafer 102, and a plurality of test pads 110 formed in the peripheral region of the device wafer 102. Figure 1C is a second top view 130 of the semiconductor device 100, in which the top cover wafer 118 is omitted to show the cavity 126. Similar to the top view 128 in Figure 1B, the top view 130 in Figure 1C shows the device wafer 102 and a plurality of test pads 110 formed in the peripheral region of the device wafer 102. The cross-sectional view in Figure 1A is taken along line A-A' in Figures 1B and 1C.

[0026] As described above, Figures 1A to 1C are provided as examples. Other examples may differ from those shown in Figures 1A to 1C.

[0027] Figures 2A through 2G are diagrams of exemplary embodiments of the bonding structure 124 (e.g., a sealing structure) described herein. As described herein, the width of the sealing structure around the cavity can be controlled such that some cavities (e.g., cavities for MEM devices formed on a PCM die) are more susceptible to gas leakage than other cavities (e.g., cavities for MEM devices formed on a product die). Higher sensitivity to gas leakage means more gas leakage into the cavity can be detected in the PCM die during testing when process variations or defects occur on the wafer. Figures 2A-2G illustrate exemplary embodiments (202, 204, 208, 212, 216, and 220) where the width D2 at one or more portions of the bonding structure 124 is smaller than the width D1 of the bonding structure 124 in exemplary embodiment 200, thus making the bonding structure 124 in the exemplary embodiments (202, 204, 208, 212, 216, 220) more susceptible to gas leakage.

[0028] As shown in Figure 2A, in exemplary embodiment 200, a bonding structure 124 (e.g., a sealing structure) is formed around and surrounds cavity 126 to hermetically seal cavity 126, and has a dimension D1 (e.g., width) in the x and y directions. The bonding structure 124 in exemplary embodiment 200 may be formed by eutectic bonding a first bonding layer 120 to a second bonding layer 122. In some embodiments, the dimension D1 may be uniformly distributed throughout the periphery of the bonding structure 124. The dimension D1 may include a range from about 5 micrometers to about 100 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0029] As shown in Figure 2B, in exemplary embodiment 202, a bonding structure 124 (e.g., a sealing structure) is formed around and surrounds cavity 126 to hermetically seal cavity 126, and has a dimension D2 (e.g., width) in the x and y directions. The bonding structure 124 in exemplary embodiment 202 may be formed by eutectic bonding a first bonding layer 120 to a second bonding layer 122. In exemplary embodiment 202, the dimension D2 is uniformly distributed throughout the periphery of the bonding structure 124 and is smaller than the dimension D1 in exemplary embodiment 200.

[0030] As shown in Figure 2C, in exemplary embodiment 204, a bonding structure 124 (e.g., a sealing structure) is formed around and surrounds cavity 126 to hermetically seal cavity 126. Some portions of the bonding structure 124 have a dimension D1 (e.g., width) in the x and y directions, while other portions of the bonding structure 124 have a dimension D2 (e.g., width) in the x direction. The bonding structure 124 in exemplary embodiment 204 may be formed by eutectic bonding of a first bonding layer 120 to a second bonding layer 122. In exemplary embodiment 204, the portion of the bonding structure 124 having dimension D2 is a recessed portion 206 of the bonding structure 124, wherein dimension D2 is smaller than dimension D1 in exemplary embodiment 200, and the remainder of the bonding structure 124 is also smaller. The recessed portions 206 are asymmetrically distributed at different points around the periphery of the bonding structure 124. One recessed portion 206 faces away from cavity 126, while the other recessed portion 206 faces cavity 126. Although two recessed portions 206 are shown, in some embodiments, the recessed portions 206 of the engagement structure 124 may be more or less than two.

[0031] As shown in Figure 2D, in exemplary embodiment 208, a bonding structure 124 (e.g., a sealing structure) is formed around and surrounds cavity 126 to hermetically seal cavity 126. Some portions of the bonding structure 124 have a dimension D1 (e.g., width) in the x and y directions, while the recessed corner portion 210 of the bonding structure 124 has a dimension D2 (e.g., width) in the x and y directions. The bonding structure 124 in exemplary embodiment 208 may be formed by eutectic bonding of a first bonding layer 120 to a second bonding layer 122. In exemplary embodiment 208, dimension D2 is smaller than dimension D1 in exemplary embodiment 200, and this is also true for the remaining portions of the bonding structure 124. The recessed corner portion 210 faces away from cavity 126. Alternatively, the recessed corner portion may face cavity 126. Although one recessed corner portion 210 is shown, in some embodiments, the bonding structure 124 may have multiple recessed corner portions 210.

[0032] As shown in Figure 2E, in exemplary embodiment 212, a bonding structure 124 (e.g., a sealing structure) is formed around and surrounds cavity 126 to hermetically seal cavity 126. Some portions of the bonding structure 124 have a dimension D1 (e.g., width) in the x and y directions, while other portions of the bonding structure 124 have a dimension D2 (e.g., width) in the x direction. The bonding structure 124 in exemplary embodiment 212 can be formed by eutectic bonding of a first bonding layer 120 to a second bonding layer 122. In exemplary embodiment 212, the portion of the bonding structure 124 having dimension D2 is a recessed portion 214 of the bonding structure 124, wherein dimension D2 is smaller than dimension D1 in exemplary embodiment 200, and the remaining portion of the bonding structure 124 is also like this. The recessed portions 214 are symmetrically distributed at opposite points around the periphery of the bonding structure 124. One recessed portion 214 faces away from cavity 126, and the other recessed portion 214 also faces away from cavity 126. Although two recessed portions 214 are shown, in some embodiments, there may be more than two recessed portions 214 symmetrically distributed in the joint structure 124.

[0033] As shown in FIG2F, in exemplary embodiment 216, a bonding structure 124 (e.g., a sealing structure) is formed around and surrounds cavity 126 to hermetically seal cavity 126. Some portions of bonding structure 124 have a dimension D1 (e.g., width) in the x and y directions, while another portion of bonding structure 124 has a dimension D2 (e.g., width) in the x direction. The bonding structure 124 in exemplary embodiment 216 may be formed by eutectic bonding of a first bonding layer 120 to a second bonding layer 122. In exemplary embodiment 216, the portion of bonding structure 124 having dimension D2 is a recessed portion 218 of bonding structure 124, wherein dimension D2 is smaller than dimension D1 in exemplary embodiment 200, and the remainder of bonding structure 124 is also such a recessed portion. The recessed portion includes a first side facing away from cavity 126 and a second side facing cavity 126. Although one recessed portion 218 is shown, in some embodiments, bonding structure 124 may have multiple recessed portions 218.

[0034] As shown in Figure 2G, in exemplary embodiment 220, a bonding structure 124 (e.g., a sealing structure) is formed around and surrounds cavity 126 to hermetically seal cavity 126. Some portions of the bonding structure 124 have a dimension D1 (e.g., width) in the x and y directions, while other portions of the bonding structure 124 have a dimension D2 (e.g., width) in the x and y directions. The bonding structure 124 in exemplary embodiment 220 may be formed by eutectic bonding of a first bonding layer 120 to a second bonding layer 122. In exemplary embodiment 220, the portion of the bonding structure 124 having dimension D2 is a recessed portion 222 of the bonding structure 124, wherein dimension D2 is smaller than dimension D1 in exemplary embodiment 200, and the same is true for the remaining portion of the bonding structure 124. The recessed portions 222 are distributed at different points on the periphery of the bonding structure 124. Each recessed portion 222 faces cavity 126. Although three recessed portions 222 are shown, in some embodiments, the recessed portions 222 of the engagement structure 124 may be more or less than three.

[0035] In the exemplary embodiments (202, 204, 208, 212, 216, and 220), the difference between size D2 and size D1 can range from about 5% to about 10%. However, other values ​​and ranges are also within the scope of this disclosure. If the difference between size D2 and size D1 is less than about 5%, the bonding structure 124 in the exemplary embodiments (202, 204, 208, 212, 216, and 220) may be insufficiently sensitive to gas leakage. Therefore, during testing to determine whether process variations and / or defects have occurred on the wafer, gas leakage may not be detectable in the PCM die including the bonding structure 124 in the exemplary embodiments (202, 204, 208, 212, 216, and 220). If the difference between size D2 and size D1 is greater than about 10%, the bonding structure 124 in the exemplary embodiments (202, 204, 208, 212, 216, and 220) may be highly susceptible to gas leakage. Therefore, during testing to determine whether process variations and / or defects have occurred on the wafer, gas leakage can easily occur in the PCM die including the bonding structure 124 in the exemplary embodiments (202, 204, 208, 212, 216, and 220), which may lead to erroneous conclusions regarding process variations and / or defects. In some embodiments, dimension D2 is included in the range of approximately 90% to approximately 95% of dimension D1. However, other values ​​and ranges are also within the scope of this disclosure.

[0036] As described above, Figures 2A to 2G are provided as examples. Other examples may differ from those shown in Figures 2A to 2G.

[0037] Figures 3A to 3D are diagrams of exemplary embodiments of the cavity structure described herein. As shown in exemplary embodiment 300 of Figure 3A, a mating structure 124 (e.g., a sealing structure) is formed around and surrounds the cavity 126 to hermetically seal the cavity 126. The mating structure 124 and the cavity 126 may have quadrilateral shapes (e.g., squares, rectangles, etc.). The mating structure 124 may also have rounded interior corners 302 and rounded exterior corners 304. In some embodiments, the corners of the mating structure 124 may be square.

[0038] As shown in the exemplary embodiment 306 of Figure 3B, a joining structure 124 (e.g., a sealing structure) is formed around and surrounds the cavity 126 to hermetically seal the cavity 126. The joining structure 124 and the cavity 126 may have a high-order (i.e., more than four sides) polygonal shape (e.g., pentagon, hexagon, etc.).

[0039] As shown in the exemplary embodiment 308 of FIG3C, a joining structure 124 (e.g., a sealing structure) is formed around and surrounds the cavity 126 to hermetically seal the cavity 126. The joining structure 124 and the cavity 126 may have a circular shape.

[0040] As shown in the exemplary embodiment 310 of Figure 3D, a joining structure 124 (e.g., a sealing structure) is formed around and surrounds the cavity 126 to hermetically seal the cavity 126. The joining structure 124 and the cavity 126 may have an elliptical shape.

[0041] As described above, Figures 3A to 3D are provided as examples. Other examples may differ from those shown in Figures 3A to 3D.

[0042] Figures 4A to 4C are diagrams of the exemplary semiconductor device described herein. As shown in Figure 4A, the exemplary semiconductor device 400 includes a first semiconductor layer portion 112a, a first MEMS structure 116a, a first top cover wafer portion 118a, a first bonding structure 124a, and a first cavity 126a. The first bonding structure 124a has a dimension D1. The figure illustrates a scenario where gas leakage 402a enters the first cavity 126a through the first bonding structure 124a.

[0043] As shown in Figure 4B, the exemplary semiconductor device 404 includes a second semiconductor layer portion 112b, a second MEMS structure 116b, a second top cover wafer portion 118b, a second bonding structure 124b, and a second cavity 126b. The second bonding structure 124b has a size D2 smaller than size D1. The figure illustrates a scenario where gas leakage 402b enters the second cavity 126b through the second bonding structure 124b.

[0044] As shown in Figure 4C, the exemplary semiconductor device 406 includes a third semiconductor layer portion 112c, a third MEMS structure 116c, a third top cover wafer portion 118c, a third bonding structure 124c, and a third cavity 126c. The third bonding structure 124c has a size D3 smaller than size D1 and smaller than size D2. The figure illustrates a scenario where gas leakage 402c enters the third cavity 126c through the third bonding structure 124c.

[0045] In some embodiments, the semiconductor devices (400, 404, and 406) are MEMS devices formed on the same device wafer (e.g., device wafer 102) and formed from different portions of the same semiconductor layer (e.g., semiconductor layer 112) and different portions of the same top cover wafer (e.g., top cover wafer 118). Alternatively, the semiconductor devices (400, 404, and 406) may be formed on the same device wafer (e.g., device wafer 102) and formed from different semiconductor layers and / or different top cover wafers. In some embodiments, dimension D2 is less than about 95% of dimension D1 and dimension D3 is less than about 95% of dimension D1.

[0046] The first MEMS structure 116a, the second MEMS structure 116b, and the third MEMS structure 116c may each include a resonator. The resonator or other pressure-sensitive device in each of the first cavity 126a, the second cavity 126b, and the third cavity 126c can be used as a sensor to detect pressure changes. For example, the quality factor (Q) of the pressure-sensitive device (e.g., the resonator) may depend on the vacuum pressure in the cavity where the pressure-sensitive device is located. The quality factor of the resonator corresponds to the ratio of the initial energy stored in the resonator to the energy lost by the resonator in one oscillation cycle. Gas leakage (402a, 402b, and 402c) can cause a decrease in the vacuum pressure (e.g., negative pressure) in the first cavity 126a, the second cavity 126b, and / or the third cavity 126c (e.g., equal to the ambient pressure outside the cavity). Therefore, the damping of the resonator increases, resulting in a greater energy loss per oscillation of the resonator (and thus a lower quality factor). Exhausting (e.g., the release of gases that may be trapped in the thin film material during the manufacturing process) can also cause changes in pressure within the cavity.

[0047] In some implementations, the width of the bonding structure surrounding the cavity (e.g., dimension D1 of the first bonding structure 124a) may be large enough to allow sufficient time for gas to diffuse into the cavity, enabling the MEMS device to operate unimpeded. In the case of the first bonding structure 124a and dimension D1, if a gas leakage path occurs through the first bonding structure 124a, the leakage amount may be too small to be detected within a given time period due to the dimension D1 (e.g., width) of the first bonding structure 124a. For example, since gas diffusion occurs over time, after a certain period, the leakage will begin to change the pressure in the cavity, thereby altering the quality factor of the MEMS device. However, because the leakage amount over time is small, the change in the quality factor over time may not be large enough to detect the gas leakage 402a entering the first cavity 126a, as the increase in damping of the MEMS device over time may be small. Because the leakage goes undetected, it may reduce the vacuum quality in the cavity, thereby reducing the sensitivity of the MEMS device, reducing the accuracy of the MEMS device, and / or causing the MEMS device to malfunction. The first cavity 126a may have the shape or other shape described in relation to the exemplary embodiments (300, 306, 308 or 310) in Figures 3A to 3C.

[0048] With the second bonding structure 124b having a dimension D2, the width of the second bonding structure surrounding the second cavity 126b is smaller than the width of the first bonding structure 124a. Therefore, the second cavity 126b is more prone to gas leakage than the first cavity 126a. Higher sensitivity to gas leakage means that a larger amount of gas leakage entering the second cavity 126b can be detected during testing when process variations or defects occur on the wafer. More specifically, the dimension D2 (e.g., width) of the second bonding structure 124b allows for the measurement of cavity pressure changes in the second cavity 126b between a first time and a second time, when the measured cavity pressure change in the first cavity 126a might be too small to detect. Changes in cavity pressure can cause a larger change in the quality factor (Q) of pressure-sensitive devices (e.g., resonators) in the second cavity 126b than in the first cavity 126a, making leaks in the semiconductor device 404 easier to detect. The dimension D2 of the second joining structure 124b can be achieved through one or more arrangements or other arrangements as described in the exemplary embodiments (202, 204, 208, 212, 216 and / or 220) in Figures 2B to 2G. Furthermore, the second cavity 126b can have the shape or other shape described in the exemplary embodiments (300, 306, 308 or 310) in Figures 3A to 3C.

[0049] With the third bonding structure 124c having a dimension D3, the width of the third bonding structure surrounding the third cavity 126c is smaller than the width of the first bonding structure 124a and the second bonding structure 124b, making the third cavity 126c more prone to gas leakage than the first cavity 126a and the second cavity 126b. The higher the sensitivity to gas leakage, the more significant the gas leakage into the third cavity 126c can be detected during testing when process variations or defects occur on the wafer. More specifically, when the measured values ​​of cavity pressure changes in the first cavity 126a and / or the second cavity 126b may be too small to be detected, the dimension D3 (e.g., width) of the third bonding structure 124b allows for the measurement of cavity pressure changes in the third cavity 126c between a first time and a second time. Changes in cavity pressure can cause a greater change in the quality factor of the pressure-sensitive device (e.g., a resonator) in the third cavity 126c than the change in the pressure-sensitive device (e.g., a resonator) in the first cavity 126a and / or the second cavity 126b, thereby making leaks in the semiconductor device 406 easier to detect. The dimension D3 of the third bonding structure 124c can be implemented by one or more arrangements or other arrangements as described in conjunction with dimension D2 of the exemplary embodiments (202, 204, 208, 212, 216 and / or 220) in Figures 2B to 2G. Furthermore, the third cavity 126c can have the shape or other shapes described in conjunction with the exemplary embodiments (300, 306, 308 or 310) in Figures 3A to 3C. The semiconductor devices (400, 404 and / or 406) can have the same or similar configuration as semiconductor device 100.

[0050] As described above, Figures 4A to 4C are provided as examples. Other examples may differ from those shown in Figures 4A to 4C.

[0051] Figure 5 is a diagram of an exemplary embodiment of the semiconductor structure described herein. As shown in exemplary embodiment 500, the semiconductor structure includes a semiconductor wafer 502 (e.g., a device wafer). The semiconductor wafer 502 includes a plurality of die groups 504, each die group 504 including a plurality of semiconductor dies. The semiconductor dies may be product dies 506, first PCM dies 508, or second PCM dies 510. The semiconductor dies may include semiconductor devices (100, 400, 404, and / or 406).

[0052] The die group 504 on the semiconductor wafer 502 may include a plurality of product dies 506. In addition to the plurality of product dies 506, the die group 504 may also include one or more first PCM dies 508 and / or one or more second PCM dies 510. In some embodiments, the product die 506 includes a semiconductor device 100 or 400 having a bonding structure 124 or 124a with a first size D1, the first PCM die 508 includes a semiconductor device 100 or 404 having a bonding structure 124 or 124b with a second size D2, and the second PCM die 510 includes a semiconductor device 100 or 406 having a bonding structure 124 or 124c with a second size D3.

[0053] As shown in Figure 5, some die groups 504 include a plurality of product dies 506 and a first PCM die 508 adjacent to one or more product dies 506. Some die groups 504 include a plurality of product dies 506 and more than one first PCM die 508. In some embodiments, the first PCM dies 508 may be adjacent to each other or located at different positions, and one or more of the plurality of product dies 506 are located between the first PCM dies 508. For example, the first PCM dies 508 may be located at opposite corners, and the product dies 506 are located between the first PCM dies 508. Some die groups 504 include a plurality of product dies 506, one or more first PCM dies 508, and one or more second PCM dies 510. In some embodiments, the first PCM dies 508 and the second PCM dies 510 are adjacent to each other or located at different positions, and one or more of the plurality of product dies 506 are located between the first PCM dies 508 and the second PCM dies 510. For example, the first PCM die 508 and the second PCM die 510 may be located at opposite corners and the product die 506 is located between the first PCM die 508 and the second PCM die 510.

[0054] The product die 506, including the MEMS device, is fabricated on a semiconductor wafer 502 together with one or more first PCM dies 508 and / or second PCM dies 510. The width (e.g., dimension D2 or D3) of the bonding structure 124 in the one or more first PCM dies 508 and / or second PCM dies 510 surrounding the cavity 126 is controlled such that the cavity 126 of the first PCM dies 508 and / or second PCM dies 510 is more susceptible to gas leakage than the cavity 126 of the product die 506. The higher the sensitivity to gas leakage, the more gas leakage in the cavities of the first PCM dies 508 and / or second PCM dies 510 can be detected during testing when process variations or defects occur on the semiconductor wafer 502. More specifically, the width (e.g., dimension D2 or dimension D3) of the bonding structure 124 of the first PCM die 508 and / or the second PCM die 510 allows for the measurement of changes in cavity pressure of the first PCM die 508 and / or the second PCM die 510 between a first time and a second time. Changes in cavity pressure may cause a greater change in the quality factor (Q) of the first PCM die 508 and / or the second PCM die 510 than a change in the product die 506, thereby making leaks in the first PCM die 508 and / or the second PCM die 510 easier to detect without using environmental stresses that could potentially damage the product die 506.

[0055] The bonding structure 124 of the first PCM die 508 and / or the second PCM die 510 may have one or more arrangements or another arrangement described in relation to the exemplary embodiments (202, 204, 208, 212, 216 and / or 220) in Figures 2B to 2G. Furthermore, the cavity 126 of the first PCM die 508 and / or the second PCM die 510 may have a shape or other shape described in relation to the exemplary embodiments (300, 306, 308 or 310) in Figures 3A to 3C. The number and location of the first PCM die 508, the second PCM die 510, and the product die on the semiconductor wafer 502 may vary.

[0056] As shown above, Figure 5 is only an example. Other examples may differ from those shown in Figure 5.

[0057] Figures 6A to 6F are diagrams of an exemplary embodiment 600 of a device wafer 102 forming the semiconductor device 100 described herein. In some embodiments, one or more semiconductor processing units may perform one or more of the techniques and / or processes described in conjunction with Figures 6A to 6F. In some embodiments, one or more of the techniques and / or processes described in conjunction with Figures 6A to 6F may be performed by other semiconductor processing units.

[0058] As shown in Figure 6A, a device wafer 102 is provided. The device wafer 102 may include a substrate provided in the form of a semiconductor wafer, such as a silicon (Si) wafer, an SOI wafer, and / or another type of semiconductor workpiece. The semiconductor device 100 may be formed on the semiconductor wafer together with other semiconductor devices.

[0059] As shown in Figure 6B, a deposition equipment is used to deposit one or more dielectric layers (e.g., ILD layers and / or ESL layers) on and / or above the device wafer 102. The deposition equipment can be used to deposit one or more dielectric layers of the interconnect layer 104 using physical vapor deposition (PVD), atomic layer deposition (ALD), chemical vapor deposition (CVD), oxidation techniques, and / or other suitable deposition techniques. In some embodiments, after depositing one or more dielectric layers of the interconnect layer 104, a planarization equipment can be used to perform a planarization operation (e.g., chemical mechanical planarization (CMP)) to planarize the one or more dielectric layers of the interconnect layer 104.

[0060] Deposition equipment, exposure equipment, developing equipment, etching equipment, planarization equipment, plating equipment and / or other semiconductor processing equipment can be used to perform various operations to form a metallization structure 106, an interconnect structure 108 and one or more test pads 110 in the interconnect layer 104 of the semiconductor device 100.

[0061] Metallization structure 106, interconnect structure 108, and test pad 110 may be formed in recesses of one or more dielectric layers of interconnect layer 104. In some embodiments, a pattern in the photoresist layer is used to etch one or more dielectric layers to form the recesses. In these embodiments, a deposition apparatus can be used to form the photoresist layer on interconnect layer 104. An exposure apparatus can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A developing apparatus can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching apparatus can be used to etch the dielectric layer according to the pattern to form the recesses. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal apparatus can be used to remove the remaining portions of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or another technique). In some implementations, a hard masking layer is used as an alternative technique for pattern-based etching of one or more dielectric layers of interconnect layer 104 to form a recess.

[0062] One or more deposition equipment can be used to deposit the metallized structure 106, interconnect structure 108, and / or test pad 110 in the recess using PVD, ALD, CVD, electroplating (e.g., electrochemical plating) and / or other suitable deposition techniques. In some embodiments, after depositing the metallized structure 106, interconnect structure 108, and / or test pad 110, a planarization equipment can be used to planarize the metallized structure 106, interconnect structure 108, and / or test pad 110.

[0063] Referring instead to FIG6C, the pattern of the photoresist layer is used to etch one or more dielectric layers of the interconnect layer 104 to form a MEMS structure cavity 602 in the interconnect layer 104. In some embodiments, a deposition apparatus can be used to form the photoresist layer on the interconnect layer 104. An exposure apparatus can be used to expose the photoresist layer to a radiation source to pattern the photoresist layer. A development apparatus can be used to develop and remove portions of the photoresist layer to expose the pattern. An etching apparatus can be used to etch the dielectric layer according to the pattern to form a recess. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal apparatus can be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or another technique). In some embodiments, a hard mask layer is used as an alternative technique for pattern-based etching of one or more dielectric layers of the interconnect layer 104 to form the MEMS structure cavity 602. In some embodiments, the depth of the cavity in the z-direction ranges from about 0.5 micrometers to about 30 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0064] As shown in Figure 6D, the semiconductor layer 112 is fused to the interconnect layer 104. In this case, the dielectric material of the interconnect layer 104 to which the fusion bonding occurs may include an oxide material, such as silicon oxide (e.g., SiOx, as SiO2) or another type of oxide material. Specifically, a bonding machine can fusedly bond the semiconductor layer 112 to the interconnect layer 104. The fusion bonding can form a hermetically sealed layer between the semiconductor layer 112 and the interconnect layer 104.

[0065] Melt bonding of semiconductor layer 112 and interconnect layer 104 may include pressing semiconductor layer 112 toward interconnect layer 104 and performing an annealing process to bond semiconductor layer 112 and interconnect layer 104 together due to atomic attraction. Melt bonding process can be used to bond silicon (Si) with silicon oxide (e.g., SiOx, such as SiO2).

[0066] In some embodiments, a planarization and / or wafer polishing apparatus may be used to perform a polishing operation on the top surface of the semiconductor layer 112 to mechanically remove the silicon material from the semiconductor layer 112. The polishing operation reduces the thickness of the semiconductor layer 112, such that the resulting semiconductor layer 112 has a thickness in the z-direction ranging from about 1 micrometer to about 100 micrometers. However, other values ​​and ranges are also within the scope of this disclosure. Thinning the semiconductor layer 112 can reduce the time consumed by the etching operation to remove portions of the semiconductor layer 112 and / or the processing consumption of the etching solution.

[0067] As shown in Figure 6E, a recess 604 is formed in the semiconductor layer 112 to expose the top surface of the interconnect structure 108. A contact structure 114 may be formed in the recess 604. In some embodiments, an etching machine can be used to etch away the dielectric mask layer according to a pattern corresponding to the location of the recess 604 in the photoresist layer to transfer the pattern to the dielectric mask layer. In some embodiments, the etching operation includes dry etching operations (e.g., plasma-based etching operations, gas-based etching operations), wet chemical etching operations, and / or another type of etching operation. In some embodiments, a photoresist removal machine can be used to remove the remaining portion of the photoresist layer (e.g., using chemical strippers, plasma ashing, and / or another technique).

[0068] After the recess 604 is formed, a conformal deposition technique (such as CVD or ALD) is used to deposit the conductive material of the contact structure 114 on the sidewalls and bottom surface of the recess 604, the top surface of the semiconductor layer 112, and the exposed top surface of the interconnect structure 108.

[0069] As further shown in Figure 6E, a first bonding layer 120 (e.g., aluminum (Al) or gold (Au)) is deposited on the top surface of the semiconductor layer 112. One or more deposition equipment can be used to deposit the first bonding layer 120 using PVD, ALD, CVD, electroplating (e.g., electrochemical plating), and / or other suitable deposition techniques. A portion of the deposited first bonding layer 120 can be removed by an etching operation to form the first bonding layer 120 into a pattern corresponding to the shape of the bonding structure 124. In some embodiments, a hard mask layer can be formed on a portion of the first bonding layer 120, corresponding to the reserved location of the first bonding layer 120. In some embodiments, for a MEMS device on product die 506, the first bonding layer 120 can be formed into a pattern including the features of exemplary embodiment 200, wherein the bonding structure 124 has a uniform dimension D1. In some embodiments, for a MEMS device on a first PCM die 508 or a second PCM die 510, the first bonding layer 120 may be formed as a pattern including features of exemplary embodiments of the bonding structure 124 (202, 204, 208, 212, 216 and / or 220), which may include uniform size D2 (or D3) or include one or more recessed portions / recessed corner portions (e.g., 206, 210, 214, 218 and / or 222) to produce size D2 (or D3) of each portion of the bonding structure 124.

[0070] As shown in Figure 6F, one or more semiconductor processing equipment can form one or more MEMS structures 116. A deposition equipment can deposit a photoresist layer on portions of the semiconductor layer 112, on the contact structure 114, and on the first bonding layer 120 via a spin coating operation. An exposure equipment can transfer a pattern from a photomask to the photoresist layer by exposing the photoresist layer to a radiation source to form a pattern in the photoresist layer. A development equipment can perform a development operation including one or more techniques to develop the pattern in the photoresist layer. An etching equipment can etch one or more portions of the semiconductor layer 112 to form a cavity 606 in the semiconductor layer 112, wherein the semiconductor layer 112 is part of one or more MEMS structures 116. In some embodiments, a solvent or chemical stripper is used to remove the remaining portion of the photoresist layer. In some embodiments, a plasma ashing process is used to remove the remaining portion of the photoresist layer. In these examples, a plasma source is used to form a plasma of oxygen or fluoride ions and react with the photoresist material. Ions in the plasma react with the photoresist material, causing the photoresist material to ashed, and then it is removed using a vacuum pump.

[0071] As described above, Figures 6A to 6F are provided as examples. Other examples may differ from those shown in Figures 6A to 6F.

[0072] Figures 7A to 7C are diagrams of an exemplary embodiment 700 of the top cover wafer 118 forming the semiconductor device 100 described herein. In some embodiments, one or more semiconductor processing units may perform one or more of the technologies and / or processes described in conjunction with Figures 7A to 7C. In some embodiments, one or more of the technologies and / or processes described in conjunction with Figures 7A to 7C may be performed by other semiconductor processing units.

[0073] As shown in Figure 7A, a top cover wafer 118 is provided. The top cover wafer 118 may include a substrate provided in the form of a semiconductor wafer, such as a silicon (Si) wafer and / or another type of semiconductor workpiece.

[0074] Referring instead to FIG7B, a second bonding layer 122 (e.g., germanium (Ge) or silicon (Si)) is deposited on the top surface of the top cover wafer 118. One or more deposition equipment may be used to deposit the second bonding layer 122 using PVD, ALD, CVD, electroplating (e.g., electrochemical plating), and / or other suitable deposition techniques. A portion of the deposited second bonding layer 122 may be removed by an etching operation to form the second bonding layer 122 into a pattern corresponding to the shape of the bonding structure 124. In some embodiments, a hard masking layer may be formed on a portion of the second bonding layer 122, corresponding to the reserved location of the second bonding layer 122. In some embodiments, for MEMS devices on product die 506, the second bonding layer 122 may be formed into a pattern including the features of exemplary embodiment 200, wherein the bonding structure 124 has a uniform dimension D1. In some embodiments, for a MEMS device on a first PCM die 508 or a second PCM die 510, the second bonding layer 122 may be formed as a pattern including features of exemplary embodiments (202, 204, 208, 212, 216 and / or 220), and its bonding structure 124 may include a uniform size D2 (or D3) or include one or more recessed portions / recessed corner portions (e.g., 206, 210, 214, 218 and / or 222) to produce a portion of the bonding structure 124 with size D2 (or D3).

[0075] As shown in Figure 7C, one or more semiconductor processing equipment can form a cavity 126 in the cap wafer 118. A deposition equipment can deposit a photoresist layer on a portion of the cap wafer and deposit a photoresist layer on the second bonding layer 122 by spin coating. An exposure equipment can transfer a pattern from a photomask to the photoresist layer by exposing the photoresist layer to a radiation source to pattern the photoresist layer. A development equipment can perform a development operation including one or more techniques to develop the pattern in the photoresist layer. An etching equipment can etch the portion of the cap wafer 118 corresponding to the location where the cavity 126 will be formed to form the cavity 126 in the cap wafer. In some embodiments, a solvent or chemical stripper is used to remove the remaining portion of the photoresist layer. In some embodiments, a plasma ashing process is used to remove the remaining portion of the photoresist layer. In these examples, the plasma source is used to form a plasma of oxygen ions or fluoride ions and react with the photoresist material. Ions in the plasma react with the photoresist material, causing the photoresist material to ashed, and then it is removed using a vacuum pump.

[0076] In some embodiments, the depth of the cavity in the z-direction may range from about 1 micrometer to about 200 micrometers. However, other values ​​and ranges are also within the scope of this disclosure.

[0077] As described above, Figures 7A to 7C are provided as examples. Other examples may differ from those shown in Figures 7A to 7C.

[0078] Figures 8A and 8B are diagrams of an exemplary embodiment 800 of the bonding and dicing of wafers using the semiconductor device 100 described herein. In some embodiments, one or more semiconductor processing units may perform one or more of the techniques and / or processes described in conjunction with Figures 8A and 8B. In some embodiments, one or more of the techniques and / or processes described in conjunction with Figures 8A and 8B may be performed by other semiconductor processing units.

[0079] As shown in Figure 8A, device wafer 102 and top cover wafer 118 can be bonded via semiconductor layer 112. A semiconductor processing apparatus (e.g., a bonding apparatus) can bond device wafer 102 and top cover wafer 118 by performing a eutectic bonding process to form eutectic bonds between a first bonding layer 120 (e.g., a metal bonding layer) of device wafer 102 and a second bonding layer 122 (e.g., a germanium (Ge) bonding layer) of top cover wafer 118. Eutectic bonding can be referred to as low-temperature bonding because the bonding between the materials of the first bonding layer 120 and the second bonding layer 122 is formed at a temperature below the melting point temperature of the materials of the first bonding layer 120 and the second bonding layer 122. The bonding apparatus can heat device wafer 102 and top cover wafer 118 to form eutectic bonds between the first bonding layer 120 and the second bonding layer 122. For example, if the first bonding layer 120 is formed of aluminum, the bonding machine can heat the device wafer 102 and the top cover wafer 118, such that the first bonding layer 120 and the second bonding layer 122 are heated to approximately 425 degrees Celsius to form eutectic bonds. In some embodiments, the eutectic bonding process can be combined with an annealing process (e.g., heating the top cover wafer 118 and the device wafer 102 to a high temperature of 1100 degrees Celsius or higher) to reduce the stress at the bonding interface caused by the eutectic bonding process.

[0080] The bonding structure 124 formed by the eutectic bond between the device wafer 102 and the top cover wafer 118 forms a cavity 126 in which one or more MEMS structures 116 are hermetically sealed. The cavity 126 allows one or more MEMS structures 116 (e.g., movable MEMS structures) to move or be actuated freely and prevents foreign objects and other contaminants from damaging the MEMS structures 116.

[0081] As shown in Figure 8B, the top cover wafer 118 is cut to expose one or more test pads 110 for CP and WAT testing.

[0082] As described above, Figures 8A and 8B are provided as examples. Other examples may differ from those shown in Figures 8A and 8B.

[0083] Figure 9 is a graph 900 showing the relationship between the quality factor (Q) and pressure changes. For example, the quality factor of a pressure-sensitive device (e.g., a resonator) in cavity 126 depends on the vacuum pressure of cavity 126. The quality factor of the resonator corresponds to the ratio of the initial energy stored in the resonator to the energy lost by the resonator in one oscillation cycle. As the vacuum pressure (e.g., negative pressure) decreases (e.g., due to gas leakage into cavity 126, making it equal to the ambient pressure outside cavity 126), the damping of the resonator increases, resulting in a greater energy loss per oscillation (and thus a lower quality factor).

[0084] Referring to chart 900, the vertical axis 902 corresponds to the quality factor, and the horizontal axis 904 corresponds to pressure. Curve 906 shows that the quality factor decreases as pressure increases. For example, a decrease in the quality factor (as shown by arrow 908 between points 910 and 912 on curve 906) corresponds to an increase in pressure (as shown by arrow 914 between points 910 and 912).

[0085] Figure 10 is a graph 1000 showing the quality factor differences between a product grain (e.g., product grain 506) with a bonding structure 124 (e.g., a sealing structure) of size D1, a first PCM grain (e.g., first PCM grain 508) with a bonding structure 124 (e.g., a sealing structure) of size D2, and a second PCM grain (e.g., second PCM grain 510) with a bonding structure 124 (e.g., a sealing structure) of size D3, between a first time and a second time.

[0086] Referring to Figure 1000, the vertical axis 1002 corresponds to the quality factor at the second time point, and the horizontal axis 1004 corresponds to the quality factor at the first time point. The highlighted sections (1006, 1008, and 1010) correspond to the ratio of the quality factor (Q) at the second time point (QT1) to the quality factor at the first time point (QT0) for the product die, the first PCM die, and the second PCM die, respectively. The ratio of QT1 to QT0 in section 1006 can be 1 or approximately 1, indicating that for the MEMS device with the bonding structure 124 of size D1, there is no change in the quality factor (e.g., no detectable change in cavity pressure between the first and second times). The QT1 to QT0 ratio of segment 1008 may be less than 1 (e.g., less than the QT1 to QT0 ratio of segment 1006), which indicates that for the MEMS device with the bonding structure 124 having size D2, the quality factor decreases between the first and second time periods (e.g., there is a detectable change in cavity pressure between the first and second time periods). The QT1 to QT0 ratio of segment 1010 may be less than the QT1 to QT0 ratio of segment 1008, which indicates that for the MEMS device with the bonding structure 124 having size D3, the quality factor further decreases between the first and second time periods (e.g., the change in cavity pressure between the first and second time periods has increased detectability).

[0087] The bonding structure 124 with dimensions D2 and D3 can detect pressure changes in the cavity of the MEMS device on the PCM die during testing, so as to identify problems in certain parts of the wafer where the PCM die is located without subjecting the MEMS device on the product die to unnecessary environmental stress and / or damage.

[0088] Figure 11 is a flowchart of an exemplary process 1100 associated with the formation of a semiconductor structure. In some embodiments, one or more semiconductor processing equipment is used to perform one or more process blocks in Figure 11, such as a deposition equipment, an exposure equipment, a developing equipment, an etching equipment, a planarization equipment, an ion implantation equipment, an annealing equipment, a wafer / die transfer equipment, and / or another type of semiconductor processing equipment.

[0089] As shown in Figure 11, process 1100 may include forming a plurality of MEMS structures (block 1110) on a first semiconductor wafer. For example, one or more semiconductor processing instruments may be used to form a plurality of MEMS structures (e.g., MEMS structure 116) on a first semiconductor wafer (e.g., device wafer 102), as described herein.

[0090] As further shown in Figure 11, process 1100 may include etching a second semiconductor wafer to form a plurality of cavities (block 1120) in the second semiconductor wafer. For example, one or more semiconductor processing equipment may be used to etch the second semiconductor wafer (e.g., top cover wafer 118) to form a plurality of cavities (e.g., first cavity 126a, second cavity 126b, third cavity 126c) in the second semiconductor wafer, as described herein.

[0091] As further shown in Figure 11, process 1100 may include bonding a second semiconductor wafer to a first semiconductor wafer (block 1130). For example, one or more semiconductor processing units may be used to bond the second semiconductor wafer to the first semiconductor wafer, as described herein. In some embodiments, each of the plurality of MEMS structures is located in one cavity of the plurality of cavities. In some embodiments, a first cavity of the plurality of cavities (e.g., first cavity 126a) is surrounded by a first bonding structure (e.g., first bonding structure 124a), which surrounds the first cavity (e.g., first cavity 126a). In some embodiments, a second cavity of the plurality of cavities (e.g., second cavity 126b or third cavity 126c) is surrounded by a second bonding structure (e.g., second bonding structure 124b or third bonding structure 124c) surrounding the second cavity. In some embodiments, the width (e.g., dimension D2 or dimension D3) of one or more portions of the second bonding structure in the direction (e.g., the x-direction) along the bonding interface between the first and second semiconductor wafers is smaller than the width (e.g., dimension D1) of the first bonding structure in the direction along the bonding interface.

[0092] Process 1100 may include additional implementations, such as any single implementation or combination of any implementations described below and / or combined with one or more other processes described elsewhere herein.

[0093] In a first embodiment, bonding the second semiconductor wafer to the first semiconductor wafer includes forming a eutectic bond between a germanium bonding layer (e.g., the second bonding layer 122) of the second semiconductor wafer and a metal bonding layer (e.g., the first bonding layer 120) of the first semiconductor wafer.

[0094] In the second embodiment, either alone or in combination with the first embodiment, each of the plurality of MEMS structures includes a device configured to detect changes in cavity pressure based on energy lost by the device.

[0095] In the third embodiment, either alone or in combination with one or more of the first and second embodiments, the one or more portions of the second joining structure (e.g., recessed portions 206, 214, 218, 222 and / or recessed corner portions 210) include recesses in the second joining structure.

[0096] In the fourth embodiment, either alone or in combination with one or more of the first to third embodiments, the third cavity of the plurality of cavities (e.g., the third cavity 126c) is surrounded by a third bonding structure (e.g., the third bonding structure 124c) surrounding the third cavity, and in the direction along the bonding interface between the first semiconductor wafer and the second semiconductor wafer, the width (e.g., dimension D3) of one or more portions of the third bonding structure is smaller than the width of one or more portions of the second bonding structure.

[0097] While Figure 11 shows an example block of process 1100, in some embodiments, process 1100 includes more blocks, fewer blocks, different blocks, or blocks arranged differently than those shown in Figure 11. Alternatively or concurrently, two or more blocks in process 1100 may be executed in parallel.

[0098] In this way, product dies including MEMS devices and one or more process control and monitoring (PCM) dies are fabricated on a wafer. The width of the sealing structure around the cavity of one or more PCM dies on the wafer is controlled so that the cavity of the PCM die is more susceptible to gas leakage than the cavity of the product die. The higher the sensitivity to gas leakage, the more gas leakage in the cavity of the PCM die can be detected during testing when process variations or defects occur on the wafer. More specifically, the width of the sealing structure allows for the measurement of changes in the cavity pressure of the PCM die between a first time and a second time. Changes in cavity pressure can cause a larger change in the quality factor (Q) of the PCM die than that of the product die, making leaks in the PCM die easier to detect without the environmental stress that would damage the product die. The sealing structure can be designed with different variations in shape and width control positions. The number of PCM dies and product dies on the wafer can also differ.

[0099] As described in more detail above, some embodiments described herein provide a semiconductor structure. The semiconductor structure includes a first semiconductor die, wherein the first semiconductor die includes a first semiconductor device. The first semiconductor device includes a first cavity, a first microelectromechanical system (MEMS) structure within the first cavity, and a first sealing structure surrounding the first cavity and between a first semiconductor layer and a second semiconductor layer of the first semiconductor device. The semiconductor structure includes a second semiconductor die, wherein the second semiconductor die includes a second semiconductor device. The second semiconductor device includes a second cavity, a second MEMS structure within the second cavity, and a second sealing structure surrounding the second cavity and between the first and second semiconductor layers of the second semiconductor device, wherein the first sealing structure is larger in the lateral direction relative to the first cavity than the second sealing structure is in the lateral direction relative to the second cavity.

[0100]

[0101] As described in more detail above, some embodiments described herein provide a semiconductor structure. The semiconductor structure includes a device wafer. The semiconductor structure includes a top cover wafer disposed above the device wafer along a first direction, wherein the top cover wafer is bonded to the device wafer. The semiconductor structure includes a first microelectromechanical system (MEMS) structure within a first cavity formed by the top cover wafer and the device wafer. The semiconductor structure includes a first bonding structure formed around the first cavity. The semiconductor structure includes a second MEMS structure within a second cavity formed by the top cover wafer and the device wafer. The semiconductor structure includes a second bonding structure formed around the second cavity, wherein the dimension of the first bonding structure in a second direction is larger than the dimension of the second bonding structure in the second direction.

[0102]

[0103] As described in detail above, some embodiments described herein provide a method. The method includes forming a plurality of microelectromechanical systems (MEMS) structures on a first semiconductor wafer. The method includes etching a second semiconductor wafer to form a plurality of cavities in the second semiconductor wafer. The method includes bonding the second semiconductor wafer to the first semiconductor wafer, wherein each of the plurality of MEMS structures is located in one of the plurality of cavities, wherein a first cavity of the plurality of cavities is surrounded by a first bonding structure, the first bonding structure enclosing the first cavity, wherein a second cavity of the plurality of cavities is surrounded by a second bonding structure, the second bonding structure enclosing the second cavity, and wherein one or more portions of the second bonding structure have a width along the bonding interface direction between the first and second semiconductor wafers that is smaller than the width of the first bonding structure along the bonding interface direction.

[0104]

[0105] The terms "approximately" and "substantially" can mean that a given quantity varies within 5% of that value (e.g., ±1%, ±2%, ±3%, ±4%, ±5% of the value). These values ​​are merely examples and are not intended to be limiting. It should be understood that, according to this disclosure, the terms "approximately" and "substantially" can refer to a percentage of the value of a given quantity.

[0106] The foregoing has outlined features of several embodiments to enable those skilled in the art to better understand the nature of this disclosure. Those skilled in the art should understand that they can readily use this disclosure as a basis for designing or modifying other processes and structures to achieve the same purposes or attain the same advantages as the embodiments described herein. Those skilled in the art should also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0107] 100, 400, 404, 406: Semiconductor devices 102: Device wafer 104: Interconnect layer 106: Metallized Structure 108: Internal Wiring Structure 110: Test pad 112: Semiconductor layer 112a: First semiconductor layer portion 112b: Second semiconductor layer portion 112c: Third semiconductor layer portion 114: Contact Structure 116: MEMS Structure 116a: First MEMS structure 116b: Second MEMS structure 116c: Third MEMS structure 118: Top Cover Wafer 118a: First top cover wafer portion 118b: Second top cover wafer portion 118c: Third top cover wafer portion 120: First bonding layer 122: Second bonding layer 124: Joint structure 124a: First joint structure / joint structure 124b: Second joint structure / joint structure 124c: Third joint structure / joint structure 126, 606: Cavity 126a: First cavity 126b: Second cavity 126c: Third cavity 128, 130: Top View 200, 202, 204, 208, 212, 216, 220, 300, 306, 308, 310, 500, 600, 700, 800: Exemplary Implementations 206, 210, 214, 218, 222: Depressed portions 210: Recessed corner portion 302: Interior angle 304: Rounded outer angle 402a, 402b, 402c: Gas leaks 502: Semiconductor wafer 504: Grain group 506: Product Grain Size 508: First PCM grain 510: Second PCM grain 602: MEMS structural cavity 604: Depression 900, 1000: Chart 902, 1002: Vertical axis 904, 1004: Horizontal axis 906: Curve 908, 914: Arrows 910, 912: points 1006, 1008, 1010: Sections 1100: Process 1110, 1120, 1130: Square A-A': line D1, D2: Width D3: Dimensions x, y, z: Direction

Claims

1. A semiconductor structure, comprising: A first semiconductor die, wherein the first semiconductor die includes a first semiconductor device, the first semiconductor device including: a first cavity; a first microelectromechanical system (MEMS) structure in the first cavity; and a first sealing structure disposed around the first cavity and between a first semiconductor layer and a second semiconductor layer of the first semiconductor device in the thickness direction of the semiconductor structure; and a second semiconductor die, wherein the second semiconductor die includes a second semiconductor device, the second semiconductor device including: a second cavity; a second MEMS structure in the second cavity; and a second sealing structure disposed around the second cavity and between a first semiconductor layer and a second semiconductor layer of the second semiconductor device in the thickness direction, wherein the first sealing structure includes a first dimension in a first lateral direction of the semiconductor structure different from the thickness direction, and the second sealing structure includes a second dimension in the first lateral direction, the first dimension being larger than the second dimension.

2. The semiconductor structure of claim 1, wherein the second sealing structure further includes a third dimension in a second lateral direction different from the first lateral direction, the second dimension and the third dimension being uniformly distributed around the second cavity.

3. The semiconductor structure as claimed in claim 1, wherein the second sealing structure comprises: The first part includes the second dimension in the first lateral direction; And the second part includes a third dimension in a second lateral direction different from the first lateral direction, wherein the third dimension is smaller than the second dimension.

4. The semiconductor structure of claim 1, wherein the difference between the second dimension of the second sealing structure and the first dimension of the first sealing structure is in the range of 5% to 10%.

5. The semiconductor structure as described in claim 1, further comprising: A third semiconductor die, wherein the third semiconductor die includes a third semiconductor device, the third semiconductor device including: a third cavity; a third microelectromechanical system (MEMS) structure in the third cavity; and a third sealing structure surrounding the third cavity and between a first semiconductor layer and a second semiconductor layer of the third semiconductor device, wherein the second dimension of the second sealing structure is larger than the third dimension of the third sealing structure in the first lateral direction.

6. A semiconductor structure, comprising: Device wafer; A top cover wafer is disposed above the device wafer in a first direction, wherein the top cover wafer is bonded to the device wafer; A first microelectromechanical system (MEMS) structure is formed in a first cavity by means of the top cover wafer and the device wafer; a first bonding structure is formed around the first cavity; a second MEMS structure is formed in a second cavity by means of the top cover wafer and the device wafer; And a second joining structure formed around the second cavity, wherein the dimension of the first joining structure in the second direction is greater than the dimension of the second joining structure in the second direction.

7. The semiconductor structure of claim 6, wherein the first bonding structure and the second bonding structure each comprise a semiconductor layer and a metal layer.

8. The semiconductor structure of claim 6, wherein the first bonding structure forms a first seal around the first cavity, and wherein the second bonding structure forms a second seal around the second cavity.

9. The semiconductor structure of claim 6, wherein the second bonding structure comprises: Multiple recessed portions are symmetrically or asymmetrically distributed in the second joining structure.

10. A method for forming a semiconductor structure, comprising: Multiple microelectromechanical system (MEMS) structures are formed on the first semiconductor wafer; The second semiconductor wafer is etched to form a plurality of cavities in the second semiconductor wafer; The method involves bonding the second semiconductor wafer to the first semiconductor wafer, wherein each of the plurality of microelectromechanical system (MEMS) structures is located in any one of the plurality of cavities, wherein a first cavity of the plurality of cavities is surrounded by a first bonding structure, the first bonding structure enclosing the first cavity, wherein a second cavity of the plurality of cavities is surrounded by a second bonding structure, the second bonding structure enclosing the second cavity, and wherein the width of one or more portions of the second bonding structure along the bonding interface direction between the first semiconductor wafer and the second semiconductor wafer is less than the width of the first bonding structure along the bonding interface direction.

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