Semiconductor gate structure and methods of forming the same

Abstract

One method includes depositing a gate dielectric layer on a first channel region; depositing a p-type work function tuning layer on the gate dielectric layer; exposing the p-type work function tuning layer to a silicon-based precursor for a period of time; and depositing an n-type work function tuning layer on the p-type work function tuning layer. Exposing the p-type work function tuning layer to the silicon-based precursor can form a silicon-containing layer on the p-type work function tuning layer.

Description

Technical Field

[0001] none. Prior Technology

[0002] Semiconductor devices are used in a variety of electronic applications, such as personal computers, mobile phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor material layers on a semiconductor substrate, and then using lithography to pattern the various material layers to form circuit components and elements on them.

[0003] The semiconductor industry is continuously increasing the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by constantly reducing the minimum feature size, thereby allowing more components to be integrated into a given area. However, as the minimum feature size decreases, additional problems arise that need to be addressed. Summary of the Invention

[0004] none. Simple Explanation of the Diagram

[0005] The features disclosed herein are best understood when studied in conjunction with the accompanying figures, and are described in the following detailed description. It should be noted that, in accordance with industry standards, the features are not drawn to scale. In fact, the dimensions of the features may be increased or decreased in any way for clarity of explanation. Figure 1 illustrates an example of a nanostructured field-effect transistor (nanostructured FET) in a three-dimensional view according to some embodiments. Figures 2, 3, 4, 5, 6, 7, 8A, 8B, 8C, 9A, 9B, 9C, 10, 11A, 11B, 11C, 12A, 12B, 12C, 13A, 13B, 13C, 14A, 14B, 14C, 15A, 15B, 15C, 16A, 16B, 16C, 17A, 17B, 17C, 18A, 18B, and 18C are views of intermediate stages in the fabrication of nanostructured FETs according to some embodiments. Figures 19A, 19B, and 19C are schematic diagrams of intermediate stages in a silicon impregnation process according to some embodiments. Figures 20A, 20B, 20C, 21A, 21B, 21C, 22A, 22B, 22C, 23A, 23B, and 23C are views of intermediate stages in the fabrication of nanostructured FETs according to some embodiments. Figures 24A, 24B, and 24C are schematic diagrams illustrating intermediate stages of forming an n-type work function tuning layer according to some embodiments. Figure 25 illustrates a growth graph of an n-type work function tuning layer according to some embodiments. Figures 26A, 26B, 26C, 27A, 27B, 27C, 28A, 28B, and 28C are views of intermediate stages in the fabrication of nanostructured FETs according to some embodiments. Figures 29, 30, 31, 32, and 33 are views of intermediate stages in the fabrication of nanostructured FETs according to some embodiments. Implementation

[0006] The following disclosure provides numerous different embodiments or instances for implementing various features of this disclosure. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For example, the formation of a first feature above or on a second feature in the following description may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where additional features may be formed between the first and second features such that the first and second features are not in direct contact. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not, in itself, indicate any relationship between the various embodiments and / or configurations discussed.

[0007] Furthermore, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms may be used herein to describe the relationship between one element or feature illustrated in the figures and another element(s). Spatial relative terms are intended to cover different orientations of the device during use or operation, other than those depicted in the figures. Devices may be oriented in other ways (rotated 90 degrees or otherwise), and the spatial relative descriptive symbols used herein may be interpreted similarly accordingly.

[0008] According to various embodiments, a silicon impregnation process is performed on the p-type work function tuning layer. The silicon impregnation process modifies the surface properties of the p-type work function tuning layer, resulting in the formation of less n-type work function tuning material on the p-type work function tuning layer. Reducing the amount of n-type work function tuning material formed on the p-type work function tuning layer in this way reduces the amount of n-type work function tuning material diffusing into the underlying p-type work function tuning layer. This reduces undesirable performance problems in p-type devices caused by the diffusion of n-type work function tuning material, such as aluminum atoms, into the p-type work function tuning layer.

[0009] The embodiments described below are in a specific context, namely, a die containing a nanostructured field-effect transistor (e.g., a "nano-FET" or "nano-FET"). However, various embodiments may be applied to dies containing other types of transistors (e.g., fin field-effect transistors, planar transistors, or the like) (instead of or in combination with nanostructured FETs).

[0010] Figure 1 illustrates an example of a nanostructure FET (e.g., nanowire FET, nanosheet FET), gate-all-around (GAA) FET, or similar, in a three-dimensional view according to some embodiments. For clarity, some features of the nanostructure FET may be omitted in Figure 1. The nanostructure FET includes a nanostructure 66 (e.g., nanosheet, nanowire, or similar) above fins 62 on a substrate 50 (e.g., a semiconductor substrate), wherein the nanostructure 66 is a semiconductor feature serving as a channel region of the nanostructure FET. Isolation regions 70, such as shallow trench isolation (STI) regions, are disposed between adjacent fins 62, which may protrude above and between adjacent isolation regions 70. The nanostructure 66 is disposed above and between adjacent isolation regions 70. Although the isolation region 70 is described / illustrated as separate from the substrate 50, as used herein, the term "substrate" may refer to a single semiconductor substrate or a combination of a semiconductor substrate and an isolation region. Furthermore, although the bottom portion of fin 62 is illustrated as being made of a single, continuous material with substrate 50, the bottom portion of fin 62 and / or substrate 50 may comprise a single material or multiple materials. In this document, fin 62 refers to the portion extending between adjacent isolation regions 70.

[0011] Gate dielectric 110 is located above the top surface of fin 62 and extends along the top, sidewalls, and bottom surface of nanostructure 66. Gate electrode 120 is located above gate dielectric 110. Gate electrode 120 may include one or more work function layers (not shown separately in Figure 1) above gate dielectric 110 and filling material above the work function layers(s). Source / drain regions 100 are disposed on fin 62 at opposite sides of gate dielectric 110 and gate electrode 120. (Multiple) source / drain regions 100 may refer to sources or drains, individually or collectively, depending on the context. An inter-layer dielectric (ILD) 104 is formed above source / drain regions 100. Contacts (described later) are formed through inter-layer dielectric 104 to source / drain regions 100. Source / drain regions 100 may be shared among various nanostructures 66. For example, adjacent source / drain regions 100 can be electrically connected, such as by fusing or merging source / drain regions 100 through epitaxial growth, or by coupling source / drain regions 100 with the same contact.

[0012] Figure 1 further illustrates the reference cross sections used in subsequent figures. Cross section A-A' is along the longitudinal axis of the fin 62 of the nanostructure FET and in the direction of current flow, for example, between the source / drain regions 100 of the nanostructure FET. Cross section B-B' is perpendicular to cross section A-A' and extends through the source / drain region 100 of the nanostructure FET. Cross section C-C' is parallel to cross section B-B' and along the longitudinal axis of the gate electrode 120. For clarity, subsequent figures refer to these reference cross sections.

[0013] Some embodiments discussed herein are described in the context of forming nanostructure FETs using a post-gate process. In other embodiments, a pre-gate process may be used. Similarly, some embodiments are envisioned for use in planar devices, such as planar FETs, or in fin field-effect transistors (FinFETs), replacing or in combination with nanostructure FETs. For example, a FinFET may include semiconductor fins on a substrate, wherein the semiconductor fins serve as semiconductor features of the channel region of the FinFET. Similarly, a planar FET may include a substrate, wherein planar portions of the substrate serve as semiconductor features of the channel region of the planar FET.

[0014] Figures 2 through 28C are views of intermediate stages in the fabrication of nanostructured FETs according to some embodiments. Figures 2, 3, 4, 5, 6, and 7 are three-dimensional views, showing a three-dimensional view similar to that in Figure 1. Figures 8A, 9A, 10, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 20A, 21A, 22A, 23A, 26A, 27A, and 28A illustrate cross-sectional views along a cross-section similar to the reference cross-section A-A' in Figure 1. Figures 8B, 9B, 11B, 12B, 13B, 14B, 15B, 16B, 17B, 18B, 20B, 21B, 22B, 23B, 26B, 27B, and 28B illustrate cross-sectional views along a cross-section similar to the reference cross-section B-B' in Figure 1. Figures 8C, 9C, 11C, 12C, 13C, 14C, 15C, 16C, 17C, 18C, 20C, 21C, 22C, 23C, 26C, 27C, and 28C illustrate cross-sectional views along a cross-section similar to the reference cross-section C-C' in Figure 1.

[0015] In Figure 2, a substrate 50 is provided. The substrate 50 may be a semiconductor substrate, such as a bulk semiconductor, a semiconductor-on-insulator (SOI) substrate, or the like, which may be doped (e.g., with p-type or n-type dopants) or undoped. The substrate 50 may be a wafer, such as a silicon wafer. Generally, an SOI substrate is a semiconductor material layer formed on an insulating layer. The insulating layer may be, for example, a buried oxide (BOX) layer, a silicon oxide layer, or the like. The insulating layer is disposed on the substrate, typically a silicon substrate or a glass substrate. Other substrates, such as multilayer substrates or gradient substrates, may also be used. In some embodiments, the semiconductor material of the substrate 50 may include silicon; germanium; compound semiconductors, including silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and / or indium antimonide; alloy semiconductors, including silicon germanium, gallium arsenide phosphide, aluminum indium arsenide, aluminum gallium arsenide, gallium indium arsenide, gallium indium phosphide, and / or gallium arsenide indium phosphide; or combinations thereof.

[0016] The substrate 50 has an n-type region 50N and a p-type region 50P. The n-type region 50N can be used to form an n-type device, such as an NMOS transistor, for example, an n-type nanostructure FET; the p-type region 50P can be used to form a p-type device, such as a PMOS transistor, for example, a p-type nanostructure FET. The n-type region 50N may or may not be physically separated from the p-type region 50P (not shown separately), and any number of device features (e.g., other active devices, doped regions, isolation structures, etc.) may be disposed between the n-type region 50N and the p-type region 50P. Although one n-type region 50N and one p-type region 50P are shown, any number of n-type regions 50N and p-type regions 50P may be provided.

[0017] Furthermore, in Figure 2, a multilayer stack 52 is formed over the substrate 50. The multilayer stack 52 includes alternating first semiconductor layers 54 and second semiconductor layers 56. The first semiconductor layers 54 are formed of a first semiconductor material, and the second semiconductor layers 56 are formed of a second semiconductor material. The semiconductor materials may each be selected from candidate semiconductor materials of the substrate 50.

[0018] In the illustrated embodiment, as will be described in more detail later, the first semiconductor layer 54 is removed, and the second semiconductor layer 56 is patterned to form channel regions for a nanostructure FET in both the n-type region 50N and the p-type region 50P. In such embodiments, the channel regions in both the n-type region 50N and the p-type region 50P may have the same material composition (e.g., silicon or another semiconductor material) and may be formed simultaneously. The first semiconductor layer 54 is a dummy layer that will be removed in a subsequent process to expose the top and bottom surfaces of the second semiconductor layer 56. The first semiconductor material of the first semiconductor layer 54 is a material with high etch selectivity relative to the etching of the second semiconductor layer 56, such as silicon germanium. The second semiconductor material of the second semiconductor layer 56 is a material suitable for both n-type and p-type devices, such as silicon.

[0019] In another embodiment (not illustrated separately), a first semiconductor layer 54 is patterned to form a channel region for a nanostructure FET in one region (e.g., p-type region 50P), and a second semiconductor layer 56 is patterned to form a channel region for a nanostructure FET in another region (e.g., n-type region 50N). The first semiconductor material of the first semiconductor layer 54 may be a material suitable for p-type devices, such as silicon germanium (e.g., Si x Ge1-x, where x can be in the range of 0 to 1), pure germanium, III-V compound semiconductors, II-VI compound semiconductors, or the like. The second semiconductor material of the second semiconductor layer 56 may be a material suitable for n-type devices, such as silicon, silicon carbide, III-V compound semiconductors, II-VI compound semiconductors, or the like. The first semiconductor material and the second semiconductor material can have high etching selectivity relative to each other, such that the first semiconductor layer 54 can be removed in the n-type region 50N without significantly removing the second semiconductor layer 56, and the second semiconductor layer 56 can be removed in the p-type region 50P without significantly removing the first semiconductor layer 54.

[0020] The multilayer stack 52 is illustrated as including three first semiconductor layers 54 and three second semiconductor layers 56. It should be understood that the multilayer stack 52 may include any number of first semiconductor layers 54 and second semiconductor layers 56. Each of the layers in the multilayer stack 52 may be grown by processes such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), or deposited by processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or similar methods. In some embodiments, some layers of the multilayer stack 52 are formed to be thinner than the other layers of the multilayer stack 52.

[0021] In Figure 3, fins 62 are formed in substrate 50, and nanostructures 64 and 66 (collectively referred to as "nanostructures 64 / 66") are formed in multilayer stack 52. In some embodiments, nanostructures 64 / 66 and fins 62 may be formed in multilayer stack 52 and substrate 50, respectively, by etching trenches in multilayer stack 52 and substrate 50. Etching may be any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), similar, or combinations thereof. Etching may be anisotropic. Forming nanostructures 64 / 66 by etching multilayer stack 52 may further define the first nanostructure 64 from the first semiconductor layer 54 and the second nanostructure 66 from the second semiconductor layer 56.

[0022] The fins 62 and nanostructures 64 / 66 can be patterned using any suitable method. For example, one or more optical lithography processes (including dual patterning or multiple patterning processes) can be used to pattern the fins 62 and nanostructures 64 / 66. Generally, dual patterning or multiple patterning processes combine optical lithography with a self-aligned process, thereby allowing the production of patterns with, for example, smaller pitches than that achievable using a single direct optical lithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using an optical lithography process. Spacers are formed next to the patterned sacrificial layer using a self-aligned process. The sacrificial layer is then removed, and the remaining spacers can then be used to pattern the fins 62 and nanostructures 64 / 66.

[0023] The fin 62 is illustrated to have substantially equal widths in both the n-type region 50N and the p-type region 50P. In some embodiments, the width of the fin 62 in the n-type region 50N may be greater than or less than the width of the fin 62 in the p-type region 50P. Furthermore, although each of the fins 62 and nanostructures 64 / 66 is illustrated to always have a constant width, in other embodiments, the fins 62 and / or nanostructures 64 / 66 may have tapered sidewalls, such that the width of each of the fins 62 and / or nanostructures 64 / 66 increases continuously in the direction toward the substrate 50. In such embodiments, each of the nanostructures 64 / 66 may have different widths and may be trapezoidal in shape.

[0024] In Figure 4, an insulating material 68 is formed over the substrate 50 and between adjacent fins 62 and adjacent nanostructures 64 / 66. The insulating material 68 may be an oxide, nitride, or combination thereof of silicon oxide, and may be formed by high-density plasma CVD (HDP-CVD), flowable CVD (FCVD), the like, or combinations thereof. Other insulating materials formed by any acceptable process may be used. In some embodiments, the insulating material 68 comprises silicon oxide formed by an FCVD process. Once the insulating material 68 is formed, an annealing process may be performed. Although the insulating material 68 is illustrated as a single layer, some embodiments may utilize multiple layers. For example, in some embodiments, a liner (not shown separately) may first be formed along the surfaces of the substrate 50, fins 62, and nanostructures 64 / 66. A filler material, such as one of the aforementioned insulating materials, may then be formed over the liner.

[0025] Insulating material 68 may be deposited over fins 62 and nanostructures 64 / 66, such that excess insulating material 68 covers nanostructures 64 / 66. A removal process is then applied to the insulating material 68 to remove excess insulating material 68 over the nanostructures 64 / 66. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etching back, a combination thereof, or similar, may be used. The planarization process exposes the nanostructures 64 / 66 such that, after the planarization process is completed, the nanostructures 64 / 66 are flush with the top surface of the insulating material 68.

[0026] In Figure 5, the insulating material 68 is recessed to form the STI region 70. The STI region 70 is adjacent to the fin 62. The recess in the insulating material 68 causes the upper portions of the fin 62 and / or nanostructures 64 / 66 to protrude from between the adjacent STI regions 70. The upper portions of the fin 62 and / or nanostructures 64 / 66 are above the STI region 70. Furthermore, the top surface of the STI region 70 may have a flat surface, a convex surface, a concave surface (such as a dish shape), or a combination thereof, as shown in the figure. The top surface of the STI region 70 may be formed into a flat, convex, and / or concave shape by appropriate etching. An acceptable etching process can be used to recess the STI region 70, such as an etching process that is selective to the material of the insulating material 68 (e.g., etching the insulating material 68 at a faster rate than etching the material of the fins 62 and nanostructures 64 / 66). For example, it can be removed using an oxide, such as dilute hydrofluoric acid (dHF).

[0027] The previously described process is only one example of how the fins 62 and nanostructures 64 / 66 are formed. In some embodiments, masking and epitaxial growth processes may be used to form the fins 62 and / or nanostructures 64 / 66. For example, a dielectric layer may be formed above the top surface of the substrate 50, and trenches may be etched through the dielectric layer to expose the underlying substrate 50. Epitaxial structures may be epitaxially grown in the trenches, and the dielectric layer may be recessed such that the epitaxial structures protrude from the dielectric layer to form the fins 62 and / or nanostructures 64 / 66. The epitaxial structures may include the alternating semiconductor materials previously described, such as a first semiconductor material and a second semiconductor material. In some embodiments of epitaxially growing epitaxial structures, the epitaxial growth material may be in-situ doped during growth, which avoids prior and / or subsequent implantation, although in-situ doping and implantation doping may be used together.

[0028] Furthermore, suitable wells (not shown separately) can be formed in fins 62, nanostructures 64 / 66, and / or STI regions 70. In embodiments with different well types, photoresist or other masks (not shown separately) can be used to achieve different implantation steps for n-type regions 50N and p-type regions 50P. For example, photoresist can be formed over fins 62, nanostructures 64 / 66, and STI regions 70 in n-type regions 50N and p-type regions 50P. The photoresist is patterned to expose p-type regions 50P. The photoresist can be formed using spin-on techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, n-type impurity implantation is performed in p-type regions 50P, and the photoresist can act as a mask to substantially prevent n-type impurities from being implanted into n-type regions 50N. n-type impurities can be phosphorus, arsenic, antimony, or similar substances implanted into the region, with a concentration in the range of approximately 10¹³ atoms / cm³ to approximately 10¹⁴ atoms / cm³. After implantation, the photoresist is removed, for example, by an acceptable ashing process.

[0029] Before or after implantation of the p-type region 50P, a photoresist or other mask (not shown separately) is formed over the fins 62, nanostructures 64 / 66, and STI region 70 in both the p-type region 50P and the n-type region 50N. The photoresist is patterned to expose the n-type region 50N. The photoresist can be formed using spin-on techniques and can be patterned using acceptable photolithography techniques. Once the photoresist is patterned, p-type impurity implantation can be performed in the n-type region 50N, and the photoresist can act as a mask to substantially prevent p-type impurities from being implanted into the p-type region 50P. The p-type impurity can be boron, boron fluoride, indium, or the like implanted in the region, with a concentration in the range of about 10¹³ atoms / cm³ to about 10¹⁴ atoms / cm³. After implantation, the photoresist can be removed, for example, by an acceptable ashing process.

[0030] After implantation of the n-type region 50N and the p-type region 50P, annealing can be performed to repair implantation damage and activate the implanted p-type and / or n-type impurities. In some embodiments, the growth material of the epitaxial fins can be in-situ doped during growth, which avoids implantation, although in-situ doping and implantation doping can be used together.

[0031] In Figure 6, a dummy dielectric layer 72 is formed on the fins 62 and / or nanostructures 64 / 66. The dummy dielectric layer 72 may be formed of silicon oxide, silicon nitride, combinations thereof, or the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 74 is formed over the dummy dielectric layer 72, and a masking layer 76 is formed over the dummy gate layer 74. The dummy gate layer 74 may be deposited over the dummy dielectric layer 72, and then planarized, for example, by a CMP process or the like. The dummy gate layer 74 may be formed of a conductive or non-conductive material and may be selected from the group including amorphous silicon, polycrystalline silicon (polysilicon), polycrystalline silicon germanium (polySiGe), metal nitrides, metal silicates, metal oxides, and metals. The material of the dummy gate layer 74 can be deposited by CVD, physical vapor deposition (PVD), sputtering deposition, or other techniques used for depositing the selected material. The dummy gate layer 74 can be formed from other materials that have high etch selectivity for etching insulating materials, such as the STI region 70 and / or the dummy dielectric layer 72. A masking layer 76 can be deposited over the dummy gate layer 74. The masking layer 76 can be formed from a dielectric material such as silicon nitride, silicon oxynitride, or the like. In this example, a single dummy gate layer 74 and a single masking layer 76 are formed across the n-type region 50N and the p-type region 50P. In the illustrated embodiment, the dummy dielectric layer 72 covers the STI region 70 such that the dummy dielectric layer 72 extends between the dummy gate layer 74 and the STI region 70. In another embodiment, the dummy dielectric layer 72 covers only the fins 62 and / or nanostructures 64 / 66.

[0032] In Figure 7, the mask layer 76 is patterned using acceptable optical lithography and etching techniques to form a mask 86. The pattern of the mask 86 can then be transferred to the dummy gate layer 74 and the dummy dielectric layer 72 to form dummy gates 84 and dummy dielectrics 82, respectively. The dummy gates 84 cover individual channel regions of the nanostructures 64 / 66. The pattern of the mask 86 can be used to separate each of the dummy gates 84 from adjacent dummy gates 84. The dummy gates 84 may also have a length direction substantially perpendicular to the length direction of the individual fins 62. The mask 86 may be removed after patterning, such as by any acceptable etching technique.

[0033] In Figures 8A through 8C, a spacer layer 90 is conformally formed on the exposed sidewalls of the mask 86 (if present), dummy gate 84, dummy dielectric 82, nanostructures 64 / 66, and fins 62 above the nanostructures 64 / 66 and the STI region 70. The spacer layer 90 may be formed of one or more dielectric materials. Figures 8A through 8C show a spacer layer 90 formed of a single layer of dielectric material, but in other embodiments, the spacer layer 90 may be formed of two or more layers of dielectric material. Acceptable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, or the like, which may be formed by deposition processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or the like. Other insulating materials formed by any acceptable process may be used. The spacer layer 90 is then etched to form spacers.

[0034] In Figures 9A to 9C, spacer layer 90 is patterned to form gate spacer 92 and fin spacer 94. Any acceptable etching process, such as dry etching, wet etching, similar, or a combination thereof, can be performed to pattern spacer layer 90. The etching can be anisotropic. During etching, spacer layer 90 has portions remaining on the sidewalls of the dummy gate 84 (thus forming gate spacer 92) and portions remaining on the sidewalls of the fins 62 and / or nanostructures 64 / 66 (thus forming fin spacer 94). After etching, fin spacer 94 and / or gate spacer 92 may have straight sidewalls or may have curved sidewalls. Additionally, STI regions 70 can also be etched during the patterning of spacer layer 90. Etching can cause portions of STI regions 70 to be recessed between the fins 62.

[0035] Furthermore, implantation (not illustrated separately) for lightly doped source / drain (LDD) regions can be performed. In embodiments with different device types, similar to the implantation of the previously described well, a mask, such as a photoresist, can be formed over the n-type region 50N while exposing the p-type region 50P, and an impurity of an appropriate type (e.g., p-type) can be implanted into the fins 62 and nanostructures 64 / 66 exposed in the p-type region 50P. The mask can then be removed. Subsequently, a mask, such as a photoresist, can be formed over the p-type region 50P while exposing the n-type region 50N, and an impurity of an appropriate type (e.g., n-type) can be implanted into the fins 62 and nanostructures 64 / 66 exposed in the n-type region 50N. The mask can then be removed. The n-type impurity can be any of the n-type impurities discussed previously, and the p-type impurity can be any of the p-type impurities discussed previously. Lightly doped source / drain regions can have impurity concentrations ranging from about 10¹⁵ atoms / cm³ to about 10¹⁹ atoms / cm³. Annealing can be used to repair implantation damage and activate implanted impurities.

[0036] It should be noted that the previous disclosure generally describes the process for forming spacers and LDD regions. Other processes and sequences may also be used. For example, fewer or additional spacers may be used, different step sequences may be used, additional spacers may be formed and removed, and / or the like. Furthermore, different structures and steps may be used to form n-type devices and p-type devices.

[0037] Referring again to Figures 9A through 9C, according to some embodiments, source / drain recesses 96 are patterned in the fins 62, nanostructures 64 / 66, and substrate 50. Epitaxial source / drain regions are then formed in the source / drain recesses 96. The source / drain recesses 96 may extend through the nanostructures 64 / 66 and into the substrate 50. In some embodiments, the fins 62 may be etched such that the bottom surface of the source / drain recesses 96 is disposed below the top surface of the STI region 70. The source / drain recesses 96 may be formed by etching the fins 62, nanostructures 64 / 66, and substrate 50 using an anisotropic etching process (such as RIE, NBE, or similar). In some embodiments, gate spacers 92 and dummy gates 84 shield portions of the fins 62, nanostructures 64 / 66, and substrate 50 during the etching process used to form the source / drain recesses 96. Each layer of the nanostructures 64 / 66 and / or fins 62 can be etched using a single etching process or multiple etching processes. After the source / drain recesses 96 have reached the desired depth, a timed etching process can be used to terminate the etching of the source / drain recesses 96.

[0038] In Figure 10, according to some embodiments, the source / drain groove 96 extends laterally to form a sidewall groove 97 in the first nanostructure 64. Specifically, the portion of the sidewall of the first nanostructure 64 exposed by the source / drain groove 96 may be recessed to form the sidewall groove 97. Thus, the sidewall groove 97 may have a height approximately the same as the height (e.g., thickness) of its corresponding first nanostructure 64. Although the sidewall of the first nanostructure 64 within the sidewall groove 97 is illustrated as flat, the sidewall may be concave or convex. The sidewall can be recessed by any acceptable etching process, such as an etching process selectively etching the material of the first nanostructure 64 (e.g., selectively etching the material of the first nanostructure 64 at a faster rate than etching the material of the second nanostructure 66). The etching may be isotropic. For example, when the second nanostructure 66 is formed of silicon and the first nanostructure 64 is formed of silicon-germanium, the etching process may be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In another embodiment, the etching process may be a dry etching using a fluorine-based gas, such as hydrogen fluoride (HF). In some cases, when forming the sidewall recess 97 (not shown), the etching process may slightly recess the second nanostructure 66 exposed by the sidewall recess 97 (e.g., remove a portion of it). In such cases, the sidewall recess 97 may have a height greater than the height (e.g., thickness) of its corresponding first nanostructure 64. In some embodiments, the same etching process may be performed consecutively to form the source / drain recess 96 and to recess the sidewalls of the first nanostructure 64 to form the sidewall recess 97. In some cases, the sidewall recess 97 may be considered a portion of the source / drain recess 96.

[0039] In Figures 11A through 11C, according to some embodiments, the internal spacer 98 is located in the sidewall recess 97. In other words, the internal spacer 98 is formed on the sidewall of the remaining portion of the first nanostructure 64. As will be described in more detail later, the source / drain regions are subsequently formed in the source / drain recess 96, and the first nanostructure 64 is subsequently replaced by the corresponding gate structure. The internal spacer 98 serves as an isolation feature between the subsequently formed source / drain regions and the subsequently formed gate structure. Furthermore, the internal spacer 98 can be used to prevent the subsequently formed source / drain regions from being damaged by subsequent etching processes, such as etching processes for the subsequent removal of the first nanostructure 64.

[0040] In some embodiments, the internal spacer 98 is formed by conformally forming an insulating material in the source / drain recess 96 and the sidewall recess 97, followed by etching the insulating material. The insulating material may be silicon nitride or silicon oxynitride, although any suitable material may be used, such as a low-k material having a k value less than about 3.5. The insulating material may be formed by a deposition process, such as ALD, CVD, or the like. The etching of the insulating material may be anisotropic. For example, the etching process may be dry etching, such as RIE, NBE, or the like. After etching of the insulating material, the remaining portion of the insulating material within the sidewall recess 97 forms the internal spacer 98.

[0041] Although the outer wall of the internal spacer 98 is illustrated as flush with (e.g., substantially coplanar with) the sidewall of the second nanostructure 66, the outer wall of the internal spacer 98 may extend beyond or be recessed from the sidewall of the second nanostructure 66. In other words, the internal spacer 98 may partially fill, completely fill, or overfill the sidewall recess 97. Furthermore, although the sidewall of the internal spacer 98 is illustrated as flat, the sidewall of the internal spacer 98 may be concave or convex. In some embodiments, the internal spacer 98 may have a thickness approximately the same as or greater than the thickness of the adjacent first nanostructure 64.

[0042] In Figures 12A to 12C, according to some embodiments, epitaxial source / drain regions 100 are formed in source / drain recesses 96 of the n-type region 50N and the p-type region 50P. The epitaxial source / drain region 100 in the n-type region 50N may be referred to as an "n-type source / drain region," and the epitaxial source / drain region 100 in the p-type region 50P may be referred to as a "p-type source / drain region." The n-type source / drain region 100 may be formed before, after, or simultaneously with the formation of the p-type source / drain region 100. In other embodiments, a semiconductor layer (not shown) may be formed in the source / drain recesses 96 before the epitaxial source / drain region 100 is formed in the source / drain recesses 96. The semiconductor layer may contain, for example, undoped silicon or the like. In other embodiments, an insulating layer (not shown) may be deposited in the source / drain groove before the epitaxial source / drain region 100 is formed in the source / drain groove 96.

[0043] In some embodiments, the epitaxial source / drain regions 100 apply stress to individual channel regions of the second nanostructure 66 within the p-type region 50P, thereby improving performance. The epitaxial source / drain regions 100 are formed in the source / drain recesses 96 such that each dummy gate 84 in the p-type region 50P is disposed between individual adjacent pairs of epitaxial source / drain regions 100. In some embodiments, gate spacers 92 are used to separate the epitaxial source / drain regions 100 from the dummy gates 84, and internal spacers 98 are used to separate the epitaxial source / drain regions 100 from the nanostructure 64 by an appropriate lateral distance, such that the epitaxial source / drain regions 100 do not short-circuit with the gate of the subsequently formed p-type nanostructure FET.

[0044] The epitaxial source / drain region 100 may also have a surface protruding from the individual surfaces of the nanostructures 64 / 66 and may have facets. For example, as a result of the epitaxial process used to form the epitaxial source / drain region 100, the upper surface of the epitaxial source / drain region 100 may have facets extending laterally outward beyond the sidewalls of the nanostructures 64 / 66. In some embodiments, these facets cause adjacent epitaxial source / drain regions 100 of the same nanostructure FET to merge. In other embodiments, as shown in Figure 12B, adjacent epitaxial source / drain regions 100 remain separated after the epitaxial process is completed. In the illustrated embodiment, fin spacers 94 are formed on the top surface of the STI region 70 to block epitaxial growth. In some other embodiments, the fin spacers 94 may cover portions of the sidewalls of the nanostructures 64 / 66 and / or the fins 62 to further block epitaxial growth. In another embodiment, the spacer etching used to form the gate spacer 92 is controlled to prevent the formation of fin spacers 94, thereby allowing the epitaxial source / drain region 100 to extend to the surface of the STI region 70. In some embodiments, the epitaxial source / drain region 100 extends above the top surface of the nanostructure 66. As a result, the top surface of the epitaxial source / drain region 100 can be positioned further away from the substrate 50 than the top surface of the adjacent nanostructure 66.

[0045] The p-type source / drain region 100 can be formed by epitaxial processes such as vapor phase epitaxy (VPE), molecular beam epitaxy (MBE), or the like. The p-type source / drain region 100 may include any acceptable material suitable for use in a p-type nanostructure FET. For example, if the second nanostructure 66 is formed of silicon, the p-type source / drain region 100 may contain a material that applies compressive strain to the second nanostructure 66, such as silicon-germanium, boron-doped silicon-germanium, germanium, germanium-tin, or the like. The p-type source / drain region 100 may be formed from a single layer of semiconductor material or from two or more sublayers of semiconductor material. The epitaxial source / drain region 100, nanostructures 64 / 66, and / or fins 62 within the p-type region 50P may be implanted with dopants, similar to the previously discussed processes for forming lightly doped source / drain regions, followed by annealing. The impurity concentration of the p-type source / drain region 100 can be between about 10¹⁹ atoms / cm³ and about 10²¹ atoms / cm³. Other concentrations are also possible. In some embodiments, the p-type source / drain region 100 may be in-situ doped during growth.

[0046] The n-type source / drain region 100 can be formed by an epitaxial process, such as VPE, MBE, or the like. The n-type source / drain region 100 can include any acceptable material suitable for use in an n-type nanostructure FET. For example, if the second nanostructure 66 is formed of silicon, the n-type source / drain region 100 can include a material that applies tensile strain to the second nanostructure 66, such as silicon, silicon carbide, phosphorus-doped silicon carbide, silicon phosphide (SiP), or the like. The n-type source / drain region 100 can be formed from a single layer of semiconductor material or from two or more sublayers of semiconductor material. The epitaxial source / drain region 100, nanostructures 64 / 66, and / or fins 62 within the n-type region 50N can be implanted with dopants, similar to the previously discussed processes for forming lightly doped source / drain regions, followed by annealing. The n-type source / drain region 100 may have an impurity concentration between about 10¹⁹ atoms / cm³ and about 10²¹ atoms / cm³. Other concentrations are also possible. In some embodiments, the n-type source / drain region 100 may be in-situ doped during growth.

[0047] In Figures 13A to 13C, a first interlayer dielectric 104 is deposited over the epitaxial source / drain region 100, fin spacer 94, gate spacer 92, mask 86 (if present), and / or dummy gate 84. The first interlayer dielectric 104 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma-enhanced CVD (PECVD), or FCVD. Suitable dielectric materials may include silicon oxide, silicon phosphate glass (PSG), borosilicate glass (BSG), borosilicate silica glass (BPSG), silica-free glass (USG), or the like. Other insulating materials formed by any acceptable process may be used.

[0048] In some embodiments, a contact etch stop layer (CESL) 102 is formed between the first interlayer dielectric 104 and the epitaxial source / drain region 100, fin spacer 94, gate spacer 92, mask 86 (if present), and / or dummy gate 84. The contact etch stop layer 102 may be formed of a dielectric material with high etch selectivity for etching the first interlayer dielectric 104, such as silicon nitride, silicon oxide, silicon oxynitride, combinations thereof, or the like, and may be formed using any suitable deposition process, such as CVD, ALD, or the like.

[0049] In Figures 14A through 14C, a removal process is performed to make the top surface of the first interlayer dielectric 104 flush with the top surface of the gate spacer 92 and the shield 86 (if present) or the dummy gate 84. In some embodiments, the removal process includes a planarization process, such as chemical mechanical polishing (CMP), polishing, etch-back, a combination thereof, or the like. The planarization process may also remove the shield 86 on the dummy gate 84 and a portion of the gate spacer 92 along the sidewall of the shield 86. After the planarization process, the top surfaces of the first interlayer dielectric 104, the gate spacer 92, and the shield 86 (if present), and / or the dummy gate 84 are substantially flush or coplanar (within process variations). Therefore, the top surfaces of the shield 86 (if present) and / or the dummy gate 84 may be exposed through the first interlayer dielectric 104.

[0050] In Figures 15A through 15C, a mask 86 (if present) and a dummy gate 84 are removed in one or more etching steps, thereby forming a groove between the gate spacers 92. In some embodiments, the dummy gate 84 and the dummy dielectric 82 are removed by an anisotropic dry etching process. For example, the etching process may include a dry etching process using multiple reactive gases, which selectively etches the material of the dummy gate 84 at a faster rate than etching the material of the first interlayer dielectric 104 and the gate spacers 92. Each groove exposes and / or covers a portion of the nanostructures 64 / 66, which serve as channel regions in the subsequently completed nanostructure FET. The portions of the nanostructures 64 / 66 serving as channel regions are disposed between adjacent pairs of epitaxial source / drain regions 100 in the n-type region 50N or between adjacent pairs of epitaxial source / drain regions 100 in the p-type region 50P. During removal, the dummy dielectric 82 can be used as an etch stop layer when the dummy gate 84 is etched. The dummy dielectric 82 can then be removed after the dummy gate 84 is removed.

[0051] Next, the remainder of the first nanostructure 64 is removed to form an opening 108 in the region between the second nanostructures 66. The remainder of the first nanostructure 64 can be removed by any acceptable etching process that selectively etches the material of the first nanostructure 64 at a faster rate than etching the material of the second nanostructure 66. The etching can be isotropic. For example, when the first nanostructure 64 is formed of silicon germanium and the second nanostructure 66 is formed of silicon, the etching process can be a wet etching using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or the like. In some embodiments, a trimming process (not shown separately) is performed to reduce the thickness of the exposed portion of the second nanostructure 66 and enlarge the opening 108. Hereinafter, the second nanostructure 66 may be referred to as nanostructure 66, and the nanostructure 66 above each fin 62 may be referred to as a "stack" of nanostructures 66.

[0052] Figures 16A to 26C illustrate intermediate steps in forming alternative gates, including gate dielectric 110 and gate electrode 120, according to some embodiments. Each pair of gate dielectric 110 and gate electrode 120 may be collectively referred to as a "gate structure" or "gate stack". Each gate structure surrounds the channel region of nanostructure 66 such that the gate structure extends along the sidewalls, bottom surface, and top surface of nanostructure 66. Some of the gate structures also extend along the sidewalls and / or top surface of fin 62.

[0053] In Figures 16A to 16C, according to some embodiments, gate dielectric 110 is formed as a replacement for the gate. Gate dielectric 110 includes one or more gate dielectric layers disposed on the sidewalls and / or top surface of fin 62; the top surface, sidewalls, and bottom surface of the channel region of nanostructure 66; the sidewalls of the internal spacers 98 of adjacent source / drain regions 100; and the sidewalls of gate spacers 92. In other words, gate dielectric 110 may be conformally deposited within opening 108. Gate dielectric 110 may also be formed on the top surface of gate spacer 92, first interlayer dielectric 104, and / or contact etch stop layer 102. Gate dielectric 110 may be formed from oxides such as silicon oxide or metal oxides, silicates such as metal silicates, combinations thereof, multilayers thereof, or the like. Alternatively, the gate dielectric 110 may be formed of a high-k dielectric material (e.g., a dielectric material having a k value greater than about 7.0), such as metal oxides or silicates of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and combinations thereof. The dielectric material(s) of the gate dielectric 110 may be formed by molecular-beam deposition (MBD), ALD, PECVD, or similar methods. Although a single-layer gate dielectric 110 is illustrated, the gate dielectric 110 may include any number of interface layers and any number of main layers. For example, the gate dielectric 110 may include an interface layer and an overlying high-k dielectric layer. The formation of the gate dielectric 110 in the n-type region 50N and the p-type region 50P may occur simultaneously, such that the gate dielectric 110 in each region is formed of the same material. In some embodiments, the gate dielectric 110 in each region can be formed by different processes, such that the gate dielectric 110 can be made of different materials and / or have different numbers of layers. When using different processes, various masking steps can be used to mask and expose appropriate regions.

[0054] Figures 17A to 27C illustrate intermediate steps in the formation of a gate electrode 120, which serves as a replacement gate portion according to some embodiments. The gate electrode 120 includes one or more work function tuning layers ("WF layers") and a filler material formed on top of the WF layers, as will be described in more detail below. The gate electrode 120 may include any number of WF layers, any number of barrier layers, any number of adhesive layers, or other layers.

[0055] In Figures 17A through 17C, according to some embodiments, a first WF layer 112 is deposited above the gate dielectric 110. The first WF layer 112 may be conformally deposited within the opening 108. For example, the first WF layer 112 is deposited above the top surface, sidewalls, and bottom surface of the channel region of the nanostructure 66. In some embodiments, the first WF layer 112 is deposited in both the n-type region 50N and the p-type region 50P using the same deposition process.

[0056] The first WF layer 112 comprises any acceptable materials(s) for tuning the work function of the device in the p-type region 50P to a desired amount, depending on the application of the device to be formed. Therefore, in some cases, the first WF layer 112 may be considered a "p-type work function tuning layer" or a "p-type WF layer". For example, the first WF layer 112 may subsequently be used as a work function tuning layer for a nanostructure FET in the p-type region 50P. The first WF layer 112 can be deposited using any acceptable deposition process. For example, when the first WF layer 112 is a p-type work function tuning layer, it may be formed from a p-type work function metal (PWFM) such as titanium nitride (TiN), tantalum nitride (TaN), combinations thereof, or the like, and may be deposited by ALD, CVD, PVD, or the like. Although the first WF layer 112 is illustrated as a single layer, the first WF layer 112 may be multilayered. For example, the first WF layer 112 may include a titanium nitride layer and a tantalum nitride layer. Other materials or combinations of materials are also possible.

[0057] In Figures 18A to 18C, according to some embodiments, a silicon immersion process 114 is performed on the first WF layer 112. After performing the silicon immersion process 114, the first WF layer 112 is referred to herein as the post-immersion first WF layer 112' or simply the first WF layer 112'. The silicon immersion process 114 forms a silicon-containing layer on the first WF layer 112, which reduces the subsequent formation of the second WF layer, as will be described in more detail below. The silicon immersion process 114 includes placing the substrate 50 in a chamber and exposing the surface of the first WF layer 112 to a silicon-based precursor for a period of time. For example, in some embodiments, the silicon immersion process 114 includes placing the substrate 50 in a chamber, introducing one or more silicon-based precursors into the chamber, and then closing the inlet and outlet of the chamber for a predetermined time. The silicon-based precursor is adsorbed or reacts with the surface of the first WF layer 112, and is discharged from the chamber after a predetermined time. The chamber may be an ALD deposition system, a plasma-enhanced ALD (PEALD) deposition system, a plasma-enhanced cyclic CVD (PECCVD) system, a pulsed CVD system, a processing chamber for an implantation system, or any other suitable processing chamber or other suitable chamber. In this way, in some cases, the silicon immersion process 114 may be considered an ALD process, a PEALD process, a PECVD process, a pulsed CVD process, or the like.

[0058] The silicon immersion process 114 can be performed at a temperature range of about 0 °C to about 900 °C and a pressure range of about 0.5 Torr to about 20 Torr, for example, by maintaining a chamber at this temperature and / or pressure. The silicon immersion process 114 can be performed for a duration ranging from about 1 second to about 600 seconds, for example, by maintaining the silicon-based precursor in a chamber for this duration. Exemplary silicon-based precursors may comprise molecules such as (but not limited to) silanes, organosilanes, or the like. Silanes may include silanes (SiH4), disilanes (Si2H6), trisilanes (Si3H8), tetrasilanes (Si4H10), the like, or any combination thereof. Organosilanes may include compounds having the empirical formula RySixH(2x+2-y), wherein R is independently methyl, ethyl, propyl, or butyl, or the like. For example, organosilanes may include methylsilane ((CH3)SiH3), dimethylsilane ((CH3)2SiH2), ethylsilane ((CH3CH2)SiH3), methyldisilanes ((CH3)Si2H5), dimethyldisilanes ((CH3)2Si2H4), hexamethyldisilanes ((CH3)6Si2), tris(dimethylamino)silane (TDMAS), analogs, or any combination thereof. Other parameters or precursors are also possible. Controlling the parameters or precursors used in the silicon impregnation process 114 can change the thickness (e.g., number of monolayers), composition (e.g., silicon percentage), or other properties of the silicon-containing layer formed by the silicon impregnation process 114.

[0059] Figures 19A, 19B, and 19C illustrate intermediate steps in forming a post-immersion first WF layer 112' using a silicon immersion process 114 according to some embodiments. Figure 19A schematically illustrates a cross-section of a portion of the first WF layer 112 covering the gate dielectric 110 prior to the silicon immersion process 114. Figure 19B schematically illustrates the first WF layer 112 and the gate dielectric 110 during the silicon immersion process 114. Figure 19C schematically illustrates the gate dielectric 110 and the post-immersion first WF layer 112' including the silicon-containing layer 116 after the silicon immersion process 114 is completed. Figures 19A to 19C are intended as illustrative; other materials or configurations are also possible.

[0060] Figure 19A illustrates a first WF layer 112 deposited on the gate dielectric 110, the deposition process being similar to the steps shown in Figures 17A through 17C. For example, the first WF layer 112 may comprise titanium nitride or the like. As shown in Figure 19A, the surface of the first WF layer 112 may be covered with hydroxide surface ligands (e.g., -OH bonds) or the like.

[0061] In Figure 19B, the first WF layer 112 is subjected to a silicon immersion process 114. A silicon-based precursor, schematically represented by silane molecules in Figure 19B, bombards or adsorbs onto the surface of the first WF layer 112 and reacts with hydroxide surface ligands. The reaction between the silicon-based precursor and the hydroxide surface ligands allows the silicon in the silicon-based precursor to bond with oxygen at the surface of the first WF layer 112. In this manner, as more silicon-based precursor reacts with hydroxide surface ligands, a silicon-containing layer 116 (see Figure 19C) can be formed at the surface of the first WF layer 112.

[0062] In Figure 19C, a silicon immersion process 114 has been performed to form a silicon-containing layer 116 covering the first WF layer 112. The first WF layer 112, together with the overlying silicon-containing layer 116, forms the immersed first WF layer 112'. The silicon-containing layer 116 may comprise a single silicon-containing layer (e.g., a silicon monolayer) or multiple silicon-containing layers (e.g., a silicon multilayer). For example, in some embodiments, the silicon-containing layer 116 may comprise a silicon oxide monolayer (e.g., SiO2) or a silicon oxide multilayer (e.g., a SiO2 multilayer), although other layer compositions are also possible. In this way, the hydroxide-OH bonds on the surface of the first WF layer 112 can be replaced by Si-O bonds (e.g., silicon-oxygen bonds) and / or Si-OH bonds (e.g., silicon-hydroxyl bonds) using the silicon immersion process 114. In some cases, the silicon-containing layer 116 may have a thickness in the range of about 5 Å to about 50 Å.

[0063] In Figures 20A to 20C, according to some embodiments, a mask 117 is formed over the p-type region 50P. The mask 117 may include, for example, a photoresist, a multilayer photoresist structure, an antireflective coating (e.g., a BARC layer), or the like. The mask 117 may be formed using suitable techniques (e.g., spin-on, or the like) and patterned using suitable optical lithography techniques to expose the n-type region 50N. In this manner, the first WF layer 112' in the p-type region 50P is protected, and the first WF layer 112' in the n-type region 50N is exposed.

[0064] In Figures 21A to 21C, according to some embodiments, an etching process is performed to remove the first WF layer 112' in the n-type region 50N. The etching process removes the silicon-containing layer 116 and the first WF layer 112 to expose the underlying gate dielectric 110 of the n-type region 50N. A mask 117 protects the first WF layer 112' in the p-type region 50P from the etching process. The etching process may include a wet etching process and / or a dry etching process. In some cases, the etching process may selectively etch the first WF layer 112' while little or no etching of the gate dielectric 110.

[0065] In Figures 22A to 22C, mask 117 is removed from the p-type region 50P. Mask 117 can be removed using suitable techniques, such as etching, ashing, or similar processes. After removing mask 117, gate dielectric 110 is exposed in the n-type region 50N, and the first WF layer 112' is exposed in the p-type region 50P.

[0066] In Figures 23A to 23C, according to some embodiments, a second WF layer 118 is deposited above the gate dielectric 110 in the n-type region 50N and above the first WF layer 112' in the p-type region 50P. The second WF layer 118 may be conformally deposited within the opening 108. For example, the second WF layer 118 is deposited above the top surface, sidewalls, and bottom surface of the channel region of the nanostructure 66. The second WF layer 118 is deposited in both the n-type region 50N and the p-type region 50P using the same deposition process. As explained in more detail below, during the deposition process, the silicon-containing layer 116 in the first WF layer 112' delays the formation of the second WF layer 118 in the p-type region 50P. Therefore, the second WF layer 118 formed in the p-type region 50P may be thinner than the second WF layer 118 formed in the n-type region 50N. In some cases, the second WF layer 118 formed on the first WF layer 112' in the p-type region 50P is referred to herein as the second WF layer 118', to distinguish it from the second WF layer 118 formed on the gate dielectric 110 in the n-type region 50N. In other cases, the second WF layer 118 may refer to both the second WF layer 118 formed in the n-type region 50N and the second WF layer 118' formed in the p-type region 50P, depending on the context. Forming a thinner second WF layer 118 in the p-type region 50P reduces the amount of second WF layer 118 material undesirably diffused into the first WF layer 112, as described in more detail below.

[0067] The second WF layer 118 comprises any acceptable materials(s) for tuning the work function of the device in the n-type region 50N to a desired amount, depending on the application of the device to be formed. Therefore, in some cases, the second WF layer 118 can be considered an "n-type work function tuning layer" or an "n-type WF layer". For example, the second WF layer 118 can subsequently be used as a work function tuning layer for a nanostructure FET in the n-type region 50N. The second WF layer 118 can be deposited using any acceptable deposition process. For example, when the second WF layer 118 is an n-type work function tuning layer, it can be formed of an n-type work function metal (NWFM), such as titanium aluminum (TiAl), titanium aluminum carbide (TiAlC), titanium aluminum nitride (TiAlN), combinations thereof, or the like, and can be deposited by ALD, CVD, PVD, or the like. Although the second WF layer 118 is shown as a single layer, it can also be multilayered.

[0068] In embodiments of the second WF layer 118 series n-type work function tuning layer, it may include a metallic element, such as aluminum, suitable for tuning the threshold voltage of an n-type device. In some cases, aluminum in the n-type work function tuning layer may diffuse into the underlying layer during subsequent process steps, particularly during high-temperature process steps. For structures where the n-type work function tuning layer is deposited over a p-type work function tuning layer, aluminum in the n-type work function tuning layer may diffuse into the p-type work function tuning layer, thereby shifting the effective work function of the p-type work function tuning layer. Aluminum or other n-type work function elements diffused into the p-type work function tuning layer can reduce the accuracy or uniformity of work function tuning in the p-type region 50P and can shift the effective work function of the p-type work function tuning layer in a way that negatively impacts device performance. For example, the presence of aluminum in the p-type work function tuning layer can unnecessarily reduce the flat-band voltage in a p-type MOS capacitor or unnecessarily increase the threshold voltage of a p-type transistor (e.g., a p-type MOSFET, a p-type nanostructure FET, or the like).

[0069] Forming a thinner n-type work function tuning layer above the p-type work function tuning layer reduces the amount of aluminum that can diffuse into the p-type work function tuning layer, thereby reducing the amount of aluminum diffusing into the p-type work function tuning layer. By reducing the amount of aluminum diffusing into the p-type work function tuning layer, the amount of shift in the work function of the p-type work function tuning layer due to the presence of aluminum can be reduced, thereby improving device performance and device uniformity.

[0070] As described herein, subjecting the first WF layer 112 in the p-type region 50P to a silicon immersion process 114 modifies the surface of the first WF layer 112 in a manner that hinders the subsequent growth of the second WF layer 118 on the first WF layer 112. In this way, a thinner second WF layer 118' can be formed on the first WF layer 112' in the p-type region 50P, while a second WF layer 118 is formed in the n-type region 50N. Therefore, the use of the silicon immersion process 114 as described herein reduces aluminum diffusion into the first WF layer 112, thereby improving the work function tuning accuracy, device performance, and device uniformity.

[0071] Turning to Figures 24A through 24C, according to some embodiments, an intermediate step in forming a second WF layer 118' on a first WF layer 112' is shown. Figures 24A and 24B schematically illustrate a cross-section of a portion of the first WF layer 112' during the deposition of the second WF layer 118'. Figure 24C schematically illustrates the formation of a portion of the second WF layer 118'. Figures 24A through 24C illustrate portions of the first WF layer 112' in the p-type region 50P, which may resemble the views shown in Figures 19A through 19C. Figures 24A through 24C are intended as illustrative; other materials or configurations are also possible.

[0072] Figures 24A to 24C illustrate embodiments of titanium aluminum (TiAl) deposited using aluminum-based and titanium-based precursors in the second WF layer 118, although other materials or precursors are also possible. For example, Figure 24A illustrates the use of trimethylaluminum (Al2(CH3)6) as an aluminum-based precursor, and Figure 24B illustrates the use of titanium tetrachloride (TiCl4) as a titanium-based precursor, although other precursors are also possible.

[0073] In Figure 24A, the first WF layer 112' is exposed to an aluminum-based precursor, which adsorbs onto and reacts with the Si-O / Si-OH bonds of the silicon-containing layer 116 to form SiOAlx containing Al-O-Si bonds (e.g., aluminum-oxygen-silicon bonds, as shown in Figure 24B). For example, in the absence of the silicon-containing layer 116, TMA molecules react with the -OH bonds on the first WF layer 112 (see Figure 19A) to form Al-methyl bonds at the surface. However, the Si-O / Si-OH bonds in the silicon-containing layer 116 cause the TMA molecules to form Al-O-Si bonds rather than Al-methyl bonds above the first WF layer 112. Figure 24B shows a monolayer SiOAlx, but in other embodiments, multilayer SiOAlx may be formed.

[0074] In Figure 24B, after the formation of Al-O-Si bonds, the first WF layer 112' is exposed to the titanium-based precursor. However, the reaction between the titanium-based precursor and the Al-O-Si bonds is not as readily observed as with other types of surfaces (such as Al-methyl bonds). Therefore, the formation of the initial titanium-aluminum layer is slowed down due to the reduced reaction rate between the titanium-based precursor and the Al-O-Si bonds. In this way, a thinner second WF layer 118' can be formed on the first WF layer 112'. Figure 24C illustrates the second WF layer 118', which comprises a titanium-aluminum monolayer; however, in other cases, multiple cycles of aluminum-based and titanium-based precursors can be used to form a titanium-aluminum multilayer.

[0075] In some cases, as described herein, the second WF layer 118' formed over the first WF layer 112' having a silicon-containing layer 116 may have a thickness that is about 0% to about 30% smaller than the thickness of the second WF layer 118 formed over the first WF layer 112 without a silicon-containing layer 116. In some cases, the thickness of the second WF layer 118' in the p-type region 50P may be in the range of about 10 Å to about 50 Å, although other thicknesses are also possible.

[0076] As an example, Figure 25 illustrates graph 200 of experimental data, showing the thickness of titanium-aluminum formed using multiple cycles. Closed circles correspond to titanium-aluminum formed on titanium nitride layers that have not undergone silicon immersion process 114, while open circles correspond to titanium-aluminum formed on titanium nitride layers that have undergone silicon immersion process 114. As shown in Figure 25, even with multiple growth cycles, the titanium-aluminum formed over titanium nitride with silicon immersion process 114 has a smaller thickness than the titanium-aluminum formed over titanium nitride without silicon immersion process 114. Therefore, graph 200 shows that silicon immersion process 114, as described herein, can reduce the growth rate and final thickness of the second WF layer 118. Graph 200 is representative; other thicknesses or growth rates are also possible.

[0077] Figures 26A to 26C illustrate the formation of a filler material 121 according to some embodiments to form a gate electrode 120 in an n-type region 50N and a p-type region 50P. The filler material 121 is deposited over a second WF layer 118 in the n-type region 50N to form the gate electrode 120 in the n-type region 50N. The filler material 121 is deposited over a first WF layer 112' and a second WF layer 118' in the p-type region 50P to form the gate electrode 120 in the p-type region 50P. The filler material 121 fills the remaining portion of the opening 108. The filler material 121 may comprise any acceptable low-resistance material. For example, the filler material 121 may be formed of a metal such as tungsten, aluminum, cobalt, ruthenium, combinations thereof, or the like, and may be deposited by ALD, CVD, PVD, or the like. Other materials or deposition techniques are also possible.

[0078] Next, a removal process can be performed to remove excess portions of the gate dielectric layer(s) and gate electrode(s), which are located above the top surfaces of the first interlayer dielectric 104, the contact etch-stop layer 102, and the gate spacer 92. In some embodiments, a planarization process, such as chemical mechanical polishing (CMP), etch-back, a combination thereof, or similar, can be used. The remaining portions of the gate dielectric layers(s) form the gate dielectric 110, and the remaining portions of the gate electrode(s) form the gate electrode 120. When a planarization process is used, the top surfaces of the gate spacer 92, the contact etch-stop layer 102, the first interlayer dielectric 104, the gate dielectric 110, and the gate electrode 120 are flush or coplanar (within process variations).

[0079] In Figures 27A to 27C, a second interlayer dielectric 124 is deposited over the gate spacer 92, the contact etch stop layer 102, the first interlayer dielectric 104, the gate dielectric 110, and the gate electrode 120. In some embodiments, the second interlayer dielectric 124 is a flowable film formed by a flowable CVD method. In some embodiments, the second interlayer dielectric 124 is formed of a dielectric material, such as PSG, BSG, BPSG, USG, or the like, and can be formed by any suitable deposition process, such as CVD, PECVD, or the like.

[0080] In some embodiments, an etch stop layer (ESL) 122 is formed between the second interlayer dielectric 124 and the gate spacer 92, the contact etch stop layer 102, the first interlayer dielectric 104, the gate dielectric 110, and the gate electrode 120. The etch stop layer 122 may be formed from a dielectric material with high etch selectivity for etching the second interlayer dielectric 124, such as silicon nitride, silicon oxide, silicon oxynitride, or the like, and may be formed by any suitable deposition process, such as CVD, ALD, or the like.

[0081] In Figures 28A to 28C, the gate contact 126 and the source / drain contact 128 are configured to contact the gate electrode 120 and the source / drain region 100, respectively. The gate contact 126 can be physically coupled and electrically coupled to the gate electrode 120. The source / drain contact 128 can be physically coupled and electrically coupled to the source / drain region 100.

[0082] As an example of forming gate contact 126 and source / drain contact 128, an opening for gate contact 126 is formed through second interlayer dielectric 124 and etch stop layer 122, and an opening for source / drain contact 128 is formed through second interlayer dielectric 124, etch stop layer 122, first interlayer dielectric 104, and contact etch stop layer 102. Acceptable optical lithography and etching techniques can be used to form the openings. A liner (not shown separately) such as a diffusion barrier layer, adhesive layer, or similar material is formed in the opening, along with a conductive material. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, or the like. The conductive material may be copper, copper alloy, silver, gold, tungsten, cobalt, aluminum, nickel, or the like. A planarization process, such as CMP, can be performed to remove excess material from the surface of second interlayer dielectric 124. The remaining lining and conductive material form the gate contact 126 and the source / drain contact 128 within the opening. The gate contact 126 and the source / drain contact 128 may be formed in different processes or in the same process. Although shown as being formed in the same cross-section, it should be understood that each of the gate contact 126 and the source / drain contact 128 may be formed in different cross-sections to prevent short circuits at the contacts.

[0083] Optionally, a metal-semiconductor alloy region 129 is formed at the interface between the source / drain region 100 and the source / drain contact 128. The metal-semiconductor alloy region 129 may be a silicate region formed from metal silicates (e.g., titanium silicate, cobalt silicate, nickel silicate, etc.), a germanide region formed from metal germanides (e.g., titanium germanide, cobalt germanide, and nickel germanide, etc.), a silicon-germanide region formed from both metal silicates and metal germanides, or similar. The metal-semiconductor alloy region 129 may be formed before the material(s) of the source / drain contact 128 by depositing metal in the opening for the source / drain contact 128 and then performing a thermal annealing process. The metal can be any metal capable of reacting with the semiconductor material of the source / drain region 100 (e.g., silicon, silicon carbide, silicon germanium, germanium, etc.) to form a low-resistance metal-semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal can be formed by deposition processes such as ALD, CVD, PVD, or similar methods. After a thermal annealing process, a cleaning process, such as wet cleaning, can be performed to remove any residual metal from the openings for the source / drain contacts 128, such as removing any residual metal from the surface of the metal-semiconductor alloy region 129. The material for the source / drain contacts 128 can then be formed on the metal-semiconductor alloy region 129.

[0084] Figures 2 through 28C illustrate an embodiment in which the first WF layer 112 is removed from the n-type region 50N after performing silicon immersion process 114. However, in other embodiments, the first WF layer 112 may be removed from the n-type region 50N before performing silicon immersion process 114. Therefore, Figures 29 through 33 illustrate intermediate steps in forming a nanostructure FET, wherein the first WF layer 112 is patterned before performing silicon immersion process 114. Figures 29 through 33 illustrate cross-sectional views similar to the reference cross-section A-A' in Figure 1. Some of the process steps shown in Figures 29 through 33 may be similar to the previously described process steps, and therefore some similar details may not be repeated.

[0085] Figure 29 shows the structure after the first WF layer 112 is deposited over the n-type region 50N and the p-type region 50P, similar to the structure shown in Figure 17A. The structure shown in Figure 29 can be formed using similar techniques or materials used to form the structures shown in Figures 17A to 17C. The first WF layer 112 in Figure 29 can be similar to that previously described for Figures 17A to 17C and can be deposited using similar techniques.

[0086] In Figure 30, according to some embodiments, a mask 157 is formed over the p-type region 50P, and the first WF layer 112 in the n-type region 50N is removed. The mask 157 may include, for example, a photoresist or the like, and may be similar to the mask 117 previously described with respect to Figures 20A through 20C. The mask 157 may be formed using suitable techniques (e.g., spin-on or the like) and patterned using suitable optical lithography techniques to expose the n-type region 50N. In this manner, the first WF layer 112 in the p-type region 50P is protected, and the first WF layer 112 in the n-type region 50N is exposed.

[0087] Referring again to Figure 30, according to some embodiments, an etching process is performed to remove the first WF layer 112 in the n-type region 50N. The etching process removes the first WF layer 112 to expose the underlying gate dielectric 110 of the n-type region 50N. A mask 157 protects the first WF layer 112 in the p-type region 50P from the etching process. The etching process may include a wet etching process and / or a dry etching process. In some cases, the etching process may selectively etch the first WF layer 112 while little or no etching of the gate dielectric 110. The etching process may be similar to the processes previously described with respect to Figures 21A through 21C.

[0088] In Figure 31, according to some embodiments, mask 157 is removed and a silicon immersion process 114 is performed. Mask 157 can be removed using suitable techniques, such as etching, ashing, or the like. After mask 157 is removed, gate dielectric 110 is exposed in n-type region 50N and first WF layer 112 is exposed in p-type region 50P. Silicon immersion process 114 can be similar to the processes previously described with respect to Figures 18A through 18C. For example, silicon immersion process 114 forms a silicon-containing layer (not shown separately) on the first WF layer 112 in p-type region 50P. In some cases, silicon immersion process 114 can also form a silicon-containing layer (not shown separately) on gate dielectric 110 in n-type region 50N. In some embodiments, any silicon-containing layer formed in n-type region 50N is retained during subsequent processing. After the silicon impregnation process 114 is performed, the first WF layer 112 is referred to herein as the impregnated first WF layer 112' or simply the first WF layer 112'.

[0089] In Figure 32, according to some embodiments, a second WF layer 118 is formed over the n-type region 50N and the p-type region 50P. The second WF layer 118 is formed over the gate dielectric 110 in the n-type region 50N and over the first WF layer 112' in the p-type region 50P. The second WF layer 118 may be similar to the second WF layer 118 previously described with respect to Figures 23A to 23C and may be formed using similar techniques. For example, the second WF layer 118 may contain aluminum. Similar to the previous discussion of the second WF layer 118, the silicon-containing layer of the first WF layer 112' formed by the silicon impregnation process 114 inhibits the formation of the second WF layer 118 on the first WF layer 112'. Therefore, the second WF layer 118 in the p-type region 50P may be formed with a smaller thickness and referred to as the second WF layer 118'.

[0090] In Figure 33, a filler material 121 is deposited over the second WF layer 118 to form a gate electrode 120, similar to that described in Figures 26A to 26C. For example, the gate electrode 120 of the n-type region 50N includes a second WF layer 118 and filler material 121, and the gate electrode 120 of the p-type region 50P includes a first WF layer 112', a second WF layer 118', and filler material 121. The filler material 121 may be similar to that described in Figures 26A to 26C and may be formed using similar techniques. In this way, a gate structure including a gate dielectric 110 and a gate electrode 120 can be formed. This structure can then be processed using appropriate process steps, such as those previously described for Figures 27A to 28C.

[0091] The embodiments offer advantages. Performing a silicon impregnation process on the p-type work function tuning layer modifies the surface of the p-type work function tuning layer, reducing the growth of the n-type work function on the surface. For example, the silicon impregnation process can form a silicon-containing layer on the p-type work function tuning layer, which reduces the growth rate and thickness of the n-type work function tuning layer. The techniques described herein allow for the formation of a thinner n-type work function tuning layer on the p-type work function tuning layer. Forming a thinner n-type work function tuning layer in this manner reduces the amount of material undesirably diffusing from the n-type work function tuning layer into the p-type work function tuning layer. For example, the techniques described herein reduce the diffusion of aluminum from the n-type work function tuning layer into the p-type work function tuning layer. Reducing the amount of aluminum diffusing into the p-type work function tuning layer reduces undesirable effects due to the presence of aluminum in the p-type work function tuning layer, such as increased threshold voltage or reduced flat-band voltage. In this way, the use of silicon impregnation processes as described herein can improve device performance and enhance device uniformity.

[0092] In an embodiment disclosed herein, a method includes depositing a gate dielectric layer on a first channel region; depositing a p-type work function tuning layer on the gate dielectric layer; exposing the p-type work function tuning layer to a silicon-based precursor for a period of time; and depositing an n-type work function tuning layer on the p-type work function tuning layer. In an embodiment, the silicon-based precursor includes at least one of silane, disilane, trisilane, tetrasilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, or tris(dimethylamino)silane. In an embodiment, the p-type work function tuning layer includes titanium nitride. In an embodiment, the n-type work function tuning layer includes aluminum. In an embodiment, exposing the p-type work function tuning layer to the silicon-based precursor forms a silicon oxide layer on the p-type work function tuning layer. In one embodiment, the method includes depositing a gate dielectric layer on a second channel region; and exposing the gate dielectric layer on the second channel region to the silicon-based precursor for a specified duration. In another embodiment, exposing the p-type work function tuning layer to the silicon-based precursor includes a process temperature ranging from 0°C to 900°C. In yet another embodiment, the duration is in the range of 1 second to 600 seconds.

[0093] In an embodiment disclosed herein, a method includes forming a first gate dielectric layer on a first channel region and forming a second gate dielectric layer on a second channel region; forming a first work function tuning layer above the first gate dielectric layer and above the second gate dielectric layer; performing a surface modification process on the first work function tuning layer to form a silicon-containing layer on the first work function tuning layer; removing the first work function tuning layer from the first gate dielectric layer; and forming a second work function tuning layer on the first work function tuning layer above the first gate dielectric layer and above the second gate dielectric layer. In an embodiment, the thickness of the second work function tuning layer on the first gate dielectric layer is greater than the thickness of the second work function tuning layer on the first work function tuning layer. In an embodiment, the growth rate of forming the second work function tuning layer on the first gate dielectric layer is greater than the growth rate of forming the second work function tuning layer on the first work function tuning layer. In an embodiment, the formation of the second work function tuning layer includes an aluminum-based precursor and a titanium-based precursor. In an embodiment, the surface modification process includes exposing a first work function tuning layer to silane molecules or organosilanes. In an embodiment, the surface modification process replaces hydroxyl bonds with silicon-oxygen bonds. In an embodiment, the silicon-containing layer is a silicon oxide monolayer. In an embodiment, forming a second work function tuning layer over the first work function tuning layer includes forming aluminum-oxygen-silicon bonds.

[0094] In the embodiments disclosed herein, the device includes a first gate structure above a first nanostructure, wherein the first gate structure includes a first gate dielectric layer; a first layer of n-type work function tuning material above the first gate dielectric layer; and a metal filler material above the first layer of n-type work function tuning material; and a second gate structure above a second nanostructure, wherein the second gate structure includes a second gate dielectric layer; a first layer of p-type work function tuning material above the second gate dielectric layer; a first silicon-containing layer above the first layer of p-type work function tuning material; a second layer of n-type work function tuning material above the first silicon-containing layer; and a metal filler material above the second layer of n-type work function tuning material. In an embodiment, the thickness of the first layer of n-type work function tuning material is greater than the thickness of the second layer of n-type work function tuning material. In an embodiment, the device includes a silicon-containing layer between the first gate dielectric layer and the first layer of n-type work function tuning material. In an embodiment, the first silicon-containing layer includes at least one silicon oxide monolayer.

[0095] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the nature of this disclosure. Those skilled in the art will understand that this disclosure can be used as a basis for designing or modifying other processes and structures for implementing the embodiments introduced herein and / or achieving the same purposes and / or advantages. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that such equivalent constructions can be modified, replaced, and substituted in various ways without departing from the spirit and scope of this disclosure.

[0096] 50:Substrate 50N: n-type region 50P: p-type area 52: Multi-layer stacking 54: First semiconductor layer 56: Second semiconductor layer 62: Fins 64: Nanostructure 66: Nanostructure 68: Insulating materials 70: Quarantine Zone / STI Zone 72: Dummy Dielectric Layer 74: Virtual gate layer 76: Masking layer 82: Dummy Dielectric 84: Dummy gate 86: Mask 90: Spare layer 92: Gate spacer 94: Fin spacers 96: Source / Drain Groove 97: Side wall groove 98: Internal spacers 100: Source / Drain Region 102: Contact Etching Termination Layer 104: First interlayer dielectric 108: Opening 110: Gate Dielectric 112: First WF layer 112': First WF layer after soaking 114: Silicon Impregnation Process 116: Silicon-containing layer 117: Mask 118: Second WF layer 118': Second WF layer 120: Gate electrode 121: Filling material 122: Etching stop layer 124: Second interlayer dielectric 126: Gate Contact 128: Source / Drain Contacts 129: Metal-Semiconductor Alloy Region 200: Chart

[0097] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A method for forming a semiconductor gate structure, comprising the following steps: depositing a gate dielectric layer on a first channel region and a second channel region; depositing a p-type work function tuning layer on the gate dielectric layer on the first channel region; exposing the p-type work function tuning layer and the gate dielectric layer on the second channel region to a silicon-based precursor for a period of time to form a first silicon-containing layer on the p-type work function tuning layer and a second silicon-containing layer on the gate dielectric layer on the second channel region, the second silicon-containing layer contacting the gate dielectric layer; and depositing an n-type work function tuning layer on the p-type work function tuning layer.

2. The method as claimed in claim 1, wherein the silica-based precursor comprises at least one of silane, disilane, trisilane, tetrasilane, methylsilane, dimethylsilane, ethylsilane, methyldisilane, dimethyldisilane, hexamethyldisilane, or tris(dimethylamino)silane.

3. The method as described in claim 1, wherein the p-type work function tuning layer comprises titanium nitride.

4. The method as described in claim 1, wherein the n-type work function tuning layer comprises aluminum.

5. A method for forming a semiconductor gate structure, comprising the following steps: forming a first gate dielectric layer on a first channel region and forming a second gate dielectric layer on a second channel region; forming a first work function tuning layer above the first gate dielectric layer and above the second gate dielectric layer, the first work function tuning layer being a p-type work function tuning layer; removing the first work function tuning layer above the second gate dielectric layer; performing a surface modification process on the first work function tuning layer and the second gate dielectric layer to form a first silicon-containing layer on the first work function tuning layer and a second silicon-containing layer on the second gate dielectric layer, the second silicon-containing layer contacting the second gate dielectric layer; The first power function tuning layer is removed from the first gate dielectric layer; and a second power function tuning layer is formed on the first gate dielectric layer and above the first power function tuning layer above the second gate dielectric layer, the second power function tuning layer being an n-type power function tuning layer.

6. The method as described in claim 5, wherein the thickness of the second power function tuning layer on the first gate dielectric layer is greater than the thickness of the second power function tuning layer above the first power function tuning layer.

7. The method as described in claim 5, wherein a growth rate for forming the second work function tuning layer on the first gate dielectric layer is greater than a growth rate for forming the second work function tuning layer above the first work function tuning layer.

8. A semiconductor gate structure comprising: a first gate structure above a first plurality of nanostructures, wherein the first gate structure comprises: a first gate dielectric layer; a first layer of an n-type work function tuning material above the first gate dielectric layer; a metal filler material above the first layer of the n-type work function tuning material; and a second silicon-containing layer between the first gate dielectric layer and the first layer of the n-type work function tuning material, wherein the second silicon-containing layer contacts the first gate dielectric layer; and a second gate structure above a second plurality of nanostructures, wherein the second gate structure comprises: a second gate dielectric layer; a first layer of a p-type work function tuning material above the second gate dielectric layer; a first silicon-containing layer above the first layer of the p-type work function tuning material; a second layer of the n-type work function tuning material above the first silicon-containing layer; and the metal filler material above the second layer of the n-type work function tuning material.

9. The semiconductor gate structure as claimed in claim 8, wherein the thickness of the first layer of the n-type work function tuning material is greater than the thickness of the second layer of the n-type work function tuning material.

10. The semiconductor gate structure as described in claim 8, further comprising a silicon-containing layer between the first gate dielectric layer and the first layer of the n-type work function tuning material.

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