Semiconductor device structure and methods of forming the same

Abstract

The embodiments disclosed herein provide a semiconductor device structure and a method for manufacturing the same. This structure includes one or more semiconductor layers disposed on a substrate portion; a source / drain region disposed adjacent to the substrate portion and between the one or more semiconductor layers; and a first stress layer disposed below the source / drain region, wherein an air gap is formed between the first stress layer and the source / drain region.

Description

Technical Field

[0001] none Prior Technology

[0002] The integrated circuit (IC) industry has experienced exponential growth. Technological advancements in IC materials and design have resulted in numerous generations of ICs, each featuring smaller and more complex circuitry than the previous generation. Throughout IC evolution, functional density (the number of interconnects per unit wafer area) has generally increased, while geometric dimensions (the smallest components (or lines) produced by the manufacturing process) have continuously decreased. This miniaturization generally provides benefits such as increased production efficiency and reduced associated costs. However, this scale reduction also increases the complexity of processing and manufacturing ICs.

[0003] Therefore, there is an urgent need to improve the processing and manufacturing methods of ICs. Summary of the Invention

[0004] none Simple Explanation of the Diagram

[0005] The various features disclosed herein are best understood when read in conjunction with the accompanying drawings and detailed description. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily scaled for clarity of discussion. Figures 1, 2, 3, 4 and 5 are perspective views illustrating the various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 6A, 6B, 6C and 6D are cross-sectional side views illustrating a semiconductor device structure according to Figure 5 of some embodiments. Figures 7A, 7B, 7C and 7D are cross-sectional side views illustrating one of the process stages of a semiconductor device structure according to some embodiments. Figures 8A and 8B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 9A and 9B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, of the various process stages of the semiconductor device structure according to some embodiments. Figures 10A and 10B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 11A and 11B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 12A and 12B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 13A, 13B, and 13C are cross-sectional side views taken along line segments AA, DD, and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 14A and 14B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 15A and 15B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 16A and 16B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 17A and 17B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 18A and 18B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 19A and 19B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 20A and 20B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 21A and 21B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 22A and 22B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 23A and 23B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 24A and 24B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 25A and 25B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 26A and 26B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 27A and 27B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 28A and 28B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 29A and 29B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 30A and 30B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 31A and 31B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 32A and 32B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 33A and 33B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 34A and 34B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 35A and 35B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 36A and 36B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Figures 37A and 37B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 38A and 38B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 39A and 39B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, of the various process stages of the semiconductor device structure according to some embodiments. Figures 40A and 40B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, according to various process stages of the semiconductor device structure of some embodiments. Figures 41A and 41B are cross-sectional side views taken along line segments AA and DD of Figure 5, respectively, at various stages of the manufacturing process of a semiconductor device structure according to some embodiments. Implementation

[0006] The following disclosure provides numerous different embodiments or examples to implement various features of this disclosure. The specific examples of elements and configurations described below are for the purpose of simplifying this disclosure. Of course, these are merely examples and are not intended to be limiting. For example, a description of a first feature formed above or on a second feature includes embodiments where the first and second features are in direct contact, and may also include embodiments where other features are formed between the first and second features, such that the first and second features are not in direct contact. Furthermore, element symbols and / or letters may be repeated in various instances of this disclosure. This repetition is for the purpose of simplicity and clarity and does not imply a relationship between the various embodiments and / or configurations discussed.

[0007] In addition, spatially relative terms, such as "beneath," "below," "lower," "above," "over," "on," "top," and "upper," are used to conveniently describe the relationship between one element or feature and another in a diagram. These spatially relative terms cover not only the orientation depicted in the diagram but also other orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatially relative terms used in this disclosure can be interpreted accordingly.

[0008] The embodiments disclosed herein provide a semiconductor device structure having an air gap between a dielectric layer and the bottom of the source / drain region to increase the carrier mobility of the source / drain region. In some embodiments, the dielectric layer is formed on the top surface of the source / drain region to further improve the carrier mobility of the source / drain region.

[0009] While the embodiments disclosed herein relate to nanostructured channel field-effect transistors (FETs), such as gate-all-around (GAA) FETs, including horizontal gate-all-around (HGAA) or vertical gate-all-around (VGAA) FETs, some embodiments of this disclosure can be applied to other processes and / or other devices, such as planar FETs, fin field-effect transistors (FinFETs), and other suitable devices. Those skilled in the art will understand that modifications and refinements can be made within the scope of this disclosure. When employing a gate-all-around FET, the FET can be patterned using any suitable method. For example, this structure can be patterned using one or more photolithography processes, including dual-patterning or multi-patterning processes. Generally, dual or multiple patterning processes combine photolithography with self-alignment processes to create a smaller pitch than that achieved using a single, direct photolithography process. For example, in one embodiment, a sacrificial layer is formed over a substrate and patterned using a photolithography process. Spacer walls are formed along the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacer walls can be patterned to form a wraparound gate structure.

[0010] Figures 1 through 24B illustrate examples of a method of manufacturing a semiconductor device structure 100 according to an embodiment of the present disclosure. It should be understood that additional operations may be provided before, during, and after the processes shown in Figures 1 through 24B, and some of the operations described below may be replaced or removed to implement other embodiments. The order of operations / processes is not limited and is interchangeable.

[0011] Figures 1 through 5 are perspective views illustrating various stages of the fabrication process of a semiconductor device structure 100 according to some embodiments. As shown in Figure 1, the semiconductor device structure 100 includes a stacked semiconductor layer 104 formed on the front side of a substrate 101. The substrate 101 may be a semiconductor substrate. The substrate 101 may include crystalline semiconductor materials, such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GeAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimony phosphide (GaSbP), gallium antimony arsenide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers to increase its performance. In one embodiment, the aforementioned insulating layer is an oxygen-containing layer.

[0012] The substrate 101 may include various regions doped with impurities (such as dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants may be, for example, phosphorus for n-type field effect transistors (NFETs) and boron for p-type field effect transistors (PFETs).

[0013] The stacked semiconductor layer 104 includes overlapping semiconductor layers made of different materials to facilitate the formation of nanostructure channels in a multi-gate device (e.g., a nanostructure channel field-effect transistor). In some embodiments, the stacked semiconductor layer 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the stacked semiconductor layer 104 includes overlapping first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials with different etch selectivity and / or oxidation rates. For example, the first semiconductor layer 106 may be made of silicon, and the second semiconductor layer 108 may be made of silicon-germanium. In some examples, the first semiconductor layer 106 may be made of silicon-germanium, and the second semiconductor layer 108 may be made of silicon. In addition, in some embodiments, either the first semiconductor layer 106 or the second semiconductor layer 108 may be or include other materials, such as germanium, silicon carbide, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, indium antimonide, gallium arsenide, aluminum indium arsenide, aluminum gallium arsenide, indium gallium arsenide, gallium phosphide, indium gallium arsenide, or any combination thereof.

[0014] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process (e.g., epitaxy). For example, the epitaxial growth of the stacked semiconductor layer 104 is performed by molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), and / or other suitable epitaxial growth processes.

[0015] The first semiconductor layer 106, or a portion thereof, forms nanostructure channels of the semiconductor device structure 100 in subsequent process stages. The term "nanostructure" in this disclosure refers to any material portion having nanometer-scale or even micrometer-scale dimensions and an elongated shape, regardless of its cross-sectional shape. Therefore, the term refers to elongated material portions with circular or substantially circular cross-sections, and bundles or strips of material portions including, for example, cylindrical or substantially rectangular cross-sections. The nanostructure channels of the semiconductor device structure 100 may be surrounded by gates. The semiconductor device structure 100 includes nanostructure transistors. Nanostructure transistors may be nanosheet transistors, nanowire transistors, all-around gate transistors, multi-bridge channel (MBC) transistors, or any transistor having gates surrounding the channel. The following further discusses the use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100.

[0016] The thickness of each first semiconductor layer 106 is in the range of about 5 nm to about 30 nm. The thickness of each second semiconductor layer 108 is equal to, less than or greater than the thickness of the first semiconductor layer 106. In some embodiments, the thickness of each second semiconductor layer 108 is in the range of about 2 nm to about 50 nm. The three first semiconductor layers 106 and the three second semiconductor layers 108 are alternately arranged, as shown in Figure 1, for illustrative purposes and not intended to limit the scope of the claims described. It is understood that any number of first semiconductor layers 106 and second semiconductor layers 108 may be formed on the stacked semiconductor layers 104, and the number of layers depends on the predetermined number of channels in the semiconductor device structure 100.

[0017] As shown in Figure 2, the fin structure 112 is composed of stacked semiconductor layers 104. The upper portion of each fin structure 112 includes a first semiconductor layer 106, a second semiconductor layer 108, and a substrate portion 116 composed of a substrate 101. The fin structure 112 is formed by patterning a hard mask layer (not shown) formed on the stacked semiconductor layers 104 using a multi-patterning operation including photolithography and etching processes. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The photolithography process includes forming a photoresist layer (not shown) over the hard mask layer; exposing the photoresist layer to form a pattern; performing a post-exposure baking process; and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, an electron beam (e-beam) lithography process may be used to pattern the photoresist layer to form a mask element. The etching process penetrates the hard mask layer and stacked semiconductor layers 104 in the unprotected area and enters the substrate 101 to form trenches 114, thereby leaving a plurality of extending fin structures 112. The trenches 114 extend along the X direction. The trenches 114 are etched by dry etching (e.g., RIE), wet etching, and / or combinations thereof. In some embodiments, each fin structure 112 has a longitudinal axis along the X direction.

[0018] As shown in Figure 3, after the fin structure 112 is formed, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structure 112 is embedded in the insulating material 118. Then, a planarization operation (such as chemical mechanical polishing (CMP) and / or etching back) is performed to expose the top of the fin structure 112. The insulating material 118 is made of silicon oxide, silicon nitride, silicon oxynitride (SiON), silicon carbonitride (SiOCN), silicon carbonitride (SiCN), fluorine-doped silicate glass (FSG), low dielectric constant (low K) material, or any suitable dielectric material. The insulating material 118 is formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced chemical vapor deposition (PECVD), or flowable chemical vapor deposition (FCVD).

[0019] As shown in Figure 4, the insulating material 118 is recessed to form an isolation region 120. The recesses in the insulating material 118 expose portions of the fin-like structures 112, such as the stacked semiconductor layer 104. The recesses in the insulating material 118 also expose trenches 114 between adjacent fin-like structures 112. The isolation region 120 is formed using a suitable process, such as a dry etching process, a wet etching process, or a combination thereof. The top surface of the insulating material 118 is flush with or below the surface of the second semiconductor layer 108 that contacts the substrate portion 116 formed from the substrate 101.

[0020] As shown in Figure 5, one or more sacrificial gate structures 130 (only one is shown in the figure) are formed over the semiconductor device structure 100. The sacrificial gate structure 130 is formed over a portion of the fin structure 112. Each sacrificial gate structure 130 includes a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a masking layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136 are formed by sequentially depositing a blanket layer of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the masking layer 136, and patterning these layers into the sacrificial gate structure 130. Then, a gate spacer 138 is formed on the sidewall of the sacrificial gate structure 130. For example, the gate spacer 138 is formed by conformally depositing one or more layers for the gate spacer 138 and anisotropically etching the one or more layers. In some embodiments, a gate gap wall 138 is also formed on the sidewall of the exposed portion of the fin structure 112. Although the figures only show one sacrificial gate structure 130, in some embodiments, two or more sacrificial gate structures 130 may be configured along the X direction.

[0021] The sacrificial gate dielectric layer 132 may comprise one or more layers of dielectric material, such as a silicon oxide-based material. The sacrificial gate electrode layer 134 may comprise silicon, such as polycrystalline silicon or amorphous silicon. The masking layer 136 may comprise more than one layer, such as an oxide layer and a nitride layer. The gate spacer 138 may be made of a dielectric material, such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or combinations thereof.

[0022] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as the channel region of the semiconductor device structure 100.

[0023] Figures 6A, 6B, 6C, and 6D are cross-sectional side views of a semiconductor device structure 100 according to some embodiments, taken along lines AA, BB, CC, and DD of Figure 5, respectively. As shown in Figures 6A, 6B, 6C, and 6D, in some embodiments, the mask layer 136 includes an oxide layer 136a and a nitride layer 136b, and the gate spacer wall 138 includes a first gate spacer wall 138a and a second gate spacer wall 138b. Furthermore, in some embodiments, the gate spacer wall 138 is formed around the exposed portion of the fin structure 112, as shown in Figure 6D.

[0024] Figures 7A, 7B, 7C, and 7D are cross-sectional side views of a semiconductor device structure 100 according to some embodiments, taken along lines AA, BB, CC, and DD of Figure 5, respectively. As shown in Figures 7A to 7D, the portion of the fin structure 112 not covered by the sacrificial gate structure 130 and the gate spacer 138 is recessed onto, at, or below the top surface of the isolation region 120. The recessed portion of the fin structure 112 can be formed by an etching process (isotropic etching or anisotropic etching), and the etching process can be selective for one or more crystal planes of the substrate 101. The etching process can be dry etching, such as RIE, NBE, etc., or wet etching, such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant. In some embodiments, as shown in Figures 7B and 7D, a portion of the insulating material 118 of the isolation region 120 is also removed during the recessing process of the exposed portion of the fin structure 112. In some embodiments, the horizontal portions of the gate gap wall 138a and gate gap wall 138b are removed, as shown in Figures 7A, 7B, 7C, and 7D. In some embodiments, a portion of the second gate gap wall 138b formed around the exposed portion of the fin structure 112 is removed, and a portion of the first gate gap wall 138a formed around the exposed portion of the fin structure 112 is recessed, as shown in Figure 7D.

[0025] Figures 8A, 9A, 10A, 11A, 12A, 13A, 14A, 15A, 16A, 17A, 18A, 19A, 20A, 21A, 22A, 23A, and 24A are cross-sectional side views of the various manufacturing stages of the semiconductor device structure 100 according to some embodiments, taken along line segment AA of Figure 5. Figures 8B, 9B, 10B, 11B, 12B, 13B, 13C, 14B, 15B, 16B, 17B, 18B, 19B, 20B, 21B, 22B, 23B, and 24B are cross-sectional side views taken along line segment DD of Figure 5, showing various stages of the manufacturing process of the semiconductor device structure 100 according to some embodiments. In some embodiments, as shown in Figures 8A and 8B, the semiconductor device structure 100 includes a first region 202 and a second region 204. In some embodiments, the first region 202 is a p-type metal-oxide-semiconductor (PMOS) region; the second region 204 is an n-type metal-oxide-semiconductor (NMOS) region. In some embodiments, the first region 202 is an NMOS region; the second region 204 is a PMOS region. Although not shown to scale in some figures, the first region 202 and the second region 204 belong to a continuous substrate 101. In some embodiments, a first-type device (e.g., an n-type device or a p-type device) may be formed in the first region 202, while a second-type device (e.g., a p-type device or an n-type device) may be formed in the second region 204. The first and second types are opposite to each other. The N-type device may be an n-type field-effect transistor, and the P-type device may be a p-type field-effect transistor.

[0026] As shown in Figure 8A, the edge portions of each second semiconductor layer 108 of the stacked semiconductor layers 104 in the first region 202 and the second region 204 are horizontally removed along the X direction. A cavity is formed at the removal site of the edge portion of the second semiconductor layer 108. In some embodiments, portions of the second semiconductor layer 108 are removed via a selective wet etching process. In an example where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the second semiconductor layer 108 can be selectively etched using a wet etchant, wherein the wet etchant can be, for example but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution.

[0027] After removing the edge portions of each of the second semiconductor layers 108, a dielectric layer is deposited in the cavity to form dielectric spacers 144. The dielectric spacers 144 can be made of a low-k material, such as SiON, SiCN, silicon oxide (SiOC), SiOCN, or silicon nitride (SiN). The dielectric spacers 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., atomic layer deposition, ALD), followed by anisotropic etching to remove portions of the conformal dielectric layer excluding the dielectric spacers 144. During the anisotropic etching process, the dielectric spacers 144 are protected by the first semiconductor layer 106. The remaining second semiconductor layers 108 can cover the spacers 144 along the X-direction.

[0028] In some embodiments, the second semiconductor layer 108 is removed and replaced with a dielectric material such as high-density SiN or SiO, rather than removing the edge portions of each second semiconductor layer 108. The edge portions of the dielectric material are removed, and dielectric spacer walls 144 are formed to cover the dielectric material.

[0029] As shown in Figures 9A and 9B, dielectric layer 137 is formed in second region 204. Dielectric layer 137 covers material (particularly semiconductor material) to prevent the semiconductor material from epitaxially growing from the semiconductor material in second region 204. Dielectric layer 137 may contain any suitable material. In some embodiments, dielectric layer 137 is an oxide, such as a metal oxide. In some embodiments, dielectric layer 137 is a nitride, such as silicon nitride. As shown in Figures 9A and 9B, dielectric layer 137 is a conformal layer formed by a conformal process, such as an ALD process. In some embodiments, dielectric layer 137 is first formed on the surfaces of first region 202 and second region 204, and a mask layer (not shown) is formed on a portion of dielectric layer 137 in second region 204. The exposed portion of dielectric layer 137 in first region 202 is removed. The mask layer may be any suitable mask layer, such as a photoresist layer or a bottom antireflective coating (BARC). Then, the masking layer in the second region 204 is removed to expose the dielectric layer 137.

[0030] As shown in Figures 10A and 10B, semiconductor material 145 and source / drain (S / D) region 146 are formed in first region 202. In some embodiments, semiconductor material 145 comprises undoped silicon and is formed epitaxially. In some embodiments, S / D region 146 may be grown vertically and horizontally into facets that may be opposite to the crystal surfaces of the materials applied to semiconductor material 145 and first semiconductor layer 106. In this disclosure, source region and drain region are used interchangeably and their structures are substantially the same. Additionally, source / drain region may refer individually or collectively to source or drain, depending on the context. For n-type channel field-effect transistors, the S / D region 146 is made of one or more layers of Si, silicon phosphide (SiP), silicon carbide (SiC), and silicon carbide phosphide (SiCP), while for p-type channel field-effect transistors, the S / D region 146 is made of one or more layers of Si, SiGe, and Ge. For p-type channel field-effect transistors, p-type dopants (e.g., boron (B)) are also included in the S / D region 146. The S / D region 146 is formed by epitaxial growth using CVD, ALD, or MBE. In some embodiments, the first region 202 is an NMOS region, and the S / D region 146 is made of one or more layers of Si, SiP, SiC, and SiCP. In some embodiments, the first region 202 is a PMOS region, and the S / D region 146 is made of one or more layers of Si, SiGe, and Ge. In some embodiments, the S / D region 146 is used for n-type channel field-effect transistors, and the S / D region 146 includes carbon that can provide tensile stress on the S / D region 146. In some embodiments, the S / D region 146 is used for p-type channel field-effect transistors, and the S / D region 146 includes germanium that can provide compressive stress. Compressive stress or tensile stress is a type of longitudinal stress that, when applied to the S / D region 146, can increase the mobility of charge carriers.

[0031] As shown in Figures 11A and 11B, dielectric layer 137 is removed in second region 204. Dielectric layer 137 can be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, dielectric layer 137 is removed by a selective etching process that does not substantially affect other materials of the semiconductor device structure 100.

[0032] As shown in Figures 12A and 12B, a stress layer 148 is deposited on the surfaces of the first region 202 and the second region 204. The stress layer 148 is deposited around the S / D region 146 in the first region 202 and on the substrate portion 116 in the second region 204, as shown in Figure 12B. The stress layer 148 may include a material that can influence the longitudinal stress of the S / D region 146. For example, by forming the stress layer 148 on top of the S / D region 146, the stress layer 148 can provide lateral stress to influence the longitudinal stress. The effect of the lateral stress on the longitudinal stress is based on the Young's modulus and Poisson's ratio of the material. In some embodiments, the stress layer 148 comprises silicon nitride (Si3N4) with a Young's modulus higher than that of the semiconductor material of the S / D region 146 and a Poisson's ratio in the range of about 0.23 to about 0.28. In some embodiments, the stress layer 148 comprises multiple layers. For example, stress layer 148 may include a Si3N4 layer and a silicon dioxide (SiO2) layer disposed on the Si3N4 layer. Even though the Young's modulus and Phuoc's ratio of the SiO2 layer are smaller than those of the Si3N4 layer, the SiO2 layer can form an air gap 149 (Figures 15A and 15B) in the second region 204, which will be described in detail below.

[0033] In some embodiments, the first region 202 is an NMOS region, and the stress layer 148 can apply tensile stress to the S / D region 146 to improve charge carrier mobility. In some embodiments, the first region 202 is a PMOS region, and the stress layer 148 can apply compressive stress to the S / D region 146 to improve charge carrier mobility. In some embodiments, the stress layer 148 includes a Si3N4 layer to which compressive stress can be applied or a Si3N4 layer to which tensile stress can be applied.

[0034] In some embodiments, the thickness of the stress layer 148 may be varied. For example, a portion of the stress layer 148 formed on the top surface of the S / D region 146 has a thickness T1, a portion of the stress layer 148 formed on the sidewall of the S / D region 146 has a thickness T2, a portion of the stress layer 148 formed on the insulating material 118 in the first region 202 has a thickness T3, and portions of the stress layer 148 formed on the substrate portion 116 and on the insulating material 118 in the second region 204 have a thickness T4. In some embodiments, thickness T1 is greater than both thickness T2 and thickness T3, and thickness T1 and thickness T4 are substantially the same. In some embodiments, the stress layer 148 is deposited by chemical vapor deposition, and the thickness of the portion of the stress layer 148 formed on the horizontal surface is greater than the thickness of the portion of the stress layer 148 formed on the vertical surface. Furthermore, the insulating material 118 in the first region 202 is located at the bottom of the opening defined by the S / D region 146, and the insulating material 118 and substrate portion 116 in the second region 204 are more exposed than the insulating material 118 in the first region 202. Therefore, in some embodiments, as shown in Figure 12B, the thickness T3 of a portion of the stress layer 148 is less than the thickness T4 of a portion of the stress layer 148 formed on the substrate portion 116 and the insulating material 118 in the second region 204. In some embodiments, a portion of the stress layer 148 formed on the masking layer 136 in the first region 202 and the second region 204 has a thickness T1 or a thickness T4.

[0035] As shown in Figures 13A and 13B, a trimming process is performed on the stress layer 148. In some embodiments, the stress layer 148 is removed except for portions formed on the S / D region 146 in the first region 202 and portions formed on the insulating material 118 and substrate portion 116 in the second region 204. As described above, the stress layers 148 have different thicknesses. Therefore, the trimming process (which may be a dry etching process or a wet etching process) removes the portions of the stress layer 148 with thinner thicknesses, while the portions of the stress layer 148 with thicker thicknesses remain on the semiconductor device structure 100, as shown in Figures 13A and 13B. For example, the thicknesses T1 and T4 of the portions of the stress layer 148 are greater than the thicknesses T2 and T3 of the portions of the stress layer 148. Therefore, by removing portions of the stress layer 148 having thicknesses T2 and T3 through a trimming process, portions of the stress layer 148 having thicknesses T1 and T4 are recessed. In some embodiments, although not shown in the figures, portions of the stress layer 148 formed on the masking layer 136 are also retained.

[0036] Figure 13C reveals another embodiment of the stress layer 148 comprising a first layer 148a and a second layer 148b. In some embodiments, the first layer 148a is made of Si3N4, and the second layer 148b is made of SiO2. The first layer 148a, made of Si3N4, contacts the S / D region 146 in the first region 202 to improve the charge carrier mobility of the S / D region 146. The second layer 148b, made of SiO2, is formed over the substrate portion 116 in the second region 204 to form an air gap 149 during subsequent processes (Figures 15A and 15B).

[0037] As shown in Figures 14A and 14B, another dielectric layer 137 is formed in the first region 202. Similar to the process described in Figures 9A and 9B, the dielectric layer 137 is first formed in the first region 202 and the second region 204, and a masking layer (not shown) is formed in the first region 202. The exposed portion of the dielectric layer 137 in the second region 204 is removed, and then the masking layer is removed.

[0038] As shown in Figures 15A and 15B, the S / D region 146 is formed in the second region 204, and the air gap 149 is formed between the S / D region 146 and the stress layer 148 in the second region 204. As described above, for an n-type channel field-effect transistor, its S / D region 146 is made of one or more layers of Si, SiP, SiC, and SiCP, while for a p-type channel field-effect transistor, its S / D region 146 is made of one or more layers of Si, SiGe, and Ge. For a p-type channel field-effect transistor, its p-type dopant (e.g., boron (B)) is also included in the S / D region 146. The S / D region 146 is formed by epitaxial growth using CVD, ALD, or MBE. In some embodiments, the second region 204 is an NMOS region, and the S / D region 146 is made of one or more layers of Si, SiP, SiC, and SiCP. In some embodiments, the second region 204 is a PMOS region, and the S / D region 146 is made of one or more layers of Si, SiGe, and Ge. In some embodiments, the S / D region 146 is used for an n-type channel field-effect transistor, and the S / D region 146 includes carbon that can provide tensile stress on the S / D region 146. In some embodiments, the S / D region 146 is used for a p-type channel field-effect transistor, and the S / D region 146 includes germanium that can provide compressive stress. Compressive stress or tensile stress is a type of longitudinal stress that can improve charge carrier mobility when applied to the S / D region 146.

[0039] In some embodiments, to ensure that the air gap 149 is formed between the S / D region 146 and the stress layer 148 in the second region 204, the stress layer 148 includes a first layer 148a and a second layer 148b (Figure 13C). As described above, in some embodiments, the second layer 148b includes SiO2. In some embodiments, the second region 204 is an NMOS region, and a carbon-containing precursor (e.g., methane (CH4)) is used during the formation of the S / D region 146. The carbon-containing precursor reacts with the SiO2 of the second layer 148b to form gases (e.g., CO2 and silane (SiH4)). Therefore, a portion of the top of the second layer 148b is removed to form the air gap 149 in the second region 204, as shown in Figures 15A and 15B. In some embodiments, the second region 204 is a PMOS region, and a germanium-containing precursor (e.g., germane (GeH4)) is used during the formation of the S / D region 146. A germanium-containing precursor reacts with the SiO2 of the second layer 148b to form water-soluble germanium dioxide (GeO2). Therefore, in some embodiments, after the S / D region 146 is formed in the second region 204, the top portion of the second layer 148b is converted into a GeO2 layer. The GeO2 layer is then removed by a wet removal process using water (e.g., deionized water). Thus, a gas gap 149 is formed between the S / D region 146 and the stress layer 148 in the second region 204, as shown in Figures 15A and 15B. To form CO2 and SiH4 gas (if the second region 204 is an NMOS region) or to form a GeO2 layer (if the second region 204 is a PMOS region), a carbon-containing precursor (for the NMOS region) or a germanium-containing precursor (for the PMOS region) can flow into the processing chamber of the semiconductor device structure 100 at different flow rates. For example, the carbon-containing or germanium-containing precursor has the highest flow rate at the beginning of the epitaxial process to form the S / D region 146 in the second region 204, allowing the carbon-containing or germanium-containing precursor to react with the second layer 148b. Therefore, the bottom of the S / D region 146 contains a higher concentration of carbon or germanium compared to other regions of the S / D region 146.

[0040] The stress layer 148 formed in the second region 204 not only prevents the S / D region 146 from growing from the substrate portion 116, but also ensures that an air gap 149 is formed between the S / D region 146 and the stress layer 148. As described above, a carbon-containing precursor or a germanium-containing precursor is included in the formation of the S / D region 146 in the second region 204 to provide tensile or compressive stress on the S / D region 146. Due to the generation of the air gap 149, the lateral growth of the S / D region 146 in the second region 204 along the X direction dominates this process. Therefore, minimum stress loss in the S / D region 146 can be achieved by suppressing the vertical growth of the S / D region 146.

[0041] The longitudinal stress of the S / D region 146 in the first region 202 is increased by including a carbon-containing precursor (for the NMOS region) or a germanium-containing precursor (for the PMOS region) during the formation of the S / D region 146 and by forming a stress layer 148 on the top surface of the S / D region 146 in the first region 202. The stress layer 148 (or the first layer 148a) is amorphous and can be formed by ALD or CVD, which have less stringent lattice matching requirements. The longitudinal stress of the S / D region 146 in the second region 204 is increased by including a carbon-containing precursor (for the NMOS region) or a germanium-containing precursor (for the PMOS region) during the formation of the S / D region and by forming an air gap 149 between the S / D region 146 and the stress layer 148.

[0042] As shown in Figures 16A and 16B, dielectric layer 137 is removed from first region 202. Dielectric layer 137 is removed through a process as described in Figures 11A and 11B. Next, as shown in Figures 17A and 17B, contact etch stop layer (CESL) 162 is conformally formed on the exposed surfaces of semiconductor device structure 100 in first region 202 and second region 204. CESL 162 covers the gate spacer wall 138, insulating material 118, and sidewalls of S / D region 146. CESL 162 comprises oxygen-containing or nitrogen-containing materials, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxynitride, etc., or combinations thereof, and is formed by CVD, PECVD, ALD, or any suitable deposition technique.

[0043] Next, as shown in Figures 18A and 18B, an interlayer dielectric (ILD) 164 is formed on CESL 162 above the semiconductor device structure 100 in the first region 202 and the second region 204. The material of the ILD layer 164 includes compounds containing Si, O, C, and / or H (e.g., silicon oxide, silicon oxyhydrogen carbide (SiCOH), or silicon carbide oxide (SiOC)). Organic materials (e.g., polymers) may also be used for the ILD layer 164. The ILD layer 164 is deposited using a PECVD process or other suitable deposition techniques. In some embodiments, after the formation of the ILD layer 164, the semiconductor device structure 100 is heat-treated to cure the ILD layer 164.

[0044] After the formation of the ILD layer 164, a planarization operation (e.g., CMP) is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed, as shown in Figures 18A and 18B. In some embodiments, after the planarization process, the ILD layer 164 is recessed, and a dielectric layer 166 is formed on the recessed ILD layer 164, as shown in Figures 19A and 19B. The dielectric layer 166 includes a nitride (e.g., silicon nitride) to protect the ILD layer 164 during subsequent processes. A second planarization process is performed to remove portions of the dielectric layer 166 formed on the sacrificial gate electrode layer 134.

[0045] As shown in Figures 20A and 20B, the sacrificial gate structure 130 and the second semiconductor layer 108 are replaced by a gate dielectric layer 170 and a gate electrode layer 172. The removal of the sacrificial gate structure 130 and the second semiconductor layer 108 forms an opening between the gate spacer 138 and the first semiconductor layer 106. The dielectric material of the dielectric layer 166 is substantially unaffected by the removal process. The sacrificial gate structure 130 can be removed using plasma dry etching and / or wet etching. The sacrificial gate electrode layer 134 is first removed by any suitable process, such as dry etching, wet etching, or a combination thereof. Subsequently, the sacrificial gate dielectric layer 132 can also be removed by any suitable process, such as dry etching, wet etching, or a combination thereof. In some embodiments, a wet etchant (e.g., a tetramethylammonium hydroxide (TMAH) solution) can be used to selectively remove the sacrificial gate electrode layer 134, rather than the gate spacer 138 and the dielectric layer 166.

[0046] The second semiconductor layer 108 is removed using a selective wet etching process. In an example where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, the chemicals used in the selective wet etching process remove the SiGe but do not substantially affect the dielectric materials of the silicon, gate spacer 138, dielectric layer 166, and dielectric spacer 144. In one embodiment, the second semiconductor layer 108 can be removed using a wet etchant or a dry etchant, wherein the wet etchant is, for example, but not limited to, hydrofluoric acid (HF), nitric acid (HNO3), hydrochloric acid (HCl), and phosphoric acid (H3PO4); and the dry etchant is, for example, a fluorine-based gas (e.g., F2) or a chlorine-based gas (e.g., Cl2), or any suitable isotropic etchant.

[0047] After forming the nanostructure channel (i.e., the exposed portion of the first semiconductor layer 106), a gate dielectric layer 170 is formed around the exposed portion of the first semiconductor layer 106, and a gate electrode layer 172 is formed on top of the gate dielectric layer 170, as shown in Figures 21A and 21B. The gate dielectric layer 170 and the gate electrode layer 172 system are referred to as the gate structure 174. In some embodiments, an interfacial layer (IL) (not shown) is formed between the gate dielectric layer 170 and the exposed surface of the first semiconductor layer 106. In some embodiments, the gate dielectric layer 170 includes one or more layers of dielectric material (e.g., silicon oxide, silicon nitride, or high dielectric constant materials, other suitable dielectric materials, and / or combinations thereof). Examples of high dielectric constant materials include hafnium dioxide (HfO2), hafnium silicon oxide (HfSiO), hafnium silicon oxynitride (HfSiON), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), hafnium zirconium oxide (HfZrO), zirconium oxide, aluminum oxide, titanium oxide, hafnium dioxide-alumina (HfO2-Al2O3) alloys, other suitable high dielectric constant materials, and / or combinations thereof. The gate dielectric layer 170 is formed using CVD, ALD, or any suitable deposition technique. Gate electrode layer 172 comprises one or more layers of conductive material (e.g., polycrystalline silicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicon, cobalt silicon, titanium nitride (TiN), tungsten nitride (WN), titanium aluminum nitride (TiAl), titanium aluminum nitride (TiAlN), tantalum carbonitride (TaCN), tantalum carbide (TaC), tantalum silicon nitride (TaSiN), metal alloys, other suitable materials, and / or any combination thereof). Gate electrode layer 172 is formed using CVD, ALD, electroplating, or other suitable deposition techniques. Gate electrode layer 172 is also deposited over dielectric layer 166. Then, gate dielectric layer 170 and gate electrode layer 172 formed over dielectric layer 166 are removed by a process such as CMP until the top surface of dielectric layer 166 is exposed.

[0048] As shown in Figures 22A and 22B, conductive contacts 180 are formed in the ILD layer 164 and electrically connected to corresponding S / D regions 146 in the first region 202 and the second region 204. The conductive contacts 180 include one or more conductive materials (e.g., ruthenium, molybdenum, cobalt, nickel, tungsten, titanium, tantalum, copper, aluminum, titanium nitride, and tantalum nitride). A siliconized layer (not shown) is disposed between the conductive contacts 180 and the S / D regions 146.

[0049] In some embodiments, conductive contacts 180 are formed on the front side of the semiconductor device structure 100, as shown in Figures 22A and 22B. In some embodiments, some conductive contacts 180 are formed on the back side of the semiconductor device structure 100, as shown in Figures 23A and 23B. For example, conductive contacts 180 electrically connected to the source region of the S / D region 146 are disposed on the back side of the semiconductor device structure 100, while conductive contacts 180 electrically connected to the drain region of the S / D region 146 are disposed on the front side of the semiconductor device structure 100. In some embodiments, as shown in Figures 24A and 24B, conductive contacts 180 for the source region of the S / D region 146 are disposed on both the front and back sides of the semiconductor device structure 100, while conductive contacts 180 for the drain region of the S / D region 146 are disposed on the front side of the semiconductor device structure 100.

[0050] Figures 25A, 26A, 27A, 28A, 29A, 30A, 31A, 32A, 33A, 34A, 35A, 36A, 37A, 38A, 39A, 40A, and 41A are cross-sectional side views taken along line segment AA of Figure 5, representing various stages of the manufacturing process of the semiconductor device structure 100 according to some alternative embodiments. Figures 25B, 26B, 27B, 28B, 29B, 30B, 31B, 32B, 33B, 34B, 35B, 36B, 37B, 38B, 39B, 40B, and 41B are cross-sectional side views taken along line segment DD of Figure 5, showing the various process stages of the semiconductor device structure 100 according to some alternative embodiments. The semiconductor device structure 100 shown in Figures 25A and 25B represents the same process stage as the semiconductor device structure 100 shown in Figures 8A and 8B. Next, as shown in Figures 26A and 26B, a stress layer 148 is deposited in the first region 202 and the second region 204. As described above, the stress layer 148 can be a single-layer or multi-layer structure. In some embodiments, the stress layer 148 includes a first layer 148a and a second layer 148b (Figure 13C).

[0051] As shown in Figures 27A and 27B, a trimming process is performed on the stress layer 148, and the remaining stress layer 148 is disposed above the substrate portion 116 and the insulating material 118 in the first region 202 and the second region 204. Then, a dielectric layer 137 is formed in the second region 204 to prevent the formation of the S / D region 146 in the second region 204, as shown in Figures 28A and 28B. As shown in Figures 29A and 29B, the S / D region 146 is formed in the first region 202, and an air gap 149 is formed between the S / D region 146 and the stress layer 148. The air gap 149 is formed using a process as described in Figures 15A and 15B. As shown in Figures 30A and 30B, the dielectric layer 137 is removed from the second region 204. Next, as shown in Figures 31A and 31B, another stress layer 210 is formed above the S / D region 146 in the first region 202. The stress layer 210 comprises the same or a different material as the stress layer 148. In some embodiments, the stress layer 148 comprises a first layer 148a and a second layer 148b, and the stress layer 210 comprises a single layer. The single layer of the stress layer 210 comprises Si3N4. In some embodiments, the S / D region 146 in the first region 202 has increased longitudinal stress due to the inclusion of carbon or germanium, the stress layer 210 located on the top surface of the S / D region 146, and the air gap 149 formed between the S / D region 146 and the stress layer 148. Therefore, the charge carrier mobility of the S / D region 146 in the first region 202 can be improved. The stress layer 210 is first deposited in the first region 202 and the second region 204, and then a trimming process is performed to remove portions of the stress layer 210, except for the portion formed on the top surface of the S / D region 146 in the first region 202. Similar to the stress layer 148, the stress layer 210 has a different thickness. As described above, the trimming process on the stress layer 210 with different thicknesses allows the stress layer 210 to remain on the top surface of the S / D region 146 in the first region 202. In some embodiments, a portion of the stress layer 210 (not shown) may remain above the stress layer 148 in the second region 204. In some embodiments, the stress layer 210 is selectively deposited over the semiconductor material of the S / D region 146, but not over the dielectric material of other elements of the semiconductor device structure 100.

[0052] As shown in Figures 32A and 32B, another dielectric layer 137 is formed in the first region 202, and the S / D region 146 is formed in the second region 204. Then, as shown in Figures 33A and 33B, the dielectric layer 137 is removed from the first region 202. Another stress layer 212 is formed on the top surface of the S / D region 146 in the second region 204, as shown in Figures 34A and 34B. The stress layer 212 comprises the same or a different material than the stress layer 210. In some embodiments, the stress layer 212 is selectively deposited over the semiconductor material of the S / D region 146, but not over the dielectric material of other elements of the semiconductor device structure 100. In some embodiments, the S / D region 146 in the second region 204 has increased longitudinal stress due to the presence of carbon or germanium, a stress layer 212 on the top surface of the S / D region 146, and an air gap 149 formed between the S / D region 146 and the stress layer 148. Therefore, the charge carrier mobility of the S / D region 146 in the second region 204 can be improved.

[0053] As shown in Figures 35A and 35B, CESL 162 is deposited in the first region 202 and the second region 204. Then, ILD layer 164 is deposited over CESL 162 in the first region 202 and the second region 204, as shown in Figures 36A and 36B. Dielectric layer 166 is formed over the recessed ILD layer 164, as shown in Figures 37A and 37B. Subsequently, the sacrificial gate structure 130 and the second semiconductor layer 108 are removed and replaced by gate dielectric layer 170 and gate electrode layer 172, as shown in Figures 38A and 38B. After depositing gate electrode layer 172, a CMP process can be performed to remove portions of the gate dielectric layer 170 and gate electrode layer 172 formed over ILD layer 164, and dielectric layer 166 can also be removed via the CMP process.

[0054] As shown in Figures 39A and 39B, conductive contacts 180 are formed on the front side of the semiconductor device structure 100. Conductive contacts 180 for the source region of the S / D region 146 are formed on the back side of the semiconductor device structure 100, as shown in Figures 40A and 40B. In some embodiments, as shown in Figures 41A and 41B, conductive contacts 180 for the source region of the S / D region 146 are disposed on both the front and back sides of the semiconductor device structure 100, while conductive contacts 180 for the drain region of the S / D region 146 are disposed on the front side of the semiconductor device structure 100.

[0055] This disclosure provides a semiconductor device structure and a method for manufacturing the same. In some embodiments, the semiconductor device structure includes an air gap 149 formed between an S / D region 146 and a stress layer 148. Furthermore, the S / D region 146 comprises carbon or germanium, and another stress layer 210 (or stress layer 212) is formed above the S / D region 146. Some embodiments offer advantages. For example, due to the inclusion of carbon or germanium, the stress layer 210 (or stress layer 212) located on the top surface of the S / D region 146, and the air gap 149 formed between the S / D region 146 and the stress layer 148, the longitudinal stress of the S / D region 146 increases. Therefore, the charge carrier mobility of the S / D region 146 can be improved.

[0056] One embodiment is a semiconductor device structure. This structure includes one or more semiconductor layers disposed on a substrate portion; a source / drain region disposed adjacent to the substrate portion and the one or more semiconductor layers; and a first stress layer disposed below the source / drain region, wherein an air gap is formed between the first stress layer and the source / drain region.

[0057] Another embodiment is a semiconductor device structure. This structure includes a first source / drain region configured adjacent to a first substrate portion in a first region; a first stress layer disposed below the first source / drain region in the first region. An air gap is formed between the first stress layer and the first source / drain region. This structure further includes a second source / drain region configured adjacent to a second substrate portion in a second region; and a second stress layer disposed on the top surface of the second source / drain region in the second region.

[0058] Another embodiment is a method for manufacturing a semiconductor device structure. This method includes forming a first fin structure in a first region and forming a second fin structure in a second region, and recessing the first and second fin structures. A first substrate portion is exposed in the first region, and a second substrate portion is exposed in the second region. The method further includes forming a first source / drain region in the first region; forming a stress layer on the top surface of the first source / drain region in the first region and on the second substrate portion in the second region; and forming a second source / drain region above the stress layer in the second region. An air gap is formed between the second source / drain region and the stress layer.

[0059] The foregoing outlines the features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art should understand that this disclosure can serve as the basis for designing or modifying other processes and structures to achieve the same objectives and / or advantages as the embodiments described herein. Those skilled in the art should also understand that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made within this disclosure without departing from its spirit and scope.

[0060] 100: Semiconductor Device Structure 101:Substrate 104: Stacked semiconductor layers 106: First semiconductor layer 108: Second semiconductor layer 112: Fin-like structure 114: Trench 116: Substrate portion 118: Insulating materials 120: Isolation Zone 130: Sacrificial gate structure 132: Sacrificial gate dielectric layer 134: Sacrificial gate electrode layer 136: Masking layer 136a: Oxide layer 136b: Nitride layer 137: Dielectric layer 138: Gate gap wall 138a: Gate gap wall 138b: Gate gap wall 144: Dielectric spacer wall 145: Semiconductor Materials 146: S / D area 148: Stress layer 148a: First layer 148b: Second layer 149: Air gap 162:CESL 164: ILD layer 166: Dielectric layer 170: Gate dielectric layer 172: Gate electrode layer 174: Gate Structure 180: Conductive contact 202: Area 1 204: Second Area 210: Stress layer 212: Stress layer T1, T2, T3, T4: Stress layer thickness

[0061] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor device structure, comprising: One or more semiconductor layers are disposed on a substrate portion; a source / drain region is disposed adjacent to the substrate portion and the semiconductor layers, wherein the source / drain region includes an element, and the concentration of the element decreases from the bottom of the source / drain region upwards; and a first stress layer is disposed below the source / drain region, wherein an air gap is formed between the first stress layer and the source / drain region.

2. The semiconductor device structure as described in claim 1, further comprising: A second stress layer is disposed on the top surface of one of the source / drain regions.

3. The semiconductor device structure as described in claim 2 further includes: A contact etch termination layer is disposed on the second stress layer.

4. The semiconductor device structure as claimed in claim 1, wherein the first stress layer includes a first layer and a second layer, and the second layer is disposed on the first layer.

5. A semiconductor device structure, comprising: A first source / drain region is configured to be adjacent to a first substrate portion in a first region, wherein the first source / drain region includes an element, and the concentration of the element decreases upward from the bottom of the first source / drain region; a first stress layer is disposed below the first source / drain region in the first region, wherein an air gap is formed between the first stress layer and the first source / drain region; a second source / drain region is configured to be adjacent to a second substrate portion in a second region; and a second stress layer is disposed on the top surface of one of the second source / drain regions in the second region.

6. The semiconductor device structure as described in claim 5 further includes: A semiconductor material is configured to be adjacent to the second substrate portion in the second region, and the second source / drain region is disposed on the semiconductor material and in contact with the semiconductor material.

7. The semiconductor device structure as claimed in claim 5, wherein the first stress layer includes a first layer and a second layer, the second layer being disposed on the first layer; and the second stress layer includes the first layer and the second layer, the second layer being disposed on the first layer.

8. A method for manufacturing a semiconductor device structure, comprising: A first fin-like structure is formed in a first region, and a second fin-like structure is formed in a second region; The first fin structure and the second fin structure are recessed, wherein a first substrate portion is exposed in the first region and a second substrate portion is exposed in the second region; a first source / drain region is formed in the first region; a stress layer is formed on a top surface of the first source / drain region in the first region and on the second substrate portion in the second region; and a second source / drain region is formed above the stress layer in the second region, wherein the second source / drain region includes an element, and the concentration of the element decreases from the bottom of the second source / drain region upwards, wherein an air gap is formed between the second source / drain region and the stress layer.

9. A method for manufacturing a semiconductor device structure as described in claim 8, wherein the stress layer includes a first layer and a second layer, and the second layer is disposed on the first layer.

10. A method of manufacturing a semiconductor device structure as claimed in claim 9, wherein a precursor of the second source / drain region reacts with the second layer to form a gas or a water-soluble material.

Images