Semiconductor structure, metal rivet structure and method for fabricating semiconductor structure

Abstract

A semiconductor structure includes: a substrate; a dielectric layer located above the substrate; a second dielectric layer disposed on the dielectric layer; a metal plug disposed in the dielectric layer and including a non-planar top surface of the metal plug, the non-planar top surface of the metal plug defining a groove; and a metal rivet structure. The metal rivet structure includes: a shaft portion passing through the second dielectric layer and including a bottom surface of the shaft portion; and a head portion located in the dielectric layer and including a top surface of the head portion and a non-planar bottom surface of the head portion, wherein the top surface of the head portion is coplanar with the bottom surface of the shaft portion, and the non-planar bottom surface of the head portion engages with the non-planar top surface of the metal plug.

Description

Technical Field

[0001] The embodiments disclosed herein are generally related to metal wires in semiconductor wafers, and more specifically to metal rivet structures and methods of manufacturing thereof. Prior Technology

[0002] The semiconductor industry has experienced rapid development due to the continuous increase in the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.). In most cases, this increase in integration density is due to the iterative reduction in the minimum feature size, which allows more components to be integrated into a given area. However, this shrinkage also increases the complexity of semiconductor manufacturing processes. Therefore, the continued advancement of integrated circuits (ICs) and devices requires similar advancements in semiconductor manufacturing processes and technologies. Summary of the Invention

[0003] none Simple Explanation of the Diagram

[0004] The various features disclosed herein can be best understood by reading the following detailed description in conjunction with the accompanying drawings. It should be noted that, in accordance with industry standard practice, the features are not drawn to scale. In fact, the dimensions of the features may be arbitrarily increased or decreased for clarity of explanation. Figure 1A is a cross-sectional view illustrating an example semiconductor structure according to some embodiments. Figure 1B is a close-up view illustrating a portion of the semiconductor structure of Figure 1A according to some embodiments. Figure 2 is a flowchart illustrating an example method according to some embodiments. Figures 3A to 3D are cross-sectional views illustrating the cross-sections of structures at various manufacturing stages according to some embodiments. Implementation

[0005] The following disclosure provides numerous different embodiments or instances for implementing various features of the provided subject matter. Specific examples of components and configurations are described below to simplify this disclosure. These are, of course, merely examples and are not intended to be limiting. For instance, in the following description, forming a first feature above or on a second feature may include embodiments where the first and second features are formed in direct contact, and may also include embodiments where an additional feature may be formed between the first and second features so that the first and second features do not directly contact each other. Furthermore, reference numerals and / or letters may be repeated in various instances of this disclosure. This repetition is for simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0006] Furthermore, depending on the context, a source / drain region can refer to either a source or a drain, individually or collectively. For example, a device may include a first source / drain region and a second source / drain region, as well as other components. The first source / drain region may be a source region, and the second source / drain region may be a drain region, and vice versa. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0007] Additionally, for ease of description, spatial relative terms such as "below," "under," "lower," "above," "upper," and similar terms are used herein to describe the relationship between one element or feature and another illustrated in the figures. Besides the orientations depicted in the figures, spatial relative terms are also intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein shall be interpreted accordingly.

[0008] Some embodiments of this disclosure are described. Additional operations may be provided before, during, and / or after the stages described in these embodiments. For different embodiments, some of the described stages may be substituted or eliminated. For different embodiments, some features described below may be substituted or eliminated, and additional features may be added. Although some embodiments are discussed where operations are performed in a particular order, these operations may be performed in another logical order.

[0009] Overview

[0010] The resistivity of metal wires in the back-end-of-line (BEOL) process of semiconductor wafers is a key factor affecting their performance and power consumption. Historically, aluminum was the primary metal used for interconnects, but due to its limitations, copper (Cu) has become the dominant material. As a material for metal wires, copper has the following advantages: low resistivity (approximately 1.72 microohm-cm), high conductivity, and good electromigration resistance.

[0011] Various factors affect the resistivity of BEOL wire. The inherent resistivity of the metal itself is a fundamental factor. Copper, with its lower resistivity, is superior to aluminum. Resistivity increases with temperature, thus affecting the overall performance of the wafer. Defects and impurities introduced during the manufacturing process increase resistivity. Mechanical stress alters the crystal structure of the metal, thereby affecting its resistivity.

[0012] Furthermore, geometry plays a crucial role in influencing the resistivity of BEOL wires. The dimensions of the wire (including width and thickness) affect resistance. As characteristic dimensions (e.g., the critical size or "CD") decrease, the relative effects of surface scattering and grain boundary scattering increase, leading to higher resistivity. Surface scattering and grain boundary scattering are two major mechanisms that contribute to the scattering of charge carriers (electrons and holes) in semiconductor materials. These scattering events can significantly affect the conductivity and other properties of semiconductors.

[0013] Surface scattering occurs when charge carriers interact with the surface of a semiconductor material. Surface atoms possess electronic properties different from bulk atoms, thus creating a potential barrier for scatterable carriers. Various factors, such as surface roughness, surface defects, surface treatments (e.g., oxidation, passivation), and the like, can influence surface scattering.

[0014] In polycrystalline metals, grain boundaries are the interfaces between different crystallites. These boundaries disrupt the periodic lattice structure and can act as scattering centers for charge carriers. Grain size distribution, grain boundary orientation, and grain boundary defects all determine grain boundary scattering.

[0015] Tungsten (W) is a key material for through-holes (TH) in semiconductor wafers due to its unique properties. Tungsten exhibits low resistivity, ensuring efficient conduction of electrical signals through TH. Tungsten can conformally fill THs with high aspect ratios, ensuring reliable electrical connections even in deep and narrow structures. Tungsten's high melting point allows it to withstand the high temperatures involved in semiconductor manufacturing processes. Tungsten is resistant to electromigration, a phenomenon that can lead to degradation and failure of metal interconnects. Furthermore, tungsten films have low inherent stress, reducing the risk of mechanical stress-induced failures in the wafer. Additionally, tungsten exhibits good adhesion to silicon and other materials used in semiconductor manufacturing.

[0016] Compared to aluminum, tungsten offers lower resistivity and better electromigration resistance, making it a more suitable choice for advanced semiconductor technologies. While copper is widely used for interconnects due to its low resistivity, tungsten can be a viable alternative in certain applications, particularly for vias with high aspect ratios or where copper diffusion is a concern.

[0017] Therefore, tungsten is widely used in various applications of semiconductor wafers. One of these applications is vertical interconnects. Tungsten is used to fill through-holes connecting different layers of the wafer, thereby enabling vertical signal transmission. Another application is contact plugs. Tungsten plugs are used to connect active devices (such as transistors) to metal interconnects, thereby ensuring reliable electrical contact.

[0018] In one example, tungsten is used as the material for the metal plug in the first contact layer (sometimes referred to as the "VD layer"), which lies between the first metal layer (sometimes referred to as the "MO layer") and the device connection layer (sometimes referred to as the "metal diffusion layer" or "MD layer"). As explained above, with the reduction of critical dimensions in advanced technology nodes (e.g., the 2nm node or "N2"), the resistance of the metal plug in the VD layer increases due to the effects of surface scattering and grain boundary scattering. It should be noted that although the VD layer is used as an example, the techniques disclosed herein are also applicable to other layers, such as "VG".

[0019] One approach to this problem is to utilize alternative metallic materials with lower resistivity, longer electron mean free path (i.e., the average distance an electron travels between collisions with other particles), and acceptable cost. However, integrating new materials with existing or known process flows is often challenging. For example, some (not all) new materials may react with existing process chemicals, leading to contamination or degradation of the equipment. Differences in the coefficients of thermal expansion between new and existing materials can introduce stress and defects during heat treatment steps. Some (not all) new materials may have different etching and deposition rates, requiring adjustments to process parameters to achieve the desired results. Furthermore, patterning some (not all) new materials may require modifications to photoresist, exposure tools, and etching processes. In addition, existing manufacturing equipment may be incompatible with new materials, necessitating modifications or the use of new tools. Optimizing the manufacturing processes for some (not all) new materials can be time-consuming and costly due to the extensive iterations and experimentation involved. Improving or acquiring new equipment can be a significant investment.

[0020] Therefore, it is necessary to reduce the resistance of the BEOL wire without changing the materials and to ensure compatibility with current processes such as barrier-free contact (BFC) processes. BFC is a critical process in semiconductor manufacturing, designed to reduce the contact resistance between metal interconnects and semiconductor devices. In conventional contact formation, a barrier layer (typically a metal silicate) is formed between the metal interconnect and the semiconductor. While preventing unwanted reactions, the barrier layer also introduces additional resistance. BFC eliminates the need for a barrier layer, allowing the metal interconnect to be directly connected to the semiconductor. This direct contact significantly reduces contact resistance, resulting in improved device performance. Integrating BFC into existing manufacturing processes requires careful optimization to avoid introducing defects or impairing device yield.

[0021] According to some embodiments disclosed herein, a semiconductor structure is provided. The semiconductor structure includes a substrate; a dielectric layer located above the substrate; a low-k dielectric layer disposed on the dielectric layer; a metal plug disposed in the dielectric layer and characterized by a non-planar top surface of the metal plug, the non-planar top surface of the metal plug defining a groove; and a metal rivet structure. The metal rivet structure includes: a shaft portion passing through the low-k dielectric layer and characterized by a bottom surface of the shaft portion; and a head portion disposed in the dielectric layer and characterized by a top surface of the head portion and a non-planar bottom surface of the head portion. The top surface of the head portion and the bottom surface of the shaft portion are coplanar, and the non-planar bottom surface of the head portion mates with the non-planar top surface of the metal plug.

[0022] As will be explained in more detail below, the increased surface area of ​​the interface between the metal rivet structure and the metal plug reduces contact resistance. Furthermore, since copper has a lower resistivity than tungsten, replacing a portion of the metal plug with a copper-containing head portion further reduces contact resistance. Details of these features will be discussed below with reference to Figures 1A through 3D.

[0023] Example semiconductor structure

[0024] Figure 1A is a cross-sectional view illustrating an example semiconductor structure 100 according to some embodiments. Figure 1B is a close-up view illustrating a portion of the semiconductor structure of Figure 1A according to some embodiments. It should be understood that Figures 1A and 1B are not drawn to scale.

[0025] In the example shown in Figure 1A, semiconductor structure 100 is located in a VD layer and an M0 layer above the VD layer. As explained above, the VD layer is located below the M0 layer and above the MD layer, providing an interconnect between the MD layer and the M0 layer. Therefore, metal tracks in the MD layer (which are electrically connected to the source and drain of a semiconductor device fabricated, for example, in a substrate (not shown) below the MD layer) can be electrically connected to metal wires in the M0 layer, which is the first metal layer in a multi-layer interconnect (MLI) structure fabricated at the back end of a semiconductor wafer using a BEOL process. It should be understood that the techniques disclosed herein are generally applicable to various types of semiconductor devices, such as Gate-All-Around Field-Effect Transistors (GAAFETs) and Complementary Field-Effect Transistors (CFETs), and their corresponding M0, VD, and MD layers.

[0026] Among other components, the semiconductor structure 100 includes a metal track 112 in the MD layer, a dielectric layer 114 in the VD layer, a metal plug 116 in the VD layer, an etch stop layer 132 between the VD layer and the MD layer, a second dielectric layer (e.g., a low-k dielectric layer) 134, and a metal contact structure (also referred to as a "metal rivet structure") 172.

[0027] Unlike conventional metal tracks in the M0 layer (which contact the metal plug in the VD layer at the interface 178 between the M0 and VD layers (shown in Figure 1B)), the metal rivet structure 172 and the metal plug 116 define a non-planar interface 188 (shown in Figure 1B). Specifically, the metal rivet structure 172 includes a shaft portion 174 and a head portion 176. The shaft portion is located in the M0 layer and the etch-stop layer 132, while the head portion 176 is located in the VD layer. In other words, unlike conventional metal tracks in the M0 layer, the head portion 176 of the metal rivet structure 172 extends into the VD layer, and specifically, into the metal plug 116. Furthermore, the metal plug 116 has a non-planar top surface defining a recess, and the recess accommodates the head portion 176. Therefore, as shown in Figure 1B, the area of ​​the interface 188 between the metal rivet structure 172 and the metal plug 116 is increased. As explained above, resistivity includes the contribution of surface scattering, which decreases with increasing surface area. Therefore, the increased surface area of ​​the interface 188 between the metal rivet structure 172 and the metal plug 116 reduces contact resistance.

[0028] In one embodiment, the metal plug 116 comprises tungsten, and the metal rivet structure 172 comprises a metal filler layer (e.g., copper) 166. Since copper has a lower resistivity than tungsten (approximately 1.68 × 10⁻⁸ Ω·m at 20°C), replacing a portion of the metal plug 116 (the portion of the groove that receives the head portion 176) with the copper-containing head portion 176 further reduces contact resistance. The more tungsten is replaced with copper, the greater the reduction in contact resistance.

[0029] As shown in Figure 1B, the shaft portion 174 is characterized by a top surface 182, a bottom surface 184, and a sidewall extending circumferentially perpendicularly (i.e., in the Z direction shown in Figure 1B) between the top surface 182 and the bottom surface 184. The shaft portion 174 includes a barrier layer 162, a lining layer 164, and a metal filler layer 166. In other words, the shaft portion 174 has a multi-layered structure.

[0030] The head portion 176 is characterized by a top surface 186. The top surface 186 of the head portion 176 and the bottom surface 184 of the shaft portion 174 intersect each other at an interface 178. The top surface 186 is planar. The area of ​​the top surface 186 is equal to or greater than the area of ​​the bottom surface 184. In other words, the area of ​​the top surface 186 is at least as large as the area of ​​the bottom surface 184. As will be discussed below, this is a result of the etching process during manufacturing. The bottom surface 188 of the head portion 176 is a curved surface. The bottom surface 188 of the head portion 176 mates with the top surface of the metal plug 116.

[0031] Top surface 186 and bottom surface 188 together surround head portion 176. Top surface 186 is the interface between head portion 176 and shaft portion 174. Top surface 186 and bottom surface 184 are coplanar. In one example, head portion 176 is a semi-ellipsoid (i.e., half an ellipsoid). In another example, head portion 176 is a hemisphere. Unlike shaft portion 174, head portion 176 includes lining layer 164 and metal filler layer 166, but no barrier layer 162. As will be discussed below, this feature (i.e., no barrier layer 162) makes the manufacturing process of metal rivet structure 172 compatible with barrier-free contact (BFC) processes.

[0032] The liner layer 164 promotes strong adhesion between the underlying dielectric layer (typically silicon dioxide) and the subsequent metal layer. The liner layer 164 prevents silicon atoms from diffusing from the substrate into the metal layer, which could reduce electrical efficiency. During the etching process, the liner layer can act as an etch stop, thereby ensuring precise control over the dimensions of the metal wiring. In one example, the liner layer 164 comprises ruthenium (Ru) and cobalt (Co). In another example, the liner layer 164 comprises Co. It should be understood that in other embodiments, the liner layer 164 may be made of other materials as needed. In one example, the thickness of the liner layer 164 is between 0.5 nanometers and 2 nanometers. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0033] Barrier layer 162 is essential to prevent copper atoms from diffusing into the underlying silicon or dielectric layer. While copper is an excellent conductor, it can migrate and cause reliability issues if not properly controlled. In one example, barrier layer 162 comprises tantalum (Ta). In another example, barrier layer 162 comprises tantalum nitride (TaN). In yet another example, barrier layer 162 comprises a combination of TaN and Ru (i.e., TaNRu), which can be fabricated using sequential deposition of TaN and Ru or co-sputtering of TaN and Ru. The use of the combination of TaN and Ru produces more reliable and durable interconnects, which are essential for the long-term performance of semiconductor devices. It should be understood that in other embodiments, barrier layer 162 may be made of other materials as needed. In one example, the thickness of barrier layer 162 is between 0.5 nanometers and 2 nanometers. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0034] The metal filler layer 166 is the primary conductor in the shaft portion 174 of the metal rivet structure 172. By combining three layers, the multilayer structure of the shaft portion 174 provides several benefits. The barrier layer 162 prevents copper diffusion, while the liner layer 164 ensures good adhesion and acts as an etch stop. The high conductivity of copper enables faster signal transmission and reduced power dissipation. The multilayer structure allows for the fabrication of smaller and more complex integrated circuits.

[0035] It should be noted that other metal tracks 160a and 160b are also disposed in the low-k dielectric layer 134, and each of them has a multilayer structure. Unlike the shaft portion 174, each of the metal tracks 160a and 160b is characterized by the bottom portion of the liner layer 164 and the bottom portion of the barrier layer 162. The metal tracks 160a and 160b in the M0 layer can extend in the Y or X direction as shown in Figure 1A to provide appropriate wiring as needed. It should be understood that more than two metal tracks may be disposed in the M0 layer as needed. Similarly, more than one metal rivet structure may be used as needed, such as the metal rivet structure 172 shown in Figure 1A. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0036] The etch stop layer 132 is operable to protect the underlying layer during the etching process, thereby ensuring precise control over the etching depth and patterning. Compared to the protected material, the etch stop layer 132 exhibits high etch resistance, good adhesion to the underlying layer, and the ability to be selectively removed after the etching process is complete. In one example, the etch stop layer 132 comprises aluminum oxide (AlOx). In another example, the etch stop layer 132 comprises aluminum nitride (AlN). In yet another example, the etch stop layer 132 comprises silicon carbonitride (SiCN). In yet another example, the etch stop layer 132 comprises silicon carbide (SiOC). In one example, the etch stop layer 132 comprises silicon carbonitride (SiOCN). It should be understood that in other embodiments, the etch stop layer 132 may use other materials as needed. In one example, the thickness of the etch stop layer 132 is between 0.5 nanometers and 10 nanometers. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0037] The low-k dielectric layer 134 acts as an interlayer dielectric (ILD), electrically isolating the different layers of the metal interconnect to prevent short circuits and ensure proper signal propagation. The low dielectric constant reduces capacitive coupling. The low-k dielectric layer 134 may contain SiON, porous SiO2, organic polymers, and similar materials, but other suitable materials may also be used. The thickness or height of the low-k dielectric layer 134 (denoted as "a" in Figure 1A) is between 15 nanometers and 25 nanometers. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0038] In the example shown in Figure 1A, the width of the shaft portion 174 in the X direction (denoted as "b" in Figure 1A) is between 6 nm and 12 nm, the thickness or height of the metal plug 116 in the Z direction (denoted as "c" in Figure 1A) is between 10 nm and 20 nm, and the width of the metal plug 116 in the X direction (denoted as "d" in Figure 1A) is between 7 nm and 15 nm. Furthermore, at the interface 178 shown in Figure 1B, the width of the head portion 176 in the X direction (denoted as "f" in Figure 1A) is equal to or greater than the width b, but less than (d-1) nm. In other words, the difference between the width d and the width f is greater than 1 nm. Furthermore, the depth or height of the head portion 176 in the Z direction (denoted as "e" in Figure 1A) is equal to or greater than 1 nm, but less than the thickness or height c. In other words, the head portion 176 does not reach the bottom surface of the metal plug 116. It should be understood that these geometries (e.g., a, b, c, d, e, as shown in Figure 1A) are illustrative and not restrictive, and other suitable geometries may be used.

[0039] Example manufacturing process flow

[0040] Figure 2 is a flowchart illustrating an example method 200 according to some embodiments. Figures 3A to 3D are cross-sectional views illustrating cross-sections of structures at various manufacturing stages according to some embodiments. In the example shown in Figure 2, method 200 includes operations 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, and 224. Additional operations may be performed. Furthermore, it should be understood that the sequences of various operations discussed above with reference to Figure 2 are provided for illustrative purposes, and therefore, different sequences may be utilized in other embodiments. These different sequences of operations will be included within the scope of the embodiments.

[0041] In operation 202, a (VD layer) metal plug is formed in a low-k dielectric layer. As shown in Figure 3A, a (VD layer) metal plug 116 is formed in a dielectric layer 114. The dielectric layer and the metal plug 116 are located in the VD layer, which is located above the MD layer shown in Figure 1A. As mentioned above, in one example, the metal plug 116 comprises tungsten. The top surface of the metal plug 116 is a planar surface at the joint.

[0042] In operation 204, a precursor layer is deposited on a low-k dielectric layer. In the example shown in Figure 3A, the low-k dielectric layer 134 is located on the etch stop layer 132, which is located on the dielectric layer 114. The precursor layer 136 is located on the low-k dielectric layer 134. The precursor layer 136 is operable to facilitate the deposition of a hard photomask in subsequent operation 206, discussed below. In one example, the precursor layer 136 comprises tetraethyl orthosilicate (TEOS). TEOS-based chemical vapor deposition (CVD) processes produce SiO2 films with excellent dielectric properties, high thermal stability, and good step coverage. TEOS can be used in various deposition techniques, including atmospheric pressure CVD (APCVD) and low-pressure CVD (LPCVD), allowing for precise control over film thickness and properties.

[0043] In operation 206, a hard photomask is deposited on the precursor layer. In the example shown in Figure 3A, hard photomask 138 is deposited on precursor layer 136. Hard photomask 138 is a thin, durable material layer used in semiconductor manufacturing to protect underlying layers during etching processes. Hard photomask 138 is more etch-resistant than photoresist, thus preventing it from being eroded during the etching process. Hard photomask also provides excellent etch selectivity, ensuring that only the desired material is removed. In one example, hard photomask 138 comprises tungsten carbide (WC). In one embodiment, tungsten carbide is formed by introducing a carbon-containing gas (such as methane or acetylene) along with the tungsten precursor into a CVD reactor. Tungsten carbide exhibits high resistance to various etchants, including those used for etching silicon dioxide and silicon nitride. In one example, hard photomask 138 comprises SiO2. In another example, hard photomask 138 comprises silicon nitride (Si3N4).

[0044] In operation 208, the hard photomask is patterned and etched. In the example shown in Figure 3A, a photoresist layer 140 is used to pattern and etch the hard photomask 138, thereby forming openings 302a, 302b, and 302c. Opening 302a is located above the metal plug 116 and corresponds to the shaft portion 174 of the metal rivet structure 172 shown in Figure 1A. Openings 302b and 302c correspond to the other MO metal tracks 160a and 160b shown in Figure 1A.

[0045] In operation 210, a low-k dielectric layer is etched using a hard photomask to form an opening. In the example shown in Figure 3B, the low-k dielectric layer 134 is etched at the location where it is exposed by the hard photomask 138.

[0046] In operation 212, the etch stop layer in the opening is removed to expose the top surface of the metal plug. In the example shown in Figure 3B, the etch stop layer 132 is etched at the location where it is exposed by the hard photomask 138. Therefore, openings 302a, 302b, and 302c extend to the top surface of the dielectric layer 114 and the metal plug 116.

[0047] In operation 214, a wet etching process is performed to remove at least a portion of the top portion of the hard photomask and metal plug to form a recess. In the example shown in Figure 3C, after the wet etching process, a portion of the hard photomask 138 is etched, forming island regions 139a, 139b, 139c, and 139d (collectively referred to as 139) of the original hard photomask 138. These island regions 139 reduce protrusions during subsequent operations of depositing the barrier layer, liner layer, and metal filler layer, thereby mitigating the risk of forming apertures in the openings 302 (collectively referred to as 302a, 302b, and 302c) when the aspect ratio is high. Furthermore, the reduced protrusions allow for a relatively thin barrier layer and a relatively thin liner layer, thereby reducing resistance. In some embodiments, the hard photomask 138 may be completely removed. In other words, the island regions 139 are not present in these embodiments.

[0048] On the other hand, since in some embodiments the hard photomask 138 contains tungsten doped carbon and the metal plug 116 contains tungsten, the metal plug 116 is also etched simultaneously. Therefore, the wet etching process has two functions simultaneously (i.e., forming the island region 139 and forming the groove 312). As a result of the wet etching process, the groove 312 is formed. The isotropic nature of the wet etching process contributes to the contour or shape of the groove 312. The groove 312 corresponds to the head portion 176 shown in Figure 1A and is formed in subsequent operations.

[0049] In some instances, the etchant used in wet etching processes is a potassium ferricyanide-based etchant (e.g., a weakly alkaline solution). In other instances, the etchant used in wet etching processes is an acid-based etchant (e.g., nitric acid, hydrofluoric acid, etc.). It should be understood that these instances are not intended to be limiting, and other suitable etchants may be used as needed. Those skilled in the art will recognize many variations, modifications, and alternatives.

[0050] In operation 216, a surface modification process is performed in the groove. In the example shown in Figure 3C, the surface of the groove 312 is modified using a surface modification process. After the surface modification process, the surface properties of the metal plug 116 in the groove 312 are modified to prevent a barrier layer from being deposited on the surface of the metal plug 116 in subsequent operations.

[0051] In one embodiment, the surface of the metal plug 116 in the groove 312 is modified by applying (e.g., by spin coating) inhibitor molecules. In one example, the inhibitor molecules comprise a self-assembled monolayer (SAM). A SAM is a molecule that can self-assemble on a surface to form a protective layer. By selectively applying the SAM to specific areas, it is possible to prevent the deposition of a barrier layer in those areas. The SAM may include head groups, end groups, and chain groups connecting the head groups and end groups to the surface of the metal plug 116 in the groove 312. The head groups exhibit hydrophilic interface properties, which result in adhesion to the surface of the metal plug 116 in the groove 312. The end groups make them less reactive to the precursors used in the deposition of the barrier layer.

[0052] In other examples, the inhibitor molecules contain small molecule inhibitors that block active sites on the surface, thereby preventing the adsorption of barrier layer precursors. In other words, SAM prevents or inhibits the deposition of the barrier layer. Those skilled in this art will recognize many variations, modifications, and alternatives.

[0053] In operation 218, a barrier layer is deposited. In the example shown in Figure 3D, barrier layer 162 is conformally deposited in openings 302a, 302b, and 302c shown in Figure 3C. Due to the surface modification process performed in operation 216 (e.g., by using SAM), barrier layer 162 is not formed on the surface of the metal plug 116 in the recess 312. Instead, barrier layer 162 is deposited on the bottom surfaces of openings 302a and 302b shown in Figure 3C. Thus, barrier-free contact is achieved at the desired location by selectively applying inhibitor molecules (e.g., SAM). In some embodiments, barrier layer 162 is formed using, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and other suitable processing techniques. Many variations, modifications, and alternatives will be recognized by those skilled in the art.

[0054] In one example, barrier layer 162 comprises tantalum (Ta). In another example, barrier layer 162 comprises tantalum nitride (TaN). In yet another example, barrier layer 162 comprises a combination of TaN and Ru (i.e., TaNRu), which can be fabricated using sequential deposition of TaN and Ru or co-sputtering of TaN and Ru. It should be understood that in other embodiments, barrier layer 162 may use other materials as needed. In one example, the thickness of barrier layer 162 is between 0.5 nanometers and 2 nanometers.

[0055] In some embodiments, a removal process is performed to remove inhibitor molecules (e.g., SAM) from the top surface of the metal plug 116 in the recess 312. In some embodiments, the removal process includes exposing the structure to a removal plasma for removing the inhibitor molecules. In other embodiments, other suitable techniques may be employed. Many variations, modifications, and alternatives will be recognized by those skilled in the art. The process is compatible with conventional barrier-free contact (BFC) processes.

[0056] In operation 220, a liner layer is deposited. In the example shown in Figure 3D, the liner layer 164 is conformally deposited in the openings 302a, 302b, and 302c and the groove 312 shown in Figure 3C. Since there is no barrier layer 162 deposited on the top surface of the metal plug 116 in the groove 312, the liner layer 164 is deposited on the top surface of the metal plug 116. In some embodiments, the barrier layer 162 is formed using, for example, physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), and other suitable processing techniques. Many variations, modifications, and alternatives will be recognized by those skilled in the art.

[0057] In one example, liner 164 comprises ruthenium (Ru) and cobalt (Co). In another example, liner 164 comprises Co. It should be understood that in other embodiments, liner 164 may be made of other materials as needed. In one example, the thickness of liner 164 is between 0.5 nanometers and 2 nanometers.

[0058] In operation 222, a metal filler layer is deposited. In the example shown in Figure 3D, the metal filler layer 166 is conformally deposited in the openings 302a, 302b, and 302c and the groove 312 shown in Figure 3C. In some embodiments, the metal filler layer 166 is formed using techniques such as electroplating, physical vapor deposition (PVD) including sputtering or evaporation, and other suitable processing techniques. Many variations, modifications, and alternatives will be recognized by those skilled in the art.

[0059] As explained above, the island region 139 shown in Figure 3C reduces protrusions during the deposition of the barrier layer 162, liner layer 164, and metal filler layer 166, thereby mitigating the risk of porosity formation in openings 302a, 302b, and 302c when the aspect ratio is high. Furthermore, the reduced protrusions allow for a relatively thin barrier layer 162 and a relatively thin liner layer 164, thereby reducing electrical resistance.

[0060] In operation 224, a planarization process is performed. In the example shown in Figure 3D, after the planarization process, excess portions of the barrier layer 162, liner layer 164, and metal filler layer 166 outside of openings 302a, 302b, and 302c are removed. The top surfaces of the low-k dielectric layer 134, barrier layer 162, liner layer 164, and metal filler layer 166 become coplanar to facilitate subsequent processing operations. In one embodiment, the planarization process is a chemical mechanical planarization (CMP) process, which involves a combination of chemical and mechanical forces to selectively remove material. A chemical slurry is applied to the wafer surface. The slurry contains chemical reagents that react with the wafer material, thereby weakening its bonds and making it more susceptible to mechanical removal. On the other hand, a rotating pad, typically made of polyurethane or other special materials, is pressed onto the wafer surface. Abrasive particles in the slurry, along with mechanical forces, remove material from high points on the wafer, thereby effectively smoothing the surface. Those familiar with this technology will recognize many variations, modifications, and alternatives.

[0061] Universal applicability of technology

[0062] Although the techniques disclosed herein are described in the context of the VD and M0 layers, it should be understood that these techniques are generally applicable to other BEOL processing applications. For example, a metal plug may be located in the M1 layer (i.e., the metal layer above and immediately following the M0 layer), and the shaft portion of the metal rivet structure may be located in the M2 layer (i.e., the metal layer above and immediately following the M0 layer). As another example, a metal plug may be located in the M0 layer, and the shaft portion of the metal rivet structure may be located in the M1 layer. For example, a metal plug may be located in the M3 layer, and the shaft portion of the metal rivet structure may be located in the M4 layer, above and immediately following the M3 layer. In short, these techniques can be applied to the interface between metal wires in two adjacent layers of a multi-layer structure (MLS) located at the back end of a semiconductor wafer.

[0063] Overview

[0064] According to some embodiments disclosed herein, a semiconductor structure is provided. The semiconductor structure includes: a substrate; a dielectric layer located above the substrate; a second dielectric layer disposed on the dielectric layer; a metal plug disposed in the dielectric layer and including a non-planar top surface of the metal plug, the non-planar top surface of the metal plug defining a groove; and a metal rivet structure. The metal rivet structure includes: a shaft portion passing through the second dielectric layer and including a bottom surface of the shaft portion; and a head portion located in the dielectric layer and including a top surface of the head portion and a non-planar bottom surface of the head portion, wherein the top surface of the head portion is coplanar with the bottom surface of the shaft portion, and the non-planar bottom surface of the head portion engages with the non-planar top surface of the metal plug.

[0065] According to some embodiments disclosed herein, a metal rivet structure disposed at the rear end of a semiconductor wafer is provided. The metal rivet structure includes: a shaft portion passing through a second dielectric layer and having a bottom surface including the shaft portion; and a head portion located in a dielectric layer below the second dielectric layer and having a top surface including the head portion and a non-planar bottom surface including the head portion, wherein the top surface of the head portion is coplanar with the bottom surface of the shaft portion, and the non-planar bottom surface of the head portion is operable to engage with the non-planar top surface of a metal plug.

[0066] According to some embodiments disclosed herein, a method is provided. This method includes: forming a metal plug in a dielectric layer; depositing a low-k dielectric layer on the dielectric layer; depositing a hard photomask on the low-k dielectric layer; patterning and etching the hard photomask; using the patterned hard photomask to etch the low-k dielectric layer to form an opening to expose the top surface of the metal plug; performing a wet etching process to remove at least a portion of the patterned hard photomask and the top portion of the metal plug to form a groove; depositing a barrier layer; depositing a liner layer; and depositing a metal filler layer.

[0067] The foregoing summary outlines features of several embodiments, enabling those skilled in the art to better understand the various aspects of this disclosure. Those skilled in the art will understand that they can readily use this disclosure as a basis for designing or improving other processes and structures to achieve the same purposes and / or advantages of the embodiments introduced herein. Those skilled in the art will also recognize that such equivalent constructions do not depart from the spirit and scope of this disclosure, and that various changes, substitutions, and modifications can be made herein without departing from the spirit and scope of this disclosure.

[0068] 100: Semiconductor Structure 112, 160a, 160b: Metal rails 114: Dielectric layer 116: Metal plug 132: Etching stop layer 134: Second dielectric layer / low-k dielectric layer 136: Precursor layer 138: Hard Photomask 139, 139a, 139b, 139c, 139d: Island areas 140: Photoresist layer 162: Barrier Layer 164: Lining layer 166: Metal filler layer 172: Metal contact structure / Metal rivet structure 174: Shaft section 176: Head section 178: Interface 182, 186: Top surface 184: Bottom surface 188: Non-planar interface / interface / bottom surface 200: Method 202, 204, 206, 208, 210, 212, 214, 216, 218, 220, 222, 224: Operations 302, 302a, 302b, 302c: Opening 312: Groove X:X direction Y: Y direction Z:Z direction a, c: thickness or height b, d, f: Width e: depth or height M0 layer: First metal layer MD layer: Device connection layer VD layer: First contact layer

[0069] Domestic storage information (please note in order of storage institution, date, and number) none Overseas storage information (please note in the order of storage country, institution, date, and number) none

Claims

1. A semiconductor structure comprising: a substrate; a dielectric layer disposed above the substrate; a second dielectric layer disposed on the dielectric layer; a metal plug disposed in the dielectric layer and including a non-planar top surface of the metal plug, the non-planar top surface of the metal plug defining a groove; and a metal rivet structure comprising: a shaft portion passing through the second dielectric layer and including a bottom surface of the shaft portion; and a head portion located in the dielectric layer and including a top surface of the head portion and a non-planar bottom surface of the head portion, wherein the top surface of the head portion is coplanar with the bottom surface of the shaft portion, and the non-planar bottom surface of the head portion engages with the non-planar top surface of the metal plug.

2. The semiconductor structure as claimed in claim 1, wherein the head portion includes a liner layer in contact with the metal plug and a metal filler layer located on the liner layer.

3. The semiconductor structure as claimed in claim 1, wherein the axial portion includes a barrier layer, a liner layer and a metal filler layer, the barrier layer laterally surrounding the liner layer and the liner layer laterally surrounding the metal filler layer.

4. The semiconductor structure as claimed in claim 1, wherein a first area of ​​the top surface of the head portion is equal to or greater than a second area of ​​the bottom surface of the shaft portion.

5. The semiconductor structure as claimed in claim 1, wherein the metal plug comprises tungsten, and a metal filler layer of the metal rivet structure comprises copper.

6. A metal rivet structure comprising: a shaft portion passing through a second dielectric layer and including a bottom surface of the shaft portion; and a head portion located in a dielectric layer below the second dielectric layer and including a top surface of the head portion and a non-planar bottom surface of the head portion, wherein the top surface of the head portion is coplanar with the bottom surface of the shaft portion, and the non-planar bottom surface of the head portion is operable to engage with a non-planar top surface of a metal plug.

7. The metal rivet structure as claimed in claim 6, wherein the head portion includes a lining layer in contact with the metal plug and a metal filler layer located on the lining layer.

8. The metal rivet structure as described in claim 6, wherein the head portion is a semi-elliptic.

9. A method of manufacturing a semiconductor structure, comprising: forming a metal plug in a dielectric layer; depositing a low-k dielectric layer on the dielectric layer; depositing a hard photomask on the low-k dielectric layer; patterning and etching the hard photomask; etching the low-k dielectric layer using the patterned hard photomask to form an opening to expose a top surface of the metal plug; performing a wet etching process to remove: at least a portion of the patterned hard photomask; and a top portion of the metal plug to form a groove; depositing a barrier layer; depositing a liner layer; and depositing a metal filler layer.

10. The method of claim 9, further comprising: performing a surface modification process in the groove to prevent the barrier layer from being deposited on the top surface of the metal plug in the groove.

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