Electronic package and substrate structure thereof
Patent Information
- Application Number
- TW114118708
- Authority / Receiving Office
- TW · TW
- Patent Type
- Patents
- Current Assignee / Owner
- Filing Date
- 2025-05-19
- Publication Date
- 2026-09-21
- Estimated Expiration
- 2045-05-18
Smart Images

Figure TWG2TB001912234_001 
Figure TWG2TB001912234_002 
Figure TWG2TB001912234_003
Abstract
Claims
1. A circuit structure comprising: An insulating body includes an insulating layer; a circuit layer disposed on the insulating body and having a plurality of electrical contact pads, wherein the plurality of electrical contact pads are used to connect a plurality of conductive bumps to electrically connect the plurality of electrical contact pads to electronic components via the plurality of conductive bumps; a plurality of conductive blind vias formed in the insulating body and electrically connected to the circuit layer, such that a single conductive blind via connects to a plurality of electrical contact pads; and a plurality of metal sheets disposed on the insulating body and adjacent to the conductive blind vias, wherein the metal sheets are spaced apart from each other and do not contact each other.
2. The circuit structure as described in claim 1, wherein, This line layer system is a line redistribution layer specification.
3. The circuit structure as described in claim 1, wherein, At least one of the complex conductive blind holes serves as a power supply circuit.
4. The circuit structure as described in claim 1, wherein, At least one of the complex conductive blind holes serves as a grounding circuit.
5. An electronic package, comprising: The circuit structure as described in any of requests 1 to 4; And the electronic component.
6. The electronic package as described in claim 5, wherein, The electronic component is located on one side of the circuit structure, while a plurality of conductive components are located on the other side.
7. An electronic package, comprising: The carrier structure includes a wiring layer; a plurality of conductive pillars disposed on one side of the carrier structure and electrically connected to the wiring layer; a covering layer covering the conductive pillars; a circuit structure as described in any of claims 1 to 4, disposed on the covering layer and electrically connected to the plurality of conductive pillars; and the electronic component.
8. The electronic package as described in claim 7, wherein, The overlay is an intermediary element embedded with a plurality of conductive silicon vias and electrically connecting the wiring layer and the line layer.
9. The electronic package as described in claim 7, wherein, The covering layer is an embedded electrical bridging element that electrically connects the wiring layer and the line layer.
10. The electronic package as described in claim 7, wherein, A plurality of conductive elements are disposed on the other side of the supporting structure.
Citation Information
Patent Citations
Electronic package, method of manufacturing same, and package substrate
CN111446216A
Semiconductor package structure and method for fabricating the same
TW200620585A
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TW202245336A
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