Memory device and operation method therefor

Abstract

A memory device and its operating method are disclosed. The memory device may be a high-capacity and high-performance 3D NAND flash memory. The operating method includes performing a programming operation on a target page, comprising first and second subprogramming operations. The first subprogramming operation includes applying a first programming pulse to a target word line corresponding to the target page to perform a first gun operation; and applying a first verification level voltage to the target word line to perform a first programming verification operation. The second subprogramming operation includes applying a second programming pulse to the target word line to perform a second gun operation; and applying a second verification level voltage to the target word line to perform a second programming verification operation. The second verification level voltage is greater than the first verification level voltage.

Claims

1. A method of operating a memory device, wherein the memory device includes a memory block having a plurality of memory cells, the plurality of memory cells being divided into a plurality of pages, and the plurality of pages corresponding to a plurality of character lines, wherein the method of operating the memory device includes: A programming operation is performed on a target page, wherein the target page is one of a plurality of pages. The programming operation includes at least one first sub-programming operation and at least one second sub-programming operation. The at least one first sub-programming operation includes: performing a first firing operation, wherein the first firing operation includes applying a first programming pulse to a target character line corresponding to the target page; and performing a first programming verification operation on the target page, wherein the first programming verification operation includes sequentially applying at least one first programming verification level voltage to the target character line, wherein the first programming verification level voltage corresponds to a current threshold voltage state. The at least one second sub-programming operation includes: performing a second firing operation, wherein the second firing operation includes applying the first programming pulse to the target character line; and performing a second programming verification operation on the target page, wherein the second programming verification operation includes sequentially applying at least one second programming verification level voltage to the target character line, wherein each of the at least one second programming verification level voltage is greater than the at least one first programming verification level voltage. The second programmed verification operation further includes: dividing the current threshold voltage state into multiple intervals based on the read gating voltage, the at least one first programmed verification level voltage, and the at least one second programmed verification level voltage, wherein each of the multiple intervals corresponds to a portion of the multiple memory cells in the target page, wherein the multiple memory cells in the target page are respectively connected to multiple bit lines, wherein, in response to a third memory cell in the target page that fails the second programmed verification operation, the voltage value of the first programmed pulse is increased by a step voltage value, and the second gun operation in the at least one second sub-programmed operation is performed on the third memory cell of the target page based on the first programmed pulse.

2. The method of operation as described in claim 1, wherein the plurality of memory cells are of a multilevel type, wherein the multilevel type means that one of the plurality of memory cells stores more than 1 bit of data.

3. The method of operation as described in claim 1, wherein the second gun operation in the at least one second subroutine operation is executed simultaneously with the first gun operation in the first operation of the at least one first subroutine operation.

4. The operating method according to request item 1, wherein, In response to a first memory cell in the target page that fails the first programming verification operation, the voltage value of the first programming pulse is increased by a step voltage value, and the first gun operation in the at least one first subprogramming operation is performed on the first memory cell of the target page based on the first programming pulse.

5. The operating method according to request item 1, wherein, In response to a second memory cell in the target page that has passed the first programmable verification operation, the second programmable verification operation in the at least one second subprogrammable operation is performed on the second memory cell of the target page.

6. The operating method according to claim 1, wherein the second gun operation further includes: According to each of the plurality of intervals, one of the plurality of bit line voltages is applied to a portion of the plurality of bit lines, wherein each of the plurality of intervals corresponds to a portion of the plurality of memory cells in the target page, wherein, in the second gun operation, the step of applying the first programmed pulse to the target word line and the step of applying the one of the plurality of bit line voltages to the portion of the plurality of bit lines according to each of the plurality of intervals are performed simultaneously.

7. The operating method according to claim 6, wherein the values ​​of the plurality of bit line voltages depend on the suppression voltage, wherein, According to each of the plurality of intervals, the step of applying one of the plurality of bit line voltages to a portion of the plurality of bit lines includes: providing one of the plurality of bit line voltages less than the suppression voltage to the word line corresponding to the third memory cell in the target page that fails the second programming verification operation; and providing one of the plurality of bit line voltages equal to the suppression voltage to the word line corresponding to the fourth memory cell in the target page that passes the second programming verification operation.

8. The operating method according to request item 1, wherein, When all of the plurality of memory cells in the target page that are in the current threshold voltage state have passed the second programmed verification operation, it is determined whether to perform the second programmed verification operation again.

9. A memory device, comprising: A memory array includes a memory block, wherein the memory block includes a plurality of memory cells, the plurality of memory cells are divided into a plurality of pages, and the plurality of pages correspond to a plurality of word lines; and a memory controller coupled to the memory block, wherein the memory controller is configured to: perform a programming operation on a target page, wherein the target page is one of the plurality of pages, wherein the programming operation includes at least one first subprogramming operation and at least one second subprogramming operation, wherein the at least one first subprogramming operation includes: performing a first firing operation, wherein the first firing operation includes applying a first programming pulse to a target word line corresponding to the target page; and performing a first programming verification operation on the target page, wherein the first programming verification operation includes sequentially applying at least one first programming verification level voltage to the target word line, wherein the at least one first programming verification level voltage corresponds to a current threshold voltage state, wherein the at least one second subprogramming operation includes: Performing a second-shot operation, wherein the second-shot operation includes applying the first programmed pulse to the target character line; and performing a second programmed verification operation on the target page, wherein the second programmed verification operation includes sequentially applying at least one second programmed verification level voltage to the target character line, wherein the at least one second programmed verification level voltage is greater than the at least one first programmed verification level voltage, wherein the second programmed verification operation further includes: dividing the current threshold voltage state into a plurality of intervals based on the read gate voltage, the at least one first programmed verification level voltage, and the at least one second programmed verification level voltage, wherein each of the plurality of intervals corresponds to a portion of the plurality of memory cells in the target page, wherein the plurality of memory cells in the target page are respectively connected to a plurality of character lines, wherein, in response to a third memory cell in the target page that fails the second programmed verification operation, the voltage value of the first programmed pulse is increased by a step voltage value, and the second-shot operation in the at least one second sub-programmed operation is performed on the third memory cell of the target page based on the first programmed pulse.

10. The memory device of claim 9, wherein the plurality of memory cells are of a multilevel type, wherein the multilevel type means that one of the plurality of memory cells stores more than 1 bit of data.

11. The memory device as claimed in claim 9, wherein the second gun operation in the at least one second subroutine operation is executed simultaneously with the first gun operation in the at least one first subroutine operation.

12. The memory device according to claim 9, wherein, In response to a first memory cell in the target page that fails the first programming verification operation, the voltage value of the first programming pulse is increased by a step voltage value, and the first gun operation in the at least one first subprogramming operation is performed on the first memory cell of the target page based on the first programming pulse.

13. The memory device according to claim 9, wherein, In response to a second memory cell in the target page that has passed the first programmable verification operation, the second programmable verification operation in the at least one second subprogrammable operation is performed on the second memory cell of the target page.

14. The memory device according to claim 9, wherein the second gun operation further includes: According to each of the plurality of intervals, one of the plurality of bit line voltages is applied to a portion of the plurality of bit lines, wherein each of the plurality of intervals corresponds to a portion of the plurality of memory cells in the target page, wherein, in the second gun operation, the step of applying the first programmed pulse to the target word line and the step of applying the one of the plurality of bit line voltages to the portion of the plurality of bit lines according to each of the plurality of intervals are performed simultaneously.

15. The memory device according to claim 14, wherein the values ​​of the plurality of bit line voltages depend on a suppression voltage, wherein, The step of applying one of the plurality of bit line voltages to a portion of the plurality of bit lines according to each of the plurality of intervals includes: providing one of the plurality of bit line voltages less than the suppression voltage to the word line corresponding to the third memory cell in the target page that fails the second programming verification operation; and providing one of the plurality of bit line voltages equal to the suppression voltage to the word line corresponding to the third memory cell in response to the fourth memory cell in the target page that passes the second programming verification operation.

16. The memory device according to claim 9, wherein, When all of the plurality of memory cells in the target page that are in the current threshold voltage state have passed the second programmed verification operation, it is determined whether to perform the second programmed verification operation again.

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